November 2006 Rev 6 1/78
1
M29W128FH
M29W128FL
128 Mbit (8Mb x 16 or 16Mb x 8, Page , Uniform Bloc k)
3V Supply Flash Memory
Feature summary
■Supply voltage
–V
CC = 2.7 to 3.6V for Program, Erase and
Read
–V
PP =12V for Fast Program (optional)
■Asynchronous Random/Page Read
– Page Width: 8 Words/16 Bytes
– Page Access: 25, 30ns
– Random Access: 60, 70ns
■Programming time
– 10µs per Byte/Word (typical)
– 4 Words / 8 Bytes Program
– 32-Word (64-Bytes) Write Buffer
■64 KByte (32 KWord) Uniform Blocks
■Program/ Erase Su spe n d an d Re su me Mode s
– Read from any Block during Pro gram
Suspend
– Read and Program anot he r Block during
Erase Suspend
■Unlock Bypass Program
– Faster Production/Batch Programming
■Common Flash Interface
– 64 bit Security Code
■100,000 Program/Erase cycles per block
■Low power consumption
– Standby and Automatic Standby
■Hardware Block Protection
–V
PP/WP pin for fast program and write
protect of the highest (M2 9W128FH) or
lowest block (M29W128FL)
■Extended Memory Block:
Extra block used as security block or to store
additional information
■Electronic Signature
– Manufacturer Code: 0020h
– Device Code:
M29W128FH: 227Eh + 2212h + 228Ah
M29W128FL: 227 Eh + 2212h + 228Bh
■ECOPACK® packages
BGA
TSOP56 (N)
14 x 20mm
TBGA64 (ZA)
10 x 13mm
www.st.com
Contents M29W128FH, M29W128FL
2/78
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Address Inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Data Input/Output or Address Input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . 12
2.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.8 VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.11 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.12 VCC supply voltage (2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.13 Vss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6 Special Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.1 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.2 Verify Extended Memory Block Protection Indicator . . . . . . . . . . . . . . . 17
3.6.3 Verify Block Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.4 Hardware Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.5 Temporary Unprotect of high voltage Protected Blocks . . . . . . . . . . . . . 18
4 Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
M29W128FH, M29W128FL Contents
3/78
4.2 Temporary Block Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.3 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.4 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.5 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.6 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.7 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.8 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.9 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.10 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.1 Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.2 Write to Buffer and Program Confirm command . . . . . . . . . . . . . . . . . . 29
5.2.3 Write to Buffer and Program Abort and Reset command . . . . . . . . . . . 29
5.2.4 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.5 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.6 Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.7 Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.8 Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.9 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.10 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.11 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 Extended Memory Block Protection commands . . . . . . . . . . . . . . . . . . . 34
5.3.1 Enter Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . 34
5.3.2 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.0.1 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.0.2 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.0.3 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.0.4 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.0.5 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.0.6 Write to Buffer and Program Abort Bit (DQ1) . . . . . . . . . . . . . . . . . . . . 38
Contents M29W128FH, M29W128FL
4/78
7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Appendix A Block addresses and Read/Modify Protection Groups . . . . . . . . . 54
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Appendix C Extended Memory Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
C.1 Factory Locked Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . 67
C.2 Customer Lockable Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . 68
Appendix D High Voltage Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
D.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
D.2 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Appendix E Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
M29W128FH, M29W128FL List of tables
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List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Bus operations, 8-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3. Read Electronic Signature, 8-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Block Protection, 8-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Bus operations, 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Read Electronic Signature, 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Block Protection, 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Hardware Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Standard commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Standard commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Fast Program commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. Fast Program commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. Extended Block Protection commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. Block Protection commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 15. Program, Erase Times and Program, Erase Endurance cycles . . . . . . . . . . . . . . . . . . . . . 36
Table 16. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 21. Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 22. Write AC characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 23. Write AC characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 24. Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 25. TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package mechanical data . . . 51
Table 26. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, packa ge mec ha n i cal da ta. . . . . . . 52
Table 27. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 28. Block Addresses and Protection Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 29. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 30. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 31. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 32. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 33. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 34. Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 35. Extended Memory Block Address and Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 36. Programmer technique Bus operations, 8-bit or 16-bit mode. . . . . . . . . . . . . . . . . . . . . . . 70
Table 37. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
List of figures M29W128FH, M29W128FL
6/78
List of figures
Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. TBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Data Polling flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 6. Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 8. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 9. Random Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 10. Page Read AC waveforms (Word mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 11. Write AC waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 12. Write AC waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. Reset/Block Temporary Unprotect AC waveforms (No Program/Erase ongoing) . . . . . . . 49
Figure 14. Reset/Block Temporary Unprotect during Program/Erase operation AC waveforms. . . . . 49
Figure 15. Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 16. TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package outline . . . . . . . . . . . 51
Figure 17. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline . . . . . . . . . . . . . . 52
Figure 18. Programmer equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 19. Programmer equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 20. In-System equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 21. In-System equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 22. Write to Buffer and Program flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . 75
M29W128FH, M29W128FL Summary description
7/78
1 Summary description
The M29W128FH and M29W128FL are 128 Mbit (16Mb x8 or 8Mb x16) non-volatile
memories that can be r ead, erased and reprogr ammed. These ope rations ca n be perf ormed
using a single low voltage (2.7 to 3.6V) supply. At Power-up the memories default to Read
mode. The M29W128FH and M29W128FL are divided into 256 thirty-two KWord (sixty-four
KByte) uniform blocks.
Progr am and Er ase commands a re written to the Command Int erf a ce of the memory. An on-
chip Program/Erase Controller simplifies the process of programming or erasing the
memory by taking care of all of the special operations that are required to update the
memory contents. The end of a program or erase opera tion can be detected and any error
conditions identified. The command set required to control the memory is consistent with
JEDEC standards.
The Chip Enable, Output Enable and Write Enable signals control the b us op erations of the
memory. They allow simple connection to most microprocessors, often without add itional
logic.
The devices support Asynchronous Random Read and Page Read from all bl ocks of the
memory array.
The M29W128FH and M29W128FL have an extr a 128 Word (256 Byte) Extended Memory
Bloc k tha t can be accesse d using a de dicat ed comman d. The Extend ed Memo ry Block can
be protected and so is useful for storing security information. However the protection is
irreversible, once protected the protection cannot be undone.
Each block can be erased independently, so it is possible to preserve valid data while old
data is erased.
The devices feature two different levels of hardware block protection to avoid unwanted
program or erase (modify):
●The VPP/WP pin protects the highest block on the M29W128FH and the lowest block
on the M29W128FL.
●The RP pin temporarily unprotects all the blocks previously protected using a High
Voltage Block Protection technique (see Appendix D: High Voltage Block Protection).
The memories are offered in TSOP56 (14 x 20mm) and TBGA64 (10 x 13mm, 1mm pit ch)
packages.
In order to meet environmental requirements, ST offers the M29W128FH and the
M29W128FL in ECOPACK® pa ckages . ECOPA CK pac kages are Lead-free . The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifica tions ar e available at: www.s t.c om .
The memories are supplied with all the bits erased (set to ’1’).
The M29W128FH and the M29W128FL will be referred to as M29W128F throughout the
document.
Summary descriptio n M29W128FH, M29W128FL
8/78
Figure 1. Logic diagram
1. Also see Appendix A and Table 28 for a full listing of the Block Addresses.
Table 1. Signal names
A0-A22 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A−1 Data Input/Output or Address Input
EChip Enable
GOutput Enable
WWrite Ena ble
RP Reset/Block Tempo rary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Sele ct
VCC Supply voltage
VPP/WP VPP/Write Protect
VSS Ground
NC Not Connected Internally
AI11525
23
A0-A22
W
DQ0-DQ14
VCC
M29W128FH
M29W128FL
E
VSS
15
G
RP
DQ15A-1
RB
VPP/WP
BYTE
M29W128FH, M29W128FL Summary description
9/78
Figure 2. TSOP connections
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A19
A8 DQ13
A17
A12
DQ14
A2
DQ12
DQ10
DQ15A-1
VCC
DQ4
DQ5
A7
DQ7
VPP/WP
A21
AI11526
M29W128FH
M29W128FL
14
1
15
28 29
42
43
56
DQ8
NC
A20
A1
A18
A4
A5
DQ1
DQ11
G
A14
A15 A16
A13 BYTE
NC
A22
VSS
E
A0
RP
VSS
A9
A10
A11
NC
NC
NC
NC
VCC
Summary descriptio n M29W128FH, M29W128FL
10/78
Figure 3. TBGA connections (top view through package)
654321
VSS
A11
A10
A8
A9
DQ3
DQ11
DQ10
A18
VPP
/
WP
RB
A0
A2
A4
A3
G
NC
NC
NC
DQ2
DQ1
DQ9
DQ8
A6
A17
A7
DQ4
VCC
DQ12
DQ5
A19
A21
RP
W
A5
DQ0
NC
NC
VSS
A1 A20
DQ7
BYTE
C
B
A
E
D
F
G
H
DQ15
A-1
87
AI11527
NC
A15
A14
A12
A13
DQ6
DQ13
DQ14
NC
A22
NC
VSS
A16
NC
NC
E
NC
NC
VCC
VCC
M29W128FH, M29W128FL Summary description
11/78
Figure 4. Block addresses
AI11528
(x8)
Address lines A22-A0, DQ15A-1
64 KBytes
FFFFFFh
FF0000h
64 KBytes
00FFFFh
000000h
64 KBytes
010000h
Total of 256
Uniform Blocks
01FFFFh
(x16)
Address lines A22-A0
32 KWords
7FFFFFh
7F8000h
32 KWords
007FFFh
000000h
32 KWords
008000h
00FFFFh
Signal descriptions M29W128FH, M29W128FL
12/78
2 Signal descriptions
See Figure 1: Logic diagram, and Table 1: Signal names , for a brief overview of the signals
connected to this device.
2.1 Address Inputs (A0-A22)
The Address Inputs select the cells in the me mory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller.
2.2 Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command Interface
of the internal state machine.
2.3 Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected addr ess during a Bus Read operation
when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status Register these bits should be ignored.
2.4 Data Input/Output or Address Input (DQ15A−1)
When the device is in x16 Bus mode, this pin behaves as a Data Input/Output pin (as DQ8-
DQ14). When the device is in x8 Bus mode, this pin behaves as an address pin; DQ15A−1
Low will select the LSB of the addressed Word, DQ15A−1 High will select the MSB.
Throughout the te xt consider references to the Data Input/Output to include this pin when
the device operates in x16 bus mode and references to the Address Inputs to include this
pin when the device operates in x8 bus mode except when stated explicitly otherwise.
2.5 Chip Enable (E)
The Chip Enab le pin, E, activ ates the memory, allo wing Bus Read a nd Bus Write operation s
to be performed. When Chip Enable is High, VIH, all other pins are ignored.
2.6 Output Enable (G)
The Output Enable pin, G, controls the Bus Read operation of the memory.
M29W128FH, M29W128FL Signal descriptions
13/78
2.7 Write Enable (W)
The Write Enable pin, W, controls the Bus Write operation of the memory’s Command
Interface.
2.8 VPP/Write Protect (VPP/WP)
The VPP/Write Protect pin provides two functions. The VPP function allows the memory to
use an external high voltage power supply to reduce the time req uired for Program
operat ions. This is achieved by bypassing the unlock cycles and /or using the multiple Word
(2 or 4 at-a-time) or multiple Byte Program (2, 4 or 8 at-a-time) commands.
The Write Protect function provides a hardware method of protecting the highest or lowest
bloc k. When V PP/Write Protect is Low, VIL, the h ighest or lo we st b loc k is pr otected; Pr ogr am
and Erase operations on this block are ignored while VPP/Write Protect is Low, even when
RP is at VID.
When VPP/Wr ite Protect is High, VIH, the memory reverts to the previous protection status
of the highest or lowest block. Program and Erase operations can now modify the data in
this block unless the block is protected using Block Protection.
Applying VPPH to the VPP/WP pin will temporarily unprotect any block previously protected
(including the highest or low est block) using a High Voltage Block Protection technique (In-
System or Programmer technique). See Table 8: Hardware Protection fo r details.
When VPP/Write Protect is raised to VPP the memory automatically en te rs th e Un lo ck
Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes.
During Unlock Byp ass Progr am oper ations the memory draw s IPP from the p in to su pply the
progr amming cir cuits. See the description of the Unlock Bypass command in th e Command
Interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than
tVHVPP (see Figure 15: Accelerated Program Timing wavefor ms).
Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the
memory may be left in an indetermin a te sta te.
The VPP/Write Protect pin must not be left floating or uncon nected or the device may
become unreliable. A 0.1µF capacitor should be connected between the VPP/Write Protect
pin and the VSS Ground pin to deco uple the curre nt surges from the pow er supply. The PCB
trac k widths must be sufficient to carry the currents required during Unloc k Bypass Progr am,
IPP
.
Signal descriptions M29W128FH, M29W128FL
14/78
2.9 Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all the b locks previously protected u sing a High Voltage
Bloc k Pr otect ion t echni que (I n -System or Pr ogrammer techn i que) . No te t hat if V PP/WP is at
VIL, then the highest or lowest block will remain protected even if RP is at VID.
A Hardware Reset is achieved by holding Reset/Bloc k Temporary Unprotect Low, VIL, for at
least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be
ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whicheve r occ urs last.
See Section 2.10: Ready/Busy Output (RB), Tabl e 24: Rese t/Block Temporary Unprot ect AC
characteristics and Figure 13 and Figure 14 for more details.
Holding RP at VID will temporarily unprotect all the blocks previously protected using a High
Voltage Block Protection technique. Program and erase operations on all blocks will be
possible. The transition from VIH to VID must be slower than tPHPHH.
2.10 Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or erase operation . During Prog ram or erase oper a ti ons Read y/Busy
is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and
Erase Suspend mode.
After a Hardw are Reset, Bus Read and Bus Write oper ations cannot begi n until Ready/Busy
becomes high-impedance. See Table 24: Reset/Block Temporary Unprotect AC
characteristics and Figure 13 and Figure 14.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.11 Byte/Word Organization Select (BYTE)
It is used to switch between the x8 and x16 Bus mode s of the memory. When Byte/Word
Organization Select is Lo w, VIL, the memory is in x8 mode, when it is High, VIH, the memory
is in x16 mode.
2.12 VCC supply voltage (2.7V to 3.6V)
VCC provides the power supply for all operations (Read, Program and Erase).
The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout
Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data
during pow er up, power down and power surges. If the Prog ram/Erase Cont roller is
progr amming or erasin g during this time then th e operation abo rts and the memory contents
being altered will be invalid.
A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations, Icc2.
M29W128FH, M29W128FL Signal descriptions
15/78
2.13 Vss ground
VSS is the reference f or all voltage me asurements . The device features two VSS pins both of
which must be connected to the system ground.
Bus operations M29W128FH, M29W128FL
16/78
3 Bus operations
There are five standard bus operations that control the de vice. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.
See Table 2 and Table 5, Bus Operations , for a summary. Typically glitches of less than 5ns
on Chip Enable, Write Enable, and Reset/Block Temporary Unprotect pins are ignored by
the memory and do not affect bus operations.
3.1 Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. To speed up the read operation the me mory array can be read in Page mode
where data is internally read and stored in a page buff er . The Page has a size of 8 Words (or
16 Bytes) and is addressed by the add ress inputs A2-A0 in x16 mode and A2-DQ15A−1 in
Byte mode.
A valid Bus Read operation inv olves setting the desired address on the Address Inputs,
applying a Low signal, VIL, to Chip Enable a nd Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the value, see Figure 9: Random Read AC
waveforms, Figure 10: Page Read AC waveforms (Word mode), and Table 21: Read AC
characteristics, for details of when the output becomes valid.
3.2 Bus Write
Bus Write operations write to the Command I nterf ace. A v alid Bus Write operat ion begins b y
setting the desire d address on the Address Inp uts. The Address In puts are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latche d by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
durin g the who le Bu s Write operation. See Figure 11 and Figure 12, Write AC Waveforms,
and Table 22 and Table 23, Write AC Characteristics, for details of the timing requirements.
3.3 Output Disable
The Data Inputs/Outputs are in the high impeda nce state when Output Enable is High, VIH.
3.4 Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Output s pins are placed in the h igh-impedance state . To reduce the Su pply Current to
the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.3V. For the
Standby current level see Table 20: DC character istics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, ICC3, for Program or Erase operations until the operation completes.
M29W128FH, M29W128FL Bus operations
17/78
3.5 Automatic Standby
If CMOS levels (VCC ± 0.3V) are used to drive the bus and the bus is inactive for tAVQV+
30ns or more the memory enters Automatic Standby wh ere the internal Supply Current is
reduced to the Standb y Supply Current, ICC2. The Data Inputs/Outputs will still output data if
a Bus Read operation is in progress.
3.6 Special Bus operations
Additional bus operations can be performed to read the Electronic Signature, verify the
Protection Stat us of the Extended Memory Block, and apply and remove Block Prot ection.
These bus operations are intended for use by programming equipment and are not usually
used in applications. They require VID to be applied to some pins.
3.6.1 Read Electronic Signature
The memory has two codes, the Manufacturer code and the Device code used to identify
the memory. These codes can accessed by performing read operations with con trol signals
and addresses set as shown in Table 3 and Table 5.
These codes can also be accessed b y issuin g an A uto Select co mmand (see Section 5.1.2:
Auto Select command).
3.6.2 Verify Extended Memory Block Protection Indicator
The Extended Memory Block is either Factory Locked or Customer Lockable.
The Protection Status of the Extended Memory Block (Factory Locked or Customer
Lockable) can be accessed by reading the Extended Memory Block Protection Indicator.
This is performed by applying the signals as shown in Table 4 and Table 7. The Protection
Status of the Extended Memory Block is then output on bit DQ7 of the Data Input/Outputs.
(see Table 2 and Table 5, Bus Operations).
The Protection Status of the Extended Memory Block can also be accessed by issuing an
Auto Select command (see Section 5.1.2: Auto Select command).
3.6.3 Verify Block Protection Status
The Protectio n Status of a Block can be directly accessed by performing a read operation
with control signals and addresses set as shown in Table 4 and Table 7.
If the Block is protected, then 01h (in x8 mode) is output on Data Input/Outputs DQ0-DQ7,
otherwise 00h is output.
3.6.4 Hardware Block Protect
The VPP/WP pin can be used to protect the highest or lowest block. When VPP/WP is at VIL
the highest or lowest block is protected and remains protected regardless of the Block
Protection Stat us or the Reset/Block Temporary Unprotect pin state.
Bus operations M29W128FH, M29W128FL
18/78
3.6.5 Temporary Unprotect of high voltage Protected Blocks
The RP pin can be use d to te mpo rarily unprotect all the blocks previously protect ed using th e In -Syste m
or the Programmer protection technique (High Voltage techniques).
Refer to Section 2.9: Reset/Block Temporary Unprotect (RP).
Tab le 2. Bus operations, 8-bit mode
Operation(1) E G W RP VPP/WP Address Inputs Data Inputs/Outputs
A22-A0, DQ15A-1 DQ14-DQ8 DQ7-DQ0
Bus Read VIL VIL VIH VIH VIH Cell Address Hi-Z Data Output
Bus Write VIL VIH VIL VIH VIH Command Address Hi-Z Data Input
Output Disable X VIH VIH VIH VIH X Hi-Z Hi-Z
Standby VIH XXV
IH VIH X Hi-Z Hi-Z
1. X = VIL or VIH.
Table 3. Read Electronic Signature, 8-bit mode
Read
Cycle(1) E G W
Address Inputs Data Inputs/Outputs
A22-A10 A9 A8-A7 A6 A5-A4 A3 A2 A1 A0 DQ15A-1 DQ14-
DQ8 DQ7-DQ0
Manufacturer
Code
VIL VIL VIH XV
ID XV
IL X
VIL VIL VIL VIL XHi-Z 20h
Device Code
(Cycle 1) VIL VIL VIL VIH X Hi-Z 7Eh (Both Devices)
Device Code
(Cycle 2) VIH VIH VIH VIL X Hi-Z 12h (Both Devices)
Device Code
(Cycle 3) VIH VIH VIH VIH XHi-Z
8Ah (M29W128FH)
8Bh (M29W128FL)
1. X = VIL or VIH.
M29W128FH, M29W128FL Bus operations
19/78
Table 4. Block Protection, 8-bit mode
Operation
(1) E G W RP VPP/
WP
Address Inputs Data Inputs/Outputs
A22-
A12 A11-
A10 A9 A8-
A7 A6 A5-
A4 A3-
A2 A1 A0 DQ15
A-1 DQ14
-DQ8 DQ7-DQ0
Verify
Extended
Memory
Block
Protection
Indicator
(bit DQ7) VIL VIL VIH VIH VIH BA X VID XV
IL XV
IL VIH
VIH
X
Hi-Z
M29W128FH
88h (factory
locked)
08h (customer
lockable)
M29W128FL
98h (factory
locked)
18h (customer
lockable)
Verify Block
Protection
Status VIL
01h
(protected)
00h
(unprotected)
Temporary
Block
Unprotect
(2) XXXV
ID X Valid Data Input
1. X = VIL or VIH. BA any Address in the Block.
2. The RP pin unprotects all the blocks that have been previously protected using a High Voltage protection Technique.
Table 5. Bus operations, 16-bit mode
Operation(1) E G W RP VPP/
WP
Address Inputs Data Inputs/Outputs
A22-A0 DQ15A-1, DQ14-DQ0
Bus Read VIL VIL VIH VIH VIH Cell Address Data Output
Bus Write VIL VIH VIL VIH VIH Command Address Data Input
Output Disable X VIH VIH VIH VIH XHi-Z
Standby VIH XXV
IH VIH XHi-Z
1. X = VIL or VIH.
Bus operations M29W128FH, M29W128FL
20/78
Table 6. Read Electronic Signature, 16-bit mode
Read Cycle(1) E G W
Address Inputs Data Inputs/Outputs
A22-
A10 A9 A8-
A7 A6 A5-
A4 A3 A2 A1 A0 DQ15A-1, DQ14-DQ0
Manufacturer
Code
VIL VIL VIH XV
ID XV
IL X
VIL VIL VIL VIL 0020h
Device Code
(Cycle 1) VIL VIL VIL VIH 227Eh
(Both Devices)
Device Code
(Cycle 2) VIH VIH VIH VIL 2212h
(Both Devices)
Device Code
(Cycle 3) VIH VIH VIH VIH 228Ah (M29W128FH)
228Bh (M29W128FL)
1. X = VIL or VIH.
Table 7. Block Protection, 16-bit mode
Operation(1) E G W RP VPP/
WP
Address Inputs Data Inputs/Outputs
A22-
A12 A11-
A10 A9 A8-
A7 A6 A5-
A4 A3-
A2 A1 A0 DQ15A-1,
DQ14-DQ0
Verify
Extended
Memory Block
Indicator
(bit DQ7) VIL VIL VIH VIH VIH BA X VID XV
IL XV
IL VIH
VIH
M29W128FH
0088h
(factory locked)
0008h
(customer lockable)
M29W128FL
0098h
(factory locked)
0018h
(customer lockable)
Verify Block
Protection
Status VIL 0001h (protected)
0000h (unprotected)
Temporary
Block
Unprotect (2) XXXV
ID X Valid Data Input
1. X = VIL or VIH. BA Any Address in the Block.
2. The RP pin unprotects all the blocks that have been previously protected using a High Voltage protection Technique.
M29W128FH, M29W128FL Hardware protection
21/78
4 Hardware protection
The M29W128F features hardware protection/unprotection. Refer to Table 8 for details on
hardwa re block protection/unprotection using VPP/WP and RP pins.
4.1 Write Protect
The VPP/WP pin protects the hig hest or lowest bloc k (refer to Section 2: Signal descriptions
for a detailed description of the sig nals).
4.2 Temporary Block Unprotect
When held at VID, the Reset/Block Temporary Unprotect pin, RP, will temporarily unprotect
all the bl ocks previously protected using a High Voltage Block Protection technique.
Tab le 8. Har dware Protection
VPP/WP RP Function
VIL
VIH Highest or lowest block protected from Program/Erase
operations
VID All blocks temporarily unprotected except the highest or
lowest block
VIH or VID VID All blocks temporarily unprotected
VPPH VIH or VID All blocks temporarily unprotected
Command interface M29W128FH, M29W128FL
22/78
5 Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to obse rve a
v alid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-
bit or 8-bit mode.
5.1 Standard commands
See either Table 9, or Table 10, depending on the configuration that is being used, for a
summary of the Standard commands.
5.1.1 Read/Reset command
The Read/Reset command returns the memory to Read mode. It also resets the errors in
the Status Register. Either one or three Bus Write operations can be used to issue the
Read/Reset command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the de vice to Read mode . If the Read/Reset command
is issued during the time-out of a Block erase operation, the memory will take up to 10µs to
abort. During the abort period no valid data can be read from the memory.
The Read/Reset command will not abort an Erase operation when issued while in Erase
Suspend.
5.1.2 Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code, the
Protection Status of e ach block (Block Protection Status) and the Extended Memory Block
Protection Indicator.
Three consecutive Bus Write operations are required to issue the Auto Select command.
Once the A uto Select command is issu ed Bus Read operations to spec ific addresses output
the Manufacturer Code, the Device Code, the Extended Memory Block Protection Indicator
and a Bloc k Protection Status (see Table 9 and Table 10 in conjunction with Table 3, Table 4,
Table 6 and Table 7). The memory remains in Auto Select mode until a Read/Reset or CFI
Query command is issued.
5.1.3 Read CFI Query command
The Read CFI Query Command is used to put the memory in Read CFI Query mode. On ce
in Read CFI Query mode, Bus Read operations to the memory will output data from the
Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the
Read CFI Query Command. This command is valid only when the device is in the Read
Array or Auto Select mode.
The Read/Reset command must be issued to return the device to the previous mode (the
Read Array mode or A uto Select mode). A second Read/Reset command is required to put
the device in Read Array mode from Auto Select mode.
M29W128FH, M29W128FL C ommand interface
23/78
See Appendix B, Table 29, Table 30, Table 31, Table 32, Table 33 and Table 34 for deta ils on
the information contained in the Common Flash Interface (CFI) memory area.
5.1.4 Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write op erations
are required to issue the Chip Erase Command and start the Program/Erase Controller.
If an y blocks are protected, then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100µs , leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possib le to issue any command to abort the operat ion. Typical
chip erase times are given in Table 15. All Bus Read operations during the Chip Erase
operation will output the Status Register on the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Chip Erase operation has completed the memory will return to the Read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command mu st be issued to reset the error condition and
return to Read mode.
The Chip Erase Comm and set s all of th e bits in unpr ot ected blocks of the memory to ’1’. All
previous data is lost.
5.1.5 Block Erase command
The Block Erase command can be used to er ase a list of one or more blocks. It sets all of
the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is
lost.
Six Bus Write operations are required to select the first block in the list. Each additional
bl ock in the list can be selected b y repeating the sixth Bus Write oper ation using the ad dress
of the additional block. The Block Erase operation starts the Program/Erase Controller after
a time-out period of 50µs after the last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any more blocks. Each additional block must
therefore be select ed within 50µs of the last block. The 50µs timer restarts when an
additional block is selected. After the sixth Bus Write operation, a Bus Read operation
outputs the Sta tus Register. See Section 6: Status register for details on how to identify if
the Program/Erase Controller has started the Block Erase operation.
After the Block Erase operation has completed, the memory returns to the Read mode,
unless an error has occurred. When an error occurs, Bus Read operations will continue to
output the Status Register. A Read/Reset command must be issued to reset the error
condition and return to Read mode.
If an y selected b l oc ks are prote cted then t hese are ignored and all the other selected b locks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100µs, lea ving the data unchanged. No error condition is
given when protected blocks are ignored.
During the Block Erase oper ation the memory will ignore all commands except the Erase
Suspend command and the Read/Reset command which is only accepted during the 50µs
time-out period. Typical block erase times are given in Table 15.
Command interface M29W128FH, M29W128FL
24/78
5.1.6 Erase Suspend command
The Erase Suspend command may be used to temporarily suspend a Block or multiple
Block Erase operation. One Bus Write operation is required to issue the command. Issuing
the Erase Suspend command retur n s the whole device to Read mode.
The Program/Erase Controller will suspend within the Erase Suspend Latency time (see
Table 15: Program, Er ase Times and Program, Erase Endurance cycles) of the Erase
Suspend Command being issued. Once the Program/Erase Controlle r has stopped the
memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend
command is issued during the period when the memory is waiting f or an additional block
(before the Program/Erase Controller starts) then the Erase is suspended immediately and
will start immediately when the Erase Resume Command is issued. It is not possible to
select any further blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program oper ations behave as normal on these blocks. If any
attempt is made to prog ram in a p rotected b loc k or in the suspended b loc k then th e Progr am
command is ignored and the data remains unchanged. The Status Register is not read and
no error condition is giv e n. Reading from blocks that are being er ased will output the Status
Register.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must b e issued to return the de vice to
Read Array mode before the Resume command will be acce pted.
During Erase Suspend a Bus Read operation to the Extended Memory Block will output the
Extended Memory Block data . Once in the Extended Block mode, the Exit Extended Block
command must be issued before the erase oper ation can be resumed.
5.1.7 Erase Resume command
The Erase Resume command is used to restart the Program/Erase Controller after an
Erase Suspend.
The de vice must be in Read Arra y mode before the Resume command will be accepted. An
Erase can be suspended and resumed more than once.
5.1.8 Program Suspend command
The Progr am Suspend command allo ws the system to int errupt a progra m operation so that
data can be read from any block. When the Program Suspend command is issued during a
progr am operation, the device suspends the prog ram opera tion within the Prog ram Suspend
Latency time (see Table 15: Program, Erase Times and Program, Erase Endurance cycles)
and updates the Status Register bits.
After the prog ram operati on has been suspended, th e syste m can rea d ar r ay data from any
address . How ever, data read from Program-Suspended addresses is not v alid.
The Program Suspend command may also be issued during a program oper ation while an
erase is suspended. In this case, data may be read from any addresse s not in Erase
Suspend or Program Suspend. If a read is needed from the Extended Memory Block area
(One-time Program area), the user must use the proper command sequences to enter and
exit this region.
The system may also issue the Auto Select command sequence when the device is in the
Program Suspend mode. The system can read as many Auto Select codes as required.
M29W128FH, M29W128FL C ommand interface
25/78
When the device exits the Auto Select mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See Aut o Select command sequence for
more information.
5.1.9 Program Resume command
After the Program Resume command is issued, the device reverts to programming. The
controller can determine the status of the program operation using the DQ7 or DQ6 status
bits , just as in the sta ndard prog r am oper ation. Refer to Section 6: Status register f or details .
The system must issue a Program Resume comman d, to exit the Program Suspend mode
and to continue the programming operation.
Further issuing of the Resume command is ignored. Another Program Suspend command
can be written after the device has resumed programming.
5.1.10 Program command
The Prog ram command can be used to prog ram a v alue to one address in the memory arra y
at a time . The command r equires f our Bus Write oper ations, the final Write operation lat ches
the address and data in the internal state machine and starts the Program/Erase Controller.
Programming can be suspended and t hen resumed by issuing a Program Suspend
command and a Program Resume command, respectively (see Section 5.1.8: Program
Suspend command and Section 5.1.9: Program Resume command).
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.
After programming has started, Bus Read operations output the Status Register content.
See Section 6: Status register f o r more det ails. Typical program t imes are g iven in Table 15:
Program, Erase Times and Program, Erase Endurance cycles.
After the progr am operation has completed the memory will return to the Read mode , unless
an error has occurr ed. When a n err or occu rs , Bus Read oper atio ns to the me mory continue
to output th e Status Register. A Read/Reset command m ust be issued to reset the error
condition and return to Read mode.
One of the Erase Commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.
Command interface M29W128FH, M29W128FL
26/78
Table 9. Standard commands, 8-bit mode
Command
Length
Bus operations(1)(2)
1st 2nd 3rd 4th 5th 6th
Add Data Add Data Add Data Add Data Add Data Add Data
Read/Reset 1X F0
3 AAA AA 555 55 X F0
Auto
Select
Manufacturer Code
3 AAA AA 555 55 AAA 90 (3) (3)
Device Code
Extended Memory
Block Protection
Indicator
Block Protection
Status
Program 4 AAA AA 555 55 AAA A0 PA PD
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6
+AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase/Progra m Suspend 1 X B0
Erase/Program Resume 1 X 30
Read CFI Query 1 AA 98
1. Grey cells represent Read cycles. The other cells are Write cycles.
2. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in
hexadecimal.
3. The Auto Select addresses and data are given in Table 3: Read Electronic Signature, 8-bit mode , and Table 4: Block
Protection, 8-bit mode, except for A9 that is ‘Don’t Care’.
M29W128FH, M29W128FL C ommand interface
27/78
Table 10. Standard commands, 16-bit mode
Command
Length
Bus operations(1)(2)
1st 2nd 3rd 4th 5th 6th
Add Data Add Data Add Data Add Data Add Data Add Data
Read/Reset 1XF0
3555AA2AA55 X F0
Auto
Select
Manufacturer Code
3 555 AA 2AA 55 555 90 (3) (3)
Device Code
Extended Memory
Block Protection
Indicator
Block Protection
Status
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase/Program Suspend 1 X B0
Erase/Program Resume 1 X 30
Read CFI Query 1 55 98
1. Gray cells represent Read cycles. The other cells are Write cycles.
2. X Don’t Care, PA Program Address, PD Program Data, BA any address in the Block. All values in the table are in
hexadecimal.
3. The Auto Select addresses and data are given in Table 6: Read Electronic Signature, 16-bit mode, and Table 7: Block
Protection, 16-bit mode, except for A9 that is ‘Don’t Care’.
Command interface M29W128FH, M29W128FL
28/78
5.2 Fast Program commands
The M29W128F offers a set of Fast Program commands to improve the programming
throughput:
●Write to Bu ffer and Program
●Double and Quadruple Word, Progr am
●Double, Quadruple and Octuple Byte Prog ram
●Unlock Bypass.
See either Table 12, or Table 11, depending on the configuration that is being used, for a
summary of the Fast Program commands.
When VPPH is applied to the VPP/ Write Protect pin the memory automatically enters the F ast
Program mode. The user can then choose to issue any of the Fast Program commands.
Care must be taken because applying a VPPH to the VPP/WP pin will temporarily unprotect
any protected block.
After programming has started, Bus Read operations in the memory output the Status
Register cont ent. Fast prog ram co mmands can be suspended and then resumed b y issuing
a Program Suspend command and a Program Resume command, respectively (see
Section 5.1.8: Progr am Suspend comma nd and Section 5.1.9: Progr am Resume command)
After the fast program operation has completed, the memory will return to the Read mode,
unless an error has occurred. When an error occurs Bus Read operations to the memory
will continue to output the Status Register. A Read/Reset command must be issued to reset
the error condition and return to Read mode. One of the Erase Commands must be used to
set all the bits in a block or in the whole memory from ’0’ to ’1’.
Typical Program times are given in Table 15: Program, Erase Times and Program, Erase
Endurance cycles.
5.2.1 Write to Buffer and Program command
The Write to Buffer and Prog ram Command mak es use o f the device’s 64-Byte Write Buffer
to speed up programming. 32 Words/64 Bytes can be loaded into the Write Buffer. Each
Write Buffer has the same A22-A5 ad dresses.The Write to Buffer and Program command
dramatically reduces system programming time compared to the standard non-buffered
Program command.
When issuing a Write to Buffer and Program command, the VPP/WP pin can be either held
High, VIH or raised to VPPH.
See Table 15 for details on typical Write to Buffer and Prog ram times in both cases.
Five successive steps are required to issue the Write to Buffer and Program command:
1. The Write to Buffer and Program command starts with two unlock cycles.
2. The third Bus Write cycle sets up the Write to Buff er and Progr am command. The setup
code can be addressed to any location within the targeted bl ock.
3. The fourth Bus Write cycle sets up the number of Words/Bytes to be programmed.
Value N is written to the same b loc k address, where N+1 is the n umber of W ords/Byt es
to be programmed. N+1 must not exceed the size of the Write Buf fer or the operation
will abort.
4. The fif th cycle loads the first address and data to be programmed.
M29W128FH, M29W128FL C ommand interface
29/78
Use N Bus Write cycles to load the address and data fo r each Word/Byte into the Write
Buffer. Addresses must lie within the range from the start address+1 to t he start address +
N-1. Optimum performance is obtained when the star t address corresponds to a 64 Byte
boundary. If the start address is not aligned to a 64 Byte boundary, the total programming
time is doubled.
All the addresses used in the Write to Buffer and Program operation must lie within the
same page.
To program the content of the Write Buff er, this command must be followed by a Write to
Buffer and Program Confir m command.
If an address is written several times during a Write to Buffer and Program operation, the
address/data counter will be decremented at each data load operation and the data will be
programmed to the last word loaded into the Buffer.
Invalid address combinations or failing to follow the correct sequence of Bus Write cycles
will abort the Write to Buffer and Program.
The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a Write to Buffer and Program operation.
If is not possib le to d etect Progr am oper ation f ails whe n changing prog rammed d ata from ‘0’
to ‘1’, that is when reprogramming data in a portion of memory already progr ammed. The
resulting data will be the logical OR between the previous value and the current value.
A Write to Buff er and Prog ram Abort and Reset command mu st be issued to ab ort the Write
to Buffer and Program operat ion and reset the device in Read mode.
See Appendix E, Figure 22: Write to Buffer and Program flowchart and Pseudo Code, for a
suggested flowchart on using the Write to Buffer and Program command.
5.2.2 Write to Buffer and Program Confirm command
The Write to Buff er an d Progr am Co nfirm command is used to confirm a Write to Buff er and
Program command and to program the N+1 Words/Bytes loaded in the Write Buffer by this
command.
5.2.3 Write to Buffer and Pr ogram Abort and Reset command
The Write to Buff er and Pro gr am Abort and Reset command is used to abort Write to Buffer
and Program command.
5.2.4 Double Word Program command
This is used to write tw o adjacent W o rds in x16 mode , sim ultaneously. The addresses of t he
two Words must differ only in A0.
Three bus write cycles are necessary to issue the command:
1. The first bus cycle sets up the command.
2. The second bus cycle latches the Address and the Data of the first Word to be written.
3. The third bus cycle latches the Address and the Data of the second Word to be written
and starts the Program/Erase Controller.
Command interface M29W128FH, M29W128FL
30/78
5.2.5 Quadruple Word Program command
This is used to write a page of four adjacent Words (or 8 adjacent Bytes), in x16 mode,
simultaneously. The addresses of the four Words must differ only in A1 and A0.
Fiv e bus write cycles are necessary to issue the command:
1. The first bus cycle sets up the command.
2. The second bus cycle latches the Address and the Data of the first Word to be written.
3. The third bus cycle latches the Address and the Data of the second Word to be written.
4. The fourth bus cycle latch es the Address and the Data of the third Word to be writt en.
5. The fifth bus cycle latches the Address and the Data of the fourth Word to be written
and starts the Program/Erase Controller.
5.2.6 Double Byte Program command
This is used to write two adjacent Bytes in x8 mode, simultaneously. The addresses of the
two Bytes must differ only in DQ15 A -1 .
Three bus write cycles are necessary to issue the command:
6. The first bus cycle sets up the command.
7. The second bus cycle latches the Address and the Data of the first Byte to be written.
8. The third bus cycle latches the Address and the Data of the second Byte to be written
and starts the Program/Erase Controller.
5.2.7 Quadruple Byte Program command
This is used to write four a djacent Bytes in x8 mode, simultaneo usly. The addresses of the
four Bytes must differ only in A0, DQ15A-1.
Fiv e bus write cycles are necessary to issue the command.
1. The first bus cycle sets up the command.
2. The second bus cycle latches the Address and the Data of the first Byte to be written.
3. The third bus cycle latches the Address and the Data of the second Byte to be written.
4. The fourth bus cycle latches the Address and the Data of the third Byte to be written.
5. The fifth bus cycle lat ches the Address and the Dat a of the f ourth Byte to be written and
starts the Program/Erase Controller.
M29W128FH, M29W128FL C ommand interface
31/78
5.2.8 Octuple Byte Program command
This is used to write eigh t adjacent Byte s, i n x8 mode, simultaneously. The addresses of the
eight Bytes must differ only in A1, A0 and DQ15A-1.
Nine bus write cycles are necessary to issue the command:
1. The first bus cycle sets up the command.
2. The second bus cycle latches the Address and the Data of the first Byte to be written.
3. The third bus cycle latches the Address and the Data of the second Byte to be written.
4. The fourth bus cycle latches the Address and the Data of the third Byte to be written.
5. The fifth bus cycle latches the Address and the Data of the fourth Byte to be written.
6. The sixth bus cycle latches the Address and the Data of the fifth Byte to be written.
7. The seventh bus cycle latches the Address and the Data of the sixth Byte to be written.
8. The eighth bus cycle latches the Address and the Data of the seventh Byte to be
written.
9. The ninth bus cycle latches the Address and the Data of the eighth Byte to be written
and starts the Program/Erase Controller.
5.2.9 Unlock Bypass command
The Unloc k Bypass command is used in conjunction with the Unlock Bypass Program
command to prog ram the memory f aster t ha n with t he stand ar d p rog ram commands . When
the cycle time to the device is long, considerable time saving can be made by using these
commands. Thr ee Bus Write oper at ions ar e requir ed to issue t he Unlock Bypass command.
Once the Unlock Bypass command has been issued, the memory enters Unlock Bypass
mode. When in Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass
Reset commands are valid. The Unlock Bypass Program command can then be issued to
program addresses within the memory, or the Unlock Bypass Reset command can be
issued to return the memory to Read mode. In Unlock Bypass mode the memory can be
read as if in Read mode.
5.2.10 Unlock Bypass Program command
The Unloc k Bypass Progr am command can be used to pr ogram on e address in the memory
array at a time. The command requires two Bus Write oper ations, the final write operation
latches the address and data and starts the Program/Erase Controller.
The Program operation u sing the Unlock Bypass Program comma nd behaves identically to
the Program operation using the Program command. The operation cannot be aborted, a
Bus Read oper ation to the memory outputs the Status Re gister . Se e the Progr am command
for details on the behavior.
5.2.11 Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unloc k Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass mode.
Command interface M29W128FH, M29W128FL
32/78
Table 11. Fast Program commands, 8-bit mode
Command
Length
Bus Writ e op erations(1)
1st 2nd 3rd 4th 5th 6th 7th 8th 9th
Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data
Write to
Buffer and
Program
N
+5 AAA AA 555 55 BA 25 BA N(2) PA(3) PD WBL
(4) PD
Write to
Buffer and
Program
Abort and
Reset
3 AAA AA 555 55 AAA F0
Write to
Buffer and
Program
Confirm
1BA
(5) 29
Double Byte
Program 3 AAA 50 PA0 PD0 PA1 PD1
Quadruple
Byte
Program 5 AAA 56 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3
Octuple
Byte
Program 9 AAA 8B PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7
Unlock
Bypass 3 AAA AA 555 55 AAA 20
Unlock
Bypass
Program 2 X A0 PA PD
Unlock
Bypass
Reset 2X 90 X 00
1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, WBL Write Buffer Location. All val ues i n the table are
in hexadecimal.
2. The maximum number of cycles in the command sequence is 68. N+1 is the number of Bytes to be programmed during the Write to B uffer
and Program operation.
3. Each buffer has the same A22-A5 addresses. A0-A4 and A-1 are used to select a Byte within the N+1 Byte page.
4. The 6th cycle has to be issued N time. WBL scans the Word inside the page.
5. BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles.
M29W128FH, M29W128FL C ommand interface
33/78
Tab le 12. Fast Program commands, 16-bit mode
Command
Length
Bus Write operations(1)
1st 2nd 3rd 4th 5th 6th
Add Data Add Data Add Data Add Data Add Data Add Data
Write to Buff er and Program N+
5555 AA 2AA 55 BA 25 BA N(2) PA(3) PD WBL
(4) PD
Write to Buff er and Program Abort and
Reset 3 555 AA 2AA 55 555 F0
Write to Buffer and Program Confirm 1 BA(5) 29
Double Word Program 3 555 50 PA0 PD0 PA1 PD1
Quadruple Word Program 5 555 56 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program 2 X A0 PA PD
Unlock Bypass Reset 2 X 90 X 00
1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, WBL Write Buffer Location. All values
in the table are in hexadecimal.
2. The maximum number of cycles in the command sequence is 36. N+1 is the number of Words to be programmed during
the Write to Buffer and Program operation.
3. Each buffer has the same A22-A5 addresses. A0-A4 are used to select a Word within the N+1 Word page.
4. The 6th cycle has to be issued N time. WBL scans the Word inside the page.
5. BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles.
Command interface M29W128FH, M29W128FL
34/78
5.3 Extended Memory Block Protection commands
The M29W128F offers a set of commands to access the Extended Memory Block and to
configure and check its protection mode.
The commands rela te d to th e Exte nd ed Memory Block Pr ot ecti on a re available in bo th 8 bit
and 16 bit memory configuration.
5.3.1 Enter Extended Memory Block command
The M29W128F has one extra 128 Word block (Extend ed Memory Block) that can only be
accessed using the Enter Extended Memory Block command.
Three Bus Write cycles are required to issue the Extended Memory Block command. Once
the command has been issued the device enters the Extended Memo ry Block mode where
all Bus Read or Prog ram operat ions are conducted on the Ext ended Memory Block. Once
the device is in the Extended Block mode, the Extended Memory Block is addressed by
using the ad dresses occupied by block 0 in the other op erating modes (see Table 28: Block
Addresses and Protection Groups).
The device remains in Extended Block mode until the Exit Extended Block command is
issued or pow er is remo ved from the de vice . Aft er po w er- up or a hard w are r eset, the device
rever ts to the Read mode where commands issued to block 0 address space will address
block 0.
Note that when the device is in the Extended Block mode, the VPP/WP pin cannot be used
for fast programming and the Unlock Bypass mode is not available.
The Extended Memory Block cannot be erased, and can be treated as one-time
programmable (OTP) memory.
In Extended Block mode , Er ase , Chip Er ase , Er ase Suspend and Er ase resume command s
are not allowed.
To exit from the Extended Block mode the Exit Extended Block command must be issued.
The Extended Memory Block can be protected by setting the Extended Memory Block
Protection Bit to ‘1’; however once protected t he protection cannot be undone.
5.3.2 Exit Extended Block command
The Exit Extended Block command is used to exit fr om the Extended Bloc k mode and return
the device to Read mode. Four Bus Write operations are required to issue the command.
M29W128FH, M29W128FL C ommand interface
35/78
Table 13. Extended Block Protection commands, 8-bit mode
Command
Length
Bus operations(1)(2)
1st 2nd 3rd 4th 5th 6th
Add Data Add Data Add Data Add Data Add Data Add Data
Enter Extended Block 3 AAA AA 555 55 AAA 88
Exit Extended Block 4 AAA AA 555 55 AAA 90 X 00
1. X Don’t Care. All values in the table are in hexadecimal.
2. Grey cells represent Read cycles. The other cells are Write cycles.
Table 14. Block Prot ection commands, 16-bit mode
Command
Length
Bus operations(1)(2)(3)
1st 2nd 3rd 4th 5th 6th 7th
Add Data Add Data Add Data Add Data Add Data Add Data Add Data
Enter Extended
Block 3 555 AA 2AA 55 555 88
Exit Extended Block 4 555 AA 2AA 55 555 90 X 00
1. Grey cells represent Read cycles. The other cells are Write cycles.
2. X Don’t Care. All values in the table are in hexadecimal.
3. During Command cycles, if the lower address bits are 555h or 2AAh then the address bits higher than A11 and data bits
higher than DQ7 are Don't Care.
Command interface M29W128FH, M29W128FL
36/78
Tab le 15. Program, Erase Times and Program, Erase Endurance cycles
Parameter Min Typ (1)(2) Max(2) Unit
Chip Erase 80 400(3) s
Block Erase (64 KBytes) 0.8 6(4) s
Erase Suspend Latency Time 50(4) µs
Byte Program
Single or Multiple Byte Program
(1, 2, 4 or 8 Bytes at-a-time) 10
200(3)
µs
Write to Buffer and Program
(64 Bytes at-a-time)
VPP/WP
=VPPH 90 µs
VPP/WP=VIH 280
Word Program
Single or Multiple Word Program
(1, 2 or 4 Words at-a-time) 10
200(3)
µs
Write to Buffer and Program
(32 Words at-a-time)
VPP/WP=
VPPH 90 µs
VPP/WP=VIH 280
Chip Program (Byte by Byte) 80 400(3) s
Chip Program (Word by Word) 40 200(3) s
Chip Program (Quadruple Byte or Double Word) 20 100(3) s
Chip Program (Octuple Byte or Quadruple W ord) 10 50(3) s
Program Suspend Latency Time 5 15 µs
Program/Er ase Cycles (per Block) 100,000 cycles
Data Retention 20 years
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.
4. Maximum value measured at worst case conditions for both temperature and VCC.
M29W128FH, M29W128FL Status register
37/78
6 Status register
The M29W128F has one Status Register. The Status Register provides information on the
current or previous Program or Erase operations. The various bits convey information and
errors on the operation. Bus Read operations from any address within the memory, always
read the Stat us Register during Program and Erase operations . It is also read during Erase
Suspend when an address within a block being erased is accessed.
The bits in the Status Register are summarized in Table 16: Status register bits.
6.0.1 Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After su ccessful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.
During Erase operations the Data P olling Bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.
Figure 5: Data P olling flowchart, giv es an e xample of how to use the Data Polling Bit. A Valid
Address is the address bein g programmed or an address within the block being erased.
6.0.2 Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Er ase Suspend. The Toggle
Bit is output on DQ6 when the Status Register is read.
During a Program/Erase operation the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address . After successful completion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will output when addressing a cell within a bloc k
being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
Figure 6: Toggle flowchart, gives an example of how to use the Data Toggle Bit.
Status register M29W128FH, M29W128FL
38/78
6.0.3 Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The
Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit is output on DQ5 when the Status Register
is read.
Note that the Prog ram command cannot change a bit se t to ’0 ’ back to ’1’ and att emptin g t o
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.
6.0.4 Erase Timer Bit (DQ3)
The Erase Timer Bit can be u sed to iden tify the st art of Program/Erase Controller oper a tion
during a Bloc k Erase command. Once the Program/Erase Controller starts erasing the
Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit
is set to ’0’ and additional blocks to be erased may be written to the Command Interface.
The Erase Timer Bit is output on DQ3 when the Status Register is read.
6.0.5 Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during
Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is
read.
During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,
etc., with successiv e Bus Read operations from ad dresses within the b locks being er ased. A
protected block is treated the same as a block not being era sed. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit change s from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read ope r at ion s f rom addre sses within the blocks being erased. Bu s Read
operat ions to addresses within bloc ks not being er ased will output the mem ory arra y data as
if in Read mode.
After an Erase operation that causes the Error Bit to be set, the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle Bit does not change if
the addressed block has erased correctly.
6.0.6 Write to Buffer and Program Abort Bit (DQ1)
The Write to Buffer and Program Abort bit, DQ1, is set to ‘1’ when a Write to Buffer and
Program operation aborts. The Write to Buffer and Program Abort and Reset command
must be issued to return the device to Read mode (see Write to Buffer and Program in
COMMANDS section).
M29W128FH, M29W128FL Status register
39/78
Figure 5. Data Polling flowc hart
Table 16. Status register bits(1)
Operation DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RB
Program DQ7 Toggle 0 – – 0 0
Program During Erase Suspend DQ7 Toggle 0 – – – 0
Write to Buffer and Program Abort DQ7 Toggle 0 – – 1 0
Program Error DQ7 Toggle 1 – – – Hi-Z
Chip Erase 0 Toggle 0 1 Toggle – 0
Block Erase before timeout 0 Toggle 0 0 Toggle – 0
0 Toggle 0 0 No Toggle – 0
Block Erase 0 Toggle 0 1 Toggle – 0
0 Toggle 0 1 No Toggle – 0
Erase Suspend 1 No Toggle 0 – Toggle – Hi-Z
Data read as normal – Hi-Z
Erase Error 0 Toggle 1 1 No Toggle – Hi-Z
0 Toggle 1 1 Toggle – Hi-Z
1. Unspecified data bits should be ignored.
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
at VALID ADDRESS
FAIL PASS
AI07760
DQ7
=
DATA YES
NO
YES
NO
DQ5 = 1
DQ7
=
DATA YES
NO
Status register M29W128FH, M29W128FL
40/78
Figure 6. Toggle flowchart
READ DQ6 at
Valid Address
START
READ DQ6
TWICE
at Valid Address
FAIL PASS
AI11530
DQ6
=
TOGGLE NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
at Valid Address
M29W128FH, M29W128FL Maximum rating
41/78
7 Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings ta ble may
cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Re fer also to the STMicroelectronics
SURE Program and other relevant quality docu ments.
Table 17. Absolute maximum ratings
Symbol Parameter Min Max Unit
TBIAS Temperature Under Bias − 50 125 °C
TSTG Storage Temperature − 65 150 °C
VIO Input or Output voltage(1)(2)
1. Minimum voltage may undershoot to −2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to VCC + 2V during transition and for less than 20ns during transitions.
− 0.6 VCC + 0.6 V
VCC Supply voltage − 0.6 4 V
VID Identification voltage − 0.6 13.5 V
VPP(3)
3. VPP must not remain at 12V for more than a total of 80hrs.
Program voltage − 0.6 13.5 V
DC and AC parameters M29W128FH, M29W128FL
42/78
8 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 18: Operating and AC measurement conditions. Designers should check that the
operat ing conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Figure 7. AC measurement load circuit
Table 18. Operating and AC measurement conditions
Parameter
M29W128FH, M29W128FL
Unit60 70
Min Max Min Max
VCC supply voltage 2.7 3.6 2.7 3.6 V
Ambient Operating Temperature − 40 85 − 40 85 °C
Load capacitance (CL)3030pF
Input Rise and Fall Times 10 10 ns
Input pulse voltages 0 to VCC 0 to VCC V
Input and Output Timing Ref. voltages VCC/2 VCC/2 V
AI05558
CL
CL includes JIG capacitance
DEVICE
UNDER
TEST
25kΩ
VCC
25kΩ
VCC
0.1µF
VPP
0.1µF
M29W128FH, M29W128FL DC and AC parameters
43/78
Figure 8. AC measurement I/O wav eform
Table 19. Device capacitance(1)
1. Sampled only, not 100% tested.
Symbol Parameter Test condition Min Max Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 12 pF
Table 20. DC characteristics
Symbol Parameter Test condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA
ICC1 Supply Current (Read) E = VIL, G = VIH,
f = 6MHz 10 mA
ICC2 Supply Current (Standby) E = VCC ± 0.2V,
RP = VCC ± 0.2V 100 µA
ICC3 (1)
1. Sampled only, not 100% tested.
Supply Current
(Program/Erase)
Program/Erase
Controller
active
VPP/WP =
VIL or VIH 20 mA
VPP/WP =
VPPH 20 mA
VIL Input Low voltage − 0.5 0.8 V
VIH Input High voltage 0.7VCC VCC + 0.3 V
VPPH Voltage for VPP/WP
Program Acceleration VCC = 2.7V ±10% 11.5 12.5 V
IPP Current for VPP/WP
Program Acceleration VCC = 2.7V ±10% 15 mA
VOL Output Low voltage IOL = 1.8mA 0.45 V
VOH Output High voltage IOH = − 100µAV
CC − 0.4 V
VID Identification voltage 11.5 12.5 V
VLKO Program/Erase Lock out
Supply voltage 1.8 2.3 V
AI05557
VCC
0V
VCC/2
DC and AC parameters M29W128FH, M29W128FL
44/78
Figure 9. Random Read AC wa veforms
AI08970
tAVAV
tAVQV tAXQX
tELQX tEHQZ
tGLQV
tGLQX tGHQX
VALID
A0-A22/
A–1
G
DQ0-DQ7/
DQ8-DQ15
E
tELQV tEHQX
tGHQZ
VALID
tBHQV
tELBL/tELBH tBLQZ
BYTE
M29W128FH, M29W128FL DC and AC parameters
45/78
Figure 10. Page Read AC waveforms (Word mode)
AI08971c
tEHQZ
tGHQX
VALID
A3-A22
A-1
G
DQ0-DQ15
E
tELQV tEHQX
tGHQZ
VALID
A0-A2 VALID VALID VALID VALID
VALID VALID VALID
tGLQV
tAVQV
tAVQV1
VALID VALID VALID VALID
VALID VALID VALID VALID
DC and AC parameters M29W128FH, M29W128FL
46/78
Table 21. Read AC characteristic s
Symbol Alt Parameter Test condition
M29W128FH,
M29W128FL Unit
60 70
tAVAV tRC Address Valid to Next Address Valid E = VIL,
G = VIL Min 60 70 ns
tAVQV tACC Address Valid to Output Valid E = VIL,
G = VIL Max 60 70 ns
tAVQV1 tPAGE Ad dress Valid to Output Valid (Page) E = VIL,
G = VIL Max 25 30 ns
tELQX(1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns
tELQV tCE Chip Enable Low to Output Valid G = VIL Max 60 70 ns
tGLQX(1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns
tGLQV tOE Output Enable Low to Output Valid E = VIL Max 20 25 ns
tEHQZ(1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 25 25 ns
tGHQZ(1) tDF Output Enable High to Output Hi-Z E = VIL Max 25 25 ns
tEHQX
tGHQX
tAXQX
tOH Chip Enable, Output Enable or Address
Transition to Output Transition Min 0 0 ns
tELBL
tELBH
tELFL
tELFH Chip Enable to BYTE Low or High Max 5 5 ns
tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 25 ns
tBHQV tFHQV BYTE High to Output Valid Max 30 30 ns
1. Sampled only, not 100% tested.
M29W128FH, M29W128FL DC and AC parameters
47/78
Figure 11. Write AC waveforms, Write Enable Controlled
AI08972
E
G
W
A0-A22/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHEL
tWHEH
tWHWL
tELWL
tAVWL
tWHGL
tWLAX
tWHDX
tAVAV
tDVWH
tWLWHtGHWL
RB
tWHRL
Table 22. Write AC characteristics, Write Enable Controlled
Symbol Alt Parameter
M29W128FH,
M29W128FL Unit
60 70
tAVAV tWC Address Valid to Next Address Valid Min 60 70 ns
tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns
tWLWH tWP Write Enable Low to Write Enable High Min 45 45 n s
tDVWH tDS Input Valid to Write Enable High Min 45 45 ns
tWHDX tDH Write Enab le High to Input Transition Min 0 0 ns
tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns
tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 ns
tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns
tWLAX tAH Write Enable Low to Addr ess Transition Min 45 45 ns
tGHWL Output Enable High to Write Enable Low Min 0 0 ns
tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns
tWHRL(1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns
tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs
1. Sampled only, not 100% tested.
DC and AC parameters M29W128FH, M29W128FL
48/78
Figure 12. Write AC waveforms, Chip Enable Controlled
AI08973
E
G
W
A0-A22/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHWL
tEHWH
tEHEL
tWLEL
tAVEL
tEHGL
tELAX
tEHDX
tAVAV
tDVEH
tELEHtGHEL
RB
tEHRL
Table 23. Write AC characteristics, Chip Enable Controlled
Symbol Alt Parameter
M29W128FH,
M29W128FL Unit
60 70
tAVAV tWC Address Valid to Next Address Valid Min 60 70 ns
tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns
tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 ns
tDVEH tDS Input Valid to Chip Enable High Min 45 45 ns
tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns
tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns
tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 30 ns
tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns
tELAX tAH Chip Enable Low to Address Transition Min 45 45 ns
tGHEL Output Enable High Chip Enable Low Min 0 0 ns
tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns
tEHRL(1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns
tVCHWL tVCS VCC High to Write Ena ble Low Min 50 50 µs
1. Sampled only, not 100% tested.
M29W128FH, M29W128FL DC and AC parameters
49/78
Figure 13. Reset/Block Temporary Unprotect AC waveforms (No Program/Erase ongoing)
Figure 14. Reset/Block Temporary Unprotect during Program/Erase operation AC waveforms
AI11300b
RB
RP tPLPX
tPHEL,
tPHGL
E, G
AI11301b
RB
RP
tPLPX
tRHEL, tRHGL
E, G
tPLYH
Table 24. Reset/Block Temporary Unprotect AC characteristics
Symbol Alt Parameter
M29W128FH,
M29W128FL Unit
60 70
tPLYH(1) tREADY RP Low to Read mode, during Program or
Erase Max 20 µs
tPLPX tRP RP Pulse Width Min 500 ns
tPHEL, tPHGL(1) tRH RP High to Write Enable Low, Chip Enable
Low, Output Enable Low Min 50 ns
tRPD RP Low to Standby Mode. Min 20 ns
tRHEL
tRHGL(1) tRB RB High to Write Enable Low, Chip Enable
Low, Output Enable Low Min 0 ns
1. Sampled only, not 100% tested.
DC and AC parameters M29W128FH, M29W128FL
50/78
Figure 15. Accelerated Program Timing waveforms
AI05563
VPP/WP
VPP
VIL or VIH tVHVPP tVHVPP
M29W128FH, M29W128FL Package mechanical
51/78
9 Package mechanical
Figure 16. TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package outline
1. Drawing is not to scale.
Table 25. TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.100 0.050 0.150 0.0039 0.0020 0.0059
A2 1.000 0.950 1.050 0.0394 0.0374 0.0413
B 0.220 0.170 0.270 0.0087 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.100 0.0039
D 20.000 19.800 20.200 0.7874 0.7795 0.7953
D1 18.400 18.300 18.500 0.7244 0.7205 0.7283
e 0.500 – – 0.0197 – –
E 14.000 13.900 14.100 0.5512 0.5472 0.5551
L 0.600 0.500 0.700 0.0236 0.0197 0.0276
α3° 0 5° 3° 0 5°
N56 56
TSOP-b
D1
E
1 N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
Package mechanical M29W128FH, M29W128FL
52/78
Figure 17. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline
1. Drawing is not to scale.
Tab le 26. TBGA64 10x13mm - 8x8 acti ve ball arra y, 1mm pitc h, packa ge mechanical
data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.300 0.200 0.350 0.0118 0.0079 0.0138
A2 0.800 0.0315
b 0.350 0.500 0.0138 0.0197
D 10.000 9.900 10.100 0.3937 0.3898 0.3976
D1 7.000 – – 0.2756 – –
ddd 0.100 0.0039
e 1.000 – – 0.0394 – –
E 13.000 12.900 13.100 0.5118 0.5079 0.5157
E1 7.000 – – 0.2756 – –
FD 1.500 – – 0.0591 – –
FE 3.000 – – 0.1181 – –
SD 0.500 – – 0.0197 – –
SE 0.500 – – 0.0197 – –
E1E
D1
D
eb
SD
SE
A2
A1
A
BGA-Z23
ddd
FD
FE
BALL "A1"
M29W128FH, M29W128FL Part numbering
53/78
10 Part numbering
Note: This product is also available with the Exten ded Memory Block factory locked. For further
details and ordering information contact your nearest ST sales office .
Devices are shipped from the factory with the memory content bi ts erased to ’1’.
F or a list of a vailab le opti ons (Spe ed, Package , etc.) or f or f urther information on an y aspect
of this device, please contact your nearest ST Sales Office.
Table 27. Ordering information scheme
Example: M29W128FH 70 N 6 F
Device type
M29
Operatin g voltage
W = VCC = 2.7 to 3.6V
Device function
128FH = 128 Mbit (x8/x16), Page, Uniform Block, Flash Memory,
Highest Block Protected by VPP/WP
128FL = 128 Mbit (x8/x16), Page, Uniform Block, Flash Memory,
Lowest Block Protected by VPP/WP
Speed
60 = 60ns
70 = 70ns
Package
N = TSOP56: 14 x 20 mm
ZA = TBGA64: 10 x13mm, 1mm pitch
Temperature range
6 = –40 to 85 °C
Option
E = ECOPACK Package, Standard Packing
F = ECOPACK Package, Tape & Reel Packing
Block addresses and Read/Modify Protection Groups M29W128FH, M29W128FL
54/78
Appendix A Block addresses and Read/Modify Protection
Groups
Table 28. Block Addresses and Protection Groups
Block Size
(KBytes/KWords) Protection Block
Group (x8) (x16)
0 64/32 Protection Group 000000h-00FFFFh 000000h-007FFFh
1 64/32 Protection Group 010000h-01FFFFh 008000h-00FFFFh
2 64/32 Protection Group 020000h-02FFFFh 010000h-017FFFh
3 64/32 Protection Group 030000h-03FFFFh 018000h-01FFFFh
464/32
Protection Group
040000h-04FFFFh 020000h-027FFFh
5 64/32 050000h-05FFFFh 028000h-02FFFFh
6 64/32 060000h-06FFFFh 030000h-037FFFh
7 64/32 070000h-07FFFFh 038000h-03FFFFh
864/32
Protection Group
080000h-08FFFFh 040000h-047FFFh
9 64/32 090000h-09FFFFh 048000h-04FFFFh
10 64/32 0A0000h-0AFFFFh 050000h-057FFFh
11 64/32 0B0000h-0BFFFFh 058000h-05FFFFh
12 64/32
Protection Group
0C0000h-0CFFFFh 060000h-067FFFh
13 64/32 0D0000h-0DFFFFh 068000h-06FFFFh
14 64/32 0E0000h-0EFFFFh 070000h-077FFFh
15 64/32 0F0000h-0FFFFFh 078000h-07FFFFh
16 64/32
Protection Group
100000h-10FFFFh 080000h-087FFFh
17 64/32 110000h-11FFFFh 088000h-08FFFFh
18 64/32 120000h-12FFFFh 090000h-097FFFh
19 64/32 130000h-13FFFFh 098000h-09FFFFh
20 64/32
Protection Group
140000h-14FFFFh 0A0000h-0A7FFFh
21 64/32 150000h-15FFFFh 0A8000h-0AFFFFh
22 64/32 160000h-16FFFFh 0B0000h-0B7FFFh
23 64/32 170000h-17FFFFh 0B8000h-0BFFFFh
24 64/32
Protection Group
180000h-18FFFFh 0C0000h-0C7FFFh
25 64/32 190000h-19FFFFh 0C8000h-0CFFFFh
26 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh
27 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh
M29W128FH, M29W128FL Block addresses and Read/Modify Protection Groups
55/78
28 64/32
Protection Group
1C0000h-1CFFFFh 0E0000h-0E7FFFh
29 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh
30 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh
31 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh
32 64/32
Protection Group
200000h-20FFFFh 100000h-107FFFh
33 64/32 210000h-21FFFFh 108000h–10FFFFh
34 64/32 220000h-22FFFFh 110000h–117FFFh
35 64/32 230000h-23FFFFh 118000h–11FFFFh
36 64/32
Protection Group
240000h-24FFFFh 120000h–127FFFh
37 64/32 250000h-25FFFFh 128000h–12FFFFh
38 64/32 260000h-26FFFFh 130000h–137FFFh
39 64/32 270000h-27FFFFh 138000h–13FFFFh
40 64/32
Protection Group
280000h-28FFFFh 140000h–147FFFh
41 64/32 290000h-29FFFFh 148000h–14FFFFh
42 64/32 2A0000h-2AFFFFh 150000h–157FFFh
43 64/32 2B0000h-2BFFFFh 158000h–15FFFFh
44 64/32
Protection Group
2C0000h-2CFFFFh 160000h–167FFFh
45 64/32 2D0000h-2DFFFFh 168000h–16FFFFh
46 64/32 2E0000h-2EFFFFh 170000h–177FFFh
47 64/32 2F0000h-2FFFFFh 178000h–17FFFFh
48 64/32
Protection Group
300000h-30FFFFh 180000h–187FFFh
49 64/32 310000h-31FFFFh 188000h–18FFFFh
50 64/32 320000h-32FFFFh 190000h–197FFFh
51 64/32 330000h-33FFFFh 198000h–19FFFFh
52 64/32
Protection Group
340000h-34FFFFh 1A0000h–1A7FFFh
53 64/32 350000h-35FFFFh 1A8000h–1AFFFFh
54 64/32 360000h-36FFFFh 1B0000h–1B7FFFh
55 64/32 370000h-37FFFFh 1B8000h–1BFFFFh
56 64/32
Protection Group
380000h-38FFFFh 1C0000h–1C7FFFh
57 64/32 390000h-39FFFFh 1C8000h–1CFFFFh
58 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh
59 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh
Table 28. Block Addresses and Protection Groups (continued)
Block Size
(KBytes/KWords) Protection Block
Group (x8) (x16)
Block addresses and Read/Modify Protection Groups M29W128FH, M29W128FL
56/78
60 64/32
Protection Group
3C0000h-3CFFFFh 1E0000h–1E7FFFh
61 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh
62 64/32 3E0000h-3EFFFFh 1F0000h–1F7FFFh
63 64/32 3F0000h-3FFFFFh 1F8000h–1FFFFFh
64 64/32
Protection Group
400000h-40FFFFh 200000h–207FFFh
65 64/32 410000h-41FFFFh 208000h–20FFFFh
66 64/32 420000h-42FFFFh 210000h–217FFFh
67 64/32 430000h-43FFFFh 218000h–21FFFFh
68 64/32
Protection Group
440000h-44FFFFh 220000h–227FFFh
69 64/32 450000h-45FFFFh 228000h–22FFFFh
70 64/32 460000h-46FFFFh 230000h–237FFFh
71 64/32 470000h-47FFFFh 238000h–23FFFFh
72 64/32
Protection Group
480000h-48FFFFh 240000h–247FFFh
73 64/32 490000h-49FFFFh 248000h–24FFFFh
74 64/32 4A0000h-4AFFFFh 250000h–257FFFh
75 64/32 4B0000h-4BFFFFh 258000h–25FFFFh
76 64/32
Protection Group
4C0000h-4CFFFFh 260000h–267FFFh
77 64/32 4D0000h-4DFFFFh 268000h–26FFFFh
78 64/32 4E0000h-4EFFFFh 270000h–277FFFh
79 64/32 4F0000h-4FFFFFh 278000h–27FFFFh
80 64/32
Protection Group
500000h-50FFFFh 280000h–287FFFh
81 64/32 510000h-51FFFFh 288000h–28FFFFh
82 64/32 520000h-52FFFFh 290000h–297FFFh
83 64/32 530000h-53FFFFh 298000h–29FFFFh
84 64/32
Protection Group
540000h-54FFFFh 2A0000h–2A7FFFh
85 64/32 550000h-55FFFFh 2A8000h–2AFFFFh
86 64/32 560000h-56FFFFh 2B0000h–2B7FFFh
87 64/32 570000h-57FFFFh 2B8000h–2BFFFFh
88 64/32
Protection Group
580000h-58FFFFh 2C0000h–2C7FFFh
89 64/32 590000h-59FFFFh 2C8000h–2CFFFFh
90 64/32 5A0000h-5AFFFFh 2D0000h–2D7FFFh
91 64/32 5B0000h-5BFFFFh 2D8000h–2DFFFFh
Table 28. Block Addresses and Protection Groups (continued)
Block Size
(KBytes/KWords) Protection Block
Group (x8) (x16)
M29W128FH, M29W128FL Block addresses and Read/Modify Protection Groups
57/78
92 64/32
Protection Group
5C0000h-5CFFFFh 2E0000h–2E7FFFh
93 64/32 5D0000h-5DFFFFh 2E8000h–2EFFFFh
94 64/32 5E0000h-5EFFFFh 2F0000h–2F7FFFh
95 64/32 5F0000h-5FFFFFh 2F8000h–2FFFFFh
96 64/32
Protection Group
600000h-60FFFFh 300000h–307FFFh
97 64/32 610000h-61FFFFh 308000h–30FFFFh
98 64/32 620000h-62FFFFh 310000h–317FFFh
99 64/32 630000h-63FFFFh 318000h–31FFFFh
100 64/32
Protection Group
640000h-64FFFFh 320000h–327FFFh
101 64/32 650000h-65FFFFh 328000h–32FFFFh
102 64/32 660000h-66FFFFh 330000h–337FFFh
103 64/32 670000h-67FFFFh 338000h–33FFFFh
104 64/32
Protection Group
680000h-68FFFFh 340000h–347FFFh
105 64/32 690000h-69FFFFh 348000h–34FFFFh
106 64/32 6A0000h-6AFFFFh 350000h–357FFFh
107 64/32 6B0000h-6BFFFFh 358000h–35FFFFh
108 64/32
Protection Group
6C0000h-6CFFFFh 360000h–367FFFh
109 64/32 6D0000h-6DFFFFh 368000h–36FFFFh
110 64/32 6E0000h-6EFFFFh 370000h–377FFFh
111 64/32 6F0000h-6FFFFFh 378000h–37FFFFh
112 64/32
Protection Group
700000h–70FFFFh 380000h–387FFFh
113 64/32 710000h–71FFFFh 388000h–38FFFFh
114 64/32 720000h–72FFFFh 390000h–397FFFh
115 64/32 730000h–73FFFFh 398000h–39FFFFh
116 64/32
Protection Group
740000h–74FFFFh 3A0000h–3A7FFFh
117 64/32 750000h–75FFFFh 3A8000h–3AFFFFh
118 64/32 760000h–76FFFFh 3B0000h–3B7FFFh
119 64/32 770000h–77FFFFh 3B8000h–3BFFFFh
120 64/32
Protection Group
780000h–78FFFFh 3C0000h–3C7FFFh
121 64/32 790000h–79FFFFh 3C8000h–3CFFFFh
122 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh
123 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh
Table 28. Block Addresses and Protection Groups (continued)
Block Size
(KBytes/KWords) Protection Block
Group (x8) (x16)
Block addresses and Read/Modify Protection Groups M29W128FH, M29W128FL
58/78
124 64/32
Protection Group
7C0000h–7CFFFFh 3E0000h–3E7FFFh
125 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh
126 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh
127 64/32 7F0000h-7FFFFFh 3F8000h-3FFFFFh
128 64/32
Protection Group
800000h–80FFFFh 400000h–407FFFh
129 64/32 810000h–81FFFFh 408000h–40FFFFh
130 64/32 820000h–82FFFFh 410000h–417FFFh
131 64/32 830000h–83FFFFh 418000h–41FFFFh
132 64/32
Protection Group
840000h–84FFFFh 420000h–427FFFh
133 64/32 850000h–85FFFFh 428000h–42FFFFh
134 64/32 860000h–86FFFFh 430000h–437FFFh
135 64/32 870000h–87FFFFh 438000h–43FFFFh
136 64/32
Protection Group
880000h–88FFFFh 440000h–447FFFh
137 64/32 890000h–89FFFFh 448000h–44FFFFh
138 64/32 8A0000h–8AFFFFh 450000h–457FFFh
139 64/32 8B0000h–8BFFFFh 458000h–45FFFFh
140 64/32
Protection Group
8C0000h–8CFFFFh 460000h–467FFFh
141 64/32 8D0000h–8DFFFFh 468000h–46FFFFh
142 64/32 8E0000h–8EFFFFh 470000h–477FFFh
143 64/32 8F0000h-8FFFFFh 478000h–47FFFFh
144 64/32
Protection Group
900000h-90FFFFh 480000h–487FFFh
145 64/32 910000h–91FFFFh 488000h–48FFFFh
146 64/32 920000h–92FFFFh 490000h–497FFFh
147 64/32 930000h–93FFFFh 498000h–49FFFFh
148 64/32
Protection Group
940000h–94FFFFh 4A0000h–4A7FFFh
149 64/32 950000h–95FFFFh 4A8000h–4AFFFFh
150 64/32 960000h–96FFFFh 4B0000h–4B7FFFh
151 64/32 970000h–97FFFFh 4B8000h–4BFFFFh
152 64/32
Protection Group
980000h–98FFFFh 4C0000h–4C7FFFh
153 64/32 990000h–99FFFFh 4C8000h–4CFFFFh
154 64/32 9A0000h–9AFFFFh 4D0000h–4D7FFFh
155 64/32 9B0000h–9BFFFFh 4D8000h–4DFFFFh
Table 28. Block Addresses and Protection Groups (continued)
Block Size
(KBytes/KWords) Protection Block
Group (x8) (x16)
M29W128FH, M29W128FL Block addresses and Read/Modify Protection Groups
59/78
156 64/32
Protection Group
9C0000h–9CFFFFh 4E0000h–4E7FFFh
157 64/32 9D0000h–9DFFFFh 4E8000h–4EFFFFh
158 64/32 9E0000h–9EFFFFh 4F0000h–4F7FFFh
159 64/32 9F0000h–9FFFFFh 4F8000h-4FFFFFh
160 64/32
Protection Group
A00000h–A0FFFFh 500000h–507FFFh
161 64/32 A10000h–A1FFFFh 508000h–50FFFFh
162 64/32 A20000h–A2FFFFh 510000h–517FFFh
163 64/32 A30000h–A3FFFFh 518000h–51FFFFh
164 64/32
Protection Group
A40000h–A4FFFFh 520000h–527FFFh
165 64/32 A50000h–A5FFFFh 528000h–52FFFFh
166 64/32 A60000h–A6FFFFh 530000h–537FFFh
167 64/32 A70000h–A7FFFFh 538000h–53FFFFh
168 64/32
Protection Group
A80000h–A8FFFFh 540000h–547FFFh
169 64/32 A90000h–A9FFFFh 548000h–54FFFFh
170 64/32 AA0000h–AAFFFFh 550000h–557FFFh
171 64/32 AB0000h–ABFFFFh 558000h–55FFFFh
172 64/32
Protection Group
AC0000h–ACFFFFh 560000h–567FFFh
173 64/32 AD0000h–ADFFFFh 568000h–56FFFFh
174 64/32 AE0000h–AEFFFFh 570000h–577FFFh
175 64/32 AF0000h-AFFFFFh 578000h–57FFFFh
176 64/32
Protection Group
B00000h–B0FFFFh 580000h–587FFFh
177 64/32 B10000h–B1FFFFh 588000h–58FFFFh
178 64/32 B20000h–B2FFFFh 590000h–597FFFh
179 64/32 B30000h-B3FFFFh 598000h–59FFFFh
180 64/32
Protection Group
B40000h–B4FFFFh 5A0000h–5A7FFFh
181 64/32 B50000h–B5FFFFh 5A8000h–5AFFFFh
182 64/32 B60000h–B6FFFFh 5B0000h–5B7FFFh
183 64/32 B70000h-B7FFFFh 5B8000h–5BFFFFh
184 64/32
Protection Group
B80000h–B8FFFFh 5C0000h–5C7FFFh
185 64/32 B90000h–B9FFFFh 5C8000h–5CFFFFh
186 64/32 BA0000h–BAFFFFh 5D0000h–5D7FFFh
187 64/32 BB0000h–BBFFFFh 5D8000h–5DFFFFh
Table 28. Block Addresses and Protection Groups (continued)
Block Size
(KBytes/KWords) Protection Block
Group (x8) (x16)
Block addresses and Read/Modify Protection Groups M29W128FH, M29W128FL
60/78
188 64/32
Protection Group
BC0000h–BCFFFFh 5E0000h–5E7FFFh
189 64/32 BD0000h–BDFFFFh 5E8000h–5EFFFFh
190 64/32 BE0000h–BEFFFFh 5F0000h–5F7FFFh
191 64/32 BF0000h–BFFFFFh 5F8000h-5FFFFFh
192 64/32
Protection Group
C00000h–C0FFFFh 600000h–607FFFh
193 64/32 C10000h–C1FFFFh 608000h–60FFFFh
194 64/32 C20000h–C2FFFFh 610000h–617FFFh
195 64/32 C30000h–C3FFFFh 618000h–61FFFFh
196 64/32
Protection Group
C40000h–C4FFFFh 620000h–627FFFh
197 64/32 C50000h–C5FFFFh 628000h–62FFFFh
198 64/32 C60000h–C6FFFFh 630000h–637FFFh
199 64/32 C70000h-C7FFFFh 638000h–63FFFFh
200 64/32
Protection Group
C80000h–C8FFFFh 640000h–647FFFh
201 64/32 C90000h–C9FFFFh 648000h–64FFFFh
202 64/32 CA0000h–CAFFFFh 650000h–657FFFh
203 64/32 CB0000h–CBFFFFh 658000h–65FFFFh
204 64/32
Protection Group
CC0000h–CCFFFFh 660000h–667FFFh
205 64/32 CD0000h–CDFFFFh 668000h–66FFFFh
206 64/32 CE0000h–CEFFFFh 670000h–677FFFh
207 64/32 CF0000h-CFFFFFh 678000h–67FFFFh
208 64/32
Protection Group
D00000h–D0FFFFh 680000h–687FFFh
209 64/32 D10000h–D1FFFFh 688000h–68FFFFh
210 64/32 D20000h–D2FFFFh 690000h–697FFFh
211 64/32 D30000h–D3FFFFh 698000h–69FFFFh
212 64/32
Protection Group
D40000h–D4FFFFh 6A0000h–6A7FFFh
213 64/32 D50000h–D5FFFFh 6A8000h–6AFFFFh
214 64/32 D60000h–D6FFFFh 6B0000h–6B7FFFh
215 64/32 D70000h-D7FFFFh 6B8000h–6BFFFFh
216 64/32
Protection Group
D80000h-D8FFFFh 6C0000h–6C7FFFh
217 64/32 D90000h-D9FFFFh 6C8000h–6CFFFFh
218 64/32 DA0000h-DAFFFFh 6D0000h–6D7FFFh
219 64/32 DB0000h-DBFFFFh 6D8000h–6DFFFFh
Table 28. Block Addresses and Protection Groups (continued)
Block Size
(KBytes/KWords) Protection Block
Group (x8) (x16)
M29W128FH, M29W128FL Block addresses and Read/Modify Protection Groups
61/78
220 64/32
Protection Group
DC0000h-DCFFFFh 6E0000h–6E7FFFh
221 64/32 DD0000h-DDFFFFh 6E8000h–6EFFFFh
222 64/32 DE0000h-DEFFFFh 6F0000h–6F7FFFh
223 64/32 DF0000h-DFFFFFh 6F8000h-6FFFFFh
224 64/32
Protection Group
E00000h-E0FFFFh 700000h–707FFFh
225 64/32 E10000h-E1FFFFh 708000h–70FFFFh
226 64/32 E20000h-E2FFFFh 710000h–717FFFh
227 64/32 E30000h-E3FFFFh 718000h–71FFFFh
228 64/32
Protection Group
E40000h-E4FFFFh 720000h–727FFFh
229 64/32 E50000h-E5FFFFh 728000h–72FFFFh
230 64/32 E60000h-E6FFFFh 730000h–737FFFh
231 64/32 E70000h-E7FFFFh 738000h–73FFFFh
232 64/32
Protection Group
E80000h-E8FFFFh 740000h–747FFFh
233 64/32 E90000h-E9FFFFh 748000h–74FFFFh
234 64/32 EA0000h-EAFFFFh 750000h–757FFFh
235 64/32 EB0000h-EBFFFFh 758000h–75FFFFh
236 64/32
Protection Group
EC0000h-ECFFFFh 760000h–767FFFh
237 64/32 ED0000h-EDFFFFh 768000h–76FFFFh
238 64/32 EE0000h-EEFFFFh 770000h–777FFFh
239 64/32 EF0000h-EFFFFFh 778000h–77FFFFh
240 64/32
Protection Group
F00000h-F0FFFFh 780000h–787FFFh
241 64/32 F10000h-F1FFFFh 788000h–78FFFFh
242 64/32 F20000h-F2FFFFh 790000h–797FFFh
243 64/32 F30000h-F3FFFFh 798000h–79FFFFh
244 64/32
Protection Group
F40000h-F4FFFFh 7A0000h–7A7FFFh
245 64/32 F50000h-F5FFFFh 7A8000h–7AFFFFh
246 64/32 F60000h-F6FFFFh 7B0000h–7B7FFFh
247 64/32 F70000h-F7FFFFh 7B8000h–7BFFFFh
248 64/32
Protection Group
F80000h-F8FFFFh 7C0000h–7C7FFFh
249 64/32 F90000h-F9FFFFh 7C8000h–7CFFFFh
250 64/32 FA0000h-FAFFFFh 7D0000h–7D7FFFh
251 64/32 FB0000h-FBFFFFh 7D8000h–7DFFFFh
252 64/32 Protection Group FC0000h-FCFFFFh 7E0000h–7E7FFFh
253 64/32 Protection Group FD0000h-FDFFFFh 7E8000h–7EFFFFh
Table 28. Block Addresses and Protection Groups (continued)
Block Size
(KBytes/KWords) Protection Block
Group (x8) (x16)
Block addresses and Read/Modify Protection Groups M29W128FH, M29W128FL
62/78
254 64/32 Protection Group FE0000h-FEFFFFh 7F0000h–7F7FFFh
255 64/32 Protection Group FF0000h-FFFFFFh 7F8000h–7FFFFFh
Table 28. Block Addresses and Protection Groups (continued)
Block Size
(KBytes/KWords) Protection Block
Group (x8) (x16)
M29W128FH, M29W128FL Common Flash Interface (CFI)
63/78
Appendix B Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from
the Flash memory device. It allo ws a syst em so ft ware to query the device t o det ermine v arious el ectrical
and timing parameters , density information and functions supported by the memory. The system can
interface easily with the device, enabling the software to upgrade itself when necessary.
When the Read CFI Query command is issued, the memory enters Read CFI Query mode and read
operations output the CFI data. Table 29, Table 30, Table 31, Table 32, Table 33 and Table 34 show the
addresses (A-1, A0-A 10) used to retrieve the data. The CFI data structure also contains a security area
where a 64 bit unique security number is written (see Table 34: Security Code Area). This area can be
accessed only in Read mode by the final user. It is impossible to change the security number after it has
been written by ST.
Table 29. Query Structure Overview(1)
Address Sub-sectio n Name Description
x16 x8
10h 20h CFI Query Identification String Command set ID and algorithm data offset
1Bh 36h System Interface Information Device timing & voltage informatio n
27h 4Eh Device Geometry Definition Flash device layout
40h 80h Primary Algorithm-specific Extended Query table Additional information specific to the Primary
Algorithm (optional)
61h C2h Security Code Area 64 bit unique device number
1. Query data are always presented on the lowest order data outputs.
Table 30. CFI Query Identification String(1)
Address Data Description Value
x16 x8
10h 20h 0051h “Q”
11h 22h 0052h Query Unique ASCII String "QRY" "R"
12h 24h 0059h "Y"
13h 26h 0002h Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm AMD
Compatible
14h 28h 0000h
15h 2Ah 0040h Address for Primary Algorithm extended Query table (see Table 33) P = 40h
16h 2Ch 0000h
17h 2Eh 0000h Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported NA
18h 30h 0000h
19h 32h 0000h Address for Alternate Algorithm extended Query table NA
1Ah 34h 0000h
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
Common Flash Interface (CFI) M29W128FH, M29W128FL
64/78
Table 31. CFI Query System Interface Information(1)
Address Data Description Value
x16 x8
1Bh 36h 0027h VCC Logic Sup ply Minimum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100mV 3.0V
1Ch 38h 0036h VCC Logi c Supply Maximum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100mV 3.6V
1Dh 3Ah 00B5h VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100mV 11.5V
1Eh 3Ch 00C5h VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 10mV 12.5V
1Fh 3Eh 0004h Typical timeout per single Byte/Word program = 2n µs 16µs
20h 40h 0000h Typ ical timeout for minimum size write buffer program = 2n µs NA
21h 42h 0009h Typ ical timeout per individual block erase = 2n ms 512ms
22h 44h 0000h Typical timeout for full Chip Erase = 2n ms NA
23h 46h 0005h Maximum timeout for Byte/Word program = 2n times typical 512µs
24h 48h 0000h Maximum timeout for write buffer program = 2n times typical NA
25h 4Ah 0004h Maximum timeout per individual block erase = 2n times typical 8s
26h 4Ch 0000h M aximum timeout for Chip Erase = 2n times typical NA
1. The values given in the above table are valid for both packages.
Table 32. De vice Geometry Definition
Address Data Description Value
x16 x8
27h 4Eh 0018h Device Size = 2n in number of Bytes 16 MBytes
28h
29h 50h
52h 0002h
0000h Flash Device Interface Code description x8, x16
Async.
2Ah
2Bh 54h
56h 0006h
0000h Maximum number of Bytes in Multiple-Byte program or Page= 2n64
2Ch 58h 0001h Number of Erase Block Regions. It specifies the number of regions
containing contiguous Erase Blocks of the same size. 1
2Dh
2Eh 5Ah
5Ch 00FFh
0000h Erase Block Region 1 Information
Number of Erase Blocks of identical size = 00FFh+1 256
2Fh
30h 5Eh
60h 0000h
0001h Erase Block Region 1 Information
Block size in Region 1 = 010 0h * 256 Byte 64
KBytes
M29W128FH, M29W128FL Common Flash Interface (CFI)
65/78
31h
32h
33h
34h
62h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information 0
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 informati on 0
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 informati on 0
Table 32. Device Geometry Definition (continued)
Address Data Description Value
x16 x8
Table 33. Primary Algori thm-Specific Extended Query Table (1)
Address Data Description Value
x16 x8
40h 80h 0050h
Primary Algorithm extended Query table unique ASCII string “PRI”
"P"
41h 82h 0052h "R"
42h 84h 0049h "I"
43h 86h 0031h Major version number, ASCII "1"
44h 88h 0033h Minor version number, ASCII "3"
45h 8Ah 000Ch Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2) Yes
46h 8Ch 0002h Erase Suspend
00 = not supported, 01 = Read only, 02 = Read an d Write 2
47h 8Eh 0001h Block Protection
00 = not supported, x = number of sectors in per group 1
48h 90h 0001h Temporary Block Unprotect
00 = not supported, 01 = supported Yes
49h 92h 0006h Block Protect /Unprotect
06 = M29W128FH/M29W128FL 6
4Ah 94h 0000h Simultaneous Operations: Not Supported NA
4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No
4Ch 98h 0002h Page Mode, 00 = not supported, 02 = 8-Word page 02
4Dh 9Ah 00B5h VPP Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100mV 11.5V
Common Flash Interface (CFI) M29W128FH, M29W128FL
66/78
4Eh 9Ch 00C5h VPP Supp ly Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100mV 12.5V
4Fh 9Eh 0000h Top/Bottom Boot Block Flag
00h = Uniform device
Uniform +
VPP/WP
Protecting
Highest or
Lowest
Block
50h A0h 0001h Program Suspend, 00 = not supported, 01 = supported Yes
1. The values given in the above table are valid for both packages.
Table 33. Primary Algori thm-Specific Extended Query Table (continued)(1)
Address Data Description Value
x16 x8
Table 34. Security Code Area
Address Data Description
x16 x8
61h C3h, C2h XXXX
64 bit: unique device number
62h C5h, C4h XXXX
63h C7h, C6h XXXX
64h C9h, C8h XXXX
M29W128FH, M29W128FL Extended Memory Block
67/78
Appendix C Extended Memory Block
The M29W128F has an extra bl ock, the Extended Memory Block, that can be accessed
using a dedicated command. This Extended Memory Block is 128 Words in x16 mode and
256 Bytes in x8 mode. It is used as a security block (to provide a permanent security
identification number) or to store additional information.
The Extended Memory Block is eith er Factory Locked or Customer Lockable, its status is
indicated by bit DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot
be changed. When set to ‘1’, it indicates that the device is factory locked and the Extended
Memory Block is protected. Wh en set t o ‘0’, it indica te s th at the device is customer lockab le
and the Extended M emory Bloc k is unprotected. Bit DQ7 bei ng permanently loc k ed to either
‘1’ or ‘0’ is ano ther security f eature which en sures that a cu stomer loc kable de vice ca nnot be
used instead of a factory locked one.
Bit DQ7 is the most significan t bit in the Extended Memory Block Verify Indicator and a
specific procedure must be followed to read it. See Verify Extend ed Memory Block
Protection Indicator in Table 4: Block Protection, 8-bit mode and Table 7: Block Protection,
16-bit mode, for details of how to read bit DQ7.
The Extended Memory Block can onl y be accessed when the de vice is in Extended Memory
Block mode. For details of how the Extende d Block mode is entered and exited, refer to the
Section 5.3.1: Enter Extended Memory Block command and Section 5.3.2: Exit Extended
Block command, and to Table 13 an d Table 9.
C.1 Factory Locked Extended Memory Block
In devices where the Extended Memory Block is factory locked, the Security Identification
Number is written to the Extended Memory Block address space (see Table 35: Extended
Memory Block Address and Data) in the factory. The DQ7 bit is set to ‘1’ and the Extended
Memory Block cannot be unprotected.
Extended Memory Block M29W128FH, M29W128FL
68/78
C.2 Customer Lockable Extended Memory Block
A device where the Extended Memory Block is customer lo ckable is delivered with the DQ7 bit set t o ‘0’
and the Extended Memory Block unprotected. It is up to the customer to pr ogram and protect the
Extended Memory Block but care must be taken because the pr otection of the Extended Memory Block
is not reversible.
There are two ways of protecting the Extended Memory Block:
●Issue the Enter Ext ended Bloc k command to place the de vice in Extended Bloc k mode, then use th e
In-System Technique with RP either at VIH or at VID (refer to Appendix D: High Voltage Block
Protection, and to the correspon ding f l owcharts , Figure 20 and Figure 21, for a detailed explanation
of the technique).
●Issue the Enter Ext ended Bloc k command to place the de vice in Extended Bloc k mode, then use th e
Programmer Techniqu e (r efer to Appendix D: High Voltage Block Protection, and to the
corresponding flowcharts, Figure 18 and Figure 19, for a detailed explanation of the technique).
Once the Extended Memory Block is programmed and protected, th e Exit Extended Block command
must be issued to exit the Extended Memory Block mode and return the device to Read mode.
Tab le 35. Extended Memory Block Address and Data
Address(1) Data
x8 x16 Factory Locked Customer Lockable
000000h-0000FFh 000000h-00007Fh Security Identification Number Determined by Customer
1. See Table 28: Block Addresses and Protection Groups.
M29W128FH, M29W128FL High Voltage Block Protection
69/78
Appendix D High Voltage Block Protection
The High Voltag e Bloc k Pro tectio n can be used t o prevent an y o per ation f rom modif ying the
data stored in the memory. The blocks are prot ected in groups, refer to Appendix A: Block
addresses and Re ad /M o dify Prot ect i on Grou ps, and Table 28 for details of the Protection
Groups. Once protecte d, Program and Erase oper ations within the protected group fail to
change the data.
There are three techniques that can be used to control Block Protection, these are the
Programmer technique, the In-System technique and Temporary Unprotection. Temporary
Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is
descr ibe d in th e S ign al De scriptions section.
To protect the Extended Memory Block issue the Enter Extended Block command and then
use either the Pro grammer or In-System tech nique. Once prot ected issue the Exit Extended
Block command to return to read mode. The Extended Memory Block protection is
irreversible, once protected the protection cannot be undone.
D.1 Programmer technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These
cannot be achieved using a stand ard microprocessor bus, therefore the technique is
recommended only for use in Programming Equipment.
To protect a group of b locks f ollow the flowchart in Figure 18: Programme r equipment Group
Protect flo wchart. To unprotect the whole chip it is necessary to protect all of the groups first,
then all grou ps can be unprotected at the same time . To unprotect the chip follow Figure 19:
Programmer equipment Ch ip Unprotect flowchart. Table 36: Programmer technique Bus
operations, 8-bit or 16-bit mode, gives a summary of each operation.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not abort the procedure before
reaching the end. Chip Unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.
High Voltage Block Protection M29W128FH, M29W128FL
70/78
D.2 In-System technique
The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP
(1). This can be achieved without violating the maximum ratings of the components on the
microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the
system.
To protect a group of blocks follow the flowchart in Figure 20: In-System equipment Group Protect
flowchart. To unprotect the whole chip it is necessary to protect all of the gr oups first, then all the groups
can be unprotected at the same time. To unprotect the chip follow Fi gure 21: In-System equipment Chip
Unprotect flowchart.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a pau se is
specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that
will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take
several seconds and a user message should be provided to show that the operation is progressing.
Note: RP can be either at VIH or at VID when using the In-System Technique to prote ct the
Extended Memory Block.
Table 36. Programmer technique Bus operations, 8-bit or 16-bit mode
Operation E G W Address Inputs
A0-A22 Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Block (Group) Protect(1) VIL VID VIL Pulse A9 = VID, A12-A22 Block Address
Others = X X
Chip Unprotect VID VID VIL Pulse A6 = VIH, A9 = VID, A12 = VIH,
A15 = VIH Others = X X
Block (Group) Protect
Verify VIL VIL VIH
A0, A2, A3, A6 = VIL, A1 = VIH
A9 = VID, A12-A22= Block Address
Others = X
Pass = xx01h
Retr y = xx00h.
Block (Group) Unprotect
Verify VIL VIL VIH
A0, A2, A3 = VIL
A1, A6 = VIH
A9 = VID, A12-A22 = Block Address
Others = X
Pass = xx00h
Retr y = xx01h.
1. Block Protection Groups are shown in Appendix D, Table 28.
M29W128FH, M29W128FL Flowcharts
71/78
Appendix E Flowcharts
Figure 18. Programmer equipment Group Protect flowchart
1. Block Protection Groups are shown in Appendix D: High Voltage Block Protection, Table 28.
ADDRESS =
GROUP ADDRESS
AI07756b
G, A9 = VID,
E = VIL
n = 0
Wait 4µs
Wait 100µs
W = VIL
W = VIH
E, G = VIH, A1 = VIH
A0, A2 to A7 = VIL
A9 = VIH
E, G = VIH
++n
= 25
START
FAILPASS
YES
NO
DATA = 01h
YES
NO
W = VIH
E = VIL
Wait 4µs
G = VIL
Wait 60ns
Read DATA
Verify Protect Set-upEnd
A9 = VIH
E, G = VIH
Flowcharts M29W128FH, M29W128FL
72/78
Figure 19. Programmer equipment Chip Unprotect flowchart
1. Block Protection Groups are shown in Appendix D: High Voltage Block Protection, Table 28.
PROTECT ALL
GROUPS
AI07757b
A6, A12, A15 = VIH(1)
E, G, A9 = VID
DATA = 00h
W = VIH
E, G = VIH
ADDRESS = CURRENT
GROUP ADDRESS
A0, A2, A3, A4, A5, A7 = VIL
A1, A6 = VIH
Wait 10ms
INCREMENT
CURRENT GROUP
n = 0
CURRENT GROUP = 0
Wait 4µs
W = VIL
++n
= 1000
START
YES
YESNO
NO LAST
GROUP
YES
NO
E = VIL
Wait 4µs
G = VIL
Wait 60ns
Read DATA
FAIL PASS
Verify Unprotect Set-upEnd
A9 = VIH
E, G = VIH A9 = VIH
E, G = VIH
M29W128FH, M29W128FL Flowcharts
73/78
Figure 20. In-System equipment Grou p Protect flowchart
1. Block Protection Groups are shown in Appendix D: High Voltage Block Protection, Table 28.
2. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Memory Block.
AI07758b
WRITE 60h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
n = 0
Wait 100µs
WRITE 40h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
RP = VIH ++n
= 25
START
PASS
YES
NO
DATA = 01h
YES
NO
RP = VIH
Wait 4µs
Verify Protect Set-upEnd
READ DATA
ADDRESS = GROUP ADDRESS
A1 = VIH, A0, A2 to A7 = VIL
RP = VID
ISSUE READ/RESET
COMMAND
WRITE 60h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
ISSUE READ/RESET
COMMAND
FAIL
Flowcharts M29W128FH, M29W128FL
74/78
Figure 21. In-System equipment Chip Unprotect flowchart
1. Block Protection Groups are shown in Appendix D: High Voltage Block Protection, Table 28.
AI07759d
WRITE 60h
ANY ADDRESS WITH
A0, A2, A3, A4, A5, A7 = VIL
A1, A6 = VIH
n = 0
CURRENT GROUP = 0
Wait 10ms
WRITE 40h
ADDRESS =
CURRENT GROUP ADDRESS
A1 = VIH, A0, A2 to A7 = VIL
RP = VIH
++n
= 1000
START
FAIL PASS
NO
DATA = 00h YESNO
RP = VIH
Wait 4µs
READ DATA
ADDRESS =
CURRENT GROUP ADDRESS
A1 = VIH, A0, A2 to A7 = VIL
RP = VID
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PROTECT ALL GROUPS
INCREMENT
CURRENT GROUP
LAST
GROUP
YES
NO
WRITE 60h
ANY ADDRESS WITH
A1 = VIH, A0, A2 to A7 = VIL
Verify Unprotect Set-upEnd
YES
M29W128FH, M29W128FL Flowcharts
75/78
Figure 22. Write to Buffer and Program flowchart and Pseudo Code
1. n+1 is the number of addresses to be programmed.
Write to Buffer F0h
Command,
Block Address
AI08968b
Start
Write Buffer Data,
Start Address
YES
Abort Write
to Buffer
FAIL OR ABORT(5)
NO
Write n(1),
Block Address
X = 0
Write Next Data,
Program Address Pair
X = X-1
Program Buffer
to Flash Block Address
Read Status Register
(DQ1, DQ5, DQ7) at
Last Loaded Address
YES
DQ7 = Data
NO
Check Status Register
(DQ5, DQ7) at
Last Loaded Address
(3)
NO
YES
Write to a Different
Block Address
Write to Buffer and
Program Aborted(2)
NO DQ5 = 1
YES
NO
DQ1 = 1
YES
YES
DQ7 = Data
(4)
NO
END
First Part of the
Write to Buffer and Program Command
X=n
Flowcharts M29W128FH, M29W128FL
76/78
2. A Write to Buffer and Program Abort and Reset must be issued to return the device in Read mode.
3. When the block address is specified, any address in the selected block address space is acceptable. However when
loading Write Buffer address with data, all addresses must fall within the selected Write Buffer page.
4. DQ7 must be checked since DQ5 and DQ7 may change simultaneously.
5. If this flowchart location is reached because DQ5=’1’, then the Write to Buffer and Program command failed. If this
flowchart location is reached because DQ1=’1’, then the Write to Buffer and Program command aborted. In both cases, the
appropriate reset command must be issued to return the device in Read mode: a Reset command if the operation failed, a
Write to Buffer and Program Abort and Reset command if the operation aborted.
6. See Table 9 and Table 10, for details on Write to Buffer and Program command sequence.
M29W128FH, M29W128FL Revision history
77/78
Revision history
Table 37. Document revision history
Date Version Changes
29-Sep-2005 0.1 First Issue.
02-Dec-2005 1
Document status changed to “Full Datasheet“.
Title updated.
Program Suspend Latency time updated in Table 15: Program, Erase
Times and Program, Erase Endur ance cycles .
07-Mar-2006 2 DQ7 changed to DQ7 for Program, Program During Erase Suspend and
Program Error in Table 16: Status registe r bi ts.
13-Mar-2006 3
Section 5.2.1: Write to Buffer and Program command, and Section 5.2.2:
Write to Buffer and Program Confirm command updated to cover 8-bit
mode. Note 2, Note 3, and Note 4 updated in Table 11: Fast Program
commands, 8-bit mode.
06-Apr-2006 4 Verify Extended Memory Block Protection bit command removed.
25-Oct-2006 5 Table 16: Status register bits updated.
06-Nov-2006 6 DQ7 was replaced by DQ7 for ‘Write to Buffer and Program Abort’ in
Table 16: Status register bits.
M29W128FH, M29W128FL
78/78
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