K4S64323LF-S(D)G/S CMOS SDRAM 2Mx32 Mobile SDRAM 90FBGA (VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V, PASR & TCSR) Revision 1.5 December 2002 Rev. 1.5 Dec 2002 K4S64323LF-S(D)G/S CMOS SDRAM 512K x 32Bit x 4 Banks Mobile SDRAM FEATURES GENERAL DESCRIPTION * * * * Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of * * 2.5V Power Supply. LVCMOS compatible with multiplexed address. Four banks operation. MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). EMRS cycle with address key programs. All inputs are sampled at the positive going edge of the system clock . Burst read single-bit write operation. Special Function Support. * * * * * -. PASR (Partial Array Self Refresh). -. TCSR (Temperature Compensated Self Refresh). DQM for masking. Auto & self refresh. 64ms refresh period (4K cycle). Extended temperature range : (-25C to 85 C). 90balls FBGA( -SXXX -Pb, -DXXX -Pb Free). * * The K4S64323LF is 67,108,864 bits synchronous high data rate system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. ORDERING INFORMATION Part No. Max Freq. K4S64323LF-S(D)G/S75 133MHz(CL=3)*1 105MHz(CL=2) K4S64323LF-S(D)G/S1H 105MHz(CL=2) K4S64323LF-S(D)G/S1L 105MHz(CL=3)*2 K4S64323LF-S(D)G/S15 66MHz(CL=2/3)*3 Interface Package LVCMOS 90FBGA Pb (Pb Free) -S(D)S ; Super Low Power, Operating Temp : -25C~85C. -S(D)G ; Low Power, Operating Temp : -25 C~85 C. Notes : 1. In case of 55MHz Frequency, CL1 can be supported. 2. In case of 40MHz Frequency, CL1 can be supported. 3. In case of 33MHz Frequency, CL1 can be supported. FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 512K x 32 512K x 32 Output Buffer 512K x 32 Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 512K x 32 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE DQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.5 Dec 2002 K4S64323LF-S(D)G/S CMOS SDRAM 90-Ball FBGA Package Dimension and Pin Configuration < Bottom View*1 > < Top View *2 > E1 9 8 7 6 5 4 3 2 90Ball(6x15) CSP 1 1 2 3 7 8 9 A DQ26 DQ24 V SS VD D DQ23 DQ21 C B DQ28 V DDQ VSSQ V DDQ VSSQ DQ19 D C VSSQ DQ27 DQ25 DQ22 DQ20 V DDQ e A B D D1 E D VSSQ DQ29 DQ30 DQ17 DQ18 V DDQ F E V DDQ DQ31 NC NC DQ16 V SSQ G F V SS DQM3 A3 A2 DQM2 VD D G A4 A5 A6 A10 A0 A1 H A7 A8 NC NC BA1 NC H J K D/2 L M J CLK CKE A9 BA0 CS RAS K DQM1 NC NC CAS WE DQM0 L V DDQ DQ8 V SS VD D DQ7 V SSQ P M VSSQ DQ10 DQ9 DQ6 DQ5 V DDQ R N VSSQ DQ12 DQ14 DQ1 DQ3 V DDQ P DQ11 V DDQ VSSQ V DDQ VSSQ DQ4 R DQ13 DQ15 V SS VD D DQ0 DQ2 N E E/2 *2: Top View A Pin Name Pin Function CLK System Clock CS Chip Select CKE Clock Enable A 0 ~ A10 Address BA0 ~ BA 1 Bank Select Address RAS Row Address Strobe *1: Bottom View CAS Column Address Strobe < Top View*2 > WE Write Enable DQM 0 ~ DQM 3 Data Input/Output Mask A1 Substrate(4Layer) b #A1 Ball Origin Indicator z SAMSUNG Week K4S64323LF-XXXX DQ 0 ~ 31 Data Input/Output V DD /V SS Power Supply/Ground VDDQ /V SSQ Data Output Power/Ground [Unit:mm] Symbol Min Typ Max A - 1.30 1.40 A1 0.30 0.35 0.40 E - 11.00 - E1 - 6.40 - D - 13.00 - D1 - 11.20 - e - 0.80 - b 0.40 0.45 0.50 z - - 0.10 Rev. 1.5 Dec 2002 K4S64323LF-S(D)G/S CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN , V OUT -1.0 ~ 3.6 V Voltage on V DD supply relative to Vss V D D, VDDQ -1.0 ~ 3.6 V TSTG -55 ~ +150 C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Notes : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25C to 85 C) Parameter Symbol Min Typ Max Unit VD D 2.3 2.5 2.7 V V DDQ 1.65 - 2.7 V Input logic high voltage VI H 0.8 x V DDQ - V DDQ + 0.3 V 1 Input logic low voltage VIL -0.3 0 0.3 V 2 Output logic high voltage VO H VDDQ-0.2V - - V IO H = -0.1mA Output logic low voltage V OL - - 0.2 V I OL = 0.1mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. VIH (max) = 3.0V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V V IN VDDQ . Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 4. Dout is disabled, 0V V OUT V DDQ. CAPACITANCE (VDD = 2.5V, TA = 23C, f = 1MHz, V REF =0.9V 50 mV) Pin Symbol Min Max Unit CCLK - 4.0 pF CIN - 4.0 pF Address(A0 ~ A10, BA 0 ~ BA 1 ) CADD - 4.0 pF D Q0 ~ DQ31 COUT - 6.0 pF Clock RAS, CAS, WE, CS, CKE, DQM0 ~ DQM3 Note Rev. 1.5 Dec 2002 K4S64323LF-S(D)G/S CMOS SDRAM DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25C to 85C) Parameter Symbol Operating Current (One Bank Active) Precharge Standby Current in power-down mode IC C 1 IC C 2P Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) Burst length = 1 tRC t R C(min) IO = 0 mA -75 -1H -1L -15 70 70 65 60 CKE V IL (max), tCC = 10ns 0.5 ICC2 PS CKE & CLK V IL (max), tCC = ICC2 N Precharge Standby Current in non power-down mode Version Test Condition CKE V IH (min), CS V IH (min), tCC = 10ns Input signals are changed one time during 20ns IC C 3NS mA 1 mA 10 mA 7 CKE V IL (max), tCC = 10ns 5 ICC3 PS CKE & CLK V IL (max), tCC = ICC3 N Note 0.5 CKE V IH (min), CLK V IL (max), tCC = IC C 2NS Input signals are stable IC C 3P Unit mA 5 CKE V IH (min), CS V IH (min), tCC = 10ns Input signals are changed one time during 20ns 20 mA CKE V IH (min), CLK V IL (max), tCC = Input signals are stable 20 mA Operating Current IC C 4 IO = 0 mA ,Page burst 85 70 70 60 mA 1 Refresh Current IC C 5 tRC tR C(min) 115 110 100 80 mA 2 Max 45C Max 85C C 4 Banks 235 350 2 Banks 210 290 1 Bank 195 270 4 Banks 130 230 2 Banks 105 170 1 Bank 90 150 TCSR Range -S(D)G Self Refresh Current IC C 6 CKE 0.2V -S(D)S uA 3 uA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S64323LF-S(D)G** 4. K4S64323LF-S(D)S** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL =V DDQ /V SSQ). Rev. 1.5 Dec 2002 K4S64323LF-S(D)G/S CMOS SDRAM AC OPERATING TEST CONDITIONS (V DD = 2.5V 0.2V, TA = -25 C to 85 C) Parameter Value Unit 0.9 x V DDQ / 0.2 V 0.5 x VDDQ V tr/tf = 1/1 ns Output timing measurement reference level 0.5 x VDDQ V Output load condition See Fig. 2 AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time VDDQ Vtt=0.5 x VDDQ 500 50 VOH (DC) = V DDQ -0.2V, IO H = -0.1mA Output VOL (DC) = 0.2V, IOL = 0.1mA Output 500 Z0=50 30pF 30pF (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETER(AC operating conditions unless otherwise noted) Parameter Version Symbol - 75 -1H -1L -15 Unit Note Row active to row active delay tRRD (min) 15 19 19 30 ns 1 RAS to CAS delay tRCD (min) 19 19 24 30 ns 1 tRP (min) 19 19 24 30 ns 1 tRAS (min) 45 50 60 60 ns 1 Row precharge time Row active time tRAS (max) Row cycle time t R C(min) Last data in to row precharge tR D L(min) Last data in to Active delay 100 ns 1 2 CLK 2,3 tDAL (min) tRDL + tRP - 3 Last data in to new col. address delay tC D L(min) 1 CLK 2 Last data in to burst stop tBDL (min) 1 CLK 2 Col. address to col. address delay tCCD (min) 1 CLK 4 ea 5 Number of valid output data 65 70 us 84 CAS latency=3 2 CAS latency=2 1 CAS latency=1 - 90 0 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode. 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop. Rev. 1.5 Dec 2002 K4S64323LF-S(D)G/S CMOS SDRAM AC CHARACTERISTICS(AC operating conditions unless otherwise noted) Parameter - 75 Symbol Min CAS latency=3 CLK cycle time CAS latency=2 tC C 9.5 tSAC CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 tO H CAS latency=1 Min -1L Max 9.5 1000 - CAS latency=3 CAS latency=2 Max 7.5 CAS latency=1 CLK to valid output delay -1H 9.5 Min - 15 Max 9.5 1000 - 12 Min Unit Note ns 1 ns 1,2 ns 2 Max 15 1000 25 15 1000 30 5.4 7 7 9 7 7 8 9 - - 20 24 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 - - 2.5 2.5 CLK high pulse width tC H 2.5 3 3 3.5 ns 3 CLK low pulse width tCL 2.5 3 3 3.5 ns 3 Input setup time tSS 2.0 2.5 2.5 3.5 ns 3 Input hold time t SH 1.0 1.5 1.5 2.0 ns 3 CLK to output in Low-Z t SLZ 1 1 1 1 ns 2 CAS latency=3 CLK to output in Hi-Z CAS latency=2 tSHZ CAS latency=1 5.4 7 7 9 7 7 8 9 - - 20 24 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Note : 1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. Rev. 1.5 Dec 2002 K4S64323LF-S(D)G/S CMOS SDRAM SIMPLIFIED TRUTH TABLE (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) COMMAND Register Mode Register Set Auto Refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X H Entry Self Refresh Exit H L H H H X X X X L L H H X V X L H L H X V Bank Active & Row Addr. H Read & Column Address Auto Precharge Disable H Write & Column Address Auto Precharge Disable Precharge X L H L L X H X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X Entry H L H X X X L H H H H X X X L V V V Bank Selection All Banks Clock Suspend or Active Power Down X H Burst Stop Precharge Power Down Mode Exit A9 ~ A 0 L DQM H No Operation Command H H X X Note 1, 2 3 3 H H Auto Precharge Enable A10 /AP L L Auto Precharge Enable BA0,1 H X X X L H H H X 3 X V 3 Row Address L Column Address (A 0 ~ A7) H L Column Address (A 0 ~ A7) H X V L X H 4 4, 5 4 4, 5 6 X X X X X X V X X X 7 Notes : 1. OP Code : Operand Code A 0 ~ A 10 & BA0 ~ BA 1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA 0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If BA 0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A 10 /AP is "High" at row precharge, BA0 and BA 1 are ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2). Rev. 1.5 Dec 2002