1
LT1737
1737fa
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
High Power
Isolated Flyback Controller
The LT
®
1737 is a monolithic switching regulator control-
ler specifically designed for the isolated flyback topology.
It drives the gate of an external MOSFET and is generally
powered from a DC supply voltage. Output voltage feed-
back information may be supplied by a variety of methods
including a third transformer winding, the primary wind-
ing or even direct DC feedback (see Applications Informa-
tion). Its gate drive capability, coupled with a suitable
external MOSFET and other power path components, can
deliver load power up to tens of Watts.
The LT1737 has a number of features not found on other
isolated flyback controller ICs. By utilizing current mode
switching techniques, it provides excellent AC and DC line
regulation. Its unique control circuitry can maintain regu-
lation well into discontinuous mode in most applications.
Optional load compensation circuitry allows for improved
load regulation. An optional undervoltage lockout pin
halts operation when the application input voltage is too
low. An optional external capacitor implements a soft-
start function.
■
Drives External Power MOSFET
■
Supply Voltage Range: 4.5V to 20V
■
Flyback Voltage Limited Only by
External Components
■
Senses Output Voltage Directly from Primary Side
Winding—No Optoisolator Required
■
Switching Frequency from 50kHz to 250kHz
with External Capacitor
■
Moderate Accuracy Regulation Without User Trims
■
Regulation Maintained Well into Discontinuous Mode
■
External I
SENSE
Resistor
■
Optional Load Compensation
■
Optional Undervoltage Lockout
■
Shutdown Feature Reduces I
Q
to 50µA Typ
■
Available in 16-Pin GN and SO Packages
■
Isolated Flyback Switching Regulators
■
Medical Instruments
■
Instrumentation Power Supplies
12V-18V to Isolated 15V Converter
PGND
ISENSE
GATE
VC
FB
R1
0.27Ω
M1
IRFL014
T1
COILTRONICS
CTX150-4
VIN
VCC
UVLO
SGND
1737 TA01
RCMPC
ROCMP
MINENAB
LT1737
ENDLYOSCAP tON
R3
3.01k
1%
C3
0.1µF
•
•
D1
MBRS1100
C2
33µF
+
R4
7.5k
VOUT = 15V
IOUT = 300mA
D2
BAS16
Q1
2N3906
R2
35.7k
1% C1
22µF
150µH 150µH
+
240k
33k
1nF 47pF 75k 150k 100k 4.7k 0.1µF
NOTE: SEE APPLICATIONS
INFORMATION FOR ADDITIONAL
COMPONENT SPECIFICATIONS
TYPICAL APPLICATIO
U
2
LT1737
1737fa
(Note 1)
V
CC
Supply Voltage................................................. 22V
UVLO Pin Voltage .................................................... V
CC
I
SENSE
Pin Voltage .................................................... 2V
FB Pin Current ..................................................... ±2mA
Operating Junction
Temperature Range
LT1737C ............................................... 0°C to 100°C
LT1737I ............................................ –40°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
ORDER PART
NUMBER
LT1737CGN
LT1737CS
LT1737IGN
LT1737IS
T
JMAX
= 125°C, θ
JA
= 110°C/W (GN)
T
JMAX
= 125°C, θ
JA
= 110°C/W (SO)
PACKAGE/ORDER I FOR ATIO
UU
W
ABSOLUTE AXI U RATI GS
WWWU
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SO
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGND
I
SENSE
SFST
R
OCMP
R
CMPC
OSCAP
V
C
FB
GATE
V
CC
t
ON
ENDLY
MINENAB
SGND
UVLO
3V
OUT
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
V
CC(MIN)
Minimum Input Voltage ●4.1 4.5 V
I
CC
Supply Current V
C
= Open ●10 15 mA
Shutdown Current V
UVLO
= 0V, V
C
= Open ●50 150 µA
Feedback Amplifier
V
FB
Feedback Voltage 1.230 1.245 1.260 V
●1.220 1.270 V
I
FB
Feedback Pin Input Current 500 nA
g
m
Feedback Amplifier Transconductance ∆l
C
= ±10µA●400 1000 1800 µmho
I
SRC
, I
SNK
Feedback Amplifier Source or Sink Current ●30 50 80 µA
V
CL
Feedback Amplifier Clamp Voltage 2.5 V
Reference Voltage/Current Line Regulation 4.75V ≤ V
IN
≤ 18V ●0.01 0.05 %/V
Voltage Gain V
C
= 1V to 2V 2000 V/V
Soft-Start Charging Current V
SFST
= 0V 25 40 50 µA
Soft-Start Discharge Current V
SFST
= 1.5V, V
UVLO
= 0V 0.8 1.5 mA
Gate Output
V
GATE
Output High Level I
GATE
= 100mA ●11.5 12.1 V
I
GATE
= 500mA ●11.0 11.8 V
Output Low Level I
GATE
= 100mA ●0.3 0.45 V
I
GATE
= 500mA ●0.6 1.0 V
I
GATE
Output Sink Current in Shutdown, V
UVLO
= 0V V
GATE
= 2V ●1.2 2.5 mA
t
r
Rise Time C
L
= 1000pF 30 ns
t
f
Fall Time C
L
= 1000pF 30 ns
GN PART MARKING
1737
1737I
Consult LTC Marketing for parts specified with wider operating temperature ranges.
3
LT1737
1737fa
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 2: Component value range guaranteed by design.
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Amplifier
V
C
Control Pin Threshold Duty Cycle = Min 0.90 1.12 1.25 V
●0.80 1.35 V
V
ISENSE
Switch Current Limit Duty Cycle ≤ 30% 220 250 270 mV
Duty Cycle ≤ 30% ●200 280 mV
Duty Cycle = 80% 220 mV
∆V
ISENSE
/∆V
C
0.30 mV
Timing
f Switching Frequency C
OSCAP
= 100pF 90 100 115 kHz
●80 125 kHz
C
OSCAP
Oscillator Capacitor Value (Note 2) 33 200 pF
t
ON
Minimum Switch On Time R
tON
= 50k 200 ns
t
ED
Flyback Enable Delay Time R
ENDLY
= 50k 200 ns
t
EN
Minimum Flyback Enable Time R
MENAB
= 50k 200 ns
R
t
Timing Resistor Value (Note 2) 24 240 kΩ
Maximum Switch Duty Cycle ●85 90 %
Load Compensation
Sense Offset Voltage 25mV
Current Gain Factor 0.80 0.95 1.05 mV
UVLO Function
V
UVLO
UVLO Pin Lockout Threshold ●1.21 1.25 1.29 V
UVLO Pin Shutdown Threshold 0.75 V
●0.4 0.95 V
I
UVLO
UVLO Pin Bias Current V
UVLO
= 1.2V –0.25 +0.1 +0.25 µA
V
UVLO
= 1.3V –4.50 –3.5 –2.50 µA
3V Output Function
V
REF
Reference Output Voltage I
LOAD
= 1mA ●2.8 3.0 3.2 V
Output Impedance 10 Ω
Current Limit ●815 mA
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LT1737
1737fa
TEMPERATURE (°C)
–50
SUPPLY CURRENT (mA)
13
12
11
10
9
8
050 75
1737 G04
–25 25 100 125
TEMPERATURE (°C)
–50
1
0
–1
–2
–3
–4
–5
–6
25 75
1737 G05
–25 0 50 100 125
UVLO PIN INPUT CURRENT (µA)
V
UVLO
= 1.3V
V
UVLO
= 1.2V
TEMPERATURE (°C)
–50
OSCILLATOR FREQUENCY (kHz)
115
110
105
100
95
90
85 25 75
1737 G06
–25 0 50 100 125
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50
MINIMUM INPUT VOLTAGE (V)
4.3
4.2
4.1
4.0
3.9
3.8
050 75
1737 G01
–25 25 100 125
TEMPERATURE (°C)
–50
SHUTDOWN VOLTAGE V
UVLO
(V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4 25 75
1737 G03
–25 0 50 100 125
Minimum Input Voltage vs
Temperature Shutdown ICC vs Temperature
Shutdown Voltage (VUVLO) vs
Temperature
Supply Current vs Temperature
UVLO Pin Input Current vs
Temperature
Oscillator Frequency vs
Temperature
I
SINK
(mA)
1
V
GATE
(V)
1.0
0.8
0.6
0.4
0.2
010 100 1000
1737 G07
T
A
= 125°C
T
A
= –55°C
T
A
= 25°C
ISOURCE (mA)
1
VCC-VGATE (V)
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0 10 100 1000
1737 G08
TA = 125°C
TA = –55°C
TA = 25°C
TEMPERATURE (°C)
–50
V
C
CLAMP VOLTAGE, SWITCHING THRESHOLD (V)
3.0
2.5
2.0
1.5
1.0
0.5
025 75
1737 G09
–25 0 50 100 125
CLAMP VOLTAGE
SWITCHING THRESHOLD
VGATE vs ISINK VCC-VGATE vs ISOURCE
VC Clamp Voltage, Switching
Threshold vs Temperature
TEMPERATURE (°C)
–50
SHUTDOWN I
CC
(µA)
125
100
75
50
25
0
050 75
1737 G02
–25 25 100 125
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LT1737
1737fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50
MINIMUM SWITCH ON TIME (ns)
275
250
225
200
175
150
125 25 75
1737 G10
–25 0 50 100 125
R
TON
= 50k
TEMPERATURE (°C)
–50
MINIMUM ENABLE TIME (ns)
275
250
225
200
175
150
125 25 75
1737 G11
–25 0 50 100 125
RMINENAB = 50k
TEMPERATURE (°C)
–50
ENABLE DELAY TIME (ns)
275
250
225
200
175
150
125 25 75
1737 G12
–25 0 50 100 125
Minimum Switch On Time vs
Temperature
Minimum Enable Time vs
Temperature
Enable Delay Time vs
Temperature
FB PIN VOLTAGE (V)
1.05
FEEDBACK AMPLIFIER OUTPUT CURRENT (µA)
1.35
1737 G13
1.15 1.25
80
60
40
20
0
–20
–40
–60
–80 1.10 1.20 1.30 1.40
T
A
= 125°C
T
A
= –55°C
T
A
= 25°C
TEMPERATURE (°C)
–50
1600
1400
1200
1000
800
600
400
200
25 75
1737 G14
–25 0 50 100 125
FEEDBACK AMPLIFIER TRANSCONDUCTANCE (µmho)
TEMPERATURE (°C)
–50
SOFT-START CHARGING CURRENT (µA)
60
50
40
30
20
10
025 75
1737 G15
–25 0 50 100 125
V(SFST) = 0V
TEMPERATURE (°C)
–50
SOFT-START SINK CURRENT (mA)
2.5
2.0
1.5
1.0
0.5
0
050 75
1737 G16
–25 25 100 125
V(SFST) = 1.5V
Feedback Amplifier Output Current
vs FB Pin Voltage
Feedback Amplifier
Transconductance vs Temperature
Soft-Start Charging Current vs
Temperature
Soft-Start Sink Current vs
Temperature
6
LT1737
1737fa
UU
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PI FU CTIO S
PGND (Pin 1): The power ground pin carries the GATE
node discharge current. This is typically a current spike of
several hundred mA with a duration of tens of nanosec-
onds. It should be connected directly to a good quality
ground plane.
I
SENSE
(Pin 2): Pin to measure switch current with external
sense resistor. The sense resistor should be of a nonin-
ductive construction as high speed performance is essen-
tial. Proper grounding technique is also required to avoid
distortion of the high speed current waveform. A preset
internal limit of nominally 250mV at this pin effects a
switch current limit.
SFST (Pin 3): Pin for optional external capacitor to effect
soft-start function. See Applications Information for
details.
R
OCMP
(Pin 4): Input pin for optional external load com-
pensation resistor. Use of this pin allows nominal com-
pensation for nonzero output impedance in the power
transformer secondary circuit, including secondary wind-
ing impedance, output Schottky diode impedance and
output capacitor ESR. In less demanding applications, this
resistor is not needed. See Applications Information for
more details.
R
CMPC
(Pin 5): Pin for external filter capacitor for optional
load compensation function. A common 0.1µF ceramic
capacitor will suffice for most applications. See Applica-
tions Information for further details.
OSCAP (Pin 6): Pin for external timing capacitor to set
oscillator switching frequency. See Applications Informa-
tion for details.
V
C
(pin 7):
This is the control voltage pin which is the
output of the feedback amplifier and the input of the
current comparator. Frequency compensation of the
overall loop is effected in most cases by placing a
capacitor between this node and ground.
FB (Pin 8): Input pin for external “feedback” resistor
divider. The ratio of this divider, times the internal band-
gap (V
BG
) reference, times the effective transformer turns
ratio is the primary determinant of the output voltage. The
Thevenin equivalent resistance of the feedback divider
should be roughly 3k. See Applications Information for
more details.
3V
OUT
(Pin 9): Output pin for nominal 3V reference. This
facilitates various user applications. This node is internally
current limited for protection and is intended to drive
either moderate capacitive loads of several hundred pF or
less, or, very large capacitive loads of 0.1µF or more. See
Applications Information for more details.
UVLO (Pin 10): This is a dual function pin that implements
both undervoltage lockout and shutdown functions. Pull-
ing this pin to near ground effects shutdown and reduces
quiescent current to tens of microamperes.
Additionally, an external resistor divider between V
IN
and
ground may be connected to this pin to implement an
undervoltage lockout function. The bias current on this pin
is a function of the state of the UVLO comparator; as the
threshold is exceeded, the bias current increases. This
creates a hysteresis band equal to the change in bias
current times the Thevenin impedance of the user’s resis-
tive divider. The user may thereby adjust the impedance of
the UVLO divider to achieve a desired degree of hysteresis.
A 100pF capacitor to ground is recommended on this pin.
See Application Information for details.
SGND (Pin 11): The signal ground pin is a clean ground.
The internal reference, oscillator and feedback amplifier
are referred to it. Keep the ground path connection to the
FB pin, OSCAP capacitor and the V
C
compensation capaci-
tor free of large ground currents.
MINENAB (Pin 12): Pin for external programming resistor
to set minimum enable time. See Applications Information
for details.
ENDLY (Pin 13): Pin for external programming resistor to
set enable delay time. See Applications Information for
details.
t
ON
(Pin 14): Pin for external programming resistor to set
switch minimum on time. See Applications Information
for details.
V
CC
(Pin 15): Supply voltage for the LT1737. Bypass this
pin to ground with 1µF or more.
GATE (Pin 16): This is the gate drive to the external power
MOSFET switch and has large dynamic currents flowing
through it. Keep the trace to the MOSFET as short as
possible to minimize electromagnetic radiation and volt-
age spikes. A series resistance of 5Ω or more may help to
dampen ringing in less than ideal layouts.
7
LT1737
1737fa
BLOCK DIAGRA
W
COMP
ENDLY
MINENABtON
IAMP
FDBK
FB
OSCAP
OSC MOSFET
DRIVER
UVLO
VCC
3VOUT
3V REG
(INTERNAL)
BIAS
VC
SOFT-START LOAD
COMPENSATION
ISENSE
GATE
PGND
ROCMP
SFST RCMPC
SGND
1737 BD
LOGIC
8
LT1737
1737fa
TI I G DIAGRA
UWW
FLYBACK ERROR A PLIFIER
W
V
SW
VOLTAGE
V
IN
GND
OFF ON
MINIMUM t
ON
ENABLE DELAY
MINIMUM ENABLE TIME
1737 TD
OFF ON
SWITCH
STATE
FLYBACK AMP
STATE
0.80×
V
FLBK
V
FLBK
COLLAPSE
DETECT
ENABLEDDISABLED DISABLED
+
–
D1
T1
•
•
•
ISOLATED
VOUT
C1
M1
+
VIN
VC
C2
R2
R1 FB
VBG
Q1 Q2
I
IM
IM
IFXD
ENAB
1737 EA
9
LT1737
1737fa
The LT1737 is a current mode switcher controller IC
designed specifically for the isolated flyback topology. The
Block Diagram shows an overall view of the system. Many
of the blocks are similar to those found in traditional
designs, including: Internal Bias Regulator, Oscillator,
Logic, Current Amplifier and Comparator, Driver and Out-
put Switch. The novel sections include a special Flyback
Error Amplifier and a Load Compensation mechanism.
Also, due to the special dynamic requirements of flyback
control, the Logic system contains additional functionality
not found in conventional designs.
The LT1737 operates much the same as traditional current
mode switchers, the major difference being a different
type of error amplifier that derives its feedback informa-
tion from the flyback pulse. Due to space constraints, this
discussion will not reiterate the basics of current mode
switcher/controllers and isolated flyback converters. A
good source of information on these topics is Application
Note AN19.
ERROR AMPLIFIER—PSEUDO DC THEORY
Please refer to the simplified diagram of the Flyback Error
Amplifier. Operation is as follows: when MOSFET output
switch M1 turns off, its drain voltage rises above the V
IN
rail. The amplitude of this flyback pulse as seen on the third
winding is given as:
VV V I ESR
N
FLBK
OUT F SEC
ST
=
++
()
•
V
F
= D1 forward voltage
I
SEC
= transformer secondary current
ESR = total impedance of secondary circuit
N
ST
= transformer effective secondary-to-third
winding turns ratio
The flyback voltage is then scaled by external resistor
divider R1/R2 and presented at the FB pin. This is then
compared to the internal bandgap reference by the differ-
ential transistor pair Q1/Q2. The collector current from Q1
is mirrored around and subtracted from fixed current
source I
FXD
at the V
C
pin. An external capacitor integrates
this net current to provide the control voltage to set the
current mode trip point.
OPERATIO
U
The relatively high gain in the overall loop will then cause
the voltage at the FB pin to be nearly equal to the bandgap
reference V
BG
. The relationship between V
FLBK
and V
BG
may then be expressed as:
VRR
RV
FLBK BG
=
+
()
12
2
Combination with the previous V
FLBK
expression yields an
expression for V
OUT
in terms of the internal reference,
programming resistors, transformer turns ratio and diode
forward voltage drop:
VV
RR
RNV I ESR
OUT BG
ST
F SEC
=
+
()
⎛
⎝
⎜⎞
⎠
⎟
12
2
1–– •
Additionally, it includes the effect of nonzero secondary
output impedance, which is discussed in further detail, see
Load Compensation Theory. The practical aspects of
applying this equation for V
OUT
are found in the Applica-
tions Information section.
So far, this has been a pseudo-DC treatment of flyback
error amplifier operation. But the flyback signal is a pulse,
not a DC level. Provision must be made to enable the
flyback amplifier only when the flyback pulse is present.
This is accomplished by the dotted line connections to the
block labeled “ENAB”. Timing signals are then required to
enable and disable the flyback amplifier.
ERROR AMPLIFIER—DYNAMIC THEORY
There are several timing signals that are required for
proper LT1737 operation. Please refer to the Timing
Diagram.
Minimum Output Switch On Time
The LT1737 effects output voltage regulation via flyback
pulse action. If the output switch is not turned on at all,
there will be no flyback pulse and output voltage informa-
tion is no longer available. This would cause irregular loop
response and start-up/latchup problems. The solution cho-
sen is to require the output switch to be on for an absolute
minimum time per each oscillator cycle. This in turn estab-
lishes a minimum load requirement to maintain regula-
tion. See Applications Information for further details.
10
LT1737
1737fa
OPERATIO
U
Enable Delay
When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans-
former primary side voltage waveform approximately rep-
resents the output voltage. This is partly due to finite rise
time on the MOSFET drain node, but more importantly,
due to transformer leakage inductance. The latter causes
a voltage spike on the primary side not directly related to
output voltage. (Some time is also required for internal
settling of the feedback amplifier circuitry.)
In order to maintain immunity to these phenomena, a fixed
delay is introduced between the switch turnoff command
and the enabling of the feedback amplifier. This is termed
enable delay. In certain cases where the leakage spike is
not sufficiently settled by the end of the enable delay
period, regulation error may result. See Application Infor-
mation for further details.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
voltage (FB referred) to a fixed reference, nominally 80%
of VBG. When the flyback waveform drops below this
level, the feedback amplifier is disabled. This action
accommodates both continuous and discontinuous mode
operation.
Minimum Enable Time
The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time.” This prevents lockup, especially when the output
voltage is abnormally low, e.g., during start-up. The mini-
mum enable time period ensures that the V
C
node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
the low load level at which output voltage regulation is lost.
See Applications Information for details.
Effects of Variable Enable Period
It should now be clear that the flyback amplifier is enabled
during only a portion of the cycle time. This can vary from
the fixed “minimum enable time” described to a maximum
of roughly the “off” switch time minus the enable delay
time. Certain parameters of flyback amp behavior will then
be directly affected by the variable enable period. These
include effective transconductance and V
C
node slew rate.
LOAD COMPENSATION THEORY
The LT1737 uses the flyback pulse to obtain information
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,
T1
M1
R3
50k
V
IN
R2 LOAD
COMP I
R1 FB
V
BG
Q1 Q2
I
M
I
M
R
OCMP
R
CMPC
R
SENSE
I
SENSE
1737 F01
Q3
–
+
A1
Figure 1. Load Compensation Diagram
11
LT1737
1737fa
transformer secondary and output capacitor. This has
been represented previously by the expression “I
SEC
•
ESR.” However, it is generally more useful to convert this
expression to an effective output impedance. Because the
secondary current only flows during the off portion of the
duty cycle, the effective output impedance equals the
lumped secondary impedance times the inverse of the OFF
duty cycle. That is:
R ESR DC
OUT
OFF
=⎛
⎝
⎜⎞
⎠
⎟
1
where
R
OUT
= effective supply output impedance
ESR = lumped secondary impedance
DC
OFF
= OFF duty cycle
Expressing this in terms of the ON duty cycle, remember-
ing DC
OFF
= 1 – DC,
R ESR DC
OUT
=⎛
⎝
⎜⎞
⎠
⎟
1
1–
DC = ON duty cycle
In less critical applications, or if output load current
remains relatively constant, this output impedance error
may be judged acceptable and the external FB resistor
divider adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error may be minimized by the use of the load compensa-
tion function.
To implement the load compensation function, a voltage is
developed that is proportional to average output switch
current. This voltage is then impressed across the external
R
OCMP
resistor, and the resulting current acts to decrease
the voltage at the FB pin. As output loading increases,
average switch current increases to maintain rough output
voltage regulation. This causes an increase in R
OCMP
resistor current which effects a corresponding increase in
flyback voltage amplitude.
Assuming a relatively fixed power supply efficiency, Eff,
Power Out = Eff • Power In
V
OUT
• I
OUT
= Eff • V
IN
• I
IN
Average primary side current may be expressed in terms
of output current as follows:
OPERATIO
U
IV
V Eff I
IN OUT
IN
OUT
=⎛
⎝
⎜⎞
⎠
⎟
••
combining the efficiency and voltage terms in a single
variable:
I
IN
= K1 • I
OUT
, where
KV
V Eff
OUT
IN
1=⎛
⎝
⎜⎞
⎠
⎟
•
Switch current is converted to voltage by the external
sense resistor and averaged/lowpass filtered by R3 and
the external capacitor on R
CMPC
. This voltage is then
impressed across the external R
OCMP
resistor by op amp
A1 and transistor Q3. This produces a current at the
collector of Q3 which is then mirrored around and then
subtracted from the FB node. This action effectively in-
creases the voltage required at the top of the R1/R2
feedback divider to achieve equilibrium. So the effective
change in V
OUT
target is:
∆=∆
()
⎛
⎝
⎜⎞
⎠
⎟
∆
∆=⎛
⎝
⎜⎞
⎠
⎟
VKI
R
RRRor
V
IKR
RRR
OUT OUT SENSE
OCMP
OUT
OUT
SENSE
OCMP
112
112
••(||)
•( || )
Nominal output impedance cancellation is obtained by
equating this expression with R
OUT
:
RK
R
RR R and
RK
R
RR R where
OUT SENSE
OCMP
OCMP SENSE
OUT
=⎛
⎝
⎜⎞
⎠
⎟
=⎛
⎝
⎜⎞
⎠
⎟
112
112
•( || )
•( || )
K1 = dimensionless variable related to V
IN
, V
OUT
and
efficiency as above
R
SENSE
= external sense resistor
R
OUT
= uncompensated output impedance
(R1||R2) = impedance of R1 and R2 in parallel
The practical aspects of applying this equation to deter-
mine an appropriate value for the R
OCMP
resistor are found
in the Applications Information section.
12
LT1737
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APPLICATIO S I FOR ATIO
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TRANSFORMER DESIGN CONSIDERATIONS
Transformer specification and design is perhaps the most
critical part of applying the LT1737 successfully. In addi-
tion to the usual list of caveats dealing with high frequency
isolated power supply transformer design, the following
information should prove useful.
Turns Ratios
Note that due to the use of the external feedback resistor
divider ratio to set output voltage, the user has relative
freedom in selecting transformer turns ratio to suit a given
application. In other words, “screwball” turns ratios like
“1.736:1.0” can scrupulously be avoided! In contrast,
simpler ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can
be employed which yield more freedom in setting total
turns and mutual inductance. Turns ratio can then be
chosen on the basis of desired duty cycle. However,
remember that the input supply voltage plus the second-
ary-to-primary referred version of the flyback pulse (in-
cluding leakage spike) must not exceed the allowed external
MOSFET breakdown rating.
Leakage Inductance
Transformer leakage inductance (on either the primary or
secondary) causes a spike after output switch turnoff. This
is increasingly prominent at higher load currents, where
more stored energy must be dissipated. In many cases a
“snubber” circuit will be required to avoid overvoltage
breakdown at the output switch node. Application Note
AN19 is a good reference on snubber design.
In situations where the flyback pulse extends beyond the
enable delay time, the output voltage regulation will be
affected to some degree. It is important to realize that the
feedback system has a deliberately limited input range,
roughly ±50mV referred to the FB node, and this works to
the user’s advantage in rejecting large, i.e., higher voltage,
leakage spikes. In other words, once a leakage spike is
several volts in amplitude, a further increase in amplitude
has little effect on the feedback system. So the user is
generally advised to arrange the snubber circuit to clamp
at as high a voltage as comfortably possible, observing
MOSFET breakdown, such that leakage spike duration is
as short as possible.
As a rough guide, total leakage inductances of several
percent (of mutual inductance) or less may require a
snubber, but exhibit little to no regulation error due to
leakage spike behavior. Inductances from several percent
up to perhaps ten percent cause increasing regulation
error.
Severe leakage inductances in the double digit percentage
range should be avoided if at all possible as there is a
potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leak-
age spike becomes such a large portion of the flyback
waveform that the processing circuitry is fooled into
thinking that the leakage spike itself is the real flyback
signal! It then reverts to a potentially stable state whereby
the top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This will typically reduce the output volt-
age abruptly to a fraction, perhaps between one-third to
two-thirds of its correct value. If load current is reduced
sufficiently, the system will snap back to normal opera-
tion. When using transformers with considerable leakage
inductance, it is important to exercise this worst-case
check for potential bistability:
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This will usually be
evident by simultaneously monitoring the V
SW
waveform
on an oscilloscope to observe leakage spike behavior
firsthand. A final note—the susceptibility of the system to
bistable behavior is somewhat a function of the load I/V
characteristics. A load with resistive, i.e., I = V/R behavior
is the most susceptible to bistability. Loads which exhibit
“CMOSsy”, i.e., I = V
2
/R behavior are less susceptible.
Secondary Leakage Inductance
In addition to the previously described effects of leakage
inductance in general, leakage inductance on the second-
ary in particular exhibits an additional phenomenon. It
forms an inductive divider on the transformer secondary,
13
LT1737
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APPLICATIO S I FOR ATIO
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which reduces the size of the primary-referred flyback
pulse used for feedback. This will increase the output
voltage target by a similar percentage. Note that unlike
leakage
spike
behavior, this phenomena is load indepen-
dent. To the extent that the secondary leakage inductance
is a constant percentage of mutual inductance (over
manufacturing variations), this can be accommodated by
adjusting the feedback resistor divider ratio.
Winding Resistance Effects
Resistance in either the primary or secondary will act to
reduce overall efficiency (P
OUT
/P
IN
). Resistance in the
secondary increases effective output impedance which
degrades load regulation, (at least before load compensa-
tion is employed).
Bifilar Winding
A bifilar or similar winding technique is a good way to
minimize troublesome leakage inductances. However, re-
member that this will increase primary-to-secondary ca-
pacitance and limit the primary-to-secondary breakdown
voltage, so bifilar winding is not always practical.
Finally, the LTC Applications group is available to assist
in the choice and/or design of the transformer. Happy
Winding!
SELECTING FEEDBACK RESISTOR DIVIDER VALUES
The expression for V
OUT
developed in the Operation sec-
tion can be rearranged to yield the following expression for
the R1/R2 ratio:
RR
R
V V I ESR
VN
OUT F SEC
BG
ST
12
2
+
()
=
++
()
•
where:
V
OUT
= desired output voltage
V
F
= switching diode forward voltage
I
SEC
• ESR = secondary resistive losses
V
BG
= data sheet reference voltage value
N
ST
= effective secondary-to-third winding turns ratio
The above equation defines only the ratio of R1 to R2, not
their individual values. However, a “second equation for
two unknowns” is obtained from noting that the Thevenin
impedance of the resistor divider should be roughly 3k for
bias current cancellation and other reasons.
SELECTING R
OCMP
RESISTOR VALUE
The Operation section previously derived the following
expressions for R
OUT
, i.e., effective output impedance and
R
OCMP
, the external resistor value required for its nominal
compensation:
R ESR DC
RK
R
RRR
OUT
OCMP SENSE
OUT
=⎛
⎝
⎜⎞
⎠
⎟
=⎛
⎝
⎜⎞
⎠
⎟
()
1
1
112
–
||
While the value for R
OCMP
may therefore be theoretically
determined, it is usually better in practice to employ
empirical methods. This is because several of the required
input variables are difficult to estimate precisely. For
instance, the ESR term above includes that of the trans-
former secondary, but its effective ESR value depends on
high frequency behavior, not simply DC winding resis-
tance. Similarly, K1 appears to be a simple ratio of V
IN
to
V
OUT
times (differential) efficiency, but theoretically esti-
mating efficiency is not a simple calculation. The sug-
gested empirical method is as follows:
Build a prototype of the desired supply using the eventual
secondary components. Temporarily ground the R
CMPC
pin to disable the load compensation function. Operate the
supply over the expected range of output current loading
while measuring the output voltage deviation. Approxi-
mate this variation as a single value of R
OUT
(straight line
approximation). Calculate a value for the K1 constant
based on V
IN
, V
OUT
and the measured (differential) effi-
ciency. These are then combined with R
SENSE
as indicated
to yield a value for R
OCMP
.
Verify this result by connecting a resistor of roughly this
value from the R
OCMP
pin to ground. (Disconnect the
ground short to R
CMPC
and connect the requisite 0.1µF
filter capacitor to ground.) Measure the output impedance
with the new compensation in place. Modify the original
R
OCMP
value if necessary to increase or decrease the
effective compensation.
14
LT1737
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SELECTING OSCILLATOR CAPACITOR VALUE
The switching frequency of the LT1737 is set by an
external capacitor connected between the OSCAP pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 2 shows the nominal relationship between
external capacitance and switching frequency. To mini-
mize stray capacitance and potential noise pickup, this
capacitor should be placed as close as possible to the IC
and the OSCAP node length/area minimized.
APPLICATIO S I FOR ATIO
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indicative of actual current level in the transformer pri-
mary, and may cause irregular current mode switching
action, especially at light load.
However, the user must remember that the LT1737 does
not “skip cycles” at light loads. Therefore, minimum on
time will set a limit on minimum delivered power and con-
sequently a minimum load requirement to maintain regu-
lation (see Minimum Load Considerations). Similarly,
minimum on time has a direct effect on short-circuit be-
havior (see Maximum Load/Short-Circuit Considerations).
The user is normally tempted to set the minimum on time
to be short to minimize these load related consequences.
(After all, a smaller minimum on time approaches the ideal
case of zero, or no minimum.) However, a longer time may
be required in certain applications based on MOSFET
switching current spike considerations.
Enable Delay Time
This function provides a programmed delay between
turnoff of the gate drive node and the subsequent enabling
of the feedback amplifier. At high loads, a primary side
voltage spike after MOSFET turnoff may be observed due
to transformer leakage inductance. This spike is not in-
dicative of actual output voltage (see Figure 4B). Delaying
the enabling of the feedback amplifier allows this system
to effectively ignore most or all of the voltage spike and
maintain proper output voltage regulation. The enable
delay time should therefore be set to the maximum ex-
pected duration of the leakage spike. This may have
COSCAP (pF)
30
50
fOSC (Hz)
100
300
100 200
1737 F02
Figure 2. fOSC vs OSCAP Value
SELECTING TIMING RESISTOR VALUES
There are three internal “one-shot” times that are pro-
grammed by external application resistors: minimum on
time, enable delay time and minimum enable time. These
are all part of the isolated flyback control technique, and
their functions have been previously outlined in the Opera-
tion section. Figure 3 shows nominal observed time ver-
sus external resistor value for these functions.
The following information should help in selecting and/or
optimizing these timing values.
Minimum On Time
This time defines a period whereby the normal switch
current limit is ignored. This feature provides immunity to
the leading edge current spike often seen at the source
node of the external power MOSFET, due to rapid charging
of its gate/source capacitance. This current spike is not
R
T
(kΩ)
20
100
500
TIME (ns)
1000
100 250
1737 F03
Figure 3. “One Shot” Times vs Programming Resistor
15
LT1737
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implications regarding output voltage regulation at mini-
mum load (see Minimum Load Considerations).
A second benefit of the enable delay time function occurs
at light load. Under such conditions the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage (see Figure 4C). So
the enable delay time should also be set long enough to
ignore the “irrelevant” portion of the flyback waveform at
light load.
Additionally, there are cases wherein the gate output is
called upon to drive a large geometry MOSFET such that
the turnoff transition is slowed significantly. Under such
circumstances, the enable delay time may be increased to
accommodate for the lengthy transition.
Average “start-up” V
C
current =
MinimumEnable Time
SwitchingFrequency ISRC
•
Minimum enable time can also have implications at light
load (see Minimum Load Considerations). The temptation
is to set the minimum enable time to be fairly short, as this
is the least restrictive in terms of minimum load behavior.
However, to provide a “reliable” minimum start-up current
of say, nominally 1µA, the user should set the minimum
enable time at no less that 2% of the switching period
(= 1/switching frequency).
CURRENT SENSE RESISTOR CONSIDERATIONS
The external current sense resistor allows the user to
optimize the current limit behavior for the particular appli-
cation under consideration. As the current sense resistor
is varied from several ohms down to tens of milliohms,
peak switch current goes from a fraction of an ampere to
tens of amperes. Care must be taken to ensure proper
circuit operation, especially with small current sense
resistor values.
For example, a peak switch current of 10A requires a
sense resistor of 0.025Ω. Note that the instantaneous
peak power in the sense resistor is 2.5W, and it must be
rated accordingly. The LT1737 has only a single sense line
to this resistor. Therefore, any parasitic resistance in the
ground side connection of the sense resistor will increase
its apparent value. In the case of a 0.025Ω sense resistor,
one milliohm
of parasitic resistance will cause a 4%
reduction in peak switch current. So resistance of printed
circuit copper traces and vias cannot necessarily be
ignored.
An additional consideration is parasitic inductance. In-
ductance in series with the current sense resistor will
accentuate the high frequency components of the current
waveform. In particular, the gate switching spike and
multimegahertz ringing at the MOSFET can be
considerably amplified. If severe enough, this can cause
erratic operation. For example, assume 3nH of parasitic
inductance (equivalent to about 0.1 inch of wire in free
space) is in series with an ideal 0.025Ω sense resistor.
A “zero” will be formed at f = R/(2πL), or 1.3MHz. Above
APPLICATIO S I FOR ATIO
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ENABLE DELAY
TIME NEEDED
1737 F04
DISCONTINUOUS
MODE
RINGING
IDEALIZED FLYBACK
WAVEFORM
MOSFET GATE DRIVE
FLYBACK WAVEFORM
WITH LARGE LEAKAGE
SPIKE AT HEAVY LOAD
“SLOW” FLYBACK
WAVEFORM AT
LIGHT LOAD
B
A
C
ENABLE
DELAY
TIME
NEEDED
Figure 4
Minimum Enable Time
This function sets a minimum duration for the expected
flyback pulse. Its primary purpose is to provide a mini-
mum source current at the V
C
node to avoid start-up
problems.
16
LT1737
1737fa
this frequency the sense resistor will behave like an
inductor.
Several techniques can be used to tame this potential
parasitic inductance problem. First, any resistor used for
current sensing purposes must be of an inherently non-
inductive construction. Mounting this resistor directly
above an unbroken ground plane and minimizing its
ground side connection will serve to absolutely minimize
parasitic inductance. In the case of low valued sense
resistors, these may be implemented as a parallel combi-
nation of several resistors for the thermal considerations
cited above. The parallel combination will help to lower the
parasitic inductance. Finally, it may be necessary to place
a “pole” between the current sense resistor and the
LT1737 I
SENSE
pin to undo the action of the inductive zero
(see Figure 5). A value of 51Ω is suggested for the resistor,
while the capacitor is selected empirically for the particular
application and layout. Using good high frequency mea-
surement techniques, the I
SENSE
pin waveform may be
observed directly with an oscilloscope while the capacitor
value is varied.
APPLICATIO S I FOR ATIO
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GATE
PARASITIC
INDUCTANCE
C
COMP
R
SENSE
L
P
1737 F05
51Ω
PGNDSGND
I
SENSE
f = R
SENSE
2πL
P
SENSE RESISTOR ZERO AT:
f = 1
2π(51Ω)C
COMP
COMPENSATING POLE AT:
C
COMP
= L
P
R
SENSE
(51Ω)
FOR CANCELLATION:
Figure 5
SOFT-START FUNCTION
The LT1737 contains an optional soft-start function that is
enabled by connecting an explicit external capacitor be-
tween the SFST pin and ground. Internal circuitry prevents
the control voltage at the V
C
pin from exceeding that on the
SFST pin.
Th
e soft-start function is enagaged whenever V
CC
power
is removed, or as a result of either undervoltage lockout
or thermal (overtemperature) shutdown. The SFST node
is then discharged rapidly to roughly a V
BE
above ground.
(Remember that the V
C
pin control node switching
threshold is deliberately set at a V
BE
plus
several hundred
millivolts.) When this condition is removed, a nominal
40µA current acts to charge up the SFST node towards
roughly 3V. So, for example, a 0.1µF soft-start capacitor
will place a 0.4V/ms limit on the ramp rate at the V
C
node.
UVLO PIN FUNCTION
The UVLO pin effects both undervoltage lockout and
shutdown functions. This is accomplished by using differ-
ent voltage thresholds for the two functions—the shut-
down function is at roughly a V
BE
above ground (0.75V at
25°C, large temperature variation), while the UVLO func-
tion is at nearly a bandgap voltage (1.25V, fairly stable with
temperature). An external resistor divider between the
input supply and ground can then be used to achieve a
user-programmable undervoltage lockout (see Figure 6a).
An additional feature of this pin is that there is a change in
the input bias current at this pin as a function of the state
of the internal UVLO comparator. As the pin is brought
above the UVLO threshold, the bias current sourced by the
part increases. This positive feedback effects a hysteresis
band for reliable switching action. Note that the size of the
hysteresis is proportional to the Thevenin impedance of
the external UVLO resistor divider network, which makes
it user programmable. As a rough rule of thumb, each 4k
or so of impedance generates about 1% of hysteresis.
(This is based on roughly 1.25V for the threshold and 3µA
for the bias current shift.)
Even in good quality ground plane layouts, it is common
for the switching node (MOSFET drain) to couple to the
UVLO pin with a stray capacitance of several
thousandths
of a pF. To ensure proper UVLO action, a 100pF capacitor
is recommended from this pin to ground as shown in
Figure 6b. This will typically reduce the coupled noise to
a few millivolts. The UVLO filter capacitor should not be
made much larger than a few hundred pF, however, as the
hysteresis action will become too slow. In cases where
further filtering is required, e.g., to attenuate high speed
supply ripple, the topology in Figure 6c is recommended.
Resistor R1 has been split into two equal parts. This
provides a node for effecting capacitor filtering of high
speed supply ripple, while leaving the UVLO pin node
impedance relatively unchanged at high frequency.
17
LT1737
1737fa
VIN
UVLO
R1
R2
VIN
UVLO
R1
R2
C1
100pF
VIN
UVLO
R1/2
R1/2
R2
1737 F06
C2
C1
100pF
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Figure 6
FREQUENCY COMPENSATION
Loop frequency compensation is performed by connect-
ing a capacitor from the output of the error amplifier (V
C
pin) to ground. An additional series resistor, often re-
quired in traditional current mode switcher controllers, is
usually not required and can even prove detrimental. The
phase margin improvement traditionally offered by this
extra resistor will usually be already accomplished by the
nonzero secondary circuit impedance, which adds a “zero”
to the loop response.
In further contrast to traditional current mode switchers,
V
C
pin ripple is generally not an issue with the LT1737. The
dynamic nature of the clamped feedback amplifier forms
an effective track/hold type response, whereby the V
C
voltage changes during the flyback pulse, but is then “held”
during the subsequent “switch on” portion of the next
cycle. This action naturally holds the V
C
voltage stable
during the current comparator sense action (current mode
switching).
OUTPUT VOLTAGE ERROR SOURCES
Conventional nonisolated switching power supply ICs
typically have only two substantial sources of output
voltage error: the internal or external resistor divider
network that connects to V
OUT
and the internal IC refer-
ence. The LT1737, which senses the output voltage in both
a dynamic and an isolated manner, exhibits additional
potential error sources to contend with. Some of these
errors are proportional to output voltage, others are fixed
in an absolute millivolt sense. Here is a list of possible
error sources and their effective contribution.
Internal Voltage Reference
The internal bandgap voltage reference is, of course,
imperfect. Its error, both at 25°C and over temperature is
already included in the specifications.
User Programming Resistors
Output voltage is controlled by the user-supplied feedback
resistor divider ratio. To the extent that the resistor ratio
differs from the ideal value, the output voltage will be
proportionally affected. Highest accuracy systems will
demand 1% components.
Schottky Diode Drop
The LT1737 senses the output voltage from the trans-
former primary side during the flyback portion of the
cycle. This sensed voltage therefore includes the forward
drop, VF, of the rectifier (usually a Schottky diode). The
nominal VF of this diode should therefore be included in
feedback resistor divider calculations. Lot to lot and
ambient temperature variations will show up as output
voltage shift/drift.
Secondary Leakage Inductance
Leakage inductance on the transformer secondary re-
duces the effective secondary-to-third winding turns ratio
(N
S
/N
T
) from its ideal value. This will increase the output
voltage target by a similar percentage. To the extent that
secondary leakage inductance is constant from part to
part, this can be accommodated by adjusting the feedback
resistor ratio.
(6c) Recommended Topology to
Filter High Frequency Ripple
(6b) Filter Capacitor
Directly on UVLO Note
(6a) “Standard” UVLO
Divider Topology
18
LT1737
1737fa
Output Impedance Error
An additional error source is caused by transformer sec-
ondary current flow through the real life nonzero imped-
ances of the output rectifier, transformer secondary and
output capacitor. Because the secondary current only
flows during the off portion of the duty cycle, the effective
output impedance equals the “DC” lumped secondary
impedance times the inverse of the off duty cycle. If the
output load current remains relatively constant, or, in less
critical applications, the error may be judged acceptable
and the feedback resistor divider ratio adjusted for nomi-
nal expected error. In more demanding applications, out-
put impedance error may be minimized by the use of the
load compensation function (see Load Compensation).
MINIMUM LOAD CONSIDERATIONS
The LT1737 generally provides better low load perfor-
mance than previous generation switcher/controllers uti-
lizing indirect output voltage sensing techniques.
Specifically, it contains circuitry to detect flyback pulse
“collapse,” thereby supporting operation well into discon-
tinuous mode. Nevertheless, there still remain constraints
to ultimate low load operation. These relate to the mini-
mum switch on time and the minimum enable time.
Discontinuous mode operation will be assumed in the
following theoretical derivations.
As outlined in the Operation section, the LT1737 utilizes a
minimum output switch on time, t
ON
. This value can be
combined with expected V
IN
and switching frequency to
yield an expression for minimum delivered power.
Minimum Power f
LVt
VI
PRI
IN ON
OUT OUT
=⎛
⎝
⎜⎞
⎠
⎟
()
=
1
2
2
•
•
This expression then yields a minimum output current
constraint:
If
LV Vt
OUT MIN
PRI OUT
IN ON() ••=⎛
⎝
⎜⎞
⎠
⎟
()
1
2
2
where
f = switching frequency
L
PRI
= transformer primary side inductance
V
IN
= input voltage
V
OUT
= output voltage
t
ON
= output switch minimum on time
An additional constraint has to do with the minimum
enable time. The LT1737 derives its output voltage infor-
mation from the flyback pulse. If the internal minimum
enable time pulse extends beyond the flyback pulse, loss
of regulation will occur. The onset of this condition can be
determined by setting the width of the flyback pulse equal
to the sum of the flyback enable delay, t
ED
, plus the
minimum enable time, t
EN
. Minimum power delivered to
the load is then:
Minimum Power f
LVtt
VI
SEC
OUT EN ED
OUT OUT
=⎛
⎝
⎜⎞
⎠
⎟+
()
[]
=
1
2
2
•
•
Which yields a minimum output constraint:
IfV
Ltt
OUT MIN OUT
SEC
ED EN()
•
=⎛
⎝
⎜⎞
⎠
⎟+
()
1
2
2
where
f = switching frequency
L
SEC
= transformer secondary side inductance
V
OUT
= output voltage
t
ED
= enable delay time
t
EN
= minimum enable time
Note that generally, depending on the particulars of input
and output voltages and transformer inductance, one of
the above constraints will prove more restrictive. In other
words, the minimum load current in a particular applica-
tion will be either “output switch minimum on time”
constrained, or “minimum flyback pulse time” constrained.
(A final note—L
PRI
and L
SEC
refer to transformer induc-
tance as seen from the primary or secondary side respec-
tively. This general treatment allows these expressions to
be used when the transformer turns ratio is nonunity.)
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MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS
The LT1737 is a current mode controller. It uses the V
C
node voltage as an input to a current comparator that turns
off the output switch on a cycle-by-cycle basis as this peak
current is reached. The internal clamp on the V
C
node,
nominally 2.5V, then acts as an output switch peak current
limit.
This 2.5V at the V
C
pin corresponds to a value of 250mV
at the I
SENSE
pin, when the (ON) switch duty cycle is less
than 40%. For a duty cycle above 40%, the internal slope
compensation mechanism lowers the effective I
SENSE
voltage limit. For example, at a duty cycle of 80%, the
nominal I
SENSE
voltage limit is 220mV. This action be-
comes the switch current limit specification. Maximum
available output power is then determined by the switch
current limit, which is somewhat duty cycle dependent
due to internal slope compensation action.
Overcurrent conditions are handled by the same mecha-
nism. The output switch turns on, the peak current is
quickly reached and the switch is turned off. Because the
output switch is only on for a small fraction of the available
period, power dissipation is controlled.
Loss of current limit is possible under certain conditions.
Remember that the LT1737 normally exhibits a minimum
switch on time, irrespective of current trip point. If the duty
cycle exhibited by this minimum on time is greater than the
ratio of secondary winding voltage (referred-to-primary)
divided by input voltage, then peak current will not be
controlled at the nominal value, and will cycle-by-cycle
ratchet up to some higher level. Expressed mathemati-
cally, the requirement to maintain short-circuit control is:
tf
VI R
VN
ON
F SC SEC
IN SP
••
•
<
+
()
where
t
ON
= output switch minimum on time
f = switching frequency
I
SC
= short-circuit output current
V
F
= output diode forward voltage at I
SC
R
SEC
= resistance of transformer secondary
V
IN
= input voltage
N
SP
= secondary-to-primary turns ratio (N
SEC
/N
PRI
)
Trouble is typically only encountered in applications with
a relatively high product of input voltage times secondary-
to-primary turns ratio and/or a relatively long minimum
switch on time. (Additionally, several real world effects such
as transformer leakage inductance, AC winding losses, and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate.)
THERMAL CONSIDERATIONS
Care should be taken to ensure that the worst-case input
voltage condition does not cause excessive die tempera-
tures. The 16-lead SO package is rated at 100°C/W, and
the 16-lead GN at 110°C/W.
Average supply current is simply the sum of quiescent
current given in the specifications section plus gate drive
current. Gate drive current can be computed as:
I
G
= f • Q
G
where
Q
G
= total gate charge
f = switching frequency
(Note: Total gate charge is more complicated than C
GS
• V
G
as it is frequently dominated by Miller effect of the C
GD
.
Furthermore, both capacitances are nonlinear in practice.
Fortunately, most MOSFET data sheets provide figures
and graphs which yield the total gate charge directly per
operating conditions.) Nearly all gate drive power is dissi-
pated in the IC, except for a small amount in the external
gate series resistor, so total IC dissipation may be com-
puted as:
P
D(TOTAL)
= V
CC
(I
Q
+ • f • Q
G
), where
I
Q
= quiescent current (from specifications)
Q
G
= total gate charge
f = switching frequency
V
CC
= LT1737 supply voltage
SWITCH NODE CONSIDERATIONS
For maximum efficiency, gate drive rise and fall times are
made as short as practical. To prevent radiation and high
frequency resonance problems, proper layout of the
components connected to the IC is essential, especially
APPLICATIO S I FOR ATIO
WUUU
20
LT1737
1737fa
APPLICATIO S I FOR ATIO
WUUU
the power paths (primary
and
secondary). B field (mag-
netic) radiation is minimized by keeping MOSFET leads,
output diode and output bypass capacitor leads as short
as possible. E field radiation is kept low by minimizing the
length and area of all similar traces. A ground plane
should always be used under the switcher circuitry to
prevent interplane coupling.
The high speed switching current paths are shown sche-
matically in Figure 7. Minimum lead length in these paths
are essential to ensure clean switching and minimal EMI.
The path containing the input capacitor, transformer pri-
mary and MOSFET, and the path containing the trans-
former secondary, output diode and output capacitor
contain “nanosecond” rise and fall times. Keep these
paths as short as possible.
GATE DRIVE RESISTOR CONSIDERATIONS
The gate drive circuitry internal to the LT1737 has been
designed to have as low an output impedance as practi-
cally possible—only a few ohms. A strong L/C resonance
is potentially presented by the inductance of the path
leading to the gate of the power MOSFET and its overall
gate capacitance. For this reason the path from the GATE
package pin to the physical MOSFET gate should be kept
as short as possible, and good layout/ground plane prac-
tice used to minimize the parasitic inductance.
An explicit series gate drive resistor may be useful in some
applications to damp out this potential L/C resonance
(typically tens of MHz). A minimum value of perhaps
several ohms is suggested, and higher values (typically a
few tens of ohms) will offer increased damping. However,
as this resistor value becomes too large, gate voltage rise
time will increase to unacceptable levels, and efficiency
will suffer due to the sluggish switching action.
Figure 7. High Speed Current Switching Paths
++
PGND
GATE
1737 F07
GATE
DISCHARGE
PATH
GATE
CHARGE
PATH
PRIMARY
POWER
PATH
SECONDARY
POWER
PATH
V
CC
V
CC
V
IN
+
21
LT1737
1737fa
TYPICAL APPLICATIO S
U
BASIC APPLICATION WITH
3-WINDING TRANSFORMER
Figure 8 shows a compact, low power application of the
LT1737. Transformer T1 is an off-the-shelf VERSA-PAC
TM
,
#VP1-0190, produced by Coiltronics. As manufactured, it
consists of six ideally identical independent windings. In
this application, two windings are stacked in series on the
primary side and three are placed in parallel on the
secondary side. This arrangement provides a 2:1 primary-
to-secondary turns ratio while maximizing overall effi-
ciency. The remaining primary side winding provides a
ground-referred version of the flyback voltage waveform
for the purpose of feedback.
The design accepts an input voltage in the range of 8V to
25V and outputs an isolated 5V. To prevent overvoltage on
the LT1737 and the gate of MOSFET M1, an LT1121 low
dropout linear regulator is employed (U2). Resistor di-
vider R11/R12 sets the output of U2 at nominally 8.25V. (A
few hundred millivolts of dropout will therefore be seen at
the very bottom of the input supply range.) The positive
going drive potential at the LT1737 GATE pin is typically 2V
or so below its V
CC
supply pin, so a logic level MOSFET has
been specified for M1.
Capacitor C6 sets the switching frequency at approxi-
mately 200kHz. Optimal load compensation for the
trans
former and secondary circuit components is set by
resistor R8. Resistor R10 provides a guaranteed mini-
mum load of about 20mA to maintain rough output voltage
regulation. The soft-start and UVLO features are unused
as shown.
PGND
ISENSE
GATE
VC
FB
R1
0.2Ω
0.5W
IRC TYPE LR 2010
M1
IRLL014
R2
5.1Ω
5%
1 10
7
3
T1
COILTRONICS
VP1-0190
6
4
2
5
R13
51Ω
5%
VCC
UVLO3VOUT
SGND
1737 F08
RCMPC
ROCMP
MINENAB
LT1737
R7
51k
5%
R6
51k
5%
C6
47pF
50V
NPO
6
8
7
3
910 15
16
2
1
2
8
3
14 13 12 4 5 11 1
ENDLYSFSTOSCAP tON
C5
1nF
25V
X7R R8
4.3k
5%
R9
68Ω
5%
D2
1N5250
D3
MBR0540
R5
51k
5%
R11
24k
5%
C1: SANYO ALUMINUM ELECTROLYTIC (35CV331GX)
C2: SANYO POSCAP (10TPC68M)
C8: SANYO POSCAP (10TPA33M)
D1: MOTOROLA 30V, 3A SCHOTTKY RECTIFIER
D2: 20V, 500mW ZENER DIODE
D3: MOTOROLA 40V, 0.5A SCHOTTKY RECTIFIER
R12
20k
5%
R4
3.92k
1%
R3
12.7k
1%
C3
1µF
25V
Z5U
C1
330µF
35V
VIN
C7
0.1µF
25V
Z5U
C9
1nF
25V
X7R
C4
470pF
50V
X7R
OUT
U2
LT1121
ADJ
INP
GND
•
•
•
•
11
8
•
12
D1
MBRD330
9
•
+
C2
68µF
10V
+
C8
33µF
10V
L1
1µH
OPTIONAL OUTPUT FILTER
+
R10
240Ω
5%
VOUT
5V
500mA
VOUT
5V
500mA
L1: COILCRAFT DO1608C-102 1µH, 0.05Ω INDUCTOR
M1: INT’L RECTIFIER IRLL014 60V, 0.2Ω LOGIC LEVEL N-CH MOSFET
U2: LINEAR TECHNOLOGY MICROPOWER LDO REGULATOR
Figure 8. 8V-25V to Isolated 5V Converter
VERSA-PAC is a trademark of Coiltronics, Inc.
22
LT1737
1737fa
TYPICAL APPLICATIO S
U
Overall power supply efficiency and output regulation
versus input voltage and load current may be seen in
Figures 9 and 10. Available output current is a function of
input voltage, varying from 650mA with 8V input to
1100mA with 25V input.
In cases when the output switching noise is objectionable,
the optional output L/C filter shown may be added. The
oscilloscope photos in Figure 11 show the dramatic reduc-
tion in output voltage ripple with the optional filter.
Note: It is theoretically possible to extend the input voltage
range of this topology higher by raising the breakdown
voltage ratings on Q1, U2 and M1, while adjusting the
transformer windings as necessary. However this ap-
proach is generally undesirable as the relatively fixed
supply current required by the LT1737 generates more
and more wasted heat in linear regulator U2 as input
voltage is increased. The LT1725, a close “cousin” of the
LT1737 is recommended in such instances.
The LT1725 is very similar to the LT1737, but it contains
an integral wide hysteresis undervoltage lockout (UVLO)
circuit that monitors the V
CC
voltage. When used in
conjunction with a 3-winding transformer to provide both
device power and output voltage feedback information,
this allows for a “trickle charge” start-up from an input
voltage of up to hundreds of volts. The LT1725 is thus well
suited to operate from “telecom” input voltages of 48V to
72V, or even offline inputs up to several hundred volts! See
the LT1725 data sheet for further information.
ILOAD (A)
20
50
40
30
90
80
70
60
1737 F09
EFFICIENCY (%)
0.01 1
0.1
VIN = 8V
VIN = 15V
VIN = 25V
I
LOAD
(mA)
0
OUTPUT VOLTAGE (V)
5.00
V
IN
= 8V
1000
1737 F10
4.75 250 500 750 1250
5.25
V
IN
= 15V
V
IN
= 25V
Figure 9. Efficiency vs ILOAD
Figure 10. Output Regulation
50mV/DIV
AC COUPLED
V
IN
= 15V 1µs/DIV 1737 F11a
I
LOAD
= 900mA
20MHz BANDWIDTH LIMITED
Without L/C Filter
50mV/DIV
AC COUPLED
V
IN
= 15V 1µs/DIV 1737 F11b
I
LOAD
= 900mA
20MHz BANDWIDTH LIMITED
With L/C Filter
Figure 11
23
LT1737
1737fa
TYPICAL APPLICATIO S
U
APPLICATION WITH 2-WINDING TRANSFORMER
The previous application example utilized a 3-winding
transformer, the third winding providing only feedback
information. Additional circuitry may be employed to
provide feedback information, thus allowing the trans-
former to be reduced to a 2-winding topology. (The cost
and size savings associated with the transformer often
make this a preferable alternative. Furthermore, a variety
of manufacturers offer off-the-shelf dual wound magnet-
ics which often can be applied as 1:1 transformers.)
Figure 12 shows an LT1737 configured for operation with
a dual wound toroid, the Coiltronics #CTX150-4
OCTA-PAC
TM
. A ground referred version of the flyback
voltage waveform is now provided by components Q1, R2,
R1
0.27Ω
0.5W
IRC TYPE LR 2010
M1
IRFL014
R10
5.1Ω
5%
13
4
T1
COILTRONICS
CTX150-4
V
IN
2
1737 F12
R6
100k
5%
R5
150k
5%
C5
47pF
50V
NPO
6
8
7
3
910 15
R9
33k
5%
R8
240k
5%
16
2
14 13 12 4 5 11 1
C3
1nF
25V
X7R R7
4.7k
5%
R11
100Ω
5%
D4
1N5252
D3
MBRS1100
R4
75k
5%
C1: AVX TPS TANTALUM (TPSE226M035R0300)
C2: AVX TPS TANTALUM (TPSE336M025R0200)
D1, D3: MOTOROLA 100V, 1A SCHOTTKY DIODE
D2: SIGNAL DIODE
D4: 24V, 500mW ZENER DIODE
R3
3.01k
1%
C8
0.1µF
25V
Z5U
C4
0.1µF
25V
Z5U
C6
470pF
50V
X7R
C7
470pF
50V
X7R
•
•
D1
MBRS1100
C2
33µF
25V
+
R13
7.5k
5%
V
OUT
15V
250mA
R12
100Ω
5%
M1: INT’L RECTIFIER 60V, 0.2Ω N-CH MOSFET
D2
BAS16
Q1
2N3906
R2
35.7k
1% C1
22µF
35V
+
PGND
I
SENSE
GATE
V
C
FB
V
CC
UVLO3V
OUT
SGNDR
CMPC
R
OCMP
MINENAB
LT1737
ENDLYSFSTOSCAP t
ON
Figure 12. 12V-18V to Isolated 15V Converter
I
LOAD
(mA)
1
60
EFFICIENCY (%)
70
80
90
10 100 1000
1737 F13
50
40
30
20
V
IN
= 12V
V
IN
= 15V V
IN
= 18V
Figure 13. Efficiency vs ILOAD
ILOAD (mA)
0
OUTPUT VOLTAGE (V)
15.0
VIN = 12V
1737 F14
14.5 100 200 300
15.5
VIN = 15V
VIN = 18V
Figure 14. Load Regulation
OCTA-PAC is a trademark of Coiltronics, Inc.
24
LT1737
1737fa
TYPICAL APPLICATIO S
U
R3 and D2. (Diode D2 prevents reverse emitter/base
breakdown in Q1 when MOSFET M1 is in the “ON” state.)
The raw flyback voltage at the drain of MOSFET M1 minus
the V
BE
of Q1 is converted to a current by R2 and then back
to a voltage at R3. Or, stated mathematically:
VV V
R
R
FB FLBK BE
=
()
⎛
⎝
⎜⎞
⎠
⎟
–3
2
Resistor R13 provides an initial pre-load to the supply
output to improve light load regulation. Resistor divider
R8/R9 sets the undervoltage lockout threshold at nomi-
nally 10.4V for turn-on, with turn-off about 600mV lower.
Overall power supply efficiency and output regulation
versus input voltage and load current may be seen in
Figures 13 and 14.
5V
IN
APPLICATION
The LT1737 is a bipolar technology IC specified to operate
down to a minimum input supply voltage of 4.5V. Although
its GATE pin drives “low” nearly to ground, its “high”
capability is limited by a headroom requirement of roughly
2V
BE
s. Thus when operating at a worst case 4.5V supply,
the GATE output will only drive up to a nominal 3V or so.
Fortunately, MOSFETs are now available with specified
performance at this level of gate voltage.
The circuit shown in Figure 15 provides an isolated 5V
output from an input between 4.5V and 5.5V. Two Si9804
low gate voltage MOSFETs are paralleled to handle the
primary-side current—up to 12A peak. This circuit pro-
vides more output power than the previous examples. It
PGND
ISENSE
GATE
VC
FB
R1
0.02Ω
M1
SI9804
10 4
9
T1
COILTRONICS
VP5-0083
VIN
3
VCC
UVLO3VOUT
SGND
1737 F15
RCMPC
ROCMP
MINENAB
LT1737
R6
51k
5%
R5
51k
5%
C5
47pF
50V
NPO
6
8
7
3
910 15
16
2
14 13 12 4 5 11 1
ENDLYSFSTOSCAP tON
C3
1nF
25V
X7R R7
2.2k
5%
R8
10Ω
5%
D4
1N5240
D3
MBR0520
R4
75k
5%
C1A-B, C2A-B: SANYO POSCAP (10TPB220M)
D1: MOTOROLA 35V, 8A SCHOTTKY DIODE
D2: SIGNAL DIODE
D3: MOTOROLA 20V, 0.5A SCHOTTKY DIODE
D4: 10V, 500mW ZENER DIODE
M1, M2: SILICONIX/VISHAY 25V, 0.023Ω N-CH MOSFET
R1: 5 × 0.10Ω, 1W (IRC LR2512)
T1: COILTRONICS TRANSFORMER
R3
3.01k
1%
C8
1µF
25V
Z5U
C4
0.1µF
25V
Z5U
C9
1nF
25V
X7R
R11
51Ω
5%
11
2
12
1
M2
SI9804
C6
4.7nF
50V
X7R
C7
2.2nF
50V
X7R
•••
•5
8
•6
7
•
D1
MBRD835L
C2A
220µF
10V
+
C2B
220µF
10V
+
R10
270Ω
5%
VOUT
5V
3A
R9
15Ω
5%
D2
BAS16
Q1
2N3906
R2
11.0k
1% C1A
220µF
10V
+
C1B
220µF
10V
+
Figure 15. 4.5V-5.5V to Isolated 5V Converter
25
LT1737
1737fa
therefore requires a physically larger transformer. The larg-
est size VERSA-PAC is used, a VP5-0083. Three windings
are paralleled for both the primary and secondary.
Overall power supply efficiency and output regulation ver-
sus load current at the nominal V
IN
= 5V may be seen in
Figures 16 and 17.
TYPICAL APPLICATIO S
U
NONISOLATED APPLICATION
While the LT1737 was designed to serve isolated flyback
applications, it is useful to note that it is also capable of
supporting nonisolated applications. These are performed
by providing a continuous pseudo-DC feedback signal to
the FB pin. (The part behaves as if the flyback waveform
is infinitely long.) Figure 18 demonstrates just such a
system.
A SEPIC topology is shown whereby a 8V to 16V input is
converted to a nonisolated 12V output. A conventional
resistive feedback divider, R3/R4 drives the FB pin. (Ca-
pacitor C7 serves to filter out high frequency ripple in the
output voltage.) A combination of an R/C network (R11/
C5) in parallel with a single capacitor (C9) on the V
C
node
provides the required loop compensation. The load com-
pensation function is unwanted, so the R
OCMP
pin is left
open and the R
CMPC
pin is grounded. An LT1121 low
dropout regulator is programmed to a nominal 8.25V
output by the R12/R13 resistor divider, and this allows the
LT1737 to drive M1, a logic level MOSFET. Minimum on
time programming resistor R5 is set to 33k to minimize the
required output preload. Minimum enable time has no
direct effect on steady state operation, but programming
resistor R7 has been set to 100k for rapid start-up. Enable
delay resistor is similarly set to 24k.
Overall power supply efficiency versus input voltage and
load current may be seen in Figure 19. Because this
application example utilizes a nonisolated topology, load
regulation is not an issue. It is typically 0.2% (25mV) from
no load to full load.
Other nonisolated switching topologies may be similarly
implemented. For example, Boost and NonIsolated Fly-
back readily suggest themselves. (A Nonisolated Flyback
topology also can be used to generate a
negative
output
voltage. In this case, the feedback is a dynamic waveform
derived from the primary side of the transformer, similar
to an isolated LT1737 application.)
0.01
60
EFFICIENCY (%)
70
80
90
0.1 1 10
1737 F16
50
40
30
20
I
LOAD
(A)
Figure 16. Efficiency vs ILOAD
I
LOAD
(A)
0
OUTPUT VOLTAGE (V)
5.00
4
1737 F17
4.75 123
5.25
Figure 17. Load Regulation
26
LT1737
1737fa
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
GN16 (SSOP) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
12
345678
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
16 15 14 13
0.189 – 0.196*
(4.801 – 4.978)
12 11 10 9
0.016 – 0.050
(0.406 – 1.270)
0.015 ± 0.004
(0.38 ± 0.10) × 45°
0° – 8° TYP
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
0.004 – 0.0098
(0.102 – 0.249)
0.0250
(0.635)
BSC
0.009
(0.229)
REF
27
LT1737
1737fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.016 – 0.050
(0.406 – 1.270)
0.010 – 0.020
(0.254 – 0.508)× 45°
0° – 8° TYP
0.008 – 0.010
(0.203 – 0.254)
12345678
0.150 – 0.157**
(3.810 – 3.988)
16 15 14 13
0.386 – 0.394*
(9.804 – 10.008)
0.228 – 0.244
(5.791 – 6.197)
12 11 10 9
S16 1098
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
28
LT1737
1737fa
TYPICAL APPLICATIO S
U
V
C
R1
0.025Ω
M1
IRLZ34S
L1
15µH
R2
2.7Ω
5%
R10
51Ω
5%
1737 F18
R7
100k
5%
R6
24k
5%
C6
47pF
50V
NPO
6
8
7
3
910 15
16
2
1
2
8
3
14 13 12 4 5 11 1
C5
4.7nF
50V
X7R
R5
33k
5%
R11
22k
5%
R12
24k
5%
C1: SANYO OS-CON (20SV150M)
C2A-B: TOKIN Y5V (IE226ZY5U-C505)
C3: SANYO POSCAP (16TPC33M)
D1: MOTOROLA 40V, 6A SCHOTTKY DIODE
R13
20k
5%
R4
3.01k
1%
R3
26.1k
1%
R8
160k
5%
R9
33k
5%
C4
1µF
25V
Z5U
C1
150µF
20V
V
IN
L2
15µH
C10
470pF
50V
X7R
C9
47pF
50V
NPO
C7
47pF
50V
NPO
OUT
U2
LT1121
ADJ
INP
GND
D1
MBRD640CT
+
C3
33µF
16V
×4
C2A
22µF
25V
C2B
22µF
25V
+
R14
750Ω
5%
V
OUT
= 12V
C8
0.1µF
25V
Z5U
L1, L2: COILTRONICS UP4B-150 INDUCTOR
M1: INT’L RECTIFIER IRLZ34S 60V, 0.05Ω LOGIC LEVEL N-CH MOSFET
R1: IRC 4 × 0.1Ω, 1W (LR2512)
PGND
I
SENSE
GATEFB
V
CC
UVLO3V
OUT
SGNDR
CMPC
R
OCMP
MINENAB
LT1737
ENDLYSFSTOSCAP t
ON
Figure 18. 8V-16V to 12V Nonisolated Converter
0.01
60
EFFICIENCY (%)
70
80
90
0.1 1 10
1737 F19
50
40
30
20
ILOAD (A)
VIN = 8V
VIN = 16V
VIN = 12V
Figure 19. Efficiency vs ILOAD
PART NUMBER DESCRIPTION COMMENTS
LT1424-5 Isolated Flyback Switching Regulator V
IN
= 3V to 20V, I
Q
= 7mA
LT1424-9 Isolated Flyback Switching Regulator V
IN
= 3V to 20V, I
Q
= 7mA
LT1425 Isolated Flyback Switching Regulator General Purpose with External Application Resistor
LT1533 Ultralow Noise 1A Switching Regulator V
IN
= 2.7V to 23V, Reduced EMI and Switching Harmonics
LT1725 General Purpose Isolated Flyback Controller Suitable for Telecom or Offline Input Voltage
LT1738 Ultra Low Noise DC/DC Controller Reduced EMI and Switching Harmonics
RELATED PARTS
© LINEAR TECHNOLOGY CORPORATION 2000
LT/LT 0605 REV A • PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
