High Accuracy, Ultralow IQ, 500 mA,
anyCAP® Low Dropout Regulator
ADP3335
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
High accuracy over line and load: ±0.9% @ 25°C,
±1.8% over temperature
Ultralow dropout voltage: 200 mV (typ) @ 500 mA
Requires only CO = 1.0 µF for stability
anyCAP = stable with any type of capacitor
(Including MLCC)
Current and thermal limiting
Low noise
Low shutdown current: < 10 nA (typ)
2.6 V to 12 V supply range
–40°C to +85°C ambient temperature range
APPLICATIONS
PCMCIA cards
Cellular phones
Camcorders, cameras
Networking systems, DSL/cable modems
Cable set-top box
MP3/CD players
DSP supplies
FUNCTIONAL BLOCK DIAGRAM
gm
CC
Q1
IN OUT
NR
R1
BANDGAP
REF
GND
SD
ADP3335
+
–
R1
R2
00147-0-001
THERMAL
PROTECTION
DRIVER
Figure 1.
NR
IN
IN
OUT
OUT
OUT
GND
SD
ADP3335
ON
OFF
V
IN
C
IN
1µF++ V
OUT
00147-0-002
5
3
2
1
4
6
7
8
C
OUT
1µF
Figure 2. Typical Application Circuit
GENERAL DESCRIPTION
The ADP3335 is a member of the ADP333x family of precision,
low dropout, anyCAP voltage regulators. It operates with an
input voltage range of 2.6 V to 12 V, and delivers a continuous
load current up to 500 mA. The ADP3335 stands out from
conventional low dropout regulators (LDOs) by using an
enhanced process enabling it to offer performance advantages
beyond its competition. Its patented design requires only a
1.0 µF output capacitor for stability. This device is insensitive to
output capacitor equivalent series resistance (ESR), and is stable
with any good quality capacitor—including ceramic (MLCC)
types for space-restricted applications. The ADP3335 achieves
exceptional accuracy of ±0.9% at room temperature and ±1.8%
over temperature, line, and load.
The dropout voltage of the ADP3335 is only 200 mV (typical) at
500 mA. This device also includes a safety current limit, thermal
overload protection, and a shutdown feature. In shutdown
mode, the ground current is reduced to less than 1 µA. The
ADP3335 has a low quiescent current of 80 µA (typical) in light
load situations.
ADP3335
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ........................................................................ 9
Application Information................................................................ 10
Output Capacitor Selection....................................................... 10
Input Bypass Capacitor.............................................................. 10
Noise Reduction ......................................................................... 10
Thermal Overload Protection .................................................. 10
Calculating Junction Temperature........................................... 10
Printed Circuit Board Layout Considerations........................ 11
LFCSP Layout Considerations.................................................. 11
Shutdown Mode ......................................................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 13
REVISION HISTORY
1/04 changed from Rev. 0 to Rev. A
Format updated...............................................................Universal
Renumbered figures .......................................................Universal
Removed Figure 22....................................................................... 6
Change to Printed Circuit Board
Layout Considerations section.................................................. 11
Added LFCSP Layout Considerations section........................ 11
Added Package Drawing................................................Universal
Changes to Ordering Guide ...................................................... 16
ADP3335
Rev. A | Page 3 of 16
SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Ambient
temperature of 85°C corresponds to a junction temperature of 125°C under pulsed full-load test conditions. Application stable with no
load. V = 6.0 V, C = C = 1.0 µF, T = –40°C to +85°C, unless otherwise noted.
IN IN OUT A
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT
Voltage Accuracy1VOUT VIN = VOUT(NOM) + 0.4 V to 12 V –0.9 +0.9 %
I
L = 0.1 mA to 500 mA
T
A = 25°C
V
IN = VOUT(NOM) + 0.4 V to 12 V –1.8 +1.8 %
I
L = 0.1 mA to 500 mA
T
A = 85°C
V
IN = VOUT(NOM) + 0.4 V to 12 V –2.3 +2.3 %
I
L = 0.1 mA to 500 mA
T
J = 150°C
Line Regulation1 V
IN = VOUT(NOM) + 0.4 V to 12 V 0.04 mV/V
I
L = 0.1 mA
T
A = 25°C
Load Regulation IL = 0.1 mA to 500 mA 0.04 mV/mA
T
A = 25°C
Dropout Voltage VDROP VOUT = 98% of VOUT(NOM)
I
L = 500 mA 200 370 mV
I
L = 300 mA 140 230 mV
I
L = 50 mA 30 110 mV
I
L = 0.1 mA 10 40 mV
Peak Load Current ILDPK VIN = VOUT(NOM) + 1 V 800 mA
Output Noise VNOISE f = 10 Hz to 100 kHz, CL = 10 µF 47 µV rms
I
L = 500 mA, CNR = 10 nF
f = 10 Hz to 100 kHz, CL = 10 µF 95 µV rms
I
L = 500 mA, CNR = 0 nF
GROUND CURRENT
In Regulation IGND IL = 500 mA 4.5 10 mA
I
L = 300 mA 2.6 6 mA
I
L = 50 mA 0.5 2.5 mA
I
L = 0.1 mA 80 110 µA
In Dropout IGND VIN = VOUT(NOM) – 100 mV 120 400 µA
I
L = 0.1 mA
In Shutdown IGNDSD SD = 0 V, VIN = 12 V 0.01 1 µA
SHUTDOWN
Threshold Voltage VTHSD ON 2.0 V
OFF 0.4 V
SD Input Current ISD 0 ≤ SD ≤ 5 V 1.2 3 µA
Output Current in Shutdown IOSD VIN = 12 V, VOUT = 0 V 0.01 5 µA
1 VIN = 2.6 V to 12 V for models with VOUT(NOM) ≤ 2.2 V.
ADP3335
Rev. A | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Input Supply Voltage –0.3 V to +16 V
Shutdown Input Voltage –0.3 V to +16 V
Power Dissipation Internally Limited
Operating Ambient Temperature Range –40°C to +85°C
Operating Junction Temperature Range –40°C to +150°C
θJA, 2-layer MSOP-8 220°C/W
θJA, 4-layer MSOP-8 158°C/W
θJA, 2-layer LFCSP-8 62°C/W
θJA, 4-layer LFCSP-8 48°C/W
Storage Temperature Range –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADP3335
Rev. A | Page 5 of 16
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
ADP3335
TOP VIEW
(Not to Scale)
OUT
1
OUT
2
OUT
3
GND
4
IN
IN
SD
NR
8
7
6
5
00147-0-022
Figure 3. 8-Lead MSOP
TOP VIEW
(Not to Scale)
ADP3335
OUT
1
OUT
2
OUT
3
GND
4
IN
IN
SD
NR
8
7
6
5
00147-0-025
Figure 4. 8-Lead LFCSP
Table 3. Pin Function Descriptions
Pin No. Mnemonic Function
1, 2, 3 OUT Output of the Regulator. Bypass to ground with a 1.0 µF or larger capacitor. All pins must be connected together
for proper operation.
4 GND Ground Pin.
5 NR Noise Reduction Pin. Used for further reduction of output noise (see the Noise Reduction section for further
details).
6 SD Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this
pin should be connected to the input pin.
7, 8 IN Regulator Input. All pins must be connected together for proper operation.
ADP3335
Rev. A | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted
00147-0-003
V
OUT
= 2.2V
I
L
= 0
150mA
300mA
500mA
2.202
2.201
2.200
2.199
2.198
2.197
2.196
2.195
2.194
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
24681012
Figure 5. Line Regulation Output Voltage vs. Supply Voltage
00147-0-004
V
OUT
= 2.2V
V
IN
= 6V
2.201
2.200
2.199
2.198
2.197
2.196
2.195
2.194
2.193
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
0 100 200 300 400 500
Figure 6. Output Voltage vs. Load Current
00147-0-005
140
120
100
80
60
40
20
0
INPUT VOLTAGE (V)
GROUND CURRENT (µA)
24681012
V
OUT
= 2.2V
I
L
= 0
I
L
= 100µA
0
Figure 7. Ground Current vs. Supply Voltage
00147-0-006
5.0
4.0
3.0
2.0
1.0
0
LOAD CURRENT (mA)
GROUND CURRENT (µA)
0 100 200 300 400 500
Figure 8. Ground Current vs. Load Current
00147-0-007
–0.4
JUNCTION TEMPERATURE (°
C)
OUTPUT CHANGE (%)
–40 45 65 85 105 125
–0.3
–0.2
–0.1
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0
1.0
–15 5 25
500mA
500mA
300mA
0
Figure 9. Output Voltage Variation vs. Junction Temperature
00147-0-008
JUNCTION TEMPERATURE (
°C)
GROUND CURRENT (mA)
–40 45 65 85 105 125
1
2
3
4
5
6
7
0
8
–15 5 25
300mA
50mA
I
L
= 500mA
0
100mA
Figure 10. Ground Current vs. Junction Temperature
ADP3335
Rev. A | Page 7 of 16
00147-0-009
OUTPUT (
mA)
DROPOUT VOLTAGE (mV)
0 400 500
0
50
100
150
200
250
100 200 300
Figure 11. Dropout Voltage vs. Output Current
00147-0-010
TIME (
sec)
INPUT/OUTPUT VOLTAGE (V)
4
0
0.5
1.0
1.5
2.0
2.5
123
3.0
V
OUT
= 2.2V
SD = V
IN
R
L
= 4.4
Ω
Figure 12. Power-Up/Power-Down
00147-0-011
TIME (µs)
V
IN
(V)
400200
0
2
4
0
1
800600
2
V
OUT
= 2.2V
SD = V
IN
R
L
= 4.4Ω
3
C
OUT
= 10µF
C
OUT
= 1µF
V
OUT
(V)
Figure 13. Power-Up Response
00147-0-012
TIME (µs)
V
OUT
(V)
8040
3.000
3.500
2.179
2.189
2.190
180140
2.200
V
OUT
= 2.2V
R
L
= 4.4
Ω
C
L
= 1µF
2.210
V
IN
(V)
Figure 14. Line Transient Response
00147-0-013
TIME (µs)
V
OUT
(V)
8040
3.000
3.500
2.179
2.189
2.190
180140
2.200
V
OUT
= 2.2V
R
L
= 4.4
Ω
C
L
= 10µF
2.210
V
IN
(V)
Figure 15. Line Transient Response
00147-0-014
TIME (µs)
I
LOAD
(mA)
400200
0
200
400
2.1
800600
2.2
V
IN
= 4V
V
OUT
= 2.2Ω
C
L
= 1µF
2.3
V
OUT
(V)
Figure 16. Load Transient Response
ADP3335
Rev. A | Page 8 of 16
00147-0-015
TIME (µs)
I
LOAD
(mA)
400
200
0
200
400
2.1
800600
2.2
V
IN
= 4V
R
L
= 4.4Ω
C
L
= 10µF
2.3
V
OUT
(V)
Figure 17. Load Transient Response
00147-0-016
TIME (µs)
400200
1
2
3
0
800600
0
2.2
V
IN
= 4V
FULL SHORT
800mΩ
SHORT
I
LOAD
(A) V
OUT
(V)
Figure 18. Short-Circuit Current
00147-0-017
TIME (µs)
V
SD
(V)
400200
0
1
2
1
800600
2
3
V
OUT
(V)
V
IN
= 4V
V
OUT
= 2.2V
R
L
= 4.4Ω1µF
10µF10µF
1µF
Figure 19. Turn On/Turn Off Response
00147-0-018
–40
–50
–60
–70
–80
–90
FREQUENCY (Hz)
RIPPLE REJECTION (dB)
10 1k 10k 100k 1M 10M
–20
–30
100
V
OUT
= 2.2V
C
L
= 1µF
I
L
= 50µA
C
L
= 1µF
I
L
= 500mA
C
L
= 10µF
I
L
= 500mA
C
L
= 10µF
I
L
= 50µA
Figure 20. Power Supply Ripple Rejection
00147-0-019
I
L
= 500mA WITH
NOISE REDUCTION
I
L
= 500mA WITHOUT
NOISE REDUCTION
I
L
= 0mA WITHOUT
NOISE REDUCTION
I
L
= 0mA WITH NOISE REDUCTION
C
NR
= 10nF
160
140
120
100
80
60
40
20
0
C
L
(µF)
RMS NOISE (µV)
010 20 30 40 50
Figure 21. RMS Noise versus CL (10 Hz to 100 kHz)
00147-0-020
100
10
1
0.1
0.01
0.001
FREQUENCY (Hz)
VOLTAGE NOISE SPECTRAL
DENSITY (µV/ Hz)
10 1k 10k 100k 1M
100
V
OUT
= 2.2V
I
L
= 1mA
C
L
= 10µF
C
NR
= 10nF C
L
= 1µF
C
NR
= 0nF
C
L
= 10µF
C
NR
= 0nF
C
L
= 1µF
C
NR
= 10nF
Figure 22. Output Noise Density
ADP3335
Rev. A | Page 9 of 16
THEORY OF OPERATION
The ADP3335 uses a single control loop for regulation and
reference functions. The output voltage is sensed by a resistive
voltage divider, R1 and R2, which is varied to provide the
available output voltage option. Feedback is taken from this
network by way of a series diode, D1, and a second resistor
divider, R3 and R4, to the input of an amplifier.
INPUT
00147-0-023
OUTPUT
COMPENSATION
CAPACITOR
R2
R1
GND
ADP3335
PTAT
CURRENT
R4
PTAT
V
OS
g
m
Q1 ATTENUATION
(V
BANDGAP
/V
OUT
)
R3 D1 (a) C
LOAD
R
LOAD
NONINVERTING
WIDEBAND
DRIVER
Figure 23. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium
produces a large, temperature proportional input offset voltage
that is repeatable and very well controlled. The temperature
proportional offset voltage combines with the complementary
diode voltage to form a virtual band gap voltage implicit in the
network, although it never appears explicitly in the circuit.
This patented design makes it possible to control the loop with
only one amplifier. This technique also improves the noise
characteristics of the amplifier by providing more flexibility in
the trade-off of noise sources that leads to a low noise design.
The R1 and R2 divider is chosen in the same ratio as the band
gap voltage to the output voltage. Although the R1 and R2
resistor divider is loaded by the D1 diode and a second
divider—R3 and R4, the values can be chosen to produce a
temperature stable output. This unique arrangement specifically
corrects for the loading of the divider, thus avoiding the error
resulting from base current loading in conventional circuits.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. This special nonin-
verting driver enables the frequency compensation to include
the load capacitor in a pole-splitting arrangement to achieve
reduced sensitivity to the value, type, and ESR of the load
capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor, because they are difficult to
stabilize due to the uncertainty of load capacitance and
resistance. The ESR value required to keep conventional LDOs
stable, moreover, changes depending on load and temperature.
These ESR limitations make designing with LDOs more
difficult because of their unclear specifications and extreme
variations over temperature.
With the ADP3335, ESR limitations are no longer a source of
design constraints. The ADP3335 can be used with virtually any
good quality capacitor and with no constraint on the minimum
ESR. This innovative design allows the circuit to be stable with
just a small 1 µF capacitor on the output. Additional advantages
of the pole-splitting scheme include superior line noise reject-
tion and very high regulator gain, which lead to excellent line
and load regulation. Impressive ±1.8% accuracy is guaranteed
over line, load, and temperature.
Additional features of the circuit include current limit, thermal
shutdown, and noise reduction.
ADP3335
Rev. A | Page 10 of 16
APPLICATION INFORMATION
OUTPUT CAPACITOR SELECTION
As with any micropower device, output transient response is a
function of the output capacitance. The ADP3335 is stable over
a wide range of capacitor values, types, and ESR (anyCAP). A
capacitor as low as 1 µF is all that is needed for stability; larger
capacitors can be used if high output current surges are
anticipated. The ADP3335 is stable with extremely low ESR
capacitors (ESR ≈ 0), such as multilayer ceramic capacitors
(MLCC) or organic semiconductor electrolytic capacitors
(OSCON). Note that the effective capacitance of some capacitor
types may fall below the minimum at extreme temperatures.
Ensure that the capacitor provides more than 1 µF over the
entire temperature range.
INPUT BYPASS CAPACITOR
An input bypass capacitor is not strictly required, but is advi-
sable in any application involving long input wires or high
source impedance. Connecting a 1 µF capacitor from IN to
ground reduces the circuit’s sensitivity to PC board layout. If a
larger value output capacitor is used, then a larger value input
capacitor is also recommended.
NOISE REDUCTION
A noise reduction capacitor (CNR) can be used, as shown in
Figure 24, to further reduce the noise by 6 dB to 10 dB
(Figure 22). Low leakage capacitors in the 100 pF to 1 nF range
provide the best performance. Since the noise reduction pin,
NR, is internally connected to a high impedance node, any con-
nection to this node should be made carefully to avoid noise
pickup from external sources. The pad connected to this pin
should be as small as possible, and long PC board traces are not
recommended.
When adding a noise reduction capacitor, maintain a minimum
load current of 1 mA when not in shutdown.
It is important to note that as CNR increases, the turn-on time
will be delayed. With NR values greater than 1 nF, this delay
may be on the order of several milliseconds.
NR
IN
IN
OUT
OUT
OUT
GND
SD
ADP3335
ON
OFF
V
IN
C
IN
1µF+
+V
OUT
00147-0-021
1
3
4
72
5
6
8
C
OUT
1µF
C
NR
Figure 24. Typical Application Circuit
THERMAL OVERLOAD PROTECTION
The ADP3335 is protected against damage from excessive
power dissipation by its thermal overload protection circuit,
which limits the die temperature to a maximum of 165°C.
Under extreme conditions (i.e., high ambient temperature and
power dissipation) where die temperature starts to rise above
165°C, the output current is reduced until the die temperature
has dropped to a safe level. The output current is restored when
the die temperature is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 150°C.
CALCULATING JUNCTION TEMPERATURE
Device power dissipation is calculated as follows:
(
)
(
)
GND
IN
LOAD
OU
T
IND IVIVVP
+
−
=
Where ILOAD and IGND are load current and ground current, and
VIN and VOUT are input and output voltages, respectively.
Assuming ILOAD = 400 mA, IGND = 4 mA, VIN = 5.0 V, and VOUT =
3.3 V, device power dissipation is
PD = (5 V – 3.3 V)400 mA + 5.0 V(4 mA) = 700 mW
The junction temperature can be calculated from the power
dissipation, ambient temperature, and package thermal
resistance. The thermal resistance is a function not only of the
package, but also of the circuit board layout. Standard test
conditions are used to determine the values published in this
data sheet, but actual performance will vary. For an LFCSP-8
package mounted on a standard 4-layer board, θJA is 48°C/W. In
the above example, where the power dissipation is 700 mW, the
temperature rise above ambient will be approximately equal to
∆TJA = 0.700 W × 48°C/W = 33.6°C
To limit the maximum junction temperature to 150°C, the
maximum allowable ambient temperature will be
TAMAX = 150°C − 33.6°C = 116.4°C
In this case, the resulting ambient temperature limitation is
above the maximum allowable ambient temperature of 85°C.
ADP3335
Rev. A | Page 11 of 16
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
All surface-mount packages rely on the traces of the PC board
to conduct heat away from the package. Use the following
general guidelines when designing printed circuit boards to
improve both electrical and thermal performance.
1. Keep the output capacitor as close as possible to the output
and ground pins.
2. Keep the input capacitor as close as possible to the input
and ground pins.
3. PC board traces with larger cross sectional areas will
remove more heat from the ADP3335. For optimum heat
transfer, specify thick copper and use wide traces.
4. It is not recommended to use solder mask or silkscreen on
the PCB traces adjacent to the ADP3335’s pins, since doing
so will increase the junction-to-ambient thermal resistance
of the package.
5. Use additional copper layers or planes to reduce the
thermal resistance. When connecting to other layers, use
multiple vias, if possible.
LFCSP LAYOUT CONSIDERATIONS
The LFCSP package has an exposed die paddle on the bottom,
which efficiently conducts heat to the PCB. In order to achieve
the optimum performance from the LFCSP package, special
consideration must be given to the layout of the PCB. Use the
following layout guidelines for the LFCSP package.
0.50
2× VIAS, 0.250∅
35µm PLATING
3.36
0.901.80
2.36
1.90
1.40
0.30
0.73
00147-0-024
Figure 25. 3 mm × 3 mm LFCSP Pad Pattern
(Dimensions shown in millimeters)
1. The pad pattern is given in Figure 25. The pad dimension
should be followed closely for reliable solder joints, while
maintaining reasonable clearances to prevent solder
bridging.
2. The thermal pad of the LFCSP package provides a low
thermal impedance path (approximately 20°C/W) to the
PCB. Therefore, the PCB must be properly designed to
effectively conduct heat away from the package. This is
achieved by adding thermal vias to the PCB, which provide
a thermal path to the inner or bottom layers. See Figure 25
for the recommended via pattern. Note that the via
diameter is small to prevent the solder from flowing
through the via and leaving voids in the thermal pad solder
joint.
Also, note that the thermal pad is attached to the die
substrate, so the thermal planes to which the thermal vias
connect must be electrically isolated or tied to VIN. Do
NOT connect the thermal pad to ground.
3. The solder mask opening should be about 120 µ (4.7 mils)
larger than the pad size, resulting in a minimum 60 µm
(2.4 mils) clearance between the pad and the solder mask.
4. The paste mask opening is typically designed to match the
pad size used on the peripheral pads of the LFCSP package.
This should provide a reliable solder joint as long as the
stencil thickness is about 0.125 mm. The paste mask for the
thermal pad needs to be designed for the maximum
coverage to effectively remove the heat from the package.
However, due to the presence of thermal vias and the size
of the thermal pad, eliminating voids may not be possible.
5. The recommended paste mask stencil thickness is
0.125 mm. A laser cut stainless steel stencil with
trapezoidal walls should be used. A “No Clean” Type 3
solder paste should be used for mounting the LFCSP
package. Also, a nitrogen purge during the reflow process is
recommended.
6. The package manufacturer recommends that the reflow
temperature should not exceed 220°C and the time above
liquidus is less than 75 seconds. The preheat ramp should
be 3°C/second or lower. The actual temperature profile
depends on the board density and must be determined by
the assembly house as to what works best.
SHUTDOWN MODE
Applying a TTL high signal to the shutdown (SD) pin or tying it
to the input pin, turns the output ON. Pulling SD down to 0.4 V
or below, or tying it to ground, turns the output OFF. In shut-
down mode, quiescent current is reduced to a typical value of
10 nA.
ADP3335
Rev. A | Page 12 of 16
OUTLINE DIMENSIONS
1
BOTTOM
VIEW
0.50
BSC
0.60 MAX PIN 1
INDICATOR
1.50
REF
0.50
0.40
0.30
0.25
MIN
0.45
2.75
BSC SQ
TOP
VIEW
12° MAX 0.80 MAX
0.65TYP
SEATING
PLANE
PIN 1
INDICATOR
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
1.90
1.75
1.60
4
1.60
1.45
1.30
3.00
BSC SQ
5
8
Figure 26. 8-Lead Frame Chip Scale Package [LFCSP]
(CP-8)
Dimensions shown in millimeters
0.80
0.60
0.40
8°
0°
4
85
4.90
BSC
PIN 1 0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 27. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ADP3335
Rev. A | Page 13 of 16
ORDERING GUIDE
Model Output Voltage1Package Option Branding Information
ADP3335ARM-1.8–RL 1.8 V RM-8 (MSOP-8) LFA
ADP3335ARM-1.8–RL7 1.8 V RM-8 (MSOP-8) LFA
ADP3335ARM-2.5–RL 2.5 V RM-8 (MSOP-8) LFC
ADP3335ARM-2.5–RL7 2.5 V RM-8 (MSOP-8) LFC
ADP3335ARMZ-2.5–RL722.5 V RM-8 (MSOP-8) LFC3
ADP3335ARM-2.85–RL 2.85 V RM-8 (MSOP-8) LFD
ADP3335ARM-2.85–R7 2.85 V RM-8 (MSOP-8) LFD
ADP3335ARMZ-2.85–R72 2.85 V RM-8 (MSOP-8) LFD3
ADP3335ARM-3.3–RL 3.3 V RM-8 (MSOP-8) LFE
ADP3335ARMZ-3.3–RL2 3.3 V RM-8 (MSOP-8) LFE3
ADP3335ARM-3.3–RL7 3.3 V RM-8 (MSOP-8) LFE
ADP3335ARM-5–REEL 5 V RM-8 (MSOP-8) LFF
ADP3335ARM-5–REEL7 5 V RM-8 (MSOP-8) LFF
ADP3335ACP-1.8–RL 1.8 V CP-8 (LFCSP-8) LFA
ADP3335ACP-1.8–RL7 1.8 V CP-8 (LFCSP-8) LFA
ADP3335ACP-2.5–RL 2.5 V CP-8 (LFCSP-8) LFC
ADP3335ACP-2.5–RL7 2.5 V CP-8 (LFCSP-8) LFC
ADP3335ACP-2.85–R7 2.85 V CP-8 (LFCSP-8) LFD
ADP3335ACP-3.3–RL 3.3 V CP-8 (LFCSP-8) LFE
ADP3335ACP-3.3–RL7 3.3 V CP-8 (LFCSP-8) LFE
ADP3335ACP-5–REEL 5 V CP-8 (LFCSP-8) LFF
ADP3335ACP-5–REEL7 5 V CP-8 (LFCSP-8) LFF
1 Contact the factory for other output voltage options.
2 Z = Pb-free part.
3 Pb-free devices have a "#" marked on the device.
ADP3335
Rev. A | Page 14 of 16
NOTES
ADP3335
Rev. A | Page 15 of 16
NOTES
ADP3335
Rev. A | Page 16 of 16
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners
C00147-0-1/04(A)
