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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TFP401A-Q1

SLDS190A –NOVEMBER 2012–REVISED FEBRUARY 2017

TI Panelbus™ Digital Receiver

1 Features

1• Qualified for Automotive Applications

• AEC-Q100 Qualified With the Following Results:

– Device Temperature Grade 3: –40°C to 85°C

Ambient Operating Temperature Range

– Device HBM ESD Classification Level H2

– Device CDM ESD Classification Level C3B

• Supports Pixel Rates Up to 165 MHz (Including

1080p and WUXGA at 60 Hz)

• Digital Visual Interface (DVI) Specification

Compliant(1)

• True-Color, 24-Bit/Pixel, 16.7M Colors at 1 or 2

Pixels per Clock

• Laser-Trimmed Internal Termination Resistors for

Optimum Fixed Impedance Matching

• Skew Tolerant Up to One Pixel-Clock Cycle

• 4× Oversampling

• Reduced Power Consumption – 1.8-V Core

Operation With 3.3-V I/Os and Supplies(2)

• Reduced Ground Bounce Using Time-Staggered

Pixel Outputs

• Low Noise and Good Power Dissipation Using TI

PowerPAD™ Packaging

• Advanced Technology Using TI 0.18-µm EPIC-5™

CMOS Process

• TFP401A-Q1 Incorporates HSYNC Jitter

Immunity(3)

(1) The TFP401A-Q1 device incorporates additional circuitry to

create a stable HSYNC from DVI transmitters that introduce

undesirable jitter on the transmitted HSYNC signal.

(2) The TFP401A-Q1 device has an internal voltage regulator that

provides the 1.8-V core power supply from the external 3.3-V

supplies.

(3) The Digital Visual Interface Specification, DVI, is an industry

standard developed by the Digital Display Working Group

(DDWG) for high-speed digital connection to digital displays.

The TFP401A-Q1 is compliant with the DVI Specification Rev.

1.0.

2 Applications

• High-Definition TV

• HD PC Monitors

• Digital Video

• HD Projectors

• DVI/HDMI Receiver

(4) HDMI video-only

3 Description

The Texas Instruments TFP401A-Q1 device is a TI

Panelbus™ flat-panel display product, and is part of a

comprehensive family of end-to-end DVI 1.0-

compliant solutions. Targeted primarily at desktop

LCD monitors and digital projectors, the TFP401A-Q1

device finds applications in any design requiring high-

speed digital interface.

The TFP401A-Q1 device supports display resolutions

up to 1080p and WUXGA in 24-bit true-color pixel

format. It also offers design flexibility to drive one or

two pixels per clock, supports TFT or DSTN panels,

and provides an option for time-staggered pixel

outputs for reduced ground bounce.

PowerPAD advanced packaging technology results in

best-of-class power dissipation, footprint, and ultralow

ground inductance.

The TFP401A-Q1 combines Panelbus circuit

innovation with TI's advanced 0.18-µm EPIC-5™

CMOS process technology, along with TI PowerPAD

package technology to achieve a reliable, low-

powered, low-noise, high-speed digital interface

solution.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TFP401A-Q1 PQFP (100) 14.00 mm × 14.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

TFP401 Diagram

TFP401A-Q1

SLDS190A –NOVEMBER 2012–REVISED FEBRUARY 2017

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 DC Digital I/O Electrical Characteristics.................... 7

6.6 DC Electrical Characteristics .................................... 7

6.7 AC Electrical Characteristics..................................... 7

6.8 Timing Requirements ............................................... 8

6.9 Switching Characteristics........................................ 10

6.10 Typical Characteristics.......................................... 11

7 Detailed Description............................................ 12

7.1 Overview................................................................. 12

7.2 Functional Block Diagram....................................... 12

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 15

8 Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Application ................................................. 17

9 Power Supply Recommendations...................... 21

9.1 DVDD...................................................................... 21

9.2 OVDD...................................................................... 21

9.3 AVDD...................................................................... 21

9.4 PVDD...................................................................... 21

10 Layout................................................................... 22

10.1 Layout Guidelines ................................................. 22

10.2 Layout Example .................................................... 23

10.3 TI PowerPAD 100-TQFP Package ....................... 26

11 Device and Documentation Support................. 27

11.1 Receiving Notification of Documentation Updates 27

11.2 Community Resources.......................................... 27

11.3 Trademarks........................................................... 27

11.4 Electrostatic Discharge Caution............................ 27

11.5 Glossary................................................................ 27

12 Mechanical, Packaging, and Orderable

Information........................................................... 27

4 Revision History

Changes from Original (November 2012) to Revision A Page

• Added the Device Information table, Pin Configuration and Functions section, ESD Ratings table, Application and

Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation

Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1

• Changed Changed Features From: "Device HBM ESD Classification Level C3B" To: "Device CDM ESD

Classification Level C3".......................................................................................................................................................... 1

• Changed the Operating free-air temperature MIN value From: 0°C To: –40°C and the MAX value From: 70°C To:

85°C in the Recommended Operating Conditions ................................................................................................................ 6

• Changed the Thermal Information table values ..................................................................................................................... 6

100

QO1

QO0

HSYNC

ODCK

OVDD

CTL3

CTL2

CTL1

GND

DVDD

QE23

QE22

QE20

QE19

QE17

QE16

OVDD

OGND

QE15

QE14

OGND

OVDD

AGND

Rx2+

Rx2−

AVDD

AGND

AVDD

Rx1−

AGND

Rx0+

Rx0−

AGND

RxC+

RxC−

AVDD

EXT_RES

PGND

RSVD

OCK_INV

QO22

QO21

QO20

QO18

QO17

QO16

GND

DVDD

QO13

QO12

QO9

QO8

OGND

OVDD

QO7

QO6

QO5

QO4

QO3

QO2

DFO

PIXS

GND

DVDD

STAG

PDO

QE0

QE2

QE3

QE4

QE5

QE6

OVDD

OGND

QE9

QE11

QE12

QE13

QE7

QO23

AVDD

QO11

QO15

QO14

OGND

QE18

SCDT

QE8

QE1

QE10

QE21

VSYNC

QO10

QO19

Rx1+

PVDD

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(1) DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output

5 Pin Configuration and Functions

PZP Package

100-Pin PQFP PowerPAD Package

(Top View)

Pin Functions

PIN TYPE(1) DESCRIPTION

NAME NO.

AGND 79, 83, 87, 89,

92 GND Analog ground – Ground reference and current return for analog circuitry

AVDD 82, 84, 88, 95 VDD Analog VDD – Power supply for analog circuitry. Nominally 3.3 V

CTL[3:1] 42, 41, 40 DO General-purpose control signals – Used for user-defined control. CTL1 is not powered down

through PDO.

DE 46 DO

Output data enable – Used to indicate time of active video display versus non-active display or

blank time. During blank, the device transmits only HSYNC, VSYNC, and CTL[3:1]. During times

of active display, or non-blank, the device transmits only pixel data, QE[23:0], and QO[23:0].

High: Active display time

Low: Blank time

DFO 1 DI

Output clock data format – Controls the output clock (ODCK) format for either TFT or DSTN panel

support. For TFT support, the ODCK clock runs continuously. For DSTN support, ODCK only

clocks when DE is high; otherwise, ODCK remains low when DE is low.

High: DSTN support – ODCK held low when DE = low

Low: TFT support – ODCK runs continuously.

GND 5, 39, 68 GND Digital ground – Ground reference and current return for digital core

DVDD 6, 38, 67 VDD Digital VDD – Power supply for digital core. Nominally 3.3 V.

EXT_RES 96 AI Internal impedance matching – The TFP401A-Q1 device has internal optimization for impedance

matching at 50 Ω. An external resistor tied to this pin has no effect on device performance.

HSYNC 48 DO Horizontal sync output

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Pin Functions (continued)

PIN TYPE(1) DESCRIPTION

NAME NO.

RSVD 99 DI Reserved. Tie this pin high for normal operation.

OVDD 18, 29, 43, 57,

78 VDD Output driver VDD – Power supply for output drivers. Nominally 3.3 V

ODCK 44 DO Output data clock – Pixel clock. The device synchronizes all pixel outputs QE[23:0] and QO[23:0]

(if in 2-pixels-per-clock mode), along with DE, HSYNC, VSYNC and CTL[3:1], to this clock.

OGND 19, 28, 45, 58,

76 GND Output driver ground – Ground reference and current return for digital output drivers

OCK_INV 100 DI

ODCK polarity – Selects ODCK edge to which pixel data (QE[23:0] and QO[23:0]) and control

signals (HSYNC, VSYNC, DE, CTL[3:1]) latch.

Normal mode:

High: Latches output data on rising ODCK edge

Low: Latches output data on falling ODCK edge

PD 2 DI

Power down – An active-low signal that controls the TFP401A-Q1 power-down state. During power

down, all output buffers switch to a high-impedance state. The device powers down all analog

circuits and disables all inputs, except for PD.

If leaving PD unconnected, an internal pullup defaults the TFP401A-Q1 device to normal

operation.

High : Normal operation

Low: Power down

PDO 9 DI

Output drive power down – An active-low signal that controls the power-down state of the output

drivers. During output drive power down, the output drivers (except SCDT and CTL1) are driven to

a high-impedance state. When PDO is left unconnected, an internal pullup defaults the TFP401A-

Q1 device to normal operation.

High: Normal operation; output drivers on

Low: Output drive powered down

PGND 98 GND PLL GND – Ground reference and current return for internal PLL.

PIXS 4 DI

Pixel select – Selects between 1- and 2-pixels-per-clock output modes. During the 2-pixels-per-

clock mode, the device outputs both even pixels, QE[23:0], and odd pixels, QO[23:0], in tandem

on a given clock cycle. During 1-pixel-per-clock mode, the device outputs even and odd pixels

sequentially, one at a time, with the even pixel first, on the even-pixel bus, QE[23:0]. (The first

pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel).

High: 2 pixels per clock

Low: 1 pixel per clock

PVDD 97 VDD PLL VDD – Power supply for internal PLL

QE[8:15] 20–27 DO

Even green-pixel output – Output for even and odd green pixels when in 1-pixel-per-clock mode.

Output for even-only green pixel when in 2-pixels-per-clock mode. Output data synchronizes to the

output data clock, ODCK.

LSB: QE8, pin 20

MSB: QE15, pin 27

QE[16:23] 30–37 DO

Even red-pixel output – Output for even and odd red pixels when in 1-pixel-per-clock mode. Output

for even-only red pixel when in 2-pixels-per-clock mode. Output data synchronizes to the output

data clock, ODCK.

LSB: QE16, pin 30

MSB: QE23, pin 37

QO[0:7] 49–56 DO

Odd blue-pixel output – Output for odd-only blue pixel when in 2-pixels-per-clock mode. Not used,

and held low, when in 1-pixel-per-clock mode. Output data synchronizes to the output data clock,

ODCK.

LSB: QO0, pin 49

MSB: QO7, pin 56

QO[8:15] 59–66 DO

Odd green-pixel output – Output for odd-only green pixel when in 2-pixels-per-clock mode. Not

used, and held low, when in 1-pixel-per-clock mode. Output data synchronizes to the output data

clock, ODCK.

LSB: QO8, pin 59

MSB: QO15, pin 66

QO[16:23] 69–75, 77 DO

Odd red-pixel output – Output for odd-only red pixel when in 2-pixels-per-clock mode. Not used,

and held low, when in 1-pixel-per-clock mode. Output data synchronizes to the output data clock,

ODCK.

LSB: QO16, pin 69

MSB: QO23, pin 77

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Pin Functions (continued)

PIN TYPE(1) DESCRIPTION

NAME NO.

QE[0:7] 10–17 DO

Even blue-pixel output – Output for even and odd blue pixels when in 1-pixel-per-clock mode.

Output for even-only blue pixel when in 2-pixels-per-clock mode. Output data synchronizes to the

output data clock, ODCK.

LSB: QE0, pin 10

MSB: QE7, pin 17

RxC+ 93 AI Clock positive receiver input – Positive side of reference clock. TMDS low-voltage signal

differential-input pair.

RxC– 94 AI Clock negative receiver input – Negative side of reference clock. TMDS low-voltage signal

differential-input pair.

Rx0+ 90 AI Channel-0 positive receiver input – Positive side of channel-0. TMDS low-voltage signal

differential-input pair.

Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank.

Rx0– 91 AI Channel-0 negative receiver input – Negative side of channel-0. TMDS low-voltage signal

differential-input pair.

Rx1+ 85 AI Channel-1 positive receiver input – Positive side of channel-1 TMDS low-voltage signal differential-

input pair.

Channel-1 receives green-pixel data in active display and CTL1 control signals in blank.

Rx1– 86 AI Channel-1 negative receiver input – Negative side of channel-1 TMDS low-voltage signal

differential-input pair.

Rx2+ 80 AI Channel-2 positive receiver input – Positive side of channel-2 TMDS low-voltage signal differential-

input pair.

Channel-2 receives red-pixel data in active display and CTL2, CTL3 control signals in blank.

Rx2– 81 AI Channel-2 negative receiver input – Negative side of channel-2 TMDS low-voltage signal

differential-input pair

SCDT 8 DO

Sync detect - Output to signal when the link is active or inactive. The link is active when DE is

actively switching. The TFP401A-Q1 device monitors the state of DE to determine link activity.

SCDT can be tied externally to PDO to power down the output drivers when the link is inactive.

High: Active link

Low: Inactive link

ST 3 DI Output drive strength select – Selects output drive strength for high- or low-current drive. (See dc

specifications for IOH and IOL versus the ST state).

High: High drive strength

Low: Low drive strength

STAG 7 DI

Staggered pixel select – An active-low signal used in the 2-pixels-per-clock pixel mode (PIXS =

high). Time-staggers the even and odd pixel outputs to reduce ground bounce. Normal operation

outputs the odd and even pixels simultaneously.

High: Normal simultaneous even-and-odd pixel output

Low: Time-staggered even-and-odd pixel output

VSYNC 47 DO Vertical sync output

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNIT

Supply-voltage range DVDD, AVDD, OVDD, PVDD –0.3 4 V

Input-voltage range, logic and analog signals –0.3 4 V

Operating ambient temperature range, TA–40 85 °C

Storage temperature, Tstg –65 150 °C

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per AEC Q100-002(1) ±2000

Charged-device model (CDM), per AEC

Q100-011

All pins ±750

Corner pins (1, 25. 26.

50. 51, 75, 76, and 100) ±750

6.3 Recommended Operating Conditions MIN NOM MAX UNIT

VDD Supply voltage (DVDD, AVDD, PVDD, OVDD) 3 3.3 3.6 V

RtSingle-ended analog-input termination resistance 45 50 55 Ω

TAOperating free-air temperature –40 25 85 °C

(1) For more information about traditional and new thermal metrics, see the Semicondictor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1) TFP401A-Q1

UNITPZP (PQFP)

100 PINS

RθJA Junction-to-ambient thermal resistance 24.9 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 13.2 °C/W

RθJB Junction-to-board thermal resistance 8.4 °C/W

ψJT Junction-to-top characterization parameter 0.2 °C/W

ψJB Junction-to-board characterization parameter 8.5 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W

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6.5 DC Digital I/O Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIH High-level digital input voltage 2 DVDD V

VIL Low-level digital input voltage 0 0.8 V

IOH High-level output drive current ST = high, VOH = 2.4 V 5 10 16.3 mA

ST = low, VOH = 2.4 V 3 6 10.3

IOL Low-level output drive current ST = high, VOL = 0.8 V 8 13 19 mA

ST = low, VOL = 0.8 V 4 7 11

IOZ Hi-Z output leakage current PD = low or PDO = low –1 1 μA

(1) Specified as dc characteristic with no overshoot or undershoot

(2) Alternating 2-pixel black and 2-pixel white patterns. ST = high, STAG = high, QE[23:0] and QO[23:0] CL= 10 pF.

(3) Analog inputs are open-circuit (transmitter disconnected from the TFP401A-Q1 device).

6.6 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VID Analog-input differential voltage(1) 75 1200 mV

VIC Analog-input common-mode voltage(1) AVDD – 300 AVDD – 37 mV

VI(OC) Open-circuit analog input voltage AVDD – 10 AVDD + 10 mV

IDD(2PIX) Normal 2-pixels-per-clock power-supply

current(2) ODCK = 82.5 MHz, 2 pixels per

clock 370 mA

IPD Power-down current(3) PD = low 10 mA

IPDO Output-drive power-down current(3) PDO = low 35 mA

(1) Specified as ac parameter to include sensitivity to overshoot, undershoot, and reflection

6.7 AC Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VID(2) Differential input sensitivity(1) 150 1560 mVp-p

fODCK ODCK frequency PIXS = low (1-PIX/CLK) 25 165 MHz

PIXS = high (2-PIX/CLK) 12.5 82.5

ODCK duty-cycle 45% 60% 75%

QE[23:0], QO[23:0], DE,

CTK[3:1], HSYNC, VSYNC 20%

80% 80%

20%

tr1 tf1

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(1) Specified by Characterization.

(2) tbit is 1/10 the pixel time, tpix.

(3) tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK, is equal to tpix when in 1-pixel-

per-clock mode or 2 tpix when in 2-pixels-per-clock mode.

(4) Measured differentially at 50% crossing using ODCK output clock as trigger

(5) Rise and fall times measured as time between 20% and 80% of signal amplitude

(6) Data and control signals are QE[23:0], QO[23:0], DE, HSYNC, VSYNC. and CTL[3:1].

6.8 Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tps Analog input intra-pair (+ to –) differential skew (1) 0.4 tbit(2)

tccs Analog input inter-pair or channel-to-channel skew (1) 1 tpix(3)

tijit Worst-case differential input-clock jitter tolerance(1)(4) 50 ps

tf1 Fall time of data and control signals(5)(6) ST = low, CL= 5 pF 2.4 ns

ST = high, CL= 10 pF 1.9

tr1 Rise time of data and control signals(5)(6) ST = low, CL= 5 pF 2.4 ns

ST = high, CL= 10 pF 1.9

tr2 Rise time of ODCK clock(5) ST = low, CL= 5 pF 2.4 ns

ST = high, CL= 10 pF 1.9

tf2 Fall time of ODCK clock(5) ST = low, CL= 5 pF 2.4 ns

ST = high, CL= 10 pF 1.9

tsu1 Setup time, data and control signal to falling edge of

ODCK

1 pixel per clock, PIXS = low,

OCK_INV = low 1.8

2 pixels per clock, PIXS = high,

STAG = high, OCK_INV = low 3.8

2 pixels and STAG, PIXS = high,

STAG = low, OCK_INV = low 0.6

th1 Hold time, data and control signal to falling edge of

ODCK

1 pixel per clock, PIXS = low,

OCK_INV = low 0.6

2 pixels and STAG, PIXS = high,

STAG = low, OCK_INV = low 2.5

2 pixels per clock, PIXS = high,

STAG = high, OCK_INV = low 2.9

tsu2 Setup time, data and control signal to rising edge of

ODCK

1 pixels per clock, PIXS = low,

OCK_INV = high 2.1

2 pixels per clock, PIXS = high,

STAG = high, OCK_INV = high 4

2 pixels and STAG, PIXS = high,

STAG = low, OCK_INV = high 1.5

th2 Hold time, data and control signal to rising edge of

ODCK

1 pixel per clock, PIXS = low,

OCK_INV = high 0.3

2 pixels and STAG, PIXS = high,

STAG = low, OCK_INV = high 2.4

2 pixels per clock, PIXS = high,

STAG = high, OCK_INV = high 2.1

tpix Pixel time(3) 6.06 40 ns

Figure 1. Rise and Fall Times of Data and Control Signals

QE[23:0], QO[23:0],

ODCK, DE, CTL[3:2],

HSYNC, VSYNC

PDO

tpd(PDOL)

VIL

QE[23:0], QO[23:0],

ODCK, DE, CTL[3:1],

HSYNC, VSYNC, SCDT

tpd(PDL)

VIL

50%

VOH

td(st)

ODCK

QE[23:0]

QE[23:0], QO[23:0] DE,

CTL[3:1], HSYNC, VSYNC

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

t(su1)

t(h1) t(h2)

t(su2)

VOH

VOL

ODCK

OCK_INV

1/fODCK

ODCK

80%

20%

80%

20%

tr2 tf2

ODCK

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Figure 2. Rise and Fall Times of ODCK

Figure 3. ODCK Frequency

Figure 4. Data Setup and Hold Times to Rising and Falling Edges of ODCK

Figure 5. ODCK High to QE[23:0] Staggered Data Output

Figure 6. Delay From PD Low to Hi-Z Outputs

Figure 7. Delay From PDO Low to Hi-Z Outputs

twL(PDL_MIN)

PD VIL

tps

50%

Rx+

Rx–

tt(HSC) tt(FSC)

SCDT

DFO, ST, PIXS, STAG,

Rx[2:0]+, Rx[2:0]–,

OCK_INV

VIH

tp(PDH-V)

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(1) Amount of time detected between DE transitions determines whether link is active or inactive. SCDT indicates link activity.

Figure 8. Delay From PD Low to High Until Inputs Are Active

Figure 9. Time From DE Transitions to SCDT Low and SCDT High

6.9 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tpd(PDL) Propagation delay time from PD low

to Hi-Z outputs 9 ns

tpd(PDOL) Propagation delay time from PDO

low to Hi-Z outputs 9 ns

tt(HSC) Delay time from DE transition to

SCDT low(1) 1e6 tpix

tt(FSC) Delay time from DE transition to

SCDT high(1) 1600 tpix

td(st) Delay time, ODCK latching edge to

QE[23:0] data output STAG = low, PIXS = high 0.25 tpix

Figure 10. Analog Input Intra-Pair Differential Skew

Figure 11. Minimum Time PD Low

Input Clock (MHz)

Imax (mA)

0 20 40 60 80 100 120 140 160 180 200

100

120

140

160

180

D001

TFP401

tDEL tDEH

tccs

50%

TX2

TX1

TX0

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Figure 12. Analog Input Channel-to-Channel Skew

Figure 13. Minimum DE Low and Maximum DE High

6.10 Typical Characteristics

Figure 14. Imax vs Input Frequency

+Latch

Channel 2

+Latch

Channel 1

+Latch

Channel 0

+PLL

Data Recovery

and

Synchronization

TMDS

Decoder

CH2(0-9)

CH1(0-9)

CH0(0-9)

Panel

Interface

RED(0-7)

CTL3

CTL2

GRN(0-7)

CTL1

BLU(0-7)

VSYNC

HSYNC

QE(0-23)

QO(0-23)

ODCK

SCDT

CTL3

CTL2

CTL1

VSYNC

HSYNC

1.8 V

Regulator

3.3 V

Internal 50-W

Termination

3.3 V

Rx2+

Rx2-

Rx1+

Rx1-

Rx0+

Rx0-

RxC+

RxC-

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7 Detailed Description

7.1 Overview

The TFP401A-Q1 device is a digital visual interface (DVI)-compliant TMDS digital receiver used in digital flat-

panel display systems to receive and decode TMDS-encoded RGB pixel data streams. In a digital display

system, a host (usually a PC or workstation) contains a TMDS-compatible transmitter that receives 24-bit pixel

data along with appropriate control signals. The host encodes the data and control signals into a high-speed low-

voltage differential serial bit stream (fit for transmission over a twisted-pair cable) to a display device. The display

device (usually a flat-panel monitor) requires a TMDS-compatible receiver like the TI TFP401A-Q1 device to

decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host.

This decoded data is then suitable for application directly to the flat-panel drive circuitry to produce an image on

the display. Host and display separation distances can be up to 5 meters or more, making serial transmission of

the pixel data preferable. Support of modern display resolutions up to UXGA requires a high-bandwidth receiver

with good jitter and skew tolerance.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 TMDS Pixel Data and Control Signal Encoding

The device transmits only one of two possible transition-minimized differential signaling (TMDS) characters for a

given pixel at a given time. The transmitter keeps a running count of the number of ones and zeros previously

sent, and transmits the character that minimizes the number of transitions to approximate a dc balance of the

transmission line.

Reception of RGB pixel data during active display time uses three TMDS channels, DE = high. The same three

channels also receive control signals, HSYNC, VSYNC, and user-defined control signals CTL[3:1]. Reception of

these control signals occurs during inactive display or blanking-time. Blanking-time is when DE = low. The

following table maps the received input data to the appropriate TMDS input channel in a DVI-compliant system.

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Feature Description (continued)

(1) Some TMDS transmitters transmit a CTL0 signal. The TFP401A-Q1 device decodes and transfers CTL[3:1] and ignores CTL0

characters. CTL0 is not available as a TFP401A-Q1 output.

Table 1. TMDS Pixel Data and Control Signal Encoding

RECEIVED PIXEL DATA

ACTIVE DISPLAY DE = HIGH INPUT CHANNEL OUTPUT PINS

(VALID FOR DE = HIGH)

Red[7:0] Channel-2 (Rx2 ±) QE[23:16] QO[23:16]

Green[7:0] Channel-1 (Rx1 ±) QE[15:8] QO[15:8]

Blue[7:0] Channel-0 (Rx0 ±) QE[7:0] QO[7:0]

RECEIVED CONTROL DATA

BLANKING DE = LOW INPUT CHANNEL OUTPUT PINS

(VALID FOR DE = LOW)

CTL[3:2] Channel-2 (Rx2 ±) CTL[3:2]

CTL[1: 0](1) Channel-1 (Rx1 ±) CTL1

HSYNC, VSYNC Channel-0 (Rx0 ±) HSYNC, VSYNC

The TFP401A-Q1 device discriminates between valid pixel TMDS characters and control TMDS characters to

determine the state of active display versus blanking, in effect, the state of DE.

7.3.2 TFP401A-Q1 Clocking and Data Synchronization

The TFP401A-Q1 device receives a clock reference from the DVI transmitter that has a period equal to the pixel

time, tpix. Another name for the frequency of this clock is the pixel rate. Because the TMDS encoded data on

Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For

example, the required pixel rate to support a UXGA resolution with 60-Hz refresh rate is 165 MHz. The TMDS

serial bit rate is 10× the pixel rate, or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on

three separate channels (or twisted-pair wires) of long distances (3–5 meters), there is no assurance of phase

synchronization between the data steams and the input reference clock. In addition, skew between the three data

channels is common. The TFP401A-Q1 device uses a 4× oversampling scheme of the input data streams to

achieve reliable synchronization with up to 1-tpix channel-to-channel skew tolerance. Accumulated jitter on the

clock and data lines due to reflections and external noise sources is also typical of high-speed serial data

transmission; hence, the TFP401A-Q1 design for high jitter tolerance.

A phase-locked loop (PLL) conditions the input clock of the TFP401A-Q1 device to remove high-frequency jitter

from the clock. The PLL provides four 10× clock outputs of different phase to locate and sync the TMDS data

streams (4× oversampling). During active display, the pixel data encoding is for transition minimization, whereas

in blank, the control data encoding is for transition maximization. Transmitting in blank for a minimum period of

time, 128 tpix, requires a DVI-compliant transmitter to ensure sufficient time for data synchronization when the

receiver sees a transition-maximized code. Synchronization during blank, when the data is transition-maximized,

ensures reliable data-bit boundary detection. Phase synchronization to the data streams, maintained as long as

the link remains active, is unique for each of the three input channels.

7.3.3 TFP401A-Q1 TMDS Input Levels and Input Impedance Matching

The TMDS inputs to the TFP401A-Q1 receiver have a fixed single-ended termination to AVDD. A laser trim

process internally optimizes the TFP401A-Q1 device to fix the impedance precisely at 50 Ω. The device functions

normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current sockets.

The fixed impedance eliminates the need for an external resistor while providing optimum impedance matching

to standard 50-ΩDVI cables.

Figure 15 shows a conceptual schematic of a DVI transmitter and TFP401A-Q1 receiver connection. A

transmitter drives the twisted-pair cable through a current source, usually using an open-drain type of output

driver. The internal resistor, matched to the cable impedance at the TFP401A-Q1 input, provides a pullup to

AVDD. Naturally, with the transmitter disconnected and the TFP401A-Q1 DVI inputs left unconnected, the

TFP401A-Q1 receiver inputs pull up to AVDD.Figure 16 shows the single-ended differential signal and full-

differential signal. The design of the TFP401A-Q1 device is for response to differential signal swings ranging

from 150 mV to 1.56 V, with common-mode voltages ranging from (AVDD – 300 mV) to (AVDD – 37 mV).

AVCC

AVCC – 1/2 VIDIFF

1/2 VIDIFF

a) Single-Ended Input Signal

+1/2 VIDIFF

–1/2 VIDIFF

VIDIFF

b) Differential Input Signal

Internal Termination

at 50 W

AVDD

DVI Compliant Cable

DATA

TI TFP401/401A

Receiver

DVI

Transmitter

Current

Source

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Figure 15. TMDS Differential Input and Transmitter Connection

Figure 16. TMDS Inputs

7.3.4 TFP401A-Q1 Device Incorporates HSYNC Jitter Immunity

Several DVI transmitters available in the market introduce jitter on the transmitted HSYNC and VSYNC signals

during the TMDS encryption process. The HSYNC signal can shift by one pixel position (one clock) from nominal

in either direction, resulting in up to two cycles of HSYNC shift. This jitter carries through to the DVI receiver, and

if the position of HSYNC shifts continuously, the receiver can lose track of the input timing, causing pixel noise to

occur on the display. For this reason, one should use a DVI-compliant receiver with HSYNC jitter immunity in all

displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem.

The TFP401A-Q1 integrates HSYNC regeneration circuitry that provides a seamless interface to these

noncompliant transmitters. The regeneration circuitry always fixes the position of the data enable (DE) signal in

relation to data, irrespective of the location of HSYNC. The TFP401A-Q1 receiver uses the DE and clock signals

to recreate stable vertical and horizontal sync signals. The circuit filters the HSYNC output of the receiver and

shifts HSYNC to the nearest eighth bit boundary, producing a stable output with respect to the data, as shown in

Figure 17. This ensures accurate data synchronization at the input of the display timing controller.

This HSYNC regeneration circuit is transparent to the monitor, and removal is unnecessary even if the

transmitted HSYNC is stable. For example, the PanelBus line of DVI 1.0-compliant transmitters, such as the

TFP6422 and TFP420, do not have the HSYNC jitter problem. The TFP401A-Q1 device operates correctly with

either compliant or noncompliant transmitters. In contrast, the TFP401A-Q1 device is ideal for customers who

have control over the transmit portion of the design, such as bundled-system manufacturers and for internal

monitor use (the DVI connection between monitor and panel modules).

HSYNC Shift by ± 1 Clock

ODCK

HSYNC IN

HSYNC OUT

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Figure 17. HSYNC Regeneration Timing Diagram

7.4 Device Functional Modes

7.4.1 TFP401A-Q1 Modes of Operation

The TFP401A-Q1 device provides system design flexibility and value by providing the system designer with

configurable options or modes of operation to support varying system architectures. Table 2 outlines the various

supportable panel modes, along with appropriate external control pin settings.

Table 2. Supported Panel Modes

PANEL PIXEL RATE ODCK LATCH EDGE ODCK DFO PIXS OCK_INV

TFT or 16-bit DSTN 1 pixel per clock Falling Free run 0 0 0

TFT or 16-bit DSTN 1 pixel per clock Rising Free run 0 0 1

TFT 2 pixels per clock Falling Free run 0 1 0

TFT 2 pixels per clock Rising Free run 0 1 1

24-bit DSTN 1 pixel per clock Falling Gated low 1 0 0

None 1 pixel per clock Rising Gated low 1 0 1

24-bit DSTN 2 pixels per clock Falling Gated low 1 1 0

24-bit DSTN 2 pixels per clock Rising Gated low 1 1 1

7.4.2 TFP401A-Q1 Output Driver Configurations

The TFP401A-Q1 device provides flexibility by offering various output driver features for use to optimize power

consumption, ground bounce, and power-supply noise. The following sections outline the output driver features

and their effects.

Output Driver Power Down (PDO = low): Pulling PDO low places all the output drivers, except CTL1 and

SCDT, into a high-impedance state. One can tie the SCDT output, which indicates link-disabled or link-inactive,

directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected.

An internal pullup on the PDO pin defaults the TFP401A-Q1 device to the normal nonpower-down output-drive

mode if left unconnected.

Drive Strength (ST = high for high drive strength, ST = low for low drive strength): The TFP401A-Q1 device

allows for selectable output drive strength on the data, control, and ODCK outputs. See the DC Electrical

Characteristics table for the values of IOH and IOL current drives for a given ST state. The high output-drive

strength offers approximately two times the drive as the low output-drive strength.

Time-Staggered Pixel Output: This option works only in conjunction with the 2-pixels-per-clock mode (PIXS =

high). Setting STAG = low time-staggers the even- and odd-pixel outputs so as to reduce the amount of

instantaneous current surge from the power supply. Depending on the PCB layout and design, this can help

reduce the amount of system ground bounce and power-supply noise. The time stagger is such that in 2-pixels-

per-clock mode, the even pixel is delayed from the latching edge of ODCK by 0.25 tcip. (tcip is the period of

ODCK. The ODCK period is 2 tpix when in 2-pixels-per-clock mode.)

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Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the

TFP401A-Q1 drive-strength and staggered-pixel options allow flexibility to reduce system power-supply noise,

ground bounce, and EMI.

Power Management: The TFP401A-Q1 device offers several system power-management features.

The output-driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode,

all output drivers except SCDT and CTL1 go into a high-impedance state while the rest of the device circuitry

remains active.

Power down (PD = low) of the TFP401A-Q1 device is a complete power down in that it powers down the digital

core, the analog circuitry, and output drivers. All output drivers go into a Hi-Z state. Of all the inputs, only PD

remains active. The TFP401A-Q1 device does not respond to any digital or analog inputs until PD is pulled high.

Both PDO and PD have internal pullups, so if left unconnected they default the TFP401A-Q1 device to normal

operating modes.

Sync Detect: The TFP401A-Q1 device offers an output, SCDT, to indicate link activity. The TFP401A-Q1 device

monitors activity on DE to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a

transition on DE, the TFP401A-Q1 device considers the link inactive, and drives SCDT low. While SCDT is low, if

two DE transitions are detected within 1600 pixel clock periods, the device considers the link active and pulls

SCDT high.

A use of SCDT is to signal a system power management circuit to initiate a system power down when the device

considers the link inactive. One can also tie the SCDT directly to the TFP401A-Q1 PDO input to power down the

output drivers when the link is inactive. It is not recommended to use SCDT to drive the PD input, because once

in complete power-down, the analog inputs are ignored and the SCDT state does not change. An external

system power-management circuit to drive PD is preferred.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TFP401A-Q1 is a DVI (Digital Visual Interface) compliant digital receiver that is used in digital flat panel

display systems to receive and decode T.M.D.S. encoded RGB pixel data streams. In a digital display system a

host, usually a PC or workstation, contains a DVI compliant transmitter that receives 24 bit pixel data along with

appropriate control signals and encodes them into a high speed low voltage differential serial bit stream fit for

transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, will

require a DVI compliant receiver like the TI TFP401A-Q1 to decode the serial bit stream back to the same 24 bit

pixel data and control signals that originated at the host. This decoded data can then be applied directly to the

flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by

distances up to 5 meters or more, serial transmission of the pixel data is preferred. The TFP401A-Q1 will support

resolutions up to UXGA.

8.2 Typical Application

Figure 18. Typical Application

8.2.1 Design Requirements

Table 3. Design Parameters

PARAMETER VALUE

Power supply 3.3 V-DC at 1 A

Input clock Single-ended

Input clock frequency range 25 MHz to 165 MHz

Output format 24 bits/pixel

Input clock latching Rising edge

I2C EEPROM support No

De-skew No

8.2.2 Detailed Design Procedure

8.2.2.1 Data and Control Signals

The trace length of data and control signals out of the receiver should be kept as close to equal as possible.

Trace separation should be ~5X Height. As a general rule, traces also should be less than 2.8 inches if possible

(longer traces can be acceptable).

Calculation:

Delay = 85 × SQRT er (1)

er = 4.35; relative permitivity of 50% resin FR-4 at 1 GHz (2)

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Delay = 177 pS/inch (3)

space

Length of rising edge = Tr(picoseconds)/Delay; Tr = 3 nS (4)

= 3000 ps/177 ps per inch (5)

= 16.9 inches (6)

space

Length of rising edge / 6 = Max length of trace for lumped circuit (7)

16.9 / 6 = 2.8 inches (8)

Figure 19. TFP401A-Q1 App Info Data and Control Signals

8.2.2.2 Configuration Options

The TFP401A-Q1 can be configured in several modes depending on the required output format, for example 1-

byte/clock, 2-bytes/clock, falling/rinsing clock edge.

You can leave place holders for future configuration changes.

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Figure 20. TFP401A-Q1 App Info Config Options

8.2.2.3 Power Supplies Decoupling

Digital, analog and PLL supplies must be decoupled from each other to avoid electrical noise on the PLL and the

core.

Figure 21. TFP401A-Q1 App Info Power Decoupling

100

150

200

250

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

Pixel Samples

B2 B1 = GND, B0 = 1

B2 B1 B0 = B7 B6 B5

Pixel Value (dec)

100

150

200

250

1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64

Pixel Samples

x=GND, y=1

x=B7, y=B6

Pixel Value (dec)

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8.2.3 Application Curves

Sometimes the Panel does not support the same format as the GPU (graphics processor unit). In these cases

the user must decide how to connect the unused bits.

The below plots show the mismatches between the 18-bit GPU and a 24-bit LCD where “x” and “y” represent the

2 LSB of the Panel.

Figure 22. 16b GPU to 24b LCD Figure 23. 18B GPU to 24b LCD

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9 Power Supply Recommendations

Use solid ground planes, tie ground planes together with as many vias as is practical. This will provide a

desirable return path for current. Each supply should be on separate split power planes, where each power plane

should be as large an area as possible. Connect PanelBus receiver power and ground pins and all bypass caps

to appropriate power or ground plane with via. Vias should be as fat and short as practical, the goal is to

minimize the inductance.

9.1 DVDD

Place one 0.01-uF capacitor as close as possible between each DVDD device pin (Pins 6, 38, 67) and ground.

9.2 OVDD

Place one 0.01-µF capacitor as close as possible between each OVDD device pin (Pins 18, 29, 43, 57, 78) and

ground.

A 22-µF tantalum capacitor should be placed between the supply and 0.01-uF capacitors.

A ferrite bead should be used between the source and the 22-uF capacitor.

9.3 AVDD

Place one 0.01-uF capacitor as close as possible between each AVDD device pin (Pins 82, 84, 88, 95) and

ground.

A 22-uF tantalum capacitor should be placed between the supply and 0.01-uF capacitors.

A ferrite bead should be used between the source and the 22-uF capacitor.

9.4 PVDD

Place three 0.01-µF capacitors in parallel as close as possible between the PVDD device pin (Pin 97) and

ground. A 22-µF tantalum capacitor should be placed between the supply and 0.01-µF capacitors. A ferrite bead

should be used between the source and the 22-uF capacitor.

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10 Layout

10.1 Layout Guidelines

10.1.1 Layer Stack

The pinout of Texas Instruments High Speed Interface (HSI) devices features differential signal pairs and the

remaining signals comprise the supply rails, VCC and ground, and lower speed signals such as control pins. As

an example, consider a device X which is a repeater/re-driver, so both its inputs and outputs are high-speed

differential signals. These guidelines can be applied to other high-speed devices such as drivers, receivers,

multiplexers, and so on.

A minimum of four layers is required to accomplish a low EMI PCB design. Layer stacking should be in the

following order (top-to-bottom): high-speed differential signal layer, ground plane, power plane and control signal

layer.

Figure 24. Layer Stack

10.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)

Trace impedance should be controlled for optimal performance. Each differential pair should be equal in length

and symmetrical and should have equal impedance to ground with a trace separation of 2X to 4X Height. A

differential trace separation of 4X Height yields about 6% cross-talk (6% effect on impedance). We recommend

that differential trace routing should be side by side, though it is not important that the differential traces be tightly

coupled together because tight coupling is not achievable on PCB traces. Typical ratios on PCB’s are only 20-

50%, 99.9% is the value of a well-balanced twisted pair cable. Each differential trace should be as short as

possible (< 2 inches preferably) with no 90° angles. These high-speed transmission traces hould be on layer 1

(top layer).

RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+ signals all route directly from the DVI connector pins to the

device, no external components are needed.

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10.2 Layout Example

• DVI connector trace matching

Figure 25. DVI Connector

• Keep data lines as far as possible from each other

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Layout Example (continued)

Figure 26. Data Route

• Connect the thermal pad to ground

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Layout Example (continued)

Figure 27. GND Route

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(1) Specified with 2-oz. (0.071 mm thick) Cu PCB plating

(2) Airflow is at 0 LFM (0 m/s) (no airflow).

(3) Measured at ambient temperature, TA= 70°C

10.3 TI PowerPAD 100-TQFP Package

The TFP401A-Q1 device comes in TI's thermally enhanced PowerPAD 100-TQFP package. The PowerPAD

package is a 14-mm × 14-mm × 1-mm TQFP outline with 0.5-mm lead pitch. The PowerPAD package has a

specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the

same outline. The TI 100-TQFP PowerPAD package offers a back-side solder plane that connects directly to the

die mount pad for enhanced thermal conduction. There is no thermal requirement for soldering the back side of

the TFP401A-Q1 device to the application board, because the device power dissipation is well within the

package capability when not soldered.

Soldering the back side of the device to the PCB ground plane is recommended for electrical considerations.

Connection of the PowerPAD back side to a PCB ground plane helps to improve EMI, ground bounce, and

power-supply noise performance, because the die pad is electrically connected to the chip substrate and hence

to chip ground.

Table 4 outlines the thermal properties of the TI 100-TQFP PowerPAD package. The 100-TQFP non-PowerPAD

package is included only for reference.

Table 4. TI 100-TQFP (14 mm × 14 mm × 1 mm) With 0.5-mm Lead Pitch

PARAMETER WITHOUT

PowerPAD™

PACKAGE

PowerPAD™ PACKAGE,

NOT CONNECTED TO PCB

THERMAL PLANE

PowerPAD™ PACKAGE,

CONNECTED TO PCB

THERMAL PLANE(1)

Theta-JA(1) (2) 45°C/W 27.3°C/W 17.3°C/W

Theta-JC(1)(2) 3.11°C/W 0.12°C/W 0.12°C/W

Maximum power dissipation(1)(2)(3) 1.6 W 2.7 W 4.3 W

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11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 Trademarks

PowerPAD, EPIC-5, Panelbus, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 23-Jun-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TFP401AIPZPRQ1 ACTIVE HTQFP PZP 100 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TFP401AI

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 23-Jun-2014

Addendum-Page 2

OTHER QUALIFIED VERSIONS OF TFP401A-Q1 :

•Catalog: TFP401A

•Enhanced Product: TFP401A-EP

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TFP401AIPZPRQ1 HTQFP PZP 100 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Jun-2014

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TFP401AIPZPRQ1 HTQFP PZP 100 1000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Jun-2014

Pack Materials-Page 2

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