Document Number: 91164 www.vishay.com
S09-0011-Rev. A, 19-Jan-09 1
Power MOSFET
IRFI9540G, SiHFI9540G
Vishay Siliconix
FEATURES
• Isolated Package
• High Voltage Isolation = 2.5 kVRMS (t = 60 s;
f = 60 Hz)
• Sink to Lead Creepage Dist. = 4.8 mm
• P-Channel
• 175 °C Operating Temperature
• Dynamic dV/dt
• Low Thermal Resistance
• Lead (Pb)-free Available
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The TO-220 FULLPAK eliminates the need for additional
insulating hardware in commercial-industrial applications.
The molding compound used provides a high isolation
capability and a low thermal resistance between the tab and
external heatsink. This isolation is equivalent to using a 100
micron mica barrier with standard TO-220 product. The
FULLPAK is mounted to a heatsink using a single clip or by
a single screw fixing.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = - 25 V, starting TJ = 25 °C, L = 7.4 mH, RG = 25 Ω, IAS = - 11 A (see fig. 12).
c. ISD ≤ - 19 A, dI/dt ≤ 170 A/µs, VDD ≤ VDS, TJ ≤ 175 °C.
d. 1.6 mm from case.
PRODUCT SUMMARY
VDS (V) - 100
RDS(on) (Ω)V
GS = - 10 V 0.20
Qg (Max.) (nC) 61
Qgs (nC) 14
Qgd (nC) 29
Configuration Single
S
G
D
P-Channel MOSFET
S
D
G
TO-220 FULLPAK
Available
RoHS*
COMPLIANT
ORDERING INFORMATION
Package TO-220 FULLPAK
Lead (Pb)-free IRFI9540GPbF
SiHFI9540G-E3
SnPb IRFI9540G
SiHFI9540G
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS - 100 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current VGS at - 10 V TC = 25 °C ID
- 11
ATC = 100 °C - 7.6
Pulsed Drain CurrentaIDM - 44
Linear Derating Factor 0.32 W/°C
Single Pulse Avalanche EnergybEAS 600 mJ
Repetitive Avalanche CurrentaIAR - 11 A
Repetitive Avalanche EnergyaEAR 4.8 mJ
Maximum Power Dissipation TC = 25 °C PD48 W
Peak Diode Recovery dV/dtcdV/dt - 5.5 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 175 °C
Soldering Recommendations (Peak Temperature) for 10 s 300d
Mounting Torque 6-32 or M3 screw 10 lbf · in
1.1 N · m
* Pb containing terminations are not RoHS compliant, exemptions may apply
www.vishay.com Document Number: 91164
2S09-0011-Rev. A, 19-Jan-09
IRFI9540G, SiHFI9540G
Vishay Siliconix
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA -65
°C/W
Maximum Junction-to-Case (Drain) RthJC -3.1
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 µA - 100 - - V
VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.087 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 2.0 - - 4.0 V
Gate-Source Leakage IGSS V
GS = ± 20 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 100 V, VGS = 0 V - - - 100 µA
VDS = - 80 V, VGS = 0 V, TJ = 150 °C - - - 500
Drain-Source On-State Resistance RDS(on) V
GS = - 10 V ID = - 6.6 Ab- - 0.20 Ω
Forward Transconductance gfs VDS = - 50 V, ID = - 6.6 Ab5.4 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
- 1400 -
pFOutput Capacitance Coss - 590 -
Reverse Transfer Capacitance Crss - 140 -
Drain to Sink Capacitance C f = 1 MHz - 12 -
Total Gate Charge Qg
VGS = - 10 V ID = - 19 A, VDS = - 80 V,
see fig. 6 and 13b
--61
nC Gate-Source Charge Qgs --14
Gate-Drain Charge Qgd --29
Turn-On Delay Time td(on)
VDD = - 50 V, ID = - 19 A,
RG = 9.1 Ω, RD= 7.4 Ω,
see fig. 10b
-24-
ns
Rise Time tr - 110 -
Turn-Off Delay Time td(off) -51-
Fall Time tf -86-
Internal Drain Inductance LD Between lead,
6 mm (0.25") from
package and center of
die contact
-4.5-
nH
Internal Source Inductance LS-7.5-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISMOSFET symbol
showing the
integral reverse
p - n junction diode
--- 11
A
Pulsed Diode Forward CurrentaISM --- 44
Body Diode Voltage VSD TJ = 25 °C, IS = - 11 A, VGS = 0 Vb--- 4.2V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = - 19 A, dI/dt = 100 A/µsb- 130 260 ns
Body Diode Reverse Recovery Charge Qrr - 0.35 0.70 µC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
D
S
G
S
D
G
Document Number: 91164 www.vishay.com
S09-0011-Rev. A, 19-Jan-09 3
IRFI9540G, SiHFI9540G
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 175 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
www.vishay.com Document Number: 91164
4S09-0011-Rev. A, 19-Jan-09
IRFI9540G, SiHFI9540G
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 91164 www.vishay.com
S09-0011-Rev. A, 19-Jan-09 5
IRFI9540G, SiHFI9540G
Vishay Siliconix
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
- 10 V
+
-
V
DS
V
DD
VGS
10 %
90 %
VDS
td(on) trtd(off) tf
R
G
I
AS
0.01 Ω
t
p
D.U.T.
L
VDS
+
-V
DD
- 10 V
Vary t
p
to obtain
required I
AS
IAS
VDS
VDD
VDS
tp
www.vishay.com Document Number: 91164
6S09-0011-Rev. A, 19-Jan-09
IRFI9540G, SiHFI9540G
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
QGS QGD
QG
VG
Charge
- 10 V
D.U.T.
- 3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
Document Number: 91164 www.vishay.com
S09-0011-Rev. A, 19-Jan-09 7
IRFI9540G, SiHFI9540G
Vishay Siliconix
Fig. 14 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.c om/ppg?91164.
P.W.Period
dI/dt
Diode recovery
dV/dt
Ripple ≤5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
V
GS
= - 10 V*
V
DD
I
SD
Driver gate drive
D.U.T. I
SD
waveform
D.U.T. V
DS
waveform
Inductor current
D = P.W.
Period
+
-
-
-
-
+
+
+
* VGS = - 5 V for logic level and - 3 V drive devices
Peak Diode Recovery dV/dt Test Circuit
VDD
• dV/dt controlled by RG
• ISD controlled by duty factor "D"
• D.U.T. - device under test
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
RG
Compliment N-Channel of D.U.T. for driver
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www.vishay.com Vishay
Revision: 08-Feb-17 1Document Number: 91000
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