LTC6915
1
6915fb
Typical applicaTion
FeaTures DescripTion
Zero Drift, Precision
Instrumentation Amplifier with
Digitally Programmable Gain
The LTC
®
6915 is a precision programmable gain instru-
mentation amplifier. The gain can be programmed to 0,
1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, or 4096
through a parallel or serial interface. The CMRR is typi-
cally 125dB with a single 5V supply with any programmed
gain. The offset is below 10µV with a temperature drift of
less than 50nV/°C.
The LTC6915 uses charge balanced sampled data tech-
niques to convert a differential input voltage into a single
ended signal that is in turn amplified by a zero-drift op-
erational amplifier.
The differential inputs operate from rail-to-rail and the
single-ended output swings from rail-to-rail. The LTC6915
can be used in single power supply applications as low as
2.7V, or with dual ±5V supplies. The LTC6915 is available
in a 16-lead SSOP package and a 12-lead DFN surface
mount package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners
Differential Bridge Amplifier with Gain Programmed through the Serial Interface
applicaTions
n 14 Levels of Programmable Gain
n 125dB CMRR Independent of Gain
n Gain Accuracy 0.1% (Typ)
n Maximum Offset Voltage of 10µV
n Maximum Offset Voltage Drift: 50nV/°C
n Rail-to-Rail Input and Output
n Parallel or Serial (SPI) Interface for Gain Setting
n Supply Operation: 2.7V to ±5.5V
n Typical Noise: 2.5µVP-P (0.01Hz to 10Hz)
n 16-Lead SSOP and 12-Lead DFN Packages
n Thermocouple Amplifiers
n Electronic Scales
n Medical Instrumentation
n Strain Gauge Amplifier
n High Resolution Data Acquisition
–
+
3V
RESISTOR
ARRAY
MUX 4-BIT
LATCH
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
HOLD_THRU
µP
TO OTHER
DEVICES
CS(D0)
DIN(D1)
CLK(D2)
DOUT(D3)
PARALLEL_SERIAL
IN+
IN_
3
2
11
6
7
8
9
R < 10k
CSCH
LTC6915 SSOP PACKAGE
0.1µF
V+
V–
SHDN
DGND
13
5
16
10
1
4
OUT
REF
15
14
CF
6915 TA01
SENSE
3V
LTC6915
2
6915fb
absoluTe MaxiMuM raTings
Total Supply Voltage (V+ to V–) ................................. 11V
Input Current ........................................................ ±10mA
|VIN+ – VREF| ........................................................5.5V
|VIN– – VREF| ........................................................5.5V
|V+ – VDGND| ........................................................5.5V
|VDGND – V–| ........................................................5.5V
Digital Input Voltage........................................... V– to V+
Operating Temperature Range
LTC6915C ..............................................–0°C to 70°C
LTC6915I .............................................–40°C to 85°C
LTC6915H .......................................... –40°C to 125°C
Junction Temperature
(GN Package) .................................................... 150°C
(DFN Package) .................................................. 125°C
Storage Temperature
(GN Package) ..................................... –65°C to 150°C
(DFN Package) ................................... –65°C to 125°C
Lead Temperature (Soldering 10 sec) ....................300°C
(Note 1)
12
11
10
9
8
7
13
V–
1
2
3
4
5
6
V+
OUT
REF
PARALLEL_SERIAL
DGND
DOUT(D3)
IN–
IN+
V–
CS(D0)
DIN(D1)
CLK(D2)
TOP VIEW
DE12 PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 160°C/W
EXPOSED PAD (PIN 13) IS V–, MUST BE SOLDERED TO PCB
TOP VIEW
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHDN
IN–
IN+
V–
HOLD_THRU
CS(D0)
DIN(D1)
CLK(D2)
V+
OUT
SENSE
REF
NC
PARALLEL_SERIAL
DGND
DOUT(D3)
TJMAX = 150°C, θJA = 135°C/W
pin conFiguraTion
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC6915CDE#PBF LTC6915CDE#TRPBF 6915 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC6915IDE#PBF LTC6915IDE#TRPBF 6915I 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC6915CGN#PBF LTC6915CGN#TRPBF 6915 16-Lead Narrow Plastic SSOP 0°C to 70°C
LTC6915IGN#PBF LTC6915IGN#TRPBF 6915I 16-Lead Narrow Plastic SSOP –40°C to 85°C
LTC6915HGN#PBF LTC6915HGN#TRPBF 6915H 16-Lead Narrow Plastic SSOP –40°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC6915CDE LTC6915CDE#TR 6915 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC6915IDE LTC6915IDE#TR 6915I 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC6915CGN LTC6915CGN#TR 6915 16-Lead Narrow Plastic SSOP 0°C to 70°C
LTC6915IGN LTC6915IGN#TR 6915I 16-Lead Narrow Plastic SSOP –40°C to 85°C
LTC6915HGN LTC6915HGN#TR 6915H 16-Lead Narrow Plastic SSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC6915
3
6915fb
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V+ = 3V, V– = 0V, VREF = 200mV
Gain Error (Note 2) AV = 1 (RL =10k) l–0.075 0 0.075 %
Gain Error (Note 2) AV = 2 to 32 (RL = 10k) l –0.5 0 0.5 %
Gain Error (Note 2) AV = 64 to 1024 (RL = 10k) l –0.6 –0.1 0.6 %
Gain Error (Note 2) AV = 2048, 4096 (RL = 10k) l–1 –0.2 1.0 %
Gain Nonlinearity AV = 1 l 3 15 ppm
VOS Input Offset Voltage (Note 3) VCM = 200mV –3 ±10 µV
Average Input Offset Drift (Note 3) TA = –40°C to 85°C
TA = 85°C to 125°C
l
l
±50
±100 nV/°C
nV/°C
IBAverage Input Bias Current (Note 4) VCM = 1.2V l 5 10 nA
IOS Average Input Offset Current (Note 4) VCM = 1.2V l 1.5 3 nA
en Input Noise Voltage DC to 10Hz 2.5 µVP-P
V+ = 3V, V– = 0V, VREF = 200mV
CMRR Common Mode Rejection Ratio AV = 1024, VCM = 0V to 3V, LTC6915C
AV = 1024, VCM = 0.1V to 2.9V, LTC6915I
AV = 1024, VCM = 0V to 3V, LTC6915I
AV = 1024, VCM = 0.1V to 2.9V, LTC6915H
AV = 1024, VCM = 0V to 2.97V, LTC6915H
l
l
l
l
l
100
100
95
100
85
119
119
119
dB
dB
dB
dB
dB
PSRR Power Supply Rejection Ratio (Note 5) VS = 2.7V to 6V l110 116 dB
Output Voltage Swing High (Referenced to V–) Sourcing 200µA
Sourcing 2mA
l
l
2.95
2.75 2.98
2.87 V
V
Output Voltage Swing Low (Referenced to V–) Sinking 200µA
Sinking 2mA
l
l
18
130 50
300 mV
mV
Supply Current, Parallel Mode No Load at OUT, VCM = 200mV l0.88 1.3 mA
Supply Current, Serial Mode (Note 6) No Load at OUT, Capacitive Load at
DOUT (CL) = 15pF, Continuous CLK
Frequency = 4MHz, CS = LOW,
Gain Control Code = 0001
l 1.1 1.65 mA
Supply Current Shutdown VSHDN = 2.7V (Hardware Shutdown)
VSHDN = 1V, Gain Control Code = 0000
(Software Shutdown)
l
l
1
125 4
180 µA
µA
SHDN Input High l2.7 V
SHDN Input Low l1 V
SHDN and HOLD_THRU Input Current (Note 2) l5 µA
Internal Op Amp Gain Bandwidth 200 kHz
Slew Rate 0.2 V/µs
Internal Sampling Frequency 3 kHz
V+ = 5V, V– = 0V, VREF = 200mV
Gain Error (Note 2) AV = 1 (RL = 10k) l–0.075 0 0.075 %
Gain Error (Note 2) AV = 2 to 32 (RL= 10k) l–0.5 0 0.5 %
Gain Error (Note 2) AV = 64 to 1024 (RL = 10k) l–0.6 –0.1 0.6 %
Gain Error (Note 2) AV = 2048, 4096 (RL = 10k) l–1 –0.2 1 %
Gain Nonlinearity AV = 1 l3 15 ppm
LTC6915
4
6915fb
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
VOS Input Offset Voltage (Note 3) VCM = 200mV –3 ±10 µV
Average Input Offset Drift (Note 3) TA = –40°C to 85°C
TA = 85°C to 125°C
l ±50
±100 nV/°C
nV/°C
Average Input Bias Current (Note 4) VCM = 1.2V l 5 10 nA
IOS Average Input Offset Current (Note 4) VCM = 1.2V l 1.5 3 nA
CMRR Common Mode Rejection Ratio AV = 1024, VCM = 0V to 5V, LTC6915C
AV = 1024, VCM = 0.1V to 4.9V, LTC6915I
AV = 1024, VCM = 0V to 5V, LTC6915I
AV = 1024, VCM = 0.1V to 4.9V, LTC6915H
AV = 1024, VCM = 0V to 4.97V, LTC6915H
l
l
l
l
l
105
105
95
100
85
125
125
125
dB
dB
dB
dB
dB
PSRR Power Supply Rejection Ratio (Note 5) VS = 2.7V to 6V l110 116 dB
Output Voltage Swing High Sourcing 200µA
Sourcing 2mA
l
l
4.95
4.80 4.99
4.93 V
V
Output Voltage Swing Low Sinking 200µA
Sinking 2mA
l
l
17
120 50
300 mV
mV
V+ = 5V, V– = 0V, VREF = 200mV
Supply Current, Parallel Mode No Load at OUT, VCM = 200mV l0.95 1.48 mA
Supply Current, Serial Mode (Note 6) No Load at OUT, Capacitive Load at
DOUT (CL) = 15pF, Continuous CLK
Frequency = 4MHz, CS = LOW,
Gain Control Code = 0001
l1.4 2 mA
Supply Current, Shutdown VSHDN = 4.5V (Hardware Shutdown)
VSHDN = 1V, Gain Control Code = 0000
(Software Shutdown)
l
l
2
135 10
200 µA
µA
SHDN Input High l4.5 V
SHDN Input Low l1 V
SHDN and HOLD_THRU Input Current (Note 2) l5 µA
Internal Op Amp Gain Bandwidth 200 kHz
Slew Rate 0.2 V/µs
Internal Sampling Frequency 3 kHz
V+ = 5V, V– = –5V, VREF = 0V
Gain Error (Note 2) AV = 1 (RL = 10k) l–0.075 0 0.075 %
Gain Error (Note 2) AV = 2 to 32 (RL = 10k) l–0.5 0 0.5 %
Gain Error (Note 2) AV = 64 to 1024 (RL = 10k) l –0.6 –0.1 0.6 %
Gain Error (Note 2) AV = 2048, 4096 (RL = 10k) l–1 –0.2 1 %
Gain Nonlinearity AV = 1 l3 15 ppm
VOS Input Offset Voltage (Note 3) VCM = 0mV 5 ±20 µV
Average Input Offset Drift (Note 3) TA = –40°C to 85°C
TA = 85°C to 125°C
l
l
±50
±100 nV/°C
nV/°C
IOS Average Input Bias Current (Note 4) VCM = 1V l 4 10 nA
Average Input Offset Current (Note 4) VCM = 1V l 1.5 3 nA
LTC6915
5
6915fb
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
CMRR Common Mode Rejection Ratio AV = 1024, VCM = –5V to 5V, LTC6915C
AV = 1024, VCM = –4.9V to 4.9V, LTC6915I
AV = 1024, VCM = –5V to 5V, LTC6915I
AV = 1024, VCM = –4.9V to 4.9V, LTC6915H
AV = 1024, VCM = –5V to 4.97V, LTC6915H
l
l
l
l
l
105
105
100
100
90
123
123
123
dB
dB
dB
dB
dB
PSRR Power Supply Rejection Ratio (Note 5) VS = 2.7V to 11V l110 116 dB
Output Voltage Swing High Sourcing 200µA
Sourcing 2mA
l
l
4.97
4.90 4.99
4.96 V
V
Output Voltage Swing Low Sinking 200µA
Sinking 2mA
l
l
–4.98
–4.90 –4.92
–4.70 V
V
Supply Current, Parallel Mode No Load, VCM = 0mV l1.1 1.6 mA
Supply Current, Serial Mode (Note 6) No Load at OUT, Capacitive Load at
DOUT (CL) = 15pF, Continuous CLK
Frequency = 4MHz, CS = LOW,
Gain Control Code = 0001
l 1.73 2.48 mA
Supply Current, Shutdown VSHDN = 4V (Hardware Shutdown)
VSHDN = 1V, Gain Control Code = 0000
(Software Shutdown)
l
l
160 25
240 µA
µA
SHDN Input High l4 V
SHDN Input Low l1 V
V+ = 5V, V– = –5V, VREF = 0V
SHDN and HOLD_THRU Input Current (Note 2) l5 µA
Internal Op Amp Gain Bandwidth 200 kHz
Slew Rate 0.2 V/µs
Internal Sampling Frequency 3 kHz
Digital I/O, All Digital I/O Voltage Referenced to DGND
VIH Digital Input High Voltage l2.0 V
VIL Digital Input Low Voltage l 0.8 V
VOH Digital Output High Voltage Sourcing 500µA lV+ – 0.3 V
VOL Digital Output Low Voltage Sinking 500µA l0.3 V
Digital Input Leakage V+ = 5V, V– = –5V, VIN = 0V to 5V l±2 µA
Timing, V+ = 2.7V to 4.5V, V– = 0V (Note 7)
t1DIN Valid to CLK Setup l60 ns
t2DIN Valid to CLK Hold l0 ns
t3CLK Low l100 ns
t4CLK High l100 ns
t5CS/LD Pulse Width l60 ns
t6LSB CLK to CS/LD l60 ns
t7CS/LD Low to CLK l30 ns
t8DOUT Output Delay CL = 15pF l125 ns
t9CLK Low to CS/LD Low l0 ns
LTC6915
6
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: These parameters are tested at ±5V supply; at 3V and 5V supplies
they are guaranteed by design.
Note 3: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels in high speed automatic test
systems. VOS is measured to a limit set by test equipment capability.
Note 4: If the total source resistance is less than 10k, no DC errors result
from the input bias current or mismatch of the input bias currents or the
mismatch of the resistances connected to IN– and IN+.
Note 5: The PSRR measurement accuracy depends on the proximity of
the power supply bypass capacitor to the device under test. Because of
this, the PSRR is 100% tested to relaxed limits at final test. However, their
values are guaranteed by design to meet the data sheet limits.
Note 6: Supply current is dependent on the clock frequency. A higher clock
frequency results in higher supply current.
Note 7: Guaranteed by design, not subject to test.
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
Timing, V+ = 4.5V to 5.5V, V– = 0V (Note 7)
t1DIN Valid to CLK Setup l30 ns
t2DIN Valid to CLK Hold l0 ns
t3CLK Low l50 ns
t4CLK High l50 ns
t5CS/LD Pulse Width l40 ns
t6LSB CLK to CS/LD l40 ns
t7CS/LD Low to CLK l20 ns
t8DOUT Output Delay CL = 15pF l 85 ns
t9CLK Low to CS/LD Low l0 ns
Timing, Dual ±4.5V to ±5.5V Supplies (Note 7)
t1DIN Valid to CLK Setup l30 ns
t2DIN Valid to CLK Hold l0 ns
t3CLK High l50 ns
t4CLK Low l50 ns
t5CS/LD Pulse Width l40 ns
t6LSB CLK to CS/LD l40 ns
t7CS/LD Low to CLK l20 ns
t8DOUT Output Delay CL = 15pF l85 ns
t9CLK Low to CS/LD Low l0 ns
LTC6915
7
6915fb
Typical perForMance characTerisTics
Input Offset Voltage vs Input
Common Mode
Input Offset Voltage vs Input
Common Mode
Input Offset Voltage vs Input
Common Mode
Error Due to Input RS vs Input
Common Mode
Error Due to Input RS vs Input
Common Mode
Error Due to Input RS vs Input
Common Mode
Input Offset Voltage vs Input
Common Mode
Input Offset Voltage vs Input
Common Mode
Input Offset Voltage vs Input
Common Mode
INPUT COMMON MODE VOLTAGE (V)
0 0.5
INPUT OFFSET VOLTAGE (µV)
1.0 2.01.5 2.5 3.0
6915 G01
0
–2
–4
–6
–8
–10
–12
–14
–16
AV = 4096
AV = 256
AV = 16
AV = 1
VS = 3V
VREF = 0.2V
TA = 25°C
INPUT COMMON MODE VOLTAGE (V)
2
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
INPUT OFFSET VOLTAGE (µV)
6915 G02
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
AV = 4096
AV = 256
AV = 16
AV = 1
VS = 5V
VREF = 0.2V
TA = 25°C
INPUT COMMON MODE VOLTAGE (V)
–5
INPUT OFFSET VOLTAGE (µV)
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14 3
6915 G03
–3 –1 15
–4 4
–2 02
AV = 4096
AV = 256
AV = 16
AV = 1
VS = ±5V
VREF = 0V
TA = 25°C
INPUT COMMON MODE VOLTAGE (V)
0 0.5
INPUT OFFSET VOLTAGE (µV)
1.0 2.01.5 2.5 3.0
6915 G04
20
15
10
5
0
–5
–10
–15
–20
VS = 3V
VREF = 0.2V
AV = 16
TA = 125°C
TA = 85°C
TA = 70°C
TA = –50°C
TA = 25°C
INPUT OFFSET VOLTAGE (µV)
20
15
10
5
0
–5
–10
–15
–20
INPUT COMMON MODE VOLTAGE (V)
14
0
6915 G05
2 3 5
VS = 5V
VREF = 0.2V
AV = 16
TA = 125°C
TA = 85°C
TA = 70°C
TA = –50°C
TA = 25°C
20
15
10
5
0
–5
–10
–15
–20
–25
INPUT COMMON MODE VOLTAGE (V)
–5
INPUT OFFSET VOLTAGE (µV)
–1 35
6915 G06
–3 1
VS = ±5V
VREF = 0V
AV = 16
TA = 125°C
TA = 85°C
TA = 70°C
TA = –50°C
TA = 25°C
INPUT COMMON MODE VOLTAGE (V)
0
0
–10
–20
–30
–40
–50 0.5 1.0 1.5 2.0
6915 G07
2.5 3.0
VS = 3V
VREF = 0.2V
R+ = R– = RS
CIN < 100pF
AV = 16
TA = 25°C
RS = 5k
RS = 10k
RS = 20k
+
–
RS
RS
CIN
RS = 15k
INPUT COMMON MODE VOLTAGE (V)
0
ADDITIONAL OFFSET (µV)
0
10
4
6915 G08
–10
–20 1235
20
VS = 5V
VREF = 0.2V
R+ = R– = RS
CIN < 100pF
AV = 16
TA = 25°C
+
–
RS
RS
CIN
RS = 15k
RS = 5k
RS = 20k
RS = 10k
INPUT COMMON MODE VOLTAGE (V)
–5
ADDITIONAL OFFSET (µV)
0
10
3
6915 G09
–10
–20 –3 –1 15
20
RS = 15k
RS = 5k
RS = 20k
VS = ±5V
VREF = 0V
R+ = R– = RS
CIN < 100pF
AV = 16
TA = 25°C
+
–
RS
RS
CIN
RS = 10k
LTC6915
8
6915fb
Typical perForMance characTerisTics
Offset Voltage vs Temperature VOS vs REF (Pin 13) VOS vs REF (Pin 13)
Gain Nonlinearity at Gain = 1
(Gain Nonlinearity Decreases for
Gain > 1) Supply Current vs Supply Voltage CMRR vs Frequency
Error Due to Input RS Mismatch
vs Input Common Mode
Error Due to Input RS Mismatch
vs Input Common Mode
Error Due to Input RS Mismatch
vs Input Common Mode
INPUT COMMON MODE VOLTAGE (V)
0 0.5
ADDITIONAL OFFSET (µV)
1.0 2.01.5 2.5 3.0
6915 G10
80
60
40
20
0
–20
–40
–60
–80
VS = 3V
VREF = 0.2V
CIN < 100pF
AV = 16
TA = 25°C
+
–
R+
R–
CIN
R+ = 0k, R– = 20k
R+ = 20k, R– = 0k
R+ = 0k, R– = 15k
R+ = 15k, R– = 0k
INPUT COMMON MODE VOLTAGE (V)
0
ADDITIONAL OFFSET (µV)
40
30
20
10
0
–10
–20
–30
–40 4.0
6915 G11
1.00.5 1.5 2.5 3.5 4.5
2.0 3.0 5.0
+
–
R+
R–
CIN
R+ = 20k, R– = 0k
VS = 5V
VREF = 0.2V
CIN < 100pF
AV = 16
TA = 25°C
R+ = 0k, R– = 20k
R+ = 15k, R– = 0k
R+ = 0k, R– = 15k
INPUT COMMON MODE VOLTAGE (V)
–5 –4 –2 0 2 4
ADDITIONAL OFFSET (µV)
30
20
10
0
–10
–20
–30 –3 –1 1 3
6915 G12
5
+
–
R+
R–
CIN
R+ = 20k, R– = 0k
VS = ±5V
VREF = 0V
CIN < 100pF
AV = 16
TA = 25°C
R+ = 0k, R– = 20k
R+ = 0k, R– = 15k
R+ = 15k, R– = 0k
TEMPERATURE (°C)
–50
INPUT OFFSET VOLTAGE (µV)
15
10
5
0
–5
–10 050 75
6915 G13
–25 25 100 125
VS = ±5V
VS = 5V
VS = 3V
VREF (V)
0
V
OS
(µV)
4.0
6915 G14
1.0 2.0 3.0
2
–3
–8
–13
–18 0.5 1.5 2.5 3.5
VIN+ = VIN– = REF
AV = 16
TA = 25°C
VS = 3V VS = 5V
VREF (V)
0 1 3 5 7 9
V
OS
(µV)
20
10
0
–10
–20
–30
–40 2 4 6 8
6915 G15
10
VIN+ = VIN– = REF
AV = 16
TA = 25°C
VS = 10V
OUTPUT VOLTAGE (V)
–2.4
GAIN NONLINEARITY (ppm)
5
4
3
2
1
0
–1
–2
–3
–4
–5 –1.2 00.6
6915 G16
–1.8 –0.6 1.2 1.8 2.4
VS = ±2.5V
VCM = VREF = 0V
RL = 10k
AV = 1
TA = 25°C
SUPPLY VOLTAGE (V)
2.5
SUPPLY CURRENT (mA)
8.5
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
6915 G17
3.5 11.5
4.5 5.5 6.5 7.5 9.5 10.5
TA = –50°C
TA = 125°C
TA = 85°C
TA = 0°C
FREQUENCY (Hz)
1
CMRR (db)
130
120
110
100
90
80
70 10 100 1000
6915 G18
VS = 3V, 5V, ±5V
VIN = 1VP-P
R+ = R– = 1k
R+ = R– = 10k
R+ = 10k, R– = 0k
+
–
R+
R–R+ = 0k, R– = 10k
LTC6915
9
6915fb
Typical perForMance characTerisTics
Output Voltage Swing vs
Output Current
Output Voltage Swing vs
Output Current
Low Gain Settling Time vs
Settling Accuracy
Settling Time vs Gain
Internal Clock Frequency vs
Supply Voltage
Additional Gain Error vs Load
Resistance
Input Voltage Noise Density
vs Frequency
Input Referred Noise in
10Hz Bandwidth
Input Referred Noise in
10Hz Bandwidth
FREQUENCY (Hz)
1
INPUT REFERRED NOISE DENSITY (nV/√Hz)
300
250
200
150
100
50
010 100 1000 10000
6915 G19
AV = 16
TA = 25°C
VS = ±5V
VS = 5V
VS = 3V
TIME (s)
0
INPUT REFFERED NOISE VOLTAGE (µV)
3
2
1
0
–1
–2
–3 2 4 6 8
6915 G20
10
VS = 3V
TA = 25°C
TIME (s)
0
INPUT REFFERED NOISE VOLTAGE (µV)
3
2
1
0
–1
–2
–3 2 4 6 8
6915 G21
10
VS = 5V
TA = 25°C
OUTPUT CURRENT (mA)
0.01
OUTPUT VOLTAGE SWING (V)
0.1 1 10
6915 G22
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
TA = 25°C VS = 5V, SOURCING
VS = 3V, SOURCING
VS = 5V, SINKING
VS = 3V, SINKING
SOURCING
SINKING
OUTPUT CURRENT (mA)
0.01
OUTPUT VOLTAGE SWING (V)
0.1 1 10
6915 G23
5
4
3
2
1
0
–1
–2
–3
–4
–5
VS = ±5V
TA = 25°C
SETTLING ACCURACY (%)
0.0001
SETTLING TIME (ms)
6915 G24
0.001 0.01 0.1
8
7
6
5
4
3
2
1
0
VS = 5V
dVOUT = 1V
G 100
TA = 25°C
GAIN (V/V)
1
SETTLING TIME (ms)
35
30
25
20
15
10
5
010 100 1000 10000
6915 G25
VS = 5V
dVOUT = 1V
0.1% ACCURACY
TA = 25°C
SUPPLY VOLTAGE (V)
2.5
CLOCK FREQUENCY (kHz)
10.5
6915 G26
4.5 6.5 8.5
3.40
3.35
3.30
3.25
3.20
3.15
3.10
TA = –55°C
TA = 85°C
TA = 125°C
TA = 25°C
LOAD RESISTANCE RL (k)
0
ADDITIONAL GAIN ERROR (%)
0.1
0
–0.1
–0.2
–0.3
–0.4 8
6915 G27
24610
AV = 4096
AV = 256
AV = 16
LTC6915
10
6915fb
pin FuncTions
IN
– (Pin 1/Pin 2): Inverting Analog Input.
SHDN (Pin 1 GN Package Only): Shutdown Pin. The IC is
shut down when SHDN is tied to V+. An internal current
source pulls this pin to V– when floating.
IN+ (Pin 2/Pin 3): Noninverting Analog Input.
V– (Pin 3/Pin 4): Negative Supply.
CS(D0) (Pin 4/Pin 6): TTL Level Input. When in serial
control mode, this pin is the chip select input (active low);
in parallel control mode, this pin is the LSB of the parallel
gain control code.
DIN(D1) (Pin 5/Pin 7): TTL Level Input. When in serial
control mode, this pin is the serial input data; in paral-
lel mode, this pin is the second LSB of the parallel gain
control code.
HOLD_THRU (Pin 5 GN Package Only): TTL Level Input
for Parallel Control Mode. When HOLD_THRU is high, the
parallel data is latched in an internal D-latch.
CLK(D2) (Pin 6/Pin 8): TTL Level Input. When in serial
control mode, this pin is the clock of the serial interface;
in parallel mode, this pin is the third LSB of the parallel
gain control code.
DOUT(D3) (Pin 7/Pin 9): TTL Level Input. When in serial
control mode, this pin is the output of the serial data; in
parallel mode, this pin is the MSB of the 4-bit parallel
gain control code. In parallel mode operation, if the data
in to DOUT (Pin 9) is from a voltage source greater than V+
(Pin12), then connect a resistor between the voltage source
and DOUT to limit the current into Pin 9 to 5mA or less.
DGND (Pin 8/Pin 10): Digital Ground.
PARALLEL_SERIAL (Pin 9/Pin 11): Interface Selection
Input. When tied to V+, the interface is in parallel mode,
i.e., the PGA gain is defined by the parallel codes (D3 ~
D0), i.e., CS(D0), DATA(D1), CLK(D2), and DOUT(D3).
When PARALLEL_SERIAL pin is tied to V–, the PGA gain
is set by the serial interface.
REF (Pin 10/Pin 13): Voltage Reference for PGA output.
OUT (Pin 11/Pin 15): Amplifier Output. The typical current
sourcing/sinking of the OUT pin is 1mA. For minimum
gain error, the load resistance should be 1k or greater
(refer to the Output Voltage Swing vs Output Current and
Gain Error vs Load Resistance in the Typical Performance
Characteristics section).
V+ (Pin 12/Pin 16): Positive Supply.
SENSE (Pin 14 GN Package Only): Sense Pin. When the
PGA drives a low resistance load and the interconnect
resistance between the OUT pin and the load is not neg-
ligible, tying the SENSE pin as close as possible to the
load can improve the gain accuracy.
(DFN/GN)
LTC6915
11
6915fb
block DiagraMs
(GN Package Only)
(DFN Package Only)
–
+
RESISTOR
ARRAY
MUX 4-BIT
LATCH
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
HOLD_THRU
CS(D0)
DIN(D1)
CLK(D2)
DOUT(D3)
PARALLEL_SERIAL
IN–
IN+3
2
11
6
7
8
9
CSCH
V+
V–
SHDN
DGND
13
5
16
10
1
4
OUT
REF
15
14
CF
6915 BD01
SENSE
GAIN
CONTROL
–
+
RESISTOR
ARRAY
MUX 4-BIT
LATCH
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
CS(D0)
DIN(D1)
CLK(D2)
DOUT(D3)
PARALLEL_SERIAL
IN–
IN+2
1
9
4
5
6
7
CSCH
V+
V–
DGND
DGND
10
12
8
3
OUT
REF
11
CF
6915 BD02
GAIN
CONTROL
LTC6915
12
6915fb
operaTion
TiMing DiagraM
D3D3 D2 D1 D0 D7 • • • • D4
D3D3D4 D2 D1 D0 D7 • • • • D4
t6
t9
t7
t3
t5
t4
t1
t8
t2
PREVIOUS BYTE CURRENT BYTE
CLK
DIN
CS/LD
DOUT
6915 TD
Theory of Operation (Refer to Block Diagrams)
The LTC6915 uses an internal capacitor (CS) to sample
a differential input signal riding on a DC common mode
voltage (the sampling rate is 3kHz and the input switch-
on resistance is 1k to 2k, depending on the power supply
voltage). This capacitor’s charge is transferred to a sec-
ond internal hold capacitor (CH) translating the common
mode voltage of the input differential signal to that of
REF pin. The resulting signal is amplified by a zero-drift
op amp in the noninverting configuration. Gain control
within the amplifier occurs by switching resistors from a
matched resistor array. The LTC6915 has 14 levels of gain,
controlled by the parallel or serial interface. A feedback
capacitor CF helps to reduce the switching noise. Due to
the input sampling, an LTC6915 may produce aliasing
errors for input signals greater than 1.5kHz (one half the
3kHz sampling frequency). However, if the input signal is
bandlimited to less than 1.5kHz then an LTC6915 is useful
as instrumentation or as a differential to single-ended AC
amplifier with programmable gain.
Parallel Interface
As shown in Figure 1, connecting PARALLEL_SERIAL
to V+ allows the gain control code to be set through the
parallel lines (D3, D2, D1, D0). When HOLD_THRU is
low (referenced to DGND) or floating, the parallel gain
control bits (D3 ~ D0) directly control the PGA gain. When
HOLD_THRU is high, the parallel gain control bits are read
into and held by a 4-bit latch. Any change at D3 ~ D0 will
not affect the PGA gain when HOLD_THRU is high. Note
that the DFN12 package does not have the HOLD_THRU
pin. Instead, it is tied to DGND internally. The DOUT(D3)
pin is bidirectional (output in serial mode, input in parallel
mode). In parallel mode, the voltage at DOUT(D3) cannot
exceed V+; otherwise, large currents can be injected to V+
through the parasitic diode (see Figure 2). Connecting a
10k resistor at the DOUT(D3) pin if parallel mode is selected
(see Figure 1) is recommended for current limiting.
Serial Interface
Connecting PARALLEL_SERIAL to V– allows the gain
control code to be set through the serial interface. When
CS is low, the serial data on DIN is shifted into an 8-bit
shift-register on the rising edge of the clock, with the MSB
transferred first (see Figure 3). Serial data on DOUT is
shifted out on the clock’s falling edge. A high CS will load
the 4 LSBs of the shift-register into a 4-bit D-latch, which
are the gain control bits. The clock is disabled internally
when CS is pulled high. Note: CLK must be low before CS
is pulled low to avoid an extra internal clock pulse.
LTC6915
13
6915fb
operaTion
DOUT is always active in serial mode (never tri-stated).
This simplifies the daisy chaining of the multiple devices.
DOUT cannot be “wire-or” to other SPI outputs. In addition,
DOUT does not return to zero at the end of transmission,
i.e. when CS is pulled high.
A LTC6915 may be daisy-chained with other LTC6915s
or other devices having serial interfaces by connecting
the DOUT to the DIN of the next chip while CLK and CS
remain common to all chips in the daisy chain. The serial
data is clocked to all the chips then the CS signal is pulled
high to update all of them simultaneously. Figure 4
shows an example of two LTC6915s in a daisy chained SPI
configuration.
Figure 1. PGA in the Parallel Control Mode
Figure 2. Bidirectional Nature of DOUT/D3 Pin Figure 3. Diagram of Serial Interface (MSB First Out)
4-BIT GAIN
CONTROL CODE
4-BIT
LATCH
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
DOUT
(D3)
CLK
DIN
CS
6915 F03
V–
V+
DGND
DOUT(D3)
6915 F02
(INTERNAL
NODE)
SHDN
IN–
IN+
V–
HOLD_THRU
CS(D0)
DIN(D1)
CLK(D2)
V+
OUT
SENSE
REF
NC
P/S
DGND
DOUT(D3)
LTC6915
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VOUT
VIN
0.1µF
PARALLEL GAIN CONTROL CODE = 1010
VOUT = 29 VIN = 512VIN
SHDN
IN–
IN+
V–
HOLD_THRU
CS(D0)
DIN(D1)
CLK(D2)
V+
OUT
SENSE
REF
NC
P/S
DGND
DOUT(D3)
LTC6915
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VOUT
VIN
0.1µF
GAIN IS SET BY MICROPROCESSOR. A 10k RESISTOR
ON DOUT(D3) PROTECT THE DEVICE WHEN VD3 > V+
µP
5V 5V
D0
D1
D2
D3
10k
6915 F01
LTC6915
14
6915fb
operaTion
Figure 4. 2 PGAs in a Daisy Chain
The amplifier’s gain is set as follows:
D3, D2, D1, D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101~
1111
Gain 0 1 2 4 8 16 32 64 128 256 512 1024 2048 4096
Input Voltage Range
The input common mode voltage range of the LTC6915
is rail-to-rail. However, the following equation limits the
size of the differential input voltage:
V– ≤ (VIN+ – VIN–) + VREF ≤ V+ – 1.3
Where VIN+ and VIN– are the voltage of the differential
input pins, V+ and V– are the positive and negative sup-
ply voltages respectively and VREF is the voltage of REF
pin. In addition, VIN+ and VIN– must not exceed the power
supply voltages, i.e.,
V– < VIN+ < V+ and V– < VIN– < V+
±5 Volt Operation
When using the LTC6915 with supplies over 5.5V, care must
be taken to limit the maximum difference between any of
the input pins (IN+ or IN– ) and the REF pin to 5.5V, i.e.,
|VIN+ – VREF| < 5.5 and |VIN– – VREF| < 5.5
If not, the device will be damaged. For example, if rail-
to-rail input operation is desired when the supplies are at
±5V, the REF pin should be 0, ±0.5V. As a second example,
if the V+ pin is 10V, and the V– and REF pins are at 0, the
inputs should not exceed 5.5V.
SHDN
IN–
IN+
V–
HOLD_THRU
CS(D0)
DIN(D1)
CLK(D2)
V+
OUT
SENSE
REF
NC
P/S
DGND
DOUT(D3)
LTC6915
#2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VOUT
DOUT
VIN
0.1µFSHDN
IN–
IN+
V–
HOLD_THRU
CS(D0)
DIN(D1)
CLK(D2)
V+
OUT
SENSE
REF
NC
P/S
DGND
DOUT(D3)
LTC6915
#1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VOUT
VIN
0.1µF
0.1µF
0.1µF
0.1µF
µP
–5V –5V
–5V
0.1µF
–5V
6915 F04
CS
DIN
CLK
CLK
DIN
CS/LD
D15 D11 D10 D9 D8 D7 D3 D2 D1 D0
GAIN CODE FOR #2 GAIN CODE FOR #1
LTC6915
15
6915fb
operaTion
Settling Time
The sampling rate is 3kHz and the input sampling period
during which CS is charged to the input differential voltage,
VIN, is approximately 150µs. First assume that on each
input sampling period, CS is charged fully to VIN. Since
CS = CH (= 1000pF), a change in the input will settle to
N bits of accuracy at the op amp noninverting input after
N clock cycles or 333µs(N). The settling time at the OUT
pin is also affected by the internal op amp. Since the gain
bandwidth of the internal op amp is typically 200kHz, the
settling time is dominated by the switched-capacitor front
end for gains below 100 (see the Low Gain Settling Time
vs Settling Accuracy and the Settling Time vs Gain graphs
in the Typical Performance Characteristics section). In ad-
dition, the worst case settling time after a device-enable
(active low on Pin 1 of a GN package) is equal to the settling
due to the gain plus the input settling time (333µs • N).
For example, if an LTC6915 is enabled with a logic high on
Pin 1 then, the maximum settling time to 10 bits of ac-
curacy (0.1%) and a gain equal to 100 is 8.33ms ([333µs
• 1024] + 5ms).
Input Current
Whenever the differential input VIN changes, CH must be
charged up to the new input voltage via CS. This results
in an input charging current during each input sampling
period. Eventually, CH and CS will reach VIN and ideally,
the input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on CS every cycle even if VIN is a DC
voltage. For example, the parasitic bottom plate capacitor
on CS must be charged from the voltage on the REF pin to
the voltage on the IN– pin every cycle. The resulting input
charging current decays exponentially during each input
sampling period with a time constant equal to RSCS. If the
voltage disturbance due to these currents settles before
the end of the sampling period, there will be no errors due
to source resistance or the source resistance mismatch
between IN+ and IN–. With RS less than 10k, no DC errors
occur due to input current mismatch.
In the Typical Performance Characteristics section of this
data sheet, there are curves showing the additional error
from non-zero source resistance in the inputs. If there
are no large capacitors across the inputs, the amplifier is
less sensitive to source resistance and source resistance
mismatch. When large capacitors are placed across the
inputs, the input charging currents are placed across
the inputs. The input charging currents described above
result in larger DC errors, especially with source resistor
mismatches.
Power Supply Bypassing
In a dual supply operation, connect a 0.1µF bypass ca-
pacitor from each power supply pin (V+ and V–) to an
analog round plance surrounding an LTC6915. The bypass
capacitor trace to the supply pins must be less than
0.2 inches (an X7R or X5R capacitor type is recommended).
In single supply operation, connect the V– pin to the analog
ground plane and bypass the V+ pin.
Shutdown Modes
The IC has two shutdown modes, hardware shutdown and
software shutdown. When SHDN is tied to V+, the IC is in
hardware shutdown mode. During this shutdown mode,
the gain setting digital interface (serial or parallel) and the
main op amp are both disabled, thus the PGA dissipates
very small supply current (see the Electrical Characteristic
table). When SHDN is floating, an internal current source
will pull it down to V–. The digital interface is turned on to
read the gain setting codes. The IC is in normal amplifica-
tion mode as long as the gain control code is other than
0000. If the gain control code is 0000, the IC operates in
software shutdown mode, i.e., the main op amp is turned
off so that the PGA dissipates less power. The DFN package
does not have hardware shutdown.
Setting the Voltage at the REF Pin
The current coming out of the REF pin may affect the
reference voltage at the REF pin (VREF). If VREF is set by
a resistive divider then the VREF voltage is a function of
the VOUT voltage (see Figure 5). In order to minimize the
VREF variations, the total resistance of R1 plus R2 should
be much less than 32k (5k or less) or use a voltage refer-
ence to set VREF.
Figure 5
–
+
REF
IREF = VOUT – VREF
32k
VOUT
V+
V–
R1
R2
LTC6915
R = 32k
6915 F05
VV
R
V
k
V
RRR k
REFOUT
=+ +
+
12
12
32 32
–
•( )
VREF
0.1µF
OUT
LTC6915
16
6915fb
package DescripTion
Typical applicaTion
Figure 6. A 2:1 Multiplexing Two LTC6915’s
with Daisy Chained Gain Control
Multiplexing Two LTC6915’s
Send a gain code of 0000 to one IC to set its output to a
high impedance state and send a gain code other than 0000
to the second IC to set it for normal amplification. If both
devices are ON, the 200Ω resistors protect the outputs.
The sense pin connection maintains gain accuracy for
loads 1k or greater.
SHDN
IN–
IN+
V–
HOLD_THRU
CS
DIN
CLK
V+
OUT
SENSE
REF
NC
PAR_SER
DGND
DOUT
LTC6915
#1
–5V
–5V
P
(TTL
LEVELS)
DATA
SELECT
CLOCK
0.1µF
0.1µF
5V
VIN1
SHDN
IN–
IN+
V–
HOLD_THRU
CS
DIN
CLK
V+
OUT
SENSE
REF
NC
PAR_SER
DGND
DOUT
LTC6915
#2
–5V
–5V
0.1µF
0.1µF
5V
VIN2 VOUT
200Ω 200Ω
6915 F06
4.00 ±0.10
(2 SIDES)
3.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
2.50 REF
16
127
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(UE12/DE12) DFN 0806 REV D
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
3.30 ±0.10
0.25 ± 0.05
0.50 BSC
1.70 ± 0.05
3.30 ±0.05
0.50 BSC
0.25 ± 0.05
GN16 (SSOP) 0204
1 2 345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ±.004
(0.38 ±0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
LTC6915
17
6915fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
B 6/11 Revised units for PSRR in Electrical Characteristics 5
(Revision history begins at Rev B)
LTC6915
18
6915fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004
LT 0611 REV B • PRINTED IN USA
relaTeD parTs
Typical applicaTion
SHDN
IN–
IN+
V–
HOLD_THRU
CS(D0)
DIN(D1)
CLK(D2)
1
2
3
4
5
6
7
8
2
3
4
5
SDO
SCK
CS
FO
8
9
7
10
REF+
REF–
IN+
IN–
16
15
14
13
12
11
10
9
V+
OUT
SENSE
REF
NC
PAR_SER
DGND
DOUT(D3)
LTC6915
C5
0.1µF C2
0.1µF
C1
0.1µF
0V MEASURE STANDBY V+
V+
V+
V+
V+
CONTROL SIGNAL
10k
16
15
14
13
12
28
VSS VSS
8 19
BRIDGE
SENSOR
R < 10K
20
10k
LT1790-1.25
VIN VOUT
GND1 GND2
C3
0.1µF C3
1µF
ZETEK
ZXM61P02F
6
4
1 2
VCC
GND
LTC2431
MOSI
MISO
SCLK
CS1
CS2
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
RB7
RAS/AN4/SS
RA4/T0CLK1
VDDPIC16LF73
1.25V
6915 F07
6
1
7
6
X1
4MHz
9
10
1
V+
OSC1/
CLKIN
OSC2/
CLKOUT
MCLR/
VPP
PART NUMBER DESCRIPTION COMMENTS
LTC1043 Dual Precision Instrumentation Switched-Capacitor
Building Block Rail-to-Rail Input, 120dB CMRR
LTC1100 Precision Zero-Drift Instrumentation Amplifier Fixed Gains of 10 or 100, 10µV Offset, 50pA Input Bias Current
LTC1101 Precision, Micropower, Single Supply Instrumentation
Amplifier Fixed Gain of 10 or 100, IS < 105µA
LTC1167 Single Resistor Gain Programmable, Precision
Instrumentation Amplifier Single Gains Set Resistor, G = 1 to 10,000 Low Noise: 7.5nV/√Hz
LTC1168 Low Power Single Resistor Gain Programmable,
Precision Instrumentation Amplifiers IS = 530µA
LTC1789-1 Single Supply, Rail-to-Rail Output, Micropower
Instrumentation Amplifier IS = 80µA Max
LTC2050 Zero-Drift Operational Amplifier SOT-23 Package
LTC2051 Dual Zero-Drift Operational Amplifier MS8 Package
LTC2052 Quad Zero-Drift Operational Amplifier GN16 Package
LTC2053 Rail-to-Rail Input and Output, Zero-Drift Instrumentation
Amplifier with Resistor-Programmable Gain MS8 Package, 10µV Max VOS, 50nV/°C Max Drift
LTC6800 Rail-to-Rail Input and Output, Instrumentation Amplifier
with Resistor-Programmable Gain MS8 Package, 100µV Max VOS, 250nV/°C Max Drift
Figure 7. Bridge Amplifier with Programmable Gain and Analog to Digital Conversion. (Standby Current Less than 100µA)