C505C C505A - Infineon Technologies

Never stop thinking.

Microcontrollers

Data Sheet, August 2000

C505

C505C

C505A

C505CA

8-bit Single-Chip Microcontroller

Edition 08. 00

Published by Infineon Technologies AG,

St.-Marti n -Str asse 53,

D-81541 München, Germany

All Rights R eserved.

Attentio n pl ease!

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characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non -infr ingement, reg arding

circuits, descriptions and c harts stated her ein.

Infineon Technologies is an approved CECC manufacturer.

Information

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Microcontrollers

Data Sheet, August 2000

Never stop thinking.

C505

C505C

C505A

C505CA

8-bit Single-Chip Microcontroller

Controller Area Network (CAN): License of Robert Bosch GmbH

C505/C505C/C505A/C505CA Data Sheet

Revision History : Current Version : 08.00

Previous Releases : 06.00, 07.99, 12.97

Page

(in previous

version

Page

(in cuttent

version)

Subjects (major changes since last revision)

General C505CA-2R and C505A-2R included

several several for C505(C)A-4R/C505(C)A-2R/C505(C)A-L only:

IDD max. values added and IDD typical values changed to only 1 digit

after decimal point

24 24 VR2 value for first step corrected from 31H to 21H

Subjects (major changes from revision 07.99 to revision 06.00)

76 76 Term ALE corrected by PALE in table “AC characteristics of

Programming Mode“

58 58 Input high current to RESET pin added (tested for C505CA-4R, C505CA-

L and C505A-4R only)

59,63 59,63 IDD typical values for C505(C)A-4R/L updated

2,57 2,57 Max. operating freq. of 20 MHz with 50% duty cycle for SAH, SAK

temperature ranges updated for all devices except C505-L, C505-2R,

C505C-L and C505C-2R

Subjects (major changes from revision 12.97 to revision 07.99)

general Versioins C505A-4R, C505A-L, C505CA-4R and C505CA-L included.

VCC and ICC replaced by VDD and IDD respectively

3 - Table “Ordering Information“ removed

10 10 EA pin function description changed

- 18 Description added for bit CSWO in SFR SYSCON

24 24 Version Registers VR1, VR2 updated

56 56 Description of Absolute Maximum Ratings changed

- 57 Table “Operating conditions” added

several several IDD values for C505/C505C and C505A-4E/C505CA-4E updated

several - AC characteristics (12 MHz) removed

83 83 Package number corrected by P-MQFP-44-2

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Data Sheet 1 08.00

C505

C505C

C505A

C505CA

8- bit Single-Chi p Microcontroller

Advance Information

•Fully compatible to standard 8051 microcontroller

•Superset of the 8051 architecture with 8 datapointers

•Up to 20 MHz operating frequency

– 375 ns instruction cycle time @16 MHz

– 300 ns instruction cycle time @20 MHz (50 % duty cycle)

•On-chip program memory (with optional memory protection)

– C505(C)(A)-2R : 16K byte on-chip ROM

– C505A-4R/C505CA-4R: 32K byte on-chip ROM

– C505A-4E/C505CA-4E: 32K byte on-chip OTP

– alternatively up to 64k byte external program memory

•256 byte on-chip RAM

•On-chip XRAM

– C505/C505C : 256 byte

– C505A/C505CA : 1K byte

(more features on next page)

Figure 1

C505 Functional Units

Oscillator

Watchdog

Timer C500 8-bit

USART

I/O

8 digit. I/O

I/O

RAM

XRAM

On-Chip Emulation Support Module

Timer 2

Watchdog Timer

8 analog inputs /

Full-CAN Controller

8 Datapoint ers

I/O (2-bit I/O port)

Port 0

Port 1

Port 2

Port 4

Port 3

C505/C505C : 8-bit

A/D Converter

C505A/C505CA : 10-bit

C505C/C 505CA only C505(C)(A)-2R : 16K ROM

C505A-4 R/C505CA -4R : 32K ROM

C505A-4E /C 505CA-4E : 32K OTP

C505/C505C: 256 by te

C505A/C505CA: 1K byte 256 byte

Program Memory

Timer

Core

C505 / C505C

C505A / C505CA

Data Sheet 2 08.00

Features (continued) :

•32 + 2 digital I/O lines

– Four 8-bit digital I/O ports

– One 2-bit digital I/O port (port 4)

– Port 1 with mixed analog/digital I/O capability

•Three 16-bit timers/counters

– Timer 0 / 1 (C501 compatible)

– Timer 2 with 4 channels for 16-bit capture/compare operation

•Full duplex serial interface with programmable baudrate generator (USART)

•Full CAN Module, version 2.0 B compliant (C505C and C505CA only)

– 256 register/data bytes located in external data memory area

– 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz

– internal CAN clock prescaler when input frequency is over 10 MHz

•On-chip A/D Conve rter

– up to 8 analog inputs

– C505/C505C : 8-bit resolution

– C505A/C505CA: 10-bit resolution

•Twelve interrupt sources with four priority levels

•On-chip emulation support logic (Enhanced Hooks Technology TM)

•Programmable 15-bit watchdog timer

•Oscillator watchdog

•Fast power on reset

•Power Saving Modes

– Slow-down mode

– Idle mode (can be combined with slow-down mode)

– Software power-down mode with wake up capability through P3.2/INT0 or P4.1/RXDC pin

•P-MQFP-44 package

•Pin configuration is compatible to C501, C504, C511/C513-family

•Temperature ranges:

SAB-C505 versions TA = 0 to 70 °C

SAF-C505 versions TA = -40 to 85°C

SAH-C505 versions TA = -40 to 110°C

SAK-C505 versions TA = -40 to 125°C

C505 / C505C

C505A / C505CA

Data Sheet 3 08.00

Note:The term C505 refers to all versions desc ribed within this document unl ess otherwise noted .

However the term C505 may also be restricted by the context to refer to only CAN-less

derivatives with 8-Bit ADC which are C505-2R and C505-L in this document.

Note: The term C505(C)(A)-2R, for simplicity, is used to stand for C505 16K byte ROM versions

within this document which are C505-2R, C505C-2R, C505A-2R and C505CA-2R.

Ordering Information

The ordering code for Infineon Technologies’ microcontrollers provides an exact reference to the

required product. This ordering code identifies:

•the derivative itself, i.e. its function set

•the specificed temperature rage

•the package and the type of delivery

For the available ordering codes for the C505 please refer to the “Product information

Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for the Mask-ROM versions are defined for each product after verification

of the respective ROM code.

Table 1

Differences in Functionality of the C505 MCUs

Device Internal Progr am Memory XRAM Size A/D Converter

Resolution CAN

Controller

ROM OTP

C505-2R 16K byte – 256 byte 8 Bit –

C505-L – – 256 byte 8 Bit –

C505C-2R 16K byte – 256 byte 8 Bit √

C505C-L – – 256 byte 8 Bit √

C505A-4R 32K byte – 1K byte 10 Bit –

C505A-2R 16K byte – 1K byte 10 Bit –

C505A-L – – 1K byte 10 Bit –

C505CA-4R 32K byte – 1K byte 10 Bit √

C505CA-2R 16K byte – 1K byte 10 Bit √

C505CA-L – – 1K byte 10 Bit √

C505A-4E – 32K byte 1K byte 10 Bit –

C505CA-4E – 32K byte 1K byte 10 Bit √

C505 / C505C

C505A / C505CA

Data Sheet 4 08.00

Figure 2

Logic Symbol

Port 0

8-bit Digital I/O

Port 1

8-bit Digital I/O /

Port 2

8-bit Digital I/O

Port 3

8-bit Digital I/O

XTAL1

XTAL2

RESET

ALE

PSEN

VAREF

VDD VSS

VAGND

8-bit Analog Inputs

Port 4

2-bit Digital I/O

C505

C505C

C505A

C505CA

C505 / C505C

C505A / C505CA

Data Sheet 5 08.00

Figure 3

C505 Pin Configuration P-MQFP-44 Package (Top View)

This pin fu nc tionality is not ava ilable in the C505/C 505A.

P0.4 / AD4

P0.5 / AD5

P0.6 / AD6

P0.7 / AD7

P4.1 / RXDC

P2.5 / A13

ALE

P2.6 / A14

P2.7 / A15

PSEN

P2.4 / A12

P2.3 / A11

P2.2 / A10

P2.1 / A9

P2.0 / A8

V DD

XTAL1

XTAL2

P3.7 / RD

P3.6 / WR

V SS

32 31 30 29 28 27 26 25 24 2322

123456789 10 11

P1.5 / AN5 / T2EX

P1.6 / AN6 / CLKOUT

P1.7 / AN7 / T2

RESET

P3.0 / RxD

P3.1 / TxD

P3.2 / INT0

P3.3 / INT1

P3.4 / T0

P3.5 / T1

P4.0 / TXDC

P0.3 / AD3

P0.2 / AD2

P0.1 / AD1

V AREF

V AGND

P1.1 / AN1 / INT4 / CC1

P1.2 / AN2 / INT5 / CC2

P1.3 / AN3 / INT6 / CC3

P1.4 / AN4

P0.0 / AD0

P1.0 / AN0 / INT3 / CC0

C505

C505C

C505A

C505CA

C505 / C505C

C505A / C505CA

Data Sheet 6 08.00

Table 2

Pin Definitions and Functions

Symbol Pin Number I/O

*) Function

P1.0-P1.7 40-44,1-3

I/O Port 1

is an 8-bit quasi-bidirectional port with internal pull-up

arrangement. Port 1 pins can be us ed for digital inpu t/output

or as analog inputs of the A/D converter. Port 1 pins that

have 1’s written to them are pulled high by internal pull-up

transistors and in that state can be used as inputs. As

inputs, port 1 pins being externally pulled low will source

current (IIL, in the DC characteristics) because of the

internal pullup transistors. Port 1 pins are assigned to be

used as analog inputs via the register P1ANA.

As secondary dig ital functi ons, p ort 1 c ontains the i nterrupt,

timer, clock, capture and compare pins. The output latch

corresponding to a secondary function must be

programmed to a one (1) for th at function to operate (except

for compare functions). The secondary functions are

assigned to the pins of port 1 as follows:

P1.0 / AN0 / INT3 / CC0 Analog input channel 0

interrupt 3 input /

capture/compare channel 0 I/O

P1.1 / AN1 / INT4 / CC1 Analog input channel 1/

interrupt 4 input /

capture/compare channel 1 I/O

P1.2 / AN2 / INT5 / CC2 Analog input channel 2 /

interrupt 5 input /

capture/compare channel 2 I/O

P1.3 / AN3 / INT6 / CC3 Analog input channel 3

interrupt 6 input /

capture/compare channe l 3 I/O

P1.4 / AN4 Analog input channel 4

P1.5 / AN5 / T2EX Analog input channel 5 / Timer 2

external reload / trigger input

P1.6 / AN6 / CLKOUT Analog input channel 6 /

system clock output

P1.7 / AN7 / T2 Analog input channel 7 /

counter 2 input

Port 1 is used for the low-order address byte during program

verification of the C505 ROM versions (i.e. C505(C)(A)-2R/

C505A-4R/C505CA-4R).

*) I = Input

O=Output

C505 / C505C

C505A / C505CA

Data Sheet 7 08.00

RESET 4 I RESET

A high level on this pin for two machine cycle while the

oscillator is running resets the device. An internal diffused

resistor to VSS permits power-on reset using only an

external capacitor to VDD.

P3.0-P3.7 5, 7-13

I/O Port 3

is an 8-bit quasi-bidirectional port with internal pull-up

arrangement. Port 3 pins that have 1’s written to them are

pulled high by the internal pull-up transistors and in that

state can be used as inputs. As inputs, port 3 pins being

externally pulled low will source current (IIL, in the DC

characteristics) because of the internal pullup transistors.

The output latch corresponding to a secondary function

must be programmed to a one (1) for that function to operate

(except for TxD and WR). The secondary functions are

assigned to the pins of port 3 as follows:

P3.0 / RxD Receiver data input (asynch.) or data

input/output (synch.) of serial interface

P3.1 / TxD Transmitter data output (asynch.) or

clock output (synch.) of serial interface

P3.2 / INT0 External interrupt 0 input / timer 0 gate

control input

P3.3 / INT1 External interrupt 1 input / timer 1 gate

control input

P3.4 / T0 Timer 0 counter input

P3.5 / T1 Timer 1 counter input

P3.6 / WR WR control output; latches the data

byte from port 0 into the external data

memory

P3.7 / RD RD control output; enables the external

data memory

*) I = Input

O=Output

Table 2

Pin Definitions and Functions

Symbol Pin Number I/O

*) Function

C505 / C505C

C505A / C505CA

Data Sheet 8 08.00

P4.0

P4.1 6

28 I/O

I/O Port 4

is a 2-bit quasi-bidirectional port with internal pull-up

arrangement. Port 4 pins that have 1’s written to them are

pulled high by the internal pull-up transistors and in that

state can be used as inputs. As inputs, port 4 pins being

externally pulled low will source current (IIL, in the DC

characteristics) because of the internal pullup transistors.

The output latch corresponding to the secondary function

RXDC must be programmed to a on e (1) fo r that function to

operate. The secondary functions are assigned to the two

pins of port 4 as follows (C505C and C505CA only) :

P4.0 / TXDC Transmitter output of CAN controller

P4.1 / RXDC Receiver input of CAN controller

XTAL2 14 O XTAL2

Output of the inverting oscillator amplifier.

XTAL1 15 I XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock generator circuits.

To drive the device from an external clock source, XTAL1

should be driven, while XTAL2 is left unconnected. To

operate above a frequency of 16 MHz, a duty cycle of the

etxernal clock signal of 50 % should be maintained.

Minimum and maximum high and low times as well as rise/

fall times specified in the AC characteristics must be

observed.

*) I = Input

O=Output

Table 2

Pin Definitions and Functions

Symbol Pin Number I/O

*) Function

C505 / C505C

C505A / C505CA

Data Sheet 9 08.00

P2.0-P2.7 18-25 I/O Port 2

is a an 8-bit quasi-bidirectional I/O port with internal pullup

resistors. Port 2 pins that have 1’s written to them are pulled

high by the i nternal pull up resistors , and in t hat st ate can be

used as inputs. As inputs, port 2 pins being e xternally pulled

low will source current (IIL, in the DC characteristics)

because of the internal pullup resistors. Port 2 emits the

high-order address byte during fetches from external

program memory and during accesses to external data

memory that use 16-bi t addres ses (MOVX @DPTR). In this

application it uses strong internal pullup transistors when

issuing 1s. During accesses to external data memory that

use 8-bit addresses (MOVX @Ri), port 2 issues the

contents of the P2 special function register and uses only

the internal pullup resistors.

PSEN 26 O The Program Store Enable

output is a control signal that enables the external program

memory to the bus during external fetch operations. It is

activated every three oscillator periods except during

external data memory accesses. Remains high during

internal program execution. This pin should not be driven

during reset operation.

ALE 27 O The Address Latch Enable

output is used for latching the low-byte of the address into

external memory during normal operation. It is activated

every three osc illator periods exc ept during an external data

memory access. When instructions are executed from

internal ROM or OTP (EA=1) the ALE generation can be

disabled by bit EALE in SFR SYSCON.

ALE should not be driven during reset operation.

*) I = Input

O=Output

Table 2

Pin Definitions and Functions

Symbol Pin Number I/O

*) Function

C505 / C505C

C505A / C505CA

Data Sheet 10 08.00

EA 29 I External Access Enable

When held at high level, instructions are fetched from the

internal program memory when the PC is less than 4000H

(C505(C)(A)-2R) or 8000H (C505A-4R/C505CA-4R/C505A-

4E/C505CA-4E). When held at low level, the C505 fetches

all instructions from external program memory.

For the C505 romless versions (i.e. C505-L, C505C-L,

C505A-L and C505CA-L) this pin must be tied low.

For the ROM protection version EA pin is latched during

reset.

P0.0-P0.7 37-30 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that

have 1’s written to them float, and in that state can be used

as high-impendance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external

program or data memory. In this application it uses strong

internal pullup transistors when issuing 1’s.

Port 0 also outputs the code bytes during program

verification in the C505 ROM versions. External pullup

resistors are required during program verification.

VAREF 38 –Reference voltage for the A/D converter.

VAGND 39 –Reference ground for the A/D converter.

VSS 16 –Ground (0V)

VDD 17 –Power Supply (+5V)

*) I = Input

O=Output

Table 2

Pin Definitions and Functions

Symbol Pin Number I/O

*) Function

C505 / C505C

C505A / C505CA

Data Sheet 11 08.00

Figure 4

Block Diagram of the C505/C505C/C505A/C505CA

Port 0

8-bit digit. I/O

Port 2

8-bit digit. I/O

Port 3

8-bit digit. I/O

Port 0

Port 1

Port 2

Port 3

OSC & Timing

CPU

Timer 0

Timer 1

Timer 2

USART

XTAL1

XTAL2

RESET

ALE

PSEN

Vss

Oscillator Watchdog

A/D Converter

8-/10-Bit

S&H MUX

AGND

AREF

Port 1

8-bit digit. I/O /

8-bit analog In

16K or 32K

ROM/

256 Byte

XRAM

256 Byte

RAM

Emulation

Support

Logic

Programmable

Watchdog Timer

Full-CAN

Controller

256 Byte

Reg./Dat

Interrupt Unit

8 datapointer s

Port 4

2-bit digit. I/O

Port 4

C505C/C505CA only.

or 1K Byte

OTP

Byte

1) 1)

1) Please refer to table 1 for device specific configuration.

Baudrate generator

C505 / C505C

C505A / C505CA

Data Sheet 12 08.00

CPU

The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities

for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program

memory resul ts from an instruc tion set consisting of 44 % one-byte, 41 % two-byte, and 15% three-

byte instructions. With a 16 MHz crystal, 58% of the instructions are executed in 375 ns (20MHz:

300 ns).

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations.

F0 General Purpose Flag

RS1

RS0 Register Bank Select Control Bits

These bits are used to select one of the four register banks.

OV Overflow Flag

Used by arithmetic instruction.

F1 General Purpose Flag

PParity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

CY AC F0 RS1 RS0 OV F1 PD0HPSW

D7HD6HD5HD4HD3HD2HD1HD0H

Bit No. MSB LSB

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07H

0 1 Bank 1 selected, data address 08H-0FH

1 0 Bank 2 selected, data address 10H-17H

1 1 Bank 3 selected, data address 18H-1FH

C505 / C505C

C505A / C505CA

Data Sheet 13 08.00

Memory Organization

The C505 CPU manipulates operands in the following four address spaces:

–On-chip program memory :16K byte ROM (C505(C)(A)-2R) or

32K byte ROM (C505A-4R/C505CA-4R) or

32K byte OTP (C505A-4E/C505CA-4E)

–Totally up to 64K byte internal/external program memory

–up to 64 Kbyte of external data memory

–256 bytes of internal data memory

–Internal XRAM data memory :256 byte (C505/C505C)

1K byte (C505A/C505CA)

–a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C505 versions.

Figure 5

C505 Memory Map Memory Map

Ext.

Int.

(EA = 1)

Ext.

Data

Memory Int. CAN

Contr.

(256 Byte)

(EA = 0)

Ext.

FFFF

8000

3FFF /

0000

Data

Memory

Ext.

F700

F6FF

0000

Regs.

Function

Special

RAM

Internal

RAM

Internal

Addr.

Indirect Addr.

Direct

Alternatively

"Code Space" "Data Space" "Internal Data Space"

MCB03632

XRAM

Internal FFFF

See table below

for detailed

Data Memory

partitioning

4000 /

7FFF

Device CAN Area

C505

C505C

C505A

C505CA

F700 F7FF

Unused Area

F800 FEFF

F700 FEFF

FF00 FFFF

XRAM Area

"Data Space" F700 to FFFF :

F700 F7FF

F800 FBFF

F700 FBFF

FF00 FFFF

FC00 FFFF

Unused

Area

C505 / C505C

C505A / C505CA

Data Sheet 14 08.00

Reset and System Clock

The reset input is an active high input at pin RESET. Since the reset is synchronized interna lly, the

RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the

oscillator is running. A pulldown resistor is internally connected to VSS to allow a power-up reset with

an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting

the RESET pin to VDD via a capacitor. Figure 6 shows the possible reset circuitries.

Figure 6

Reset Circuitries

RESET

a) b)

VDD

C505

C505C

C505A

C505CA

RESET

C505

C505C

C505A

C505CA

RESET

C505

C505C

C505A

C505CA

C505 / C505C

C505A / C505CA

Data Sheet 15 08.00

Figure 7 shows the recommended oscillator circuits for crystal and external clock operation.

Figure 7

Recommended Oscillator Circuitries

XTAL1

XTAL2

C = 20 pF ± 10pF for crystal operation

2-20

MHz

C = 20pF ± 10pF for crystal operation

External

Clock

Signal

VDD

N.C. XTAL2

XTAL1

C505

C505C

C505A

C505CA

C505

C505C

C505A

C505CA

C505 / C505C

C505A / C505CA

Data Sheet 16 08.00

Multiple Datapointers

As a functional enhancement to the standard 8051 architecture, the C505 contains eight 16-bit

datapointers instead of only one datapointer. The in struction set uses just one of these datapointers

at a time. The selection of the actual datapointer is done in the special function regsiter DPSEL.

Figure 8 illustrates the datapointer addressing mechanism.

Figure 8

External Data Memory Addressing using Multiple Datapointers

DPH(83 ) DPL(82 )

DPTR0

DPTR7

.0.1.2-----

DPSEL(92 )

DPSEL Selected

Data-

pointer

.2 .1 .0

DPTR 0000

0 0 1 DPTR 1

0 1 0 DPTR 2

0 1 1 DPTR 3

1 0 0 DPTR 4

1 0 1 DPTR 5

1 1 0 DPTR 6

1 1 1 DPTR 7

MCD00779

External Data Memory

C505 / C505C

C505A / C505CA

Data Sheet 17 08.00

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative

way to control the execution of C500 MCUs and to gain extensive information on the internal

operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.

Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation

and production chips are identical.

The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500

together with an EH-IC to function similar to a bond-ou t chip. This simpli fies the design and reduces

costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate

all operating modes of the different versions of the C500 microcontrollers. This includes emulation

of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in

single step mode and to read the SFRs after a break.

Figure 9

Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks

Emulation Concept to control the operation of the device during emulation and to transfer

informations about the programm execution and data transfer between the external emulation

hardware (ICE-system) and the C500 MCU.

1“Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Infineon

Technologies.

MCS02647

SYSCON

PCON

TCON

RESET

PSEN

ALE

Port 0

Port 2

I/O Ports

Optional Port 3 Port 1

C500

MCU Interface Circuit

Enhanced Hooks

RPort 0RPort 2

RTCON

RPCON

RSYSCON

TEA TALE TPSEN

EH-IC

Target System Interface

ICE-System Interface

to Emulation Hardware

C505 / C505C

C505A / C505CA

Data Sheet 18 08.00

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in

the special function register area. The special function register area consists of two portions : the

standard specia l function register area and the mapp ed spec ial func tion regi ster area. Fiv e special

function register of the C505 (PCON1,P1ANA, VR0, VR1, VR2) are located in the mapped special

function register area. For accessing the mapped special function register area, bit RMAP in special

function register SYSCON must be set. All other special function registers are located in the

standard special function register area which is accessed when RMAP is cleared (“0“).

The registers and data locations of the CAN controller (CAN-SFRs) are located in the external data

memory area at addresses F700H to F7FFH..

Special Function Register SYSCON (Address B1H) Reset Value : XX100X01B

(C505CA only) Reset Value : XX100001B

As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not

cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed,

the bit RMAP must be cleared/set respectively by software.

All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are

bitaddressable.

The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers

and registers that provide an interface between the CPU and the other on-chip peripherals. The

SFRs of the C505 are listed in table 3 and table 4. In table 3 they are organized in groups which

refer to the functional blocks of the C505. The CAN-SFRs (applicable for the C505C and C505CA

only) are also included in table 3. Table 4 illustrates the contents of the SFRs in numeric order of

their addresses. Table 5 list the CAN-SFRs in numeric order of their addresses.

Bit Function

RMAP Special function register map bit

RMAP = 0 : The access to the non-mapped (standard) special function register

area is enabled.

RMAP = 1 : The access to the mapped spec ial fun ction register area is enabled.

CSWO CAN Controller switch-off bit

CSWO = 0 : CAN Controller is enabled (default after reset).

CSWO = 1 : CAN Controller is switched off.

76543210

EALE RMAP CMOD

B1HSYSCON

Bit No. MSB LSB

CSWO XMAP1

–– XMAP0

The functions of the shaded bits are not described here.

1) This bit is only available in the C505CA.

C505 / C505C

C505A / C505CA

Data Sheet 19 08.00

Table 3

Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

DPH

DPL

DPSEL

PSW

SYSCON2)

VR0 4)

VR1 4)

VR2 4)

Accumulator

B-Register

Data Pointer, High Byte

Data Pointer, Low Byte

Data Pointer Select Register

Program Status Word Register

Stack Pointer

System Control Register

Version Register 0

Version Register 1

Version Register 2

E0H 1)

F0H 1)

83H

82H

92H

D0H 1)

81H

B1H

FCH

FDH

FEH

00H

XXXXX000B 3)

00H

07H

XX100X01B 3) 6)

XX100001B 3) 7)

C5H

05H

A/D-

Converter ADCON0 2)

ADCON1

ADDAT

ADST

ADDATH

ADDATL

P1ANA 2) 4)

A/D Converter Control Register 0

A/D Converter Control Register 1

A/D Converter Data Reg. (C505/C505C)

A/D Converter Start Reg. (C505/C505C)

A/D Converter High Byte Data Register

(C505A/C505CA)

A/D Converter Low Byte Data Register

(C505A/C505CA)

Port 1 Analog Input Selection Register

D8H 1)

DCH

D9H

DAH

D9H

DAH

90H

00X00000B 3)

01XXX000B 3)

00H

XXH 3)

00H

00XXXXXXB 3)

FFH

Interrupt

System IEN0 2)

IEN1 2)

IP0 2)

IP1

TCON 2)

T2CON 2)

SCON 2)

IRCON

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Priority Register 0

Interrupt Priority Register 1

Timer Control Register

Timer 2 Control Register

Serial Channel Control Register

Interrupt Request Control Register

A8H 1)

B8H 1)

A9H

B9H

88H 1)

C8H 1)

98H 1)

C0H 1)

00H

XX000000B 3)

00H

00X00000B

00H

XRAM XPAGE

SYSCON2)

Page Address Register for Extended on-chip

XRAM and CAN Controller

System Control Register

91H

B1H

00H

XX100X01B 3) 6)

XX100001B 3) 7)

1) Bit-addre ssable specia l fun ction registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved

4) This SFR is a m apped SFR. For ac ce ssing this SFR, bit RM AP in SFR SYSC ON mu s t be set.

5) The conten t of th is SF R varies with the act ual s t ep of th e C5 05 (eg. 01H for the first step)

6) C505 / C505A/C505C on ly

7) C505CA only

C505 / C505C

C505A / C505CA

Data Sheet 20 08.00

Ports P0

P1ANA 2) 4)

Port 0

Port 1

Port 1 Analog Input Selection Register

Port 2

Port 3

Port 4

80H 1)

90H 1)

A0H 1)

B0H 1)

E8H 1)

FFH

XXXXXX11B

Serial

Channel ADCON0 2)

PCON 2)

SBUF

SCON

SRELL

SRELH

A/D Converter Control Register 0

Power Control Register

Serial Channel Buffer Register

Serial Channel Control Register

Serial Channel Reload Register, low byte

Serial Channel Reload Register, high byte

D8H 1)

87H

99H

98H 1)

AAH

BAH

00X00000B 3)

00H

XXH 3)

00H

D9H

XXXXXX11B 3)

Timer 0/

Timer 1 TCON

TH0

TH1

TL0

TL1

TMOD

Timer 0/1 Control Register

Timer 0, High Byte

Timer 1, High Byte

Timer 0, Low Byte

Timer 1, Low Byte

Timer Mode Register

88H 1)

8CH

8DH

8AH

8BH

89H

00H

Compare/

Capture

Unit /

Timer 2

CCEN

CCH1

CCH2

CCH3

CCL1

CCL2

CCL3

CRCH

CRCL

TH2

TL2

T2CON

IEN0 2)

IEN1 2)

Comp./Capture Enable Reg.

Comp./Capture Reg. 1, High Byte

Comp./Capture Reg. 2, High Byte

Comp./Capture Reg. 3, High Byte

Comp./Capture Reg. 1, Low Byte

Comp./Capture Reg. 2, Low Byte

Comp./Capture Reg. 3, Low Byte

Reload Regist er High Byte

Reload Register Low Byte

Timer 2, High Byte

Timer 2, Low Byte

Timer 2 Control Register

Interrupt Enable Register 0

Interrupt Enable Register 1

C1H

C3H

C5H

C7H

C2H

C4H

C6H

CBH

CAH

CDH

CCH

C8H 1)

A8H 1)

B8H 1)

00H 3)

00H

00X00000B 3)

00H

Watchdog WDTREL

IEN0 2)

IEN1 2)

IP0 2)

Watchdog Timer Reload Register

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Priority Register 0

86H

A8H 1)

B8H 1)

A9H

00H

Pow. Save

Modes PCON 2)

PCON1 4) Power Control Register

Power Control Register 1 87H

88H 1) 00H

0XX0XXXXB 3)

1) Bit-addressable special function registe rs

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Table 3

Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

C505 / C505C

C505A / C505CA

Data Sheet 21 08.00

CAN

Controller

(C505C/

C505CA

only)

BTR0

BTR1

GMS0

GMS1

UGML0

UGML1

LGML0

LGML1

UMLM0

UMLM1

LMLM0

LMLM1

MCR0

MCR1

UAR0

UAR1

LAR0

LAR1

MCFG

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

Control Register

Status Register

Interrupt Register

Bit Timing Register Low

Bit Timing Register High

Global Mask Short Register Low

Global Mask Short Register High

Upper Global Mask Long Register Low

Upper Global Mask Long Register High

Lower Global Mask Long Register Low

Lower Global Mask Long Register High

Upper Mask of Last Message Register Low

Upper Mask of Last Message Register High

Lower Mask of Last Message Register Low

Lower Mask of Last Message Register High

Message Object Registers :

Message Control Register Low

Message Control Register High

Upper Arbitration Register Low

Upper Arbitration Register High

Lower Arbitration Register Low

Lower Arbitration Register High

Message Configuration Register

Message Data Byte 0

Message Data Byte 1

Message Data Byte 2

Message Data Byte 3

Message Data Byte 4

Message Data Byte 5

Message Data Byte 6

Message Data Byte 7

F700H

F701H

F702H

F704H

F705H

F706H

F707H

F708H

F709H

F70AH

F70BH

F70CH

F70DH

F70EH

F70FH

F7n0H 5)

F7n1H 5)

F7n2H 5)

F7n3H 5)

F7n4H 5)

F7n5H 5)

F7n6H 5)

F7n7H 5)

F7n8H 5)

F7n9H 5)

F7nAH 5)

F7nBH 5)

F7nCH 5)

F7nDH 5)

F7nEH 5)

01H

XXH 3)

UUH 3)

0UUUUUUUB 3)

UUH 3)

UUU11111B 3)

UUH 3)

UUUUU000B 3)

UUH 3)

UUUUU000B 3)

UUH 3)

UUUUU000B 3)

UUUUUU00B3)

XXH 3)

1) Bit-addre ssable specia l fun ction registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by

a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation

4) SFR is loca te d in th e m apped SFR area. For accessing thi s SFR, bit RMAP in SF R SYSCON mu st be s et.

5) The notatio n “n“ (n= 1 to F) in the me ssage object ad dres s def inition define s the num ber of the related

message object.

Table 3

Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

C505 / C505C

C505A / C505CA

Data Sheet 22 08.00

Table 4

Contents of the SFRs, SFRs in numeric order of their addresses

Addr Register Content

after

Reset1)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

80H 2) P0 FFH.7 .6 .5 .4 .3 .2 .1 .0

81HSP 07H.7 .6 .5 .4 .3 .2 .1 .0

82HDPL 00H.7 .6 .5 .4 .3 .2 .1 .0

83HDPH 00H.7 .6 .5 .4 .3 .2 .1 .0

86HWDTREL 00HWDT

PSEL .6 .5 .4 .3 .2 .1 .0

87HPCON 00HSMOD PDS IDLS SD GF1 GF0 PDE IDLE

88H 2) TCON 00HTF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

88H 3) PCON1 0XX0-

XXXXBEWPD – – WS – – – –

89HTMOD 00HGATE C/T M1 M0 GATE C/T M1 M0

8AHTL0 00H.7 .6 .5 .4 .3 .2 .1 .0

8BHTL1 00H.7 .6 .5 .4 .3 .2 .1 .0

8CHTH0 00H.7 .6 .5 .4 .3 .2 .1 .0

8DHTH1 00H.7 .6 .5 .4 .3 .2 .1 .0

90H 2) P1 FFHT2 CLK-

OUT T2EX .4 INT6 INT5 INT4 .INT3

90H 3) P1ANA FFHEAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0

91HXPAGE 00H.7 .6 .5 .4 .3 .2 .1 .0

92HDPSEL XXXX-

X000B–––––.2 .1 .0

98H 2) SCON 00HSM0 SM1 SM2 REN TB8 RB8 TI RI

99HSBUF XXH.7 .6 .5 .4 .3 .2 .1 .0

A0H2) P2 FFH.7 .6 .5 .4 .3 .2 .1 .0

A8H2) IEN0 00HEA WDT ET2 ES ET1 EX1 ET0 EX0

A9HIP0 00HOWDS WDTS .5 .4 .3 .2 .1 .0

AAHSRELL D9H.7 .6 .5 .4 .3 .2 .1 .0

1) X means that the value is undefined and the location is reserved

2) Bit-ad dressabl e s p ec ial funct ion registers

3) SFR is loc at ed in t he m apped SFR area. For accessing th is SF R, bit RMAP in SFR SYS C ON m us t be set.

C505 / C505C

C505A / C505CA

Data Sheet 23 08.00

B0H2) P3 FFHRD WR T1 T0 INT1 INT0 TxD RxD

B1HSYSCON

3) XX10-

0X01B––EALE RMAP CMOD –XMAP1 XMAP0

B1HSYSCON

4) XX10-

0001B––EALE RMAP CMOD CSWO XMAP1 XMAP0

B8H 2) IEN1 00HEXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC

B9HIP1 XX00-

0000B––.5 .4 .3 .2 .1 .0

BAHSRELH XXXX-

XX11B––––––.1 .0

C0H2) IRCON 00HEXF2 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC

C1HCCEN 00HCOCA

H3 COCAL

3COCA

H2 COCAL

2COCA

H1 COCAL

1COCA

H0 COCAL

C2HCCL1 00H.7 .6 .5 .4 .3 .2 .1 .0

C3HCCH1 00H.7 .6 .5 .4 .3 .2 .1 .0

C4HCCL2 00H.7 .6 .5 .4 .3 .2 .1 .0

C5HCCH2 00H.7 .6 .5 .4 .3 .2 .1 .0

C6HCCL3 00H.7 .6 .5 .4 .3 .2 .1 .0

C7HCCH3 00H.7 .6 .5 .4 .3 .2 .1 .0

C8H2) T2CON 00X0-

0000BT2PS I3FR –T2R1 T2R0 T2CM T2I1 T2I0

CAHCRCL 00H.7 .6 .5 .4 .3 .2 .1 .0

CBHCRCH 00H.7 .6 .5 .4 .3 .2 .1 .0

CCHTL2 00H.7 .6 .5 .4 .3 .2 .1 .0

CDHTH2 00H.7 .6 .5 .4 .3 .2 .1 .0

D0H2) PSW 00HCY AC F0 RS1 RS0 OV F1 P

D8H2) ADCON0 00X0-

0000BBD CLK –BSY ADM MX2 MX1 MX0

1) X means that the value is undefined and the location is reserved

2) Bit-ad dressabl e s p ec ial funct ion registers

3) C505 /C505C/C505 A only

4) C505CA only

Table 4

Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

Addr Register Content

after

Reset1)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

C505 / C505C

C505A / C505CA

Data Sheet 24 08.00

D9H ADDAT 6) 00H.7 .6 .5 .4 .3 .2 .1 .0

D9HADDATH

7) 00H.9 .8 .7 .6 .5 .4 .3 .2

DAHADST 6) XXXX-

XXXXB––––––––

DAHADDATL

7) 00XX-

XXXXB.1 .0 ––––––

DCHADCON1 01XX-

X000BADCL1 ADCL0 –––MX2 MX1 MX0

E0H2) ACC 00H.7 .6 .5 .4 .3 .2 .1 .0

E8H2) P4 XXXX-

XX11B––– – – – RXDC TXDC

F0H2) B00H.7 .6 .5 .4 .3 .2 .1 .0

FCH3)4) VR0 C5H11000101

FDH3)4) VR1 05H 00000101

FEH3)4) VR2 5) 01H8)

12H9)

32H10)

.7 .6 .5 .4 .3 .2 .1 .0

1) X means that the value is undefined and the location is reserved

2) Bit-ad dressabl e s p ec ial funct ion registers

3) SFR is loc at ed in t he m apped SFR area. For accessing th is SF R, bit RMAP in SFR SYS C ON m us t be set.

4) These are read-only registers

5) The content of this SFR varies with the actual of the step C505 (eg. 01H or 11 H or 21H fo r the fir st ste p)

6) C505 / C505C only

7) C505A / C505CA only

8) C505 / C505C AB step only

9) C505A-4E / C505CA-4E BA step only (11H for the AA step)

10) C505A-4R / C505CA-4R BA step only

Table 4

Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

Addr Register Content

after

Reset1)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

C505 / C505C

C505A / C505CA

Data Sheet 25 08.00

Table 5

Contents of the CAN Registers in numeric order of their addresses

(C505C/C505CA only)

Addr.

n=1-FH

after

Reset 2)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

F700HCR 01HTEST CCE 0 0 EIE SIE IE INIT

F701HSR XXHBOFF EWRN –RXOK TXOK LEC2 LEC1 LEC0

F702HIR XXHINTID

F704HBTR0 UUHSJW BRP

F705HBTR1 0UUU.

UUUUB0 TSEG2 TSEG1

F706HGMS0 UUHID28-21

F707HGMS1 UUU1.

1111BID20-18 11111

F708HUGML0 UUHID28-21

F709HUGML1 UUHID20-13

F70AHLGML0 UUHID12-5

F70BHLGML1 UUUU.

U000BID4-0 000

F70CHUMLM0 UUHID28-21

F70DHUMLM1 UUHID20-18 ID17-13

F70EHLMLM0 UUHID12-5

F70FHLMLM1 UUUU.

U000BID4-0 000

F7n0HMCR0 UUHMSGVAL TXIE RXIE INTPND

F7n1HMCR1 UUHRMTPND TXRQ MSGLST

CPUUPD NEWDAT

F7n2HUAR0 UUHID28-21

F7n3HUAR1 UUHID20-18 ID17-13

F7n4HLAR0 UUHID12-5

F7n5HLAR1 UUUU.

U000BID4-0 000

F7n6HMCFG UUUU.

UU00BDLC DIR XTD 0 0

1) The nota tio n “n“ (n= 1 to F) in the addre ss definition de fines the numbe r of the relat ed message object.

2) “X“ mea ns tha t th e valu e is undef ined an d the loca tion is r eserved . “U“ m eans that t he v alue is unc hange d

by a reset operation. “U“ va lues are undefined (as “X“) after a power-on reset operation

C505 / C505C

C505A / C505CA

Data Sheet 26 08.00

F7n7HDB0 XXH.7 .6 .5 .4 .3 .2 .1 .0

F7n8HDB1 XXH.7 .6 .5 .4 .3 .2 .1 .0

F7n9HDB2 XXH.7 .6 .5 .4 .3 .2 .1 .0

F7nAHDB3 XXH.7 .6 .5 .4 .3 .2 .1 .0

F7nBHDB4 XXH.7 .6 .5 .4 .3 .2 .1 .0

F7nCHDB5 XXH.7 .6 .5 .4 .3 .2 .1 .0

F7nDHDB6 XXH.7 .6 .5 .4 .3 .2 .1 .0

F7nEHDB7 XXH.7 .6 .5 .4 .3 .2 .1 .0

1) The nota tio n “n“ (n= 1 to F) in the addre ss definition de fines the numbe r of the relat ed message object.

2) “X“ mea ns tha t th e valu e is undef ined an d the loca tion is r eserved . “U“ m eans that t he v alue is unc hange d

by a reset operation. “U“ va lues are undefined (as “X“) after a power-on reset operation

Table 5

Contents of the CAN Registers in numeric order of their addresses (cont’d)

(C505C/C505CA only)

Addr.

n=1-FH

after

Reset 2)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

C505 / C505C

C505A / C505CA

Data Sheet 27 08.00

I/O Ports

The C505 has four 8-bit I/O ports and one 2-bit I/O port. Port 0 is an open-drain bidirectional I/O

port, while ports 1 to 4 are quasi-bidirectional I/O ports with internal pullup resistors. That means,

when configured as inputs, ports 1 to 4 will be pulled high and will source current when externally

pulled low. Port 0 will float when configured as input.

The output dri vers of port 0 and 2 and the input buffers of port 0 are also used for accessing external

memory. In this application, port 0 outputs the low byte of the external memory address, time

multiplexed with the byte be ing written or read. Port 2 outputs the h igh byte of t he external m emory

address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR

contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET .

Port 4 is 2-bit I/O port with CAN controller specific alternate functions. The eight analog input lines

are realized as mixed digital/analog inputs. The 8 analog inputs, AN0-AN7, are located at the port

1 pins P1.0 to P1.7. After reset, all analog inputs are disabled and the related pins of port 1 are

configured as digital inputs. The analog function of a specific port 1 pin is enabled by bits in the SFR

P1ANA. Writing a 0 to a bit position of P1ANA assigns the corresponding pin to operate as analog

input.

Note : P1ANA is a mapped SFR and can be only accessed if bit RMAP in SFR SYSCON is set.

C505 / C505C

C505A / C505CA

Data Sheet 28 08.00

Timer / Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 :

In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the

count rate is fOSC/6.

In the “counter” function the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a

falling edge the max. count rate is fOSC/12. External inputs INT0 and INT1 (P3.2, P3.3) can be

programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the

input clock logic.

Figure 10

Timer/Counter 0 and 1 Input Clock Logic

Table 6

Timer/Counter 0 and 1 Operating Modes

Mode Description TMOD Input Clock

M1 M0 internal external (max)

0 8-bit timer/counter with a

divide-by-32 prescaler 00 fOSC/6x32 fOSC/12x32

1 16-bit timer/counter 0 1

fOSC/6 fOSC/12

2 8-bit timer/counter with

8-bit autoreload 10

3 Timer/counter 0 used as one

8-bit timer/counter and one

8-bit timer

Timer 1 stops

MCS03117

OSC

C/T = 0

C/T = 1

Control

TR1

P3.5/T1

(TMOD)

P3.2/INT0

Timer 0/1

Input Clock

OSC

P3.4/T0

TR0

Gate

P3.3/INT1

C505 / C505C

C505A / C505CA

Data Sheet 29 08.00

Timer/Counter 2 with Compare/Capture/Reload

The timer 2 of the C505 provides additional compare/capture/reload features. which allow the

selection of the following operating modes:

–Compare : up to 4 PWM signals with 16-bit/300 ns resolution (@ 20 MHz clock)

–Capture : up to 4 high speed capture inputs with 300 ns resolution

–Reload : modulation of timer 2 cycle time

The block diagram in figure 11 shows the general configuration of timer 2 with the additional

compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as

multifunctional port functions at port 1.

Figure 11

Timer 2 Block Diagram

MCB02730

Comparator

CCL3/CCH3

Capture

Input/

Output

Control

P1.0/

INT3/

CC0

CC1

INT4/

P1.1/

CC2

INT5/

P1.2/

CC3

INT6/

P1.2/

CCL2/CCH2

Comparator

CCL1/CCH1

Comparator

CRCL/CRCH

Comparator

Bit16 16 Bit 16 Bit 16 Bit

OSC

÷6

÷12

OSC

T2PS

Sync.

P1.7/

T2EX

P1.5/ Sync.

T2I1

T2I0

Timer 2

TH2TL2 TF2

Reload

EXEN2

Reload

EXF2 Interrupt

Request

Compare

C505 / C505C

C505A / C505CA

Data Sheet 30 08.00

Timer 2 Operating Modes

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A

roll-over of the count va lue in TL2/TH2 from all 1 ’s to a ll 0’s sets the timer overflow flag TF2 in SFR

IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer

2 operation.

Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler

offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency.

Gated Timer Mode : In gated timer function, the external input pin T2 (P1.7) functions as a gate to

the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the

counting proce dure. This facilitates pulse width measurements. The external gate signal is sampled

once every machine cycle.

Event Counter Mode : In the event counter function. the timer 2 is incremented in response to a 1-

to-0 transition at its co rresponding ex ternal input pin T2 (P1.7). In this func tion, the ex ternal input is

sampled every machine cycle. Since it takes two machine cycles (12 oscillator periods) to recognize

a 1-to-0 transition, the maximum count rate is 1/6 of the oscillator frequency. There are no

restrictions on the duty cycle of the exte rnal input signal, but to en sure that a given level i s sampled

at least once before it changes, it must be held for at least one full machine cycle.

Reload of Timer 2 : Two reload modes are selectable:

In mode 0, when ti mer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but a lso causes the timer

2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.

In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon-

ding input pin P1.5/T2EX. This transition will also se t flag EXF2 if bit EXEN2 in SFR IEN1 has been

set.

C505 / C505C

C505A / C505CA

Data Sheet 31 08.00

Timer 2 Compare Modes

The compare function of a timer/register combination operates as follows : the 16-bit value stored

in a compare or c ompare/c apture registe r is compared with the c ontents of t he tim er regi ster; i f the

count value in the timer register matches the stored value, an appropriate output signal is generated

at a corresponding port pin and an interrupt can be generated.

Compare Mode 0

In compare mode 0, upon matching the timer and compare register contents, the output signal

changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode

0 is enabled, the appropriate output pin is controll ed by the timer circ uit only and writing to the port

will have no effect. Figure 12 shows a functional diagram of a port circuit when used in compare

mode 0. The port latch is directly controll ed by the timer ov erflow and compare ma tch sig nals. The

input line from the internal bus and the write-to-latch line of the port latch are disconnected when

compare mode 0 is enabled.

Figure 12

Port Latch in Compare Mode 0

MCS02661

Latch

Port Q

CLK

DPort

Read Pin

Read Latch

Port Circuit

Internal

Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare

Match

Overflow

Timer

16 Bit

Bit16

C505 / C505C

C505A / C505CA

Data Sheet 32 08.00

Compare Mode 1

If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the

new value will not appear at the output pin until the next compare match occurs. Thus, it can be

choosen whether th e output signal h as to make a n ew transition (1-to- 0 or 0-to-1, depending on the

actual pin-level) or should keep its old value at the time when the timer value matches the stored

compare value.

In compare mode 1 (see figure 13) the port circuit consists of two separate latches. One latch

(which acts as a "shadow latch") can be written under software control, but its value will only be

transferred to the port latch (and thus to the port pin) when a compare match occurs.

Figure 13

Compare Function in Compare Mode 1

Timer 2 Capture Modes

Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the

current 16-bit val ue of the tim er 2 registers TL 2 and TH2. Two different modes are provided for this

function.

In mode 0, the external event causing a capture is :

–for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1

–for the CRC register : a positive or negativ e transition at the correspon ding pin, depending

on the status of the bit I3FR in SFR T2CON.

In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture

contents will be latched into the appropriate capture register in the cycle following the write

instruction. In this mode no interrupt request will be generated.

MCS02662

Latch

Port Q

QCLK

Read Pin

CLK

Shadow

Latch

Read Latch

Port Circuit

Internal

Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare

Match

Port

16 Bit

C505 / C505C

C505A / C505CA

Data Sheet 33 08.00

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three

asynchronous modes) as illustrated in table 7.

For clarification some terms regarding the difference between "baud rate clock" and "baud rate"

should be mentione d. In the asynchronous modes the serial interfaces require a c lock rate which is

16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have

to provide a "bau d rate clock" (output signal in figure 14 to the serial i nterface which - there divided

by 16 - results in the actual "baud rate". Further, the abbrevation fOSC refers to the oscillator

frequency (crystal or external clock operation).

The variable baud rate s for modes 1 and 3 of th e serial interfac e can be derive d either from timer 1

or from a decdicated baud rate generator (see figure 14).

Table 7

USART Operating Modes

Mode SCON Description

SM0 SM1

0 0 0 Shift register mode, fixed baud rate

Serial data enters and exits through R×D; T×D outputs the shi ft

clock; 8-bit are transmitted/received (LSB first)

1 0 1 8-bit UART, variable baud rate

10 bits are transmitted (through T×D) or received (at R×D)

2 1 0 9-bit UART, fixed baud rate

11 bits are transmitted (through T×D) or received (at R×D)

3 1 1 9-bit UART, variable baud rate

Like mode 2

C505 / C505C

C505A / C505CA

Data Sheet 34 08.00

Figure 14

Block Diagram of Baud Rate Generation for the Serial Interface

Table 8 below lists the values/formulas for the baud rate calculation of the serial interface with its

dependencies of the control bits BD and SMOD.

Table 8

Serial Interface - Baud Rate Dependencies

Serial Interface

Operating Modes Active Control Bits Ba ud Rate Calculation

BD SMOD

Mode 0 (Shift Register) –– fOSC / 6

Mode 1 (8-bit UART)

Mode 3 (9-bit UART) 0 X Controlled by timer 1 overflow :

(2SMOD ×timer 1 overflow rate) / 32

1 X Controlled by baud rate generator

(2SMOD ×fOSC) /

(32 ×baud rate generator overflow rate)

Mode 2 (9-bit UART) –0

1fOSC / 32

fOSC / 16

MCS02733

Rate

OSC

(SMOD)

Baud

Clock

PCON.7

(SM0/

SM1)

SCON.7

SCON.6

Only one mode

can be selected

ADCON0.7

(BD)

Baud

Rate

Generator

(SRELH

SRELL)

Timer 1

Mode 2

Mode 0

Note: The switch configuration shows the reset state.

Mode 3

Mode 1

Overflow

C505 / C505C

C505A / C505CA

Data Sheet 35 08.00

CAN Controller (C505C and C505CA only)

The on-chip CAN controller, compliant to version 2.0B, is the functional heart which provides all

resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the

extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the

CPU of as much o verhead as possible when c ontrolling many di fferent message obj ects (up to 15).

This includes bus arbitration, resending of garbled messages, error handling, interrupt generation,

etc. In order to implement the physical layer, external components have to be connected to the

C505C/C505CA.

The internal bus interface connects the on-chip CAN controller to the internal bus of the

microcontroll er. The registers and dat a locations of the CAN interface are m apped to a specific 256

byte wide address range of th e external data memory area (F700H to F7FFH) and can be accessed

using MOVX instructions. Figure 15 shows a block diagram of the on-chip CAN controller.

The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel

access t o the whole data or remo te frame for the acc eptance mat ch test and the para llel trans fer of

the frame to and from the Intelligent Memory.

The Bit Stream Processor (BS P) is a sequencer controlling the sequential data stream between

the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and

the parallel dat a stream between the TX/RX Shift Register and the Intelli gent Memory such that the

processes of reception, arbitration, transmission, and error signalling are performed according to

the CAN protocol. Note that the automatic retransmis sion of mes sages which have been c orrupted

by noise or other external error conditions on the bus line is handled by the BSP.

The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to

be transmitted after the data bytes and checks the CRC code of incoming messages. This is done

by dividing the data stream by the code generator polynomial.

The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its

counters, the Receive Error Counter and the Transmit Error Counter, are incremented and

decremented by commands from the Bit Stream Processor. According to the values of the error

counters, the CAN controller is set into the states error active, error passive and busoff.

The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline related bit

timing according to the CAN protocol. The BTL synchronizes on a recessive to dominant busline

transition at Start of Fra me (hard synchronization) and on any further recessive to dominant busline

transition, if the CAN controller its elf does n ot transmit a dominant bi t (resynchroni zation). The BTL

also provides programmable time segments to compensate for the propagation delay time and for

phase shifts and to define the position of the Sample Point in the bit time. The programming of the

BTL depends on the baudrate and on external physical delay times.

The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message objects of

maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of

control and status bits. After the initial configuration, the Intelligent Memory can handle the

reception and transmission of data without further microcontroller actions.

C505 / C505C

C505A / C505CA

Data Sheet 36 08.00

Figure 15

CAN Controller Block Diagram

MCB02736

Bit

Timing

Logic

Timing

Generator

BTL-Configuration

CRC

Gen./Check

TX/RX Shift Register

TXDC RXDC

Intelligent

Interrupt

Memory

Processor

Status

Stream

Bit

Error

Logic

Management

Messages

Handlers

Control

Status +

to internal Bus

Clocks

Control

Messages

(to all)

C505 / C505C

C505A / C505CA

Data Sheet 37 08.00

CAN Controller Software Initialization

The very first step of the initialization is the CAN controller input clock selection. A divide-by-2

prescaler is enabled by de fault after reset (figure 16). Setting bi t CMOD (SYSCON.3) di sable s the

prescaler. The purpose of the prescaler selection is:

–to ensure that the CAN controller is operable when fosc is over 10 MHz (bit CMOD =0)

–to achieve the maximum CAN baudrate of 1 Mbaud when fosc is 8 MHz (bit CMOD=1)

Figure 16

CAN controller Input Clock Selection

Note : The switch configura tio n s how s th e res et stat e of bit CMOD.

SYSCON.3

(CMOD)

MCS03296

fOSC Full-CAN

Module

CAN

Condition: CMOD = 0, when > 10 MHz

OSC

Frequency (MHz) CMOD

(SYSCON.3) BRP

(BTR0.0-5) CAN

baudrate

(Mbaud/sec)

fOSC fCAN

8 8 1 000000B1

8 4 0 000000B0.5

16 8 0 000000B1

C505 / C505C

C505A / C505CA

Data Sheet 38 08.00

8-Bit A/D Converter (C505 and C505C only)

The C505/C505C includes a high performance / high speed 8-bit A/D converter (ADC) with 8 analog

input channels. It operates with a successive approximation technique and provides the following

features:

–8 multiplexed input channels (port 1), which can also be used as digital outputs/inputs

–8-bit resolution

–Internal start-of-conversion trigger

–Interrupt request generation after each conversion

–Single or continuous conversion mode

The 8-bit ADC uses two clock signals for operation : the conversion clock fADC (=1/tADC) and the

input clock fIN (1/tIN). fADC is derived from the C505 system clock fOSC which is applied at the XTAL

pins via the ADC clock prescaler as shown in figure 17. The input clock is equal to fOSC. The

conversion clock fADC is limited to a maximum frequency of 1.25 MHz. Therefore, the ADC clock

prescaler must be programmed to a value which assures that the conversion clock does not exceed

1.25 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.

Figure 17

8-Bit A/D Converter Clock Selection

MCS03299

fOSC

MUX

Clock Prescaler

Conversion Clock

Input Clock

fADC

ADCL1

A / D

Converter

Condition: ADC max

f< 1.25 MHz IN

f=fOSC =CLP

ADCL0

MCU System Clock

Rate (fOSC)fIN

[MHz] Prescaler

Ratio fADC

[MHz] ADCL1 ADCL0

2 MHz 2 ÷ 4 0.5 0 0

5 MHz 5 ÷ 4 1.25 0 0

6 MHz 6 ÷ 8 0.75 0 1

10 MHz 10 ÷ 8 1.25 0 1

12 MHz 12 ÷ 16 0.75 1 0

16 MHz 16 ÷ 16110

20 MHz 20 ÷ 16 1.25 1 0

C505 / C505C

C505A / C505CA

Data Sheet 39 08.00

Figure 18

Block Diagram of the 8-Bit A/D Converter

ADC

Shaded Bit locations are not used in ADC-functions.

AGND

AREF

OSC

Port 1

Conversion

Prescaler

Clock

MUX

fConversion Clock

Input Clock fIN

S&H

ADCON1 (DC )

ADCON0 (D8 )

ADCL1

ADCL0

IRCON (C0 )

P1ANA (90 )

EAN7 EAN6

BSY

EAN5 EAN4

IEN1 (B8 )

Write to ADST

MCB03298

(DA )

ADST

conversion

Converter

A / D

Continuous Mode

Single /

Start of

MSB

LSB

(D9 )

ADDAT

Bus

Internal

ADM MX2

MX2

EAN3 EAN2

MX1

MX0

EAN1

IADC

EAN0

EADC

Bus

Internal

CLK

SWI

IEX3

IEX4

IEX5IEX6

TF2EXF2

ECAN

EX3

EX4

EX5EX6

SWDT

EXEN2

C505 / C505C

C505A / C505CA

Data Sheet 40 08.00

10-Bit A/D Converter (C505A and C505CA only)

The C505A/C505CA includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8

analog input channels. It operates with a successive approximation technique and uses self

calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D

converter provides the following features:

–8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs

–10-bit resolution

–Single or continuous conversion mode

–Internal start-of-conversion trigger capability

–Interrupt request generation after each conversion

–Using successive approximation conversion technique via a capacitor array

–Built-in hidden calibration of offset and linearity errors

The 10-bit ADC use s two clock si gnals for op eration : the c onve rsion cloc k f ADC (=1/tADC) and the

input clock fIN (=1/tIN). fADC is derived from the C505 system clock fOSC which is applied at the

XTAL pins. The inpu t cl ock fIN is equal to fOSC The con version fADC clock is limited to a maximum

frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which

assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the

bits ADCL1 and ADCL0 of SFR ADCON1.

Figure 19

10-Bit A/D Converter Clock Selection

MCS03635

fOSC

MUX

Clock Prescaler

Conversion Clock

Input Clock

fADC

ADCL1

A / D

Converter

Condition: ADC max

f< 2 MHz IN

f=fOSC =CLP

ADCL0

MCU System Clock

Rate (fOSC)fIN

[MHz] Prescaler

Ratio fADC

[MHz] ADCL1 ADCL0

2 MHz 2 ÷ 4 0.5 0 0

6 MHz 6 ÷ 4 1.5 0 0

8 MHz 8 ÷ 4200

12 MHz 12 ÷ 8 1.5 0 1

16 MHz 16 ÷ 8201

20 MHz 20 ÷ 16 1.25 1 0

C505 / C505C

C505A / C505CA

Data Sheet 41 08.00

Figure 20

Block Diagram of the 10-Bit A/D Converter

ADC

Shaded Bit locations are not used in ADC-functions.

AGND

AREF

OSC

Port 1

Conversion

Prescaler

Clock

MUX

fConversion Clock

Input Clock f

S&H

ADCON1 (DC )

ADCON0 (D8 )

ADCL1

ADCL0

IRCON (C0 )

P1ANA (90 )

EAN7 EAN6

BSY

EAN5 EAN4

IEN1 (B8 )

Write to ADDATL

MCB03636

(DA )

ADST

conversion

Converter

A / D

Continuous Mode

Single /

Start of

MSB

LSB

(D9 )

ADDAT

Bus

Internal

ADM MX2

MX2

EAN3 EAN2

MX1

MX0

EAN1

IADC

EAN0

EADC

Bus

Internal

IEX5

EX5

EXF2

EXEN2

BD CLK

TF2

SWDT

IEX6

EX6

IEX4

EX4

IEX3

EX3

SWI

ECAN

ADDATH

(D9

)ADDATL

(DA

)

C505 / C505C

C505A / C505CA

Data Sheet 42 08.00

Interrupt System

The C505 provides 12 interrupt vectors with four priority levels. Five interrupt requests can be

generated by the on-chip peri pherals (timer 0, timer 1, timer 2, serial interfac e, A/D converter). One

interrupt can be generated by the CAN controller (C505C and C505CA only) or by a software setting

and in this case the interrupt vector is the same. Six interrupts may be triggered externally (P3.2/

INT0, P3.3/INT1, P1.0/AN0/INT3/CC0, P1.1/AN1/INT4/CC1, P1.2/AN2/INT5/CC2, P1.3/AN3/INT6/

CC3). Additionally, the P1.5/AN5/T2EX can trigger an interrupt. The wake-up from power-down

mode interrupt has a s peci al functi onali ty whic h a llows to exit from the software power-down mode

by a short low pulse at either pin P3.2/INT0 or the pin P4.1/RXDC.

Figure 21 to 23 give a general overview of the interrupt sources and illustrate the request and the

control flags which are described in the next sections. Table 9 lists all interrupt sources with their

request flags and interrupt vector addresses.

Table 9

Interrupt Source and Vectors

Interrupt Source Interrupt Vector Address Interrupt Request Flags

External Interrupt 0 0003HIE0

Timer 0 Overflow 000BHTF0

External Interrupt 1 0013HIE1

Timer 1 Overflow 001BHTF1

Serial Channel 0023HRI / TI

Timer 2 Overflow / Ext. Reload 002BHTF2 / EXF2

A/D Converter 0043HIADC

CAN Controller / Software Interrupt 004BH– / SWI

External interrupt 3 0053HIEX3

External Interrupt 4 005BHIEX4

External Interrupt 5 0063HIEX5

External interrupt 6 006BHIEX6

Wake-up from power-down mode 007BH–

C505 / C505C

C505A / C505CA

Data Sheet 43 08.00

Figure 21

Interrupt Structure, Overview Part 1

Note: Each of the 15 CAN controller message objects (C505C and C505CA only), shown in the

shaded area of Figure 21 provides the bits/flags.

ET0

IP1.1 IP0.1

IADC EADC

EX0

IP1.0 IP0.0

IE0

IEN0.0

TCON.1 0003H

0043

000B

004B

IEN1.0

IRCON.0

IEN1.1

IEN0.1

A / D Converter

IEN0.7

Highest

Priority Level

Lowest

Priority Level

MCB03303

IT0

TCON.5

TF0

TCON.0

P3.2 /

INT0

Overflow

Timer 0

Bit addressable

Request flag is cleared by hardware

IRCON.1

C505C and C505CA Only

ECAN

SWI

MCR0.5 / 4

MCR0.3 / 2

Receive

Message

Transmit

Message

Error

Status

MCR0.0 / 1

INTPND

CR.1CR.3

RXIE

TXIE >1

EIE

CR.2

SIE

CAN Controller Interrupt Sources

ECAN

C505 / C505C

C505A / C505CA

Data Sheet 44 08.00

Figure 22

Interrupt Structure, Overview Part 2

ET1

IEX3 EX3

EX1

IP1.2 IP0.2

IE1

IEN0.2

TCON.3 0013

0053

001B

005B

IEN1.2

IRCON.2

IEN1.3

IEN0.3

IEN0.7

Highest

Priority Level

Lowest

Priority Level

MCB03304

IT1

TCON.7

TF1

TCON.2

P3.3 /

INT1

Overflow

Timer 1

Bit addressable

Request flag is cleared by hardware

AN0 /

INT3 /

T2CON.6

I3FR

P1.0 /

CC0

IP0.3IP1.3

IRCON.3

IEX4

AN1 /

P1.1 /

INT4 /

CC1 EX4

C505 / C505C

C505A / C505CA

Data Sheet 45 08.00

Figure 23

Interrupt Structure, Overview Part 3

ET2

IEX5 EX5

IP1.4 IP0.4

IEN0.4

SCON.0 0023H

0063

002B

006B

IEN1.4

IRCON.4

IEN1.5

IEN0.5

IEN0.7

Highest

Priority Level

Lowest

Priority Level

MCB03305

USART

Overflow

Timer 2

Bit addressable

Request flag is cleared by hardware

IP0.5IP1.5

IRCON.5

IEX6

AN2 /

P1.2 /

INT5 /

CC2

EX6

SCON.1

CC3

INT6 /

P1.3 /

IRCON.7

EXF2

TF2

IRCON.6 >1

IEN1.7

EXEN2

AN5 /

T2EX

P1.5 /

C505 / C505C

C505A / C505CA

Data Sheet 46 08.00

Fail Save Mechanisms

The C505 offers e nhance d fail safe me chanisms , which all ow an automati c recovery from soft ware

upset or hardware failure :

–a programmable watchdog timer (WDT), with variable time-out period from 192 µs up to

approx. 393.2 ms at 16 MHz (314.5 ms at 20 MHz).

–an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller i nto reset state in c ase the on-chip osc illator fails; i t also provides the clock for

a fast internal reset after power-on.

The watchdog timer in the C505 is a 15-bit timer, which is incremented by a count rate of fOSC/12

upto fOSC/192. The system clock of the C505 is divided by two prescalers, a divide-by-two and a

divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the

watchdog timer can be written. Figure 24 shows the block diagram of the watchdog timer unit.

Figure 24

Block Diagram of the Programmable Watchdog Timer

The watchdog timer can be started by software (bit SWDT in SFR IEN1) but it cannot be stopped

during active mode of the device. If the software fails to refresh the running watchdog timer an

internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the

content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh

sequence consists of two consequtive instructions which set the bits WDT and SWDT each. The

reset cause (external reset or reset caused by the watchdog) can be examined by software (flag

WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and

power down mode of the processor.

MCB03306

IP0 (A9 )

OSC

WDTS

2 16

WDTL

WDTH

/ 6

External HW Reset

Control Logic

IEN0 (A8 )

IEN1 (B8 )

670

WDT Reset - Request

WDTPSEL

WDTREL (86 )

WDT

SWDT

OWDS

C505 / C505C

C505A / C505CA

Data Sheet 47 08.00

Oscillator Watchdog

The oscillator watchdog unit serves for three functions:

–Monitoring of the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency

of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC

oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-

chip oscillator has a higher frequency than the RC oscillator), the part, in order to allow the

oscillator to stabilize, executes a final reset phase of typ. 1 ms; then the oscillator watchdog

reset is released and the part starts program execution from address 0000H again.

–Fast internal reset after power-on

The oscillator watchd og unit provides a cl ock supply for the reset before the on -chip oscillator

has started. The oscillator watchdog unit also works identically to the monitoring function.

–Control of external wake-up from software power-down mode

When the power-down mode is left by a low level at the P3.2/INT0 pin or the P4.1/RXDC pin,

the oscillator watchd og unit as sures that the mi croco ntrolle r resumes operatio n (exec ution of

the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the

RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when

power-down mode is released. When the on-chip oscillator has a higher frequency than the

RC oscillator, the microcontroller starts program execution by processing a power down

interrupt after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.

C505 / C505C

C505A / C505CA

Data Sheet 48 08.00

Figure 25

Functional Block Diagram of the Oscillator Watchdog

Int. Clock

XTAL2

XTAL1

OWDS

MCB03308

IP0 (A9 )

3 MHz

fRC

Delay

P4.1 / RXDC

Start /

Stop

Start /

Stop

Mode Activated

Power - Down

Power-Down Mode

Wake - Up Interrupt

Internal Reset

P3.2 / INT0 Control

(PCON1.4)(PCON1.7)

EWPD

Frequency

Comparator

On-Chip

Oscillator

Logic

Oscillator

Logic

Control

P4.1/RXDC

C505 / C505C

C505A / C505CA

Data Sheet 49 08.00

Power Saving Modes

The C505 provides two basic power saving modes, the idle mode and the power down mode.

Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate

in normal operating mode and it can be also used for further power reduction in idle mode.

–Idle mode

In the idle mode the main oscillator of the C505 continues to run, but the CPU is gated off from

the clock signal. All peripheral units are further provided with the clock. The CPU status is

preserved in its entirety. The idle mode can be terminated by any enabled interrupt of a

peripheral unit or by a hardware reset.

–Power down mode

The operation of the C50 5 is comple tely stopped a nd the oscill ator is turned off. Th is mode is

used to save the contents of the internal RAM with a very low standby current. Power down

mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/

INT0.or P4.1/RXDC.

–Slow down mode

The controller keeps up the full operating functionality, but its normal clock frequency is

internally divided by 32. This slows down all parts of the controller, the CPU and all

peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency

significantly reduces power consumption.

In the power down mode of operati on, VDD can be reduced to m inimize power consumpti on. It must

be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD

is restored to its normal operating lev el, before the power down mode is terminat ed. Table 10 gives

a general overview of the entry and exit procedures of the power saving modes.

Table 10

Power Saving Modes Overview

Mode Entering

(Instruction

Example)

Leaving by Remarks

Idle Mode ORL PCON, #01H

ORL PCON, #20H Ocurrence of an

interrupt from a

peripheral unit

CPU clock is stopped;

CPU maintains their data;

peripheral units are active (if

enabled) and provided with

clock

Hardware Reset

Power Down Mode ORL PCON, #02H

ORL PCON, #40H Hardware Reset O scillator is stopped;

contents of on-chip RAM and

SFR’s are maintained;

Short low pulse at

pin P3.2/INT0 or

P4.1/RXDC

Slow Down Mode ORL PCON,#10H ANL PCON,#0EFH

Hardware Reset

Oscillator frequency is

reduced to 1/32 of its nominal

frequency

C505 / C505C

C505A / C505CA

Data Sheet 50 08.00

OTP Memory Operation (C505A-4E and C505CA-4E only)

The C505A-4E/C505CA-4E contains a 32K by te one-ti me program mable (OTP) program me mory.

With the C505A-4E/C505CA-4E fast programming cycles are achieved (1 byte in 100 µsec). Also

several levels of OTP memory protection can be selected.

For programming of the device, the C505A-4E/C505CA-4E must be put into the programming

mode. This typically is done not in-system but in a special programming hardware. In the

programming mode the C505A-4E/C505CA-4E operates as a slave device similar as an EPROM

standalone m emory device and mus t be controlled with add ress/data informatio n, control lines, and

an external 11.5V programming voltage. Figure 26 shows the pins of the C505A-4E/C505CA-4E

which are required for controlling of the OTP programming mode.

Figure 26

Programming Mode Configuration

Port 0 D0-D7

VDD VSS

C505A-4E

C505CA-4E

PROG

A0-A7 / Port 2

EA/VPP

PMSEL0

PSEL

RESET

PSEN

PMSEL1 PRD

A8-A14

PALE

XTAL1

XTAL2

C505 / C505C

C505A / C505CA

Data Sheet 51 08.00

Pin Configuration in Programming Mode

Figure 27

P-MQFP-44 Pin Configuration of the C505A-4E/C505CA-4E in Programming Mode (Top View)

EA / V

N.C.

A5 / A13

PROG

A6 / A14

PSEN

A4 / A12

A3 / A11

A2 / A10

A1 / A9

A0 / A8

VDD

XTAL1

XTAL2

N.C.

VSS

32 31 30 29 28 27 26 25 24 2322

123456789 10 11

N.C.

RESET

PMSEL0

PMSEL1

PSEL

PRD

PALE

N.C.

C505A-4E

C505CA-4E

C505 / C505C

C505A / C505CA

Data Sheet 52 08.00

The following Table 11 contains the fun ction al desc ripti on of all C505A-4E/C505CA-4E pins wh ich

are required for OTP memory programming.

Table 11

Pin Definitions and Functions in Programming Mode

Symbol Pin Number I/O

*) Function

RESET 4 I Reset

This input must be at static “1“ (active) level during the whole

programming mode.

PMSEL0

PMSEL1 5

IProgramming mode selection pins

These pins are used to select the different access modes in

programming mode. PMSEL1,0 must satisfy a setup time to the

rising edge of PALE. When the logic level of PMSEL1,0 is

changed, PALE must be at low level.

PSEL 8IBasic programming mode select

This input is used for the basic programming mode selection

and must be switched according figure 3-1.

PRD 9IProgramming mode read strobe

This input is used for read access control for OTP memory read,

Version Register read, and lock bit read operations.

PALE 10 I Programming address latch enable

PALE is used to latch the hi gh address li nes. The high a ddress

lines mus t satisfy a setup a nd hold time to/from the falli ng edge

of PALE. PALE must be at low level when the logic level of

PMSEL1,0 is changed.

XTAL2 14 O XTAL2

Output of the inverting oscillator amplifier.

XTAL1 15 I XTAL1

Input to the oscillator amplifier.

VSS 16 –Circuit ground potential

must be applied in programming mode.

VDD 17 –Power supply terminal

must be applied in programming mode.

*) I = Input

O=Output

PMSEL1 PMSEL0 Access Mode

00Reserved

0 1 Read version bytes

1 0 Program/read lock bits

1 1 Program/read OTP memory byte

C505 / C505C

C505A / C505CA

Data Sheet 53 08.00

P2.0-7 18-25 I Address lines

P2.0-7 are used as multiplexed address input lines A0-A7 and

A8-A14. A8-A14 must be latched with PALE.

PSEN 26 I Program store enable

This input must be at static “0“ level during the whole

programming mode.

PROG 27 I Programming mode write strobe

This input is used in programming mode as a write strobe for

OTP memory program, and lock bit write operations During

basic programm ing mode selection a lo w level must be appli ed

to PROG .

EA/VPP 29 –External Access / Programming voltage

This pin must be at 11.5V (VPP) voltage level during

programming of an OTP memory byte or lock bit. During an

OTP memory read op eration th is pi n mus t be at VIH high level.

This pin is also us ed for basic programmi ng mode selectio n. At

basic programm ing mode selection a lo w level must be appli ed

to EA/VPP.

D7-0 30-37 I/O Data lines 0-7

During programming mode, data bytes are transferred via the

bidirectional port 0 data lines.

N.C. 1-3, 6, 11-13,

28, 38-44 –Not Connected

These pins should not be connected in programming mode.

*) I = Input

O=Output

Table 11

Pin Definitions and Functions in Programming Mode (cont’d)

Symbol Pin Number I/O

*) Function

C505 / C505C

C505A / C505CA

Data Sheet 54 08.00

Basic Programming Mode Selection

The basic programming mode selection scheme is shown in figure 28.

Figure 28

Basic Programming Mode Selection

RESET

PSEN

PROG

EA/VPP

“1“

“0“

PSEL

“0“

VDD

Clock

(XTAL1/XTAL2)

stable

PRD

PALE

“1“

“0“

Ready for access

mode selection

During this period signals

are not actively driven

0V VIH

VPP

PMSEL1,0 0,1

C505 / C505C

C505A / C505CA

Data Sheet 55 08.00

Lock Bits Programming / Read

The C505A-4E/C505CA-4E has two programmable lock bits which, when programmed according

tabie 13, provide four levels of protection for the on-chip OTP code memory. The state of the lock

bits can also be read.

Table 12

Access Modes Selection

Access Mode EA/

VPP PROG PRD PMSEL Address

(Port 2) Data

(Port 0)

Program OTP memory byte VPP HH H A0-7

A8-14 D0-7

Read OTP memory byte VIH H

Program OTP lock bits VPP HH L –D1,D0 see

table 13

Read OTP lock bits VIH H

Read OTP version byte VIH H L H Byte addr.

of sign. byte D0-7

Table 13

Lock Bit Protection Types

Lock Bits at D1,D0 Protection

Level Protection Type

D1 D0

1 1 Level 0 The OTP lock feature is disabled. During normal operation of

the C505A-4E/C505CA-4E, the state of the EA pin is not

latched on reset.

1 0 Level 1 During normal operation of the C505A-4E/C505CA-4E, MOVC

instructions executed from external program memory are

disabled from fetching code bytes from internal memory. EA is

sampled and latched on reset. An OTP memory read operation

is only possible using the ROM/OTP verification mode 2 for

protection level 1. Further programming of the OTP memory is

disabled (reprogramming security ).

0 1 Level 2 Same as level 1, but also OTP memory read operation using

OTP verification mode is disabled.

0 0 Level 3 Same as level 2; but additionally external code execution by

setting EA=low during normal operation of the C505A-4E/

C505CA-4E is no more possible.

External code execution, which is initiated by an internal

program (e.g. by an internal jump instruction above the ROM

boundary), is still possible.

C505 / C505C

C505A / C505CA

Data Sheet 56 08.00

Absolute Maximum Ratings

Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for longer

periods may affect device reliability. During absolute maximum rating overload conditions

(VIN >VDD or VIN <VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed

the values defined by the absolute maximum ratings.

Parameter Symbol Limit Values Unit Notes

min. max.

Storage temperature TST –65 150 ° C –

Voltage on VDD pins with respect

to ground (VSS)VDD –0.5 6.5 V –

Voltage on any pin with respect

to ground (VSS)VIN –0.5 VDD + 0.5 V –

Input current on any pin during

overload condition –10 10 mA –

Absolute sum of all input currents

during overload condition | 100 mA | mA –

Power dissipation PDISS 1W–

C505 / C505C

C505A / C505CA

Data Sheet 57 08.00

Operating Conditions

Parameter Symbol Limit Values Unit Notes

min. max.

Supply voltage VDD 4.25 5.5 V Active mode,

fosc max = 20 MHz

2 5.5 V PowerDown mode

Ground voltage VSS 0 V Reference voltage

Ambient temperature °C–

SAB-C505 TA070

SAF-C505 TA-40 85

SAH-C505 TA-40 110

SAK-C505 TA-40 125

Analog reference

voltage VAREF 4VDD + 0.1 V –

Analog ground voltage VAGND VSS –0.1 VSS + 0.2 V –

Analog input voltage VAIN VAGND -0.2 VAREF +0.2 V –

XTAL clock fosc 220

(with 50% duty

cycle)

MHz 1)

1) For the extended temperature range -40 °C to 110 °C (SAH) and -40 °C to 125 °C (SAK), the

devices C505-2R, C505-L, C505C-2R and C505C-L have the max. operating frequency of

16MHz with 50% clock duty cycle.

C505 / C505C

C505A / C505CA

Data Sheet 58 08.00

DC Characteristics

(Operating Conditions apply)

Notes see page 60

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input low voltages

all except EA, RESET

EA pin

RESET pin

VIL

VIL1

VIL2

–0.5

0.2 VDD - 0.1

0.2 VDD - 0.3

0.2 VDD + 0.1

–

Input high voltages

all except XTAL1, RESET

XTAL1 pin

RESET pin

VIH

VIH1

VIH2

0.2 VDD +0.9

0.7 VDD

0.6 VDD

VDD + 0.5

–

Output low voltages

Ports 1, 2, 3, 4

Port 0, ALE, PSEN VOL

VOL1

–

–0.45

0.45 V

VIOL = 1.6 mA 1)

IOL = 3.2 mA 1)

Output high voltages

Ports 1, 2, 3, 4

Port 0 in external bus mode,

ALE, PSEN

VOH

VOH2

2.4

0.9 VDD

2.4

0.9 VDD

–

IOH =–80 µA

IOH =–10 µA

IOH =–800 µA

IOH =–80 µA 2)

Logic 0 input current

Ports 1, 2, 3, 4 IIL –10 –70 µAVIN =0.45V

Logical 1-to-0 transition current

Ports 1, 2, 3, 4 ITL –65 –650 µAVIN =2V

Input leakage current

Port 0, AN0-7 (Port 1), EA ILI –±1µA0.45<VIN <VDD

Input high current to RESET IIH 5100µA

14)

0.6 VDD <VIN<VDD

Pin capacitance CIO –10 pF fc=1MHz,

TA=25°C

Overload current IOV –± 5mA 3) 4)

Programming voltage VPP 10.9 12.1 V11.5 V ± 5% 5)

Supply current at EA/VPP 30 mA 6)

C505 / C505C

C505A / C505CA

Data Sheet 59 08.00

Power Supply Currents

Notes see page 60

Parameter Symbol Limit Values Unit Test Condition

typ. 12) max.13)

C505 /

C505C Active Mode 12 MHz

20 M Hz IDD

IDD

19.3

31.3 27.0

39 mA 7)

Idle Mode 12 MHz

20 M Hz IDD

IDD

10.3

16.2 13.0

21.0 mA 8)

Active Mode with

slow-down enabled 12 MHz

20 M Hz IDD

IDD

3.9

4.8 5.5

7.5 mA 9)

Idle Mode with

slow-down enabled 12 MHz

20 M Hz IDD

IDD

3.2

4.0 5.0

7.0 mA 10)

Power down current IPD 10 50 µAVDD = 2..5.5 V 11)

C505A-

C505CA

-4E

Active Mode 16 MHz

20 M Hz IDD

IDD

28.7

35.2 30.7

37.6 mA 7)

Idle Mode 16 MHz

20 M Hz IDD

IDD

14.9

17.7 15.9

18.9 mA 8)

Active Mode with

slow-down enabled 16 MHz

20 M Hz IDD

IDD

9.9

12.3 12.8

15.6 mA 9)

Idle Mode with

slow-down enabled 16 MHz

20 M Hz IDD

IDD

5.1

6.3 5.6

6.8 mA 10)

Power down current IPD 5.6 20 µAVDD = 2..5.5 V 11)

C505A-

4R /

C505CA

-4R /

C505A-

2R /

C505CA

-2R /

C505A-

L /

C505CA

-L

Active Mode 16 MHz

20 M Hz IDD

IDD

22.8

27.6 29.2

35.3 mA 7)

Idle Mode 16 MHz

20 M Hz IDD

IDD

12.7

15.0 16.3

19.3 mA 8)

Active Mode with

slow-down enabled 16 MHz

20 M Hz IDD

IDD

6.6

7.3 8.2

9.3 mA 9)

Idle Mode with

slow-down enabled 16 MHz

20 M Hz IDD

IDD

5.0

5.3 5.9

6.5 mA 10)

Power down current IPD 5.3 30 µAVDD = 2..5.5 V 11)

C505 / C505C

C505A / C505CA

Data Sheet 60 08.00

Notes :

1) Capacitive lo ading on port s 0 and 2 may c ause spurious noise p uls es t o be superimposed on the VOL of ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these

pins ma ke 1- to-0 trans itions durin g bus o peration. In the w orst ca se (capac itive loadi ng > 100 pF), the noi se

pulse on AL E line may exce ed 0.8 V. In such cases it may be des irable to qua lify ALE with a schmitt -trigger,

or use an ad dres s latch with a schm it t-trigger strob e input.

2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the

0.9 VDD specification when the address lines are stabilizing.

3) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified

operat ing range (i.e. VOV > VDD +0.5V or VOV < VSS - 0.5 V). The absolute sum of inp ut currents on all port

pins m ay not exceed 50 mA. The supply voltage VDD and VSS must remain within the specified limits.

4) Not 100% tested, guaranteed by des ign characterization.

5) Only valid for C505 A-4E and C505CA-4E.

6) Only valid for C505 A-4E and C505CA-4E in progra m m ing m ode.

7) IDD (active mode) is measured with:

XTAL1 driven with tR, tF= 5 ns, 50% duty cycle , VIL =VSS +0.5V, VIH =VDD –0.5 V; XTAL 2 = N.C.;

EA =Port 0=RESET=VDD ; all other pins are disconnected.

8) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL1 driven with tR, tF= 5 n s, 50% duty cycle, VIL =VSS +0.5V, VIH =VDD –0.5 V; XTAL2 = N.C.;

RESET = EA =VSS ; Port0 = VDD ; all other pins are disconnected; the microcontroller is put into idle mode by

software;

9) IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled;

XTAL1 driven with tR, tF= 5 n s, 50% duty cycle, VIL =VSS +0.5V, VIH =VDD –0.5 V; XTAL2 = N.C.;

RESET = EA =VSS ; all other pins are disconnected; the microcontroller is put into slow-down mode by

software;

10) IDD (idle mo de w ith s low-d own mode ) is me asure d wit h all outpu t pin s dis conn ected and with a ll p eriphera ls

disabled;

XTAL1 driven with tR, tF= 5 n s, 50% duty cycle, VIL =VSS +0.5V, VIH =VDD –0.5 V; XTAL2 = N.C.;

RESET = EA =VSS ; Port0 = VDD ; all other pins are disco nnected; the m icrocontroller is p ut into idle mode

with slow- dow n enabled by so ftw are;

11) IPD (power-d ow n m ode) is measured under following conditions :

Port 0 = EA = VDD ; RESET =VSS ; XTAL2 = N.C.; XTAL1 = VSS ; VAGND =VSS ; VAREF =VDD ;

all other pins are disconnect ed.

12) The typical IDD values are periodically measured at TA = +25 °C but not 100% tested.

13) The maximum IDD values are mea s ured under worst cas e c onditions (TA = 0 °C or -40 °C and VDD =5.5V)

14) The values are valid for C505C A-4R, C505C A-2R , C505CA-L, C505A-4R, C505A-2R and C505A-L only.

C505 / C505C

C505A / C505CA

Data Sheet 61 08.00

Figure 29

IDD Diagram of C505 and C505C

C505/C505C : Power Supply Current Calculation Formulas

Note : fosc is the oscillator frequenc y in MHz . IDD values are giv en in mA.

Parameter Symbol Formula

Active mode IDD typ

IDD max

1.5 * fOSC + 1.3

1.5 * fOSC + 9.0

Idle mode IDD typ

IDD max

0.74 * fOSC + 1.4

1.0 * fOSC + 1.0

Active mode with

slow-down enabled IDD typ

IDD max

0.11 * fOSC + 2.6

0.25 * fOSC + 2.5

Idle mode with

slow-down enabled IDD typ

IDD max

0.1 * fOSC + 2.0

0.25 * fOSC + 2.0

IDD

[mA]

IDD max

IDD typ

fOSC

[MHz]

12842016

C505

C505C

Idle Mode

Active Mode

Idle Mode+Slow-down

Active Mode+Slow-down

C505 / C505C

C505A / C505CA

Data Sheet 62 08.00

Figure 30

IDD Diagram of C505A-4E and C505CA-4E

C505A-4E/C505CA-4E : Power Supply Current Calculation Formulas

Note : fosc is the oscillator frequenc y in MHz . IDD values are giv en in mA.

Parameter Symbol Formula

Active mode IDD typ

IDD max

1.63 * fOSC + 2.6

1.74 * fOSC + 2.8

Idle mode IDD typ

IDD max

0.69 * fOSC + 3.9

0.74 * fOSC + 4.1

Active mode with

slow-down enabled IDD typ

IDD max

0.6 * fOSC + 0.3

0.7 * fOSC + 1.6

Idle mode with

slow-down enabled IDD typ

IDD max

0.3 * fOSC + 0.3

0.3 * fOSC + 0.8

IDD

[mA]

IDD max

IDD typ

fOSC

[MHz]

12842016

C505A-4E

C505CA-4E

Idle Mode

Active Mode

Idle Mode+Slow-down

Active Mode+Slow-down

C505 / C505C

C505A / C505CA

Data Sheet 63 08.00

Figure 31

IDD Diagram of C505A-4R/C505A-2R/C505A-L/C505CA-4R/C505CA-2R/C505CA-L

C505A-4R/C505A-2R/C505A-L/C505CA-4R/C505CA-2R/C505CA-L :

Power Supply Current Calculation Formulas

Note : fosc is the oscillator frequenc y in MHz . IDD values are giv en in mA.

Parameter Symbol Formula

Active mode IDD typ

IDD max

1.19 * fOSC + 3.77

1.54 * fOSC + 4.47

Idle mode IDD typ

IDD max

0.57 * fOSC + 3.55

0.75 * fOSC + 4.26

Active mode with

slow-down enabled IDD typ

IDD max

0.18 * fOSC + 3.74

0.28 * fOSC + 3.67

Idle mode with

slow-down enabled IDD typ

IDD max

0.07 * fOSC + 3.91

0.14 * fOSC + 3.64

IDD

[mA]

IDD max

IDD typ

fOSC

[MHz]

12842016

C505A-4R

C505A-2R

C505A-L

C505CA-4R

C505CA-2R

C505CA-L

Active Mode

Idle Mode

Active Mode+Slow-down

Idle Mode+Slow-down

C505 / C505C

C505A / C505CA

Data Sheet 64 08.00

A/D Converter Characteristics of C505 and C505C

(Operating Conditions apply)

Notes see next page.

Clock calculation table :

Further timing conditions : tADC min = 800 ns

tIN = 1 / fOSC = tCLP

Parameter Symbol Limit Values Unit Test Condition

min. max.

Analog input voltage VAIN VAGND -

0.2 VAREF +

0.2 V1)

Sample time tS–64 x tIN

32 x tIN

16 x tIN

8 x tIN

ns Prescaler ÷ 32

Prescaler ÷ 16

Prescaler ÷ 8

Prescaler ÷ 4 2)

Conversion cycle time tADCC –320 x tIN

160 x tIN

80 x tIN

40 x tIN

ns Prescaler ÷ 32

Prescaler ÷ 16

Prescaler ÷ 8

Prescaler ÷ 4 3)

Total unadjusted error TUE –± 2LSBV

SS+0.5V ≤ VAIN ≤ VDD-0.5V 4)

Internal resistance of

reference voltage source RAREF –tADC / 500

- 1 kΩtADC in [ns] 5) 6)

Internal resistance of

analog source RASRC –tS / 500

- 1 kΩtS in [ns] 2) 6)

ADC input capacitance CAIN –50 pF 6)

Clock Prescaler

Ratio ADCL1, 0 tADC t

S t

ADCC

÷ 32 1 1 32 x tIN 64 x tIN 320 x tIN

÷ 16 1 0 16 x tIN 32 x tIN 160 x tIN

÷ 8 0 1 8 x tIN 16 x tIN 80 x tIN

÷ 4 0 0 4 x tIN 8 x tIN 40 x tIN

C505 / C505C

C505A / C505CA

Data Sheet 65 08.00

Notes:

1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in

these cases will be 00H or FFH, respecti ve ly.

2) During the sam ple t ime the in put cap aci tance CAIN must b e cha rged /disch arged b y th e exter nal source. The

interna l res istance of the analog sou rc e mu st allow the capaci ta nc e to reac h th eir fi nal v olt age level within tS.

After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.

3) This parameter includes the sample time tS, the time for determining the digital result. Values for the

conversio n clo ck tADC depend on programming and can be taken from the table on the previous page.

4) TUE (max.) is tested at –40 ≤ TA ≤=125 °C ; VDD ≤ 5.5 V; VAREF ≤ VDD + 0.1 V and VSS=≤ VAGND. It is

guaranteed by design characterization for all other voltages within the defined voltage range.

If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload

currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is

permissible.

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the

indicated time. The max im um int ernal resistanc e results from the programmed co nv ers ion timing.

6) Not 100% tested, but guaranteed by des ign characteriz at ion.

C505 / C505C

C505A / C505CA

Data Sheet 66 08.00

A/D Converter Characteristics of C505A and C505CA

(Operating Conditions apply)

Notes see next page.

Clock calculation table :

Further timing conditions : tADC min = 500 ns

tIN = 1 / fOSC = tCLP

Parameter Symbol Limit Values Unit Test Condition

min. max.

Analog input voltage VAIN VAGND VAREF V1)

Sample time tS–64 x tIN

32 x tIN

16 x tIN

8 x tIN

ns Prescaler ÷ 32

Prescaler ÷ 16

Prescaler ÷ 8

Prescaler ÷ 4 2)

Conversion cycle time tADCC –384 x tIN

192 x tIN

96 x tIN

48 x tIN

ns Prescaler ÷ 32

Prescaler ÷ 16

Prescaler ÷ 8

Prescaler ÷ 4 3)

Total unadjusted error TUE –± 2LSBV

SS+0.5V ≤ VAIN ≤ VDD-0.5V 4)

–± 4LSBV

SS < VAIN < VDD+0.5V

VDD - 0.5 V < VAIN < VDD 4)

Internal resistance of

reference voltage source RAREF –tADC / 250

- 0.25 kΩtADC in [ns] 5) 6)

Internal resistance of

analog source RASRC –tS / 500

- 0.25 kΩtS in [ns] 2) 6)

ADC input capacitance CAIN –50 pF 6)

Clock Prescaler

Ratio ADCL1, 0 tADC t

S t

ADCC

÷ 32 1 1 32 x tIN 64 x tIN 384 x tIN

÷ 16 1 0 16 x tIN 32 x tIN 192 x tIN

÷ 8 0 1 8 x tIN 16 x tIN 96 x tIN

÷ 4 0 0 4 x tIN 8 x tIN 48 x tIN

C505 / C505C

C505A / C505CA

Data Sheet 67 08.00

Notes:

1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in

these cases will be X000H or X3F FH, respe ctively.

2) During the sam ple t ime the in put cap aci tance CAIN must b e cha rged /disch arged b y th e exter nal source. The

interna l res istance of the analog sou rc e mu st allow the capaci ta nc e to reac h th eir fi nal v olt age level within tS.

After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.

3) This parameter includes the sample time tS, the time for determining the digital result and the time for the

calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on

the pr evio us page.

4) TUE is tested at VAREF = 5.0 V , VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all

other voltages within the defined voltage range.

If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload

currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is

permissible.

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the

indicated time. The max im um int ernal resistanc e results from the programmed co nv ers ion timing.

6) Not 100% tested, but guaranteed by des ign characteriz at ion.

C505 / C505C

C505A / C505CA

Data Sheet 68 08.00

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle)

(Operating Conditions apply)

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics

*) Interfa cin g t he C505 to dev ic es w it h f loat times up to 20 ns is permis s ible. This lim it ed bus conten tio n w ill not

cause any damage to port 0 driv ers.

Parameter Symbol Limit Values Unit

16-MHz clock

Duty Cycle

0.4 to 0.6

Variable Clock

1/CLP= 2 MHz to 16 MHz

min. max. min. max.

ALE pulse width tLHLL 48 –CLP - 15 –ns

Address setup to ALE tAVLL 10 –TCLHmin -15 –ns

Address hold after ALE tLLAX 10 –TCLHmin -15 –ns

ALE to valid instruction in tLLIV –75 –2 CLP - 50 ns

ALE to PSEN tLLPL 10 –TCLLmin -15 –ns

PSEN pulse width tPLPH 73 –CLP+

TCLHmin -15 –ns

PSEN to valid instruction in tPLIV –38 –CLP+

TCLHmin- 50 ns

Input instruction hold after PSEN tPXIX 0–0–ns

Input instruction float after PSEN tPXIZ *) –15 –TCLLmin -10 ns

Address valid after PSEN tPXAV *) 20 –TCLLmin - 5 –ns

Address to valid instruction in tAVIV –95 –2 CLP +

TCLHmin -55 ns

Address float to PSEN tAZPL -5 –-5 –ns

C505 / C505C

C505A / C505CA

Data Sheet 69 08.00

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d)

External Data Memory Characteristics

Parameter Symbol Limit Values Unit

16-MHz clock

Duty Cycle

0.4 to 0.6

Variable Clock

1/CLP= 2 MHz to 16 MHz

min. max. min. max.

RD pulse width tRLRH 158 –3 CLP - 30 –ns

WR pulse width tWLWH 158 –3 CL P - 30 –ns

Address hold after ALE tLLAX2 48 –CLP - 15 –ns

RD to valid data in tRLDV –100 –2 CLP+

TCLHmin - 50 ns

Data hold after RD tRHDX 0–0–ns

Data float after RD tRHDZ –51 –CLP - 12 ns

ALE to valid data in tLLDV –200 –4 CLP - 50 ns

Address to valid data in tAVDV –200 –4 CLP +

TCLHmin -75 ns

ALE to WR or RD tLLWL 73 103 CLP +

TCLLmin - 15 CLP+

TCLLmin+ 15 ns

Address valid to WR tAVWL 95 –2 CLP - 30 –ns

WR or RD high to ALE high tWHLH 10 40 TCLHmin - 15 TCLHmin + 15 ns

Data valid to WR transiti on tQVWX 5–TCLLmin - 20 –ns

Data setup before WR tQVWH 163 –3 CLP +

TCLLmin - 50 –ns

Data hold after WR tWHQX 5–TCLHmin - 20 –ns

Address float after RD tRLAZ –0–0ns

C505 / C505C

C505A / C505CA

Data Sheet 70 08.00

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d)

Note: The 16 MHz values in the tables are given as an example for a typica l duty cycle variation of

the oscillator clock from 0.4 to 0.6.

External Clock Drive Characteristics

Parameter Symbol CP U Clock = 16 MHz

Duty Cycle 0.4 to 0.6 Variable CPU Clock

1/CLP = 2 to 16 MHz Unit

min. max. min. max.

Oscillator period CLP 62.5 62.5 62.5 500 ns

High time TCLH25 –25 CLP - TCLLns

Low time TCLL25 –25 CLP - TCLHns

Rise time tR–10 –10 ns

Fall time tF–10 –10 ns

Oscillator duty cycle DC 0.4 0.6 25 / CLP 1 - 25 / CLP –

Clock cycle TCL 25 37.5 CLP * DCmin CLP * DCmax ns

C505 / C505C

C505A / C505CA

Data Sheet 71 08.00

AC Characteristics (20 MHz, 0.5 Duty Cycle)

(Operating Conditions apply)

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics

*) Interfa cin g t he C505 to dev ic es w it h f loat times up to 20 ns is permis s ible. This lim it ed bus conten tio n w ill not

cause any damage to port 0 driv ers.

Parameter Symbol Limit Values Unit

20 MHz clock

0.5 Duty Cycle Variable Clock

1/CLP = 2 MHz to 20 MHz

min. max. min. max.

ALE pulse width tLHLL 35 –CLP - 15 –ns

Address setup to ALE tAVLL 10 –CLP/2 - 15 –ns

Address hold after ALE tLLAX 10 –CLP/2 - 15 –ns

ALE to valid instruction in tLLIV –55 –2 CLP - 45 ns

ALE to PSEN tLLPL 10 –CLP/2 - 15 –ns

PSEN pulse width tPLPH 60 –3/2 CLP

- 15 –ns

PSEN to valid instruction in tPLIV –25 –3/2 CLP

- 50 ns

Input instruction hold after PSEN tPXIX 0–0–ns

Input instruction float after PSEN tPXIZ *) –20 –CLP/2 - 5 ns

Address valid after PSEN tPXAV *) 20 –CLP/2 - 5 –ns

Address to valid instruction in tAVIV –65 –5/2 CLP

- 60 ns

Address float to PSEN tAZPL - 5 –- 5 –ns

C505 / C505C

C505A / C505CA

Data Sheet 72 08.00

AC Characteristics (20 MHz, 0.5 Duty Cycle, cont’d)

External Data Memory Characteristics

Parameter Symbol Limit Values Unit

20 MHz clock

0.5 Duty Cycle Variable Clock

1/CLP = 2 MHz to 20 MHz

min. max. min. max.

RD pulse width tRLRH 120 –3 CLP - 3 0 –ns

WR pulse width tWLWH 120 –3 CLP - 30 –ns

Address hold after ALE tLLAX2 35 –CLP - 15 –ns

RD to valid data in tRLDV –75 –5/2 CLP- 50 ns

Data hold after RD tRHDX 0–0–ns

Data float after RD tRHDZ –38 –CLP - 12 ns

ALE to valid data in tLLDV –150 –4 CLP - 50 ns

Address to valid data in tAVDV –150 –9/2 CLP - 75 ns

ALE to WR or RD tLLWL 60 90 3/2 CLP - 15 3/2 CLP + 15 ns

Address valid to WR tAVWL 70 –2 CLP - 30 –ns

WR or RD high to ALE high tWHLH 10 40 CLP/2 - 15 CLP/2 + 15 ns

Data valid to WR transiti on tQVWX 5–CLP/2 - 20 –ns

Data setup before WR tQVWH 125 –7/2 CLP - 50 –ns

Data hold after WR tWHQX 5–CLP/2 - 20 –ns

Address float after RD tRLAZ –0–0ns

External Clock Drive Characteristics

Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 2 MHz to 20 MHz

min. max.

Oscillator period CLP 50 500 ns

High time TCLH15 CLP-TCLLns

Low time TCLL15 CLP-TCLHns

Rise time tR–10 ns

Fall time tF–10 ns

Oscillator duty cycle DC 0.5 0.5 –

C505 / C505C

C505A / C505CA

Data Sheet 73 08.00

Figure 32

Program Memory Read Cycle

MCT00096

ALE

PSEN

Port 2

LHLL

A8 - A15 A8 - A15

A0 - A7 Instr.IN A0 - A7

Port 0

AVLL PLPH

LLPL

LLIV

PLIV

AZPL

LLAX

PXIZ

PXIX

AVIV

PXAV

C505 / C505C

C505A / C505CA

Data Sheet 74 08.00

Figure 33

Data Memory Read Cycle

MCT00097

ALE

PSEN

Port 2

WHLH

Port 0

tLLDV tRLRH

tLLWL

tRLDV

tAVLL tLLAX2 tRLAZ

tAVWLtAVDV

tRHDX

tRHDZ

A0 - A7 from

Ri or DPL from PCL

A0 - A7 Instr.

Data IN

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

C505 / C505C

C505A / C505CA

Data Sheet 75 08.00

Figure 34

Data Memory Write Cycle

Figure 35

External Clock Drive on XTAL1

MCT00098

ALE

PSEN

Port 2

WHLH

Port 0

WLWH

LLWL

QVWX

AVLL

LLAX2

QVWH

AVWL

WHQX

A0 - A7 from

Ri or DPL from PCL

A0 - A7 Instr.IN

Data OUT

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

TCL

CLP

0.2 V

0.7

V- 0.1

MCT03310

XTAL1

0.7VDD

0.2VDD - 0.1

C505 / C505C

C505A / C505CA

Data Sheet 76 08.00

AC Characteristics of Programming Mode (C505A-4E and C505CA-4E only)

VDD = 5 V ±10 %; VPP = 11.5 V ±5%; TA = 25 °C ±10 °C

Parameter Symbol Limit Values Unit

min. max.

PALE pulse width tPAW 35 –ns

PMSEL setup to PALE rising edge tPMS 10 –

Address setup to PALE, PROG, or PRD

falling edge tPAS 10 –ns

Address hold after PALE, PROG, or PRD

falling edge tPAH 10 –ns

Address, data setup to PROG or PRD tPCS 100 –ns

Address, data hold after PROG or PRD tPCH 0–ns

PMSEL setup to PROG or PRD tPMS 10 –ns

PMSEL hold after PROG or PRD tPMH 10 –ns

PROG pulse width tPWW 100 –µs

PRD pulse widt h tPRW 100 –ns

Address to valid data out tPAD –75 ns

PRD to valid data out tPRD –20 ns

Data hold after PRD tPDH 0–ns

Data float after PRD tPDF –20 ns

PROG high between two consecutive PROG

low pulses tPWH1 1–µs

PRD high between two consecutive PRD lo w

pulses tPWH2 100 ns

XTAL clock period tCLKP 83.3 500 ns

C505 / C505C

C505A / C505CA

Data Sheet 77 08.00

Figure 36

Programming Code Byte - Write Cycle Timing

tPAW

tPMS

PAH

PAS

A8-A14 A0-A7

D0-D7

PCS

tPWW

tPCH

tPWH

MCT03642

H, H

PALE

PMSEL1,0

Port 2

Port 0

PROG

Notes: PRD must be high during a programming write cycle.

C505 / C505C

C505A / C505CA

Data Sheet 78 08.00

Figure 37

Verify Code Byte - Read Cycle Timing

tPAW

tPMS

PAH

PAS

A8-A14 A0-A7

PAD

D0-D7

tPDH

tPDFPRD

PCS

tPRW

tPCH

tPWH

MCT03643

H, H

PALE

PMSEL1,0

Port 2

Port 0

PRD

PROG must be high during a programming read cycle.Notes:

C505 / C505C

C505A / C505CA

Data Sheet 79 08.00

Figure 38

Lock Bit Access Timing

Figure 39

Version Byte Read Timing

H, L H, L

D0, D1 D0, D1

PCS

PMS

PMH

PCH

PWW

PMS

PRD

PDH

PDF

PMH

PRW

MCT03644

PMSEL1,0

Port 0

PROG

PRD

PALE should be low during a lock bit read / write cycle.Note:

e. g. FD

D0-7

PCS

PMS

PDH

PDF

PMH

MCT03645

Port 2

Port 0

PRD

PMSEL1,0 L, H

PRW

PRD

PCH

PROG must be high during a programming read cycle.Note:

C505 / C505C

C505A / C505CA

Data Sheet 80 08.00

ROM/OTP Verification Characteristics for C505

ROM Verification Mode 1 (C505(C)(A)-2R and C505(C)A-4R only)

Figure 40

ROM Verification Mode 1

Parameter Symbol Limit Values Unit

min. max.

Address to valid data tAVQV –5 CLP ns

P1.0 - P1.7

P2.0 - P2.6

Port 0

Address

Data OUT

Address: P1.0 - P1.7 = A0 - A7

P2.0 - P2.5 = A8 - A14

Data: P0.0 - P0.7 = D0 - D7

Inputs: P2.6, P2.7, PSEN =

ALE, EA =

RESET =

IH2

AVQV

MCT03693

P2.6 P2.7, PS EN = VSS

ALE, EA = VIH

RESET = VIH2

Inputs:

Note: P2.6 should be connected to VSS for C505(C)(A)-2R

C505 / C505C

C505A / C505CA

Data Sheet 81 08.00

ROM/OTP Verification Characteristics for C505 (cont’d)

ROM/OTP Verification Mode 2

Figure 41

ROM/OTP Verification Mode 2

Parameter Symbol Limit Values Unit

min. typ max.

ALE pulse width tAWD –CLP –ns

ALE period tACY –6 CLP –ns

Data valid after ALE tDVA ––2 CLP ns

Data stable after ALE tDSA 4 CLP ––ns

P3.5 setup to ALE low tAS –tCL –ns

Oscillator frequency 1/ CLP 4–6MHz

MCT02613

ACY

AWD

DSA

DVA

Data Valid

ALE

Port 0

P3.5

C505 / C505C

C505A / C505CA

Data Sheet 82 08.00

Figure 42

AC Testing: Input, Output Waveforms

Figure 43

AC Testing : Float Waveforms

Figure 44

Recommended Oscillator Circuits for Crystal Oscillator

0.45 V VDD

0.2 -0.1

+0.90.2 DD

Test Points

MCT00039

VDD -0.5 V

AC Inputs during testing are driven at VDD - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.

Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’.

MCT00038

Load

-0.1 V

+0.1 V

Load

Timing Reference

Points

-0.1 V

+0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage

occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.

IOL/IOH ≥±20 mA

MCS03311

2 - 20

MHz

XTAL2

XTAL1 XTAL1

XTAL2

N.C.

External Oscillator

Signal

Crystal Oscillator Mode Driving from External Source

Crystal Mode: C = 20 pF 10 pF (incl. stray capacitance)

C505 / C505C

C505A / C505CA

Data Sheet 83 08.00

Figure 45

P-MQFP-44 Package Outline

P-MQFP-44-2 (SMD)

(Plastic Metric Quad Flat Package)

GPM05622

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”Dimensions in mm

SMD = Surface Mounted Device

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