© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 9
1Publication Order Number:
MC14553B/D
MC14553B
3-Digit BCD Counter
The MC14553B 3−digit BCD counter consists of 3 negative edge
triggered BCD counters that are cascaded synchronously. A quad latch
at the output of each counter permits storage of any given count. The
information is then time division multiplexed, providing one BCD
number or digit at a time. Digit select outputs provide display control.
All outputs are TTL compatible.
An on−chip oscillator provides the low−frequency scanning clock
which drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays,
digital panel meters, and as a building block for general logic
applications.
Features
•TTL Compatible Outputs
•On−Chip Oscillator
•Cascadable
•Clock Disable Input
•Pulse Shaping Permits Very Slow Rise Times on Input Clock
•Output Latches
•Master Reset
•These Devices are Pb−Free and are RoHS Compliant
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter Symbol Value Unit
DC Supply Voltage Range VDD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
Vin,
Vout
−0.5 to VDD
+ 0.5
V
Input Current (DC or Transient) per Pin Iin ±10 mA
Output Current (DC or Transient) per Pin Iout +20 mA
Power Dissipation, per Package (Note 1) PD500 mW
Ambient Temperature Range TA−55 to +125 °C
Storage Temperature Range Tstg −65 to +150 °C
Lead Temperature (8−Second Soldering) TL260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained to
the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
Device Package Shipping
ORDERING INFORMATION
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MC14553BCPG PDIP−16
(Pb−Free)
500 Units / Rail
MARKING
DIAGRAMS
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
Figure 1. Block Diagram
12
10
11
13
9
7
6
5
14
2
1
15
VDD = PIN 16
VSS = PIN 8
43
CLOCK
LE
DIS
MR
Q0
Q1
Q2
Q3
O.F.
DS1
DS2
DS3
CIA CIB
PDIP−16
P SUFFIX
CASE 648
16
1
MC14553BCP
AWLYYWWG
1
MC14553B
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2
TRUTH TABLE
Inputs
Outputs
Master
Reset Clock Disable LE
0 0 0 No Change
0 0 0 Advance
0 X 1 X No Change
0 1 0 Advance
0 1 0 No Change
0 0 X X No Change
0 X X Latched
0 X X 1 Latched
1 X X 0 Q0 = Q1 = Q2 = Q3 = 0
X = Don’t Care
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol
VDD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min
Typ
(Note 2) Max Min Max
Output Voltage “0” Level
Vin = VDD or 0
VOL 5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD
VOH 5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL 5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH 5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Current
(VOH = 4.6 Vdc) Source −
(VOH = 9.5 Vdc) Pin 3
(VOH = 13.5 Vdc)
IOH 5.0
10
15
– 0.25
– 0.62
– 1.8
−
−
−
– 0.2
– 0.5
– 1.5
– 0.36
– 0.9
– 3.5
−
−
−
−0.14
−0.35
−1.1
−
−
−
mAdc
(VOH = 4.6 Vdc) Source −
(VOH = 9.5 Vdc) Other
(VOH = 13.5 Vdc) Outputs
5.0
10
15
– 0.64
– 1.6
– 4.2
−
−
−
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
−
−
−
– 0.36
– 0.9
– 2.4
−
−
−
mAdc
(VOL = 0.4 Vdc) Sink −
(VOL = 0.5 Vdc) Pin 3
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.5
1.1
1.8
−
−
−
0.4
0.9
1.5
0.88
2.25
8.8
−
−
−
0.28
0.65
1.20
−
−
−
mAdc
(VOL = 0.4 Vdc) Sink − Other
(VOL = 0.5 Vdc) Outputs
(VOL = 1.5 Vdc)
5.0
10
15
3.0
6.0
18
−
−
−
2.5
5.0
15
4.0
8.0
20
−
−
−
1.6
3.5
10
−
−
−
mAdc
Input Current Iin 15 −±0.1 −±0.00001 ±0.1 −±1.0 mAdc
Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF
Quiescent Current (Per Package)
MR = VDD
IDD 5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.010
0.020
0.030
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent, Per Package)
(CL = 50 pF on all outputs, all buffers switching)
IT5.0
10
15
IT = (0.35 mA/kHz) f + IDD
IT = (0.85 mA/kHz) f + IDD
IT = (1.50 mA/kHz) f + IDD
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,
V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
MC14553B
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3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic Figure Symbol VDD Min
Typ
(Note 6) Max Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
2a tTLH,
tTHL 5.0
10
15
−
−
−
100
50
40
200
100
80
ns
Clock to BCD Out 2a tPLH,
tPHL
5.0
10
15
−
−
−
900
500
200
1800
1000
400
ns
Clock to Overflow 2a tPHL 5.0
10
15
−
−
−
600
400
200
1200
800
400
ns
Reset to BCD Out 2b tPHL 5.0
10
15
−
−
−
900
500
300
1800
1000
600
ns
Clock to Latch Enable Setup Time
Master Reset to Latch Enable Setup Time
2b tsu 5.0
10
15
600
400
200
300
200
100
−
−
−
ns
Removal Time
Latch Enable to Clock
2b trem 5.0
10
15
– 80
– 10
0
– 200
– 70
– 50
−
−
−
ns
Clock Pulse Width 2a tWH(cl) 5.0
10
15
550
200
150
275
100
75
−
−
−
ns
Reset Pulse Width 2b tWH(R) 5.0
10
15
1200
600
450
600
300
225
−
−
−
ns
Reset Removal Time −trem 5.0
10
15
– 80
0
20
– 180
– 50
– 30
−
−
−
ns
Input Clock Frequency 2a fcl 5.0
10
15
−
−
−
1.5
5.0
7.0
0.9
2.5
3.5
MHz
Input Clock Rise Time 2b tTLH 5.0
10
15
No
Limit
ns
Disable, MR, Latch Enable
Rise and Fall Times
−tTLH,
tTHL
5.0
10
15
−
−
−
−
−
−
15
5.0
4.0
ms
Scan Oscillator Frequency
(C1 measured in mF)
1 fosc 5.0
10
15
−
−
−
1.5/C1
4.2/C1
7.0/C1
−
−
−
Hz
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14553B
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4
Figure 2. 3−Digit Counter Timing Diagram (Reference Figure 4)
1000
999
998
997
996
995
994
993
992
991
990
901
900
899
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
UNITS CLOCK
UNITS Q0
UNITS Q1
UNITS Q2
UNITS Q3
TENS CLOCK
TENS Q0
TENS Q3
HUNDREDS
CLOCK
HUNDREDS Q0
HUNDREDS Q3
DISABLE
OVERFLOW
MASTER
RESET
SCAN
OSCILLATOR
DIGIT SELECT 1
DIGIT SELECT 2
DIGIT SELECT 3
UP AT 80 UP AT 980
UP AT 800
(DISABLES CLOCK WHEN HIGH)
UNITS
TENS
HUNDREDS
PULSE
GENERATOR
(a) 16 VDD
Q3
Q2
Q1
Q0
O.F.
DS1
DS2
DS3
8V
SS
C
LE
DIS
MR
CL
CL
CL
CL
CL
GENERATOR
1
(b) VDD
Q3
Q2
Q1
Q0
O.F.
DS1
DS2
DS3
VSS
C
LE
MR
DIS
CL
CL
CL
CL
CL
GENERATOR
2
GENERATOR
3
20 ns
20 ns
90%
10%
tPLH tPHL
50%
50%
tTHL
tTLH
10% 90% 50%
1/fcl
tWL(cl)
999
1000
tTLH
50%
OVERFLOW
BCD OUT
CLOCK
90%
10%
trem
tPHL, tPLH
50%
50%
50%
tWH(R)
tsu
tPHL
MASTER RESET
BCD OUT
LATCH
ENABLE
CLOCK
Figure 3. Switching Time Test Circuits and Waveforms
tsu
tPHL
MC14553B
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5
OPERATING CHARACTERISTICS
The MC14553B three−digit counter, shown in Figure 4,
consists of three negative edge−triggered BCD counters
which are cascaded in a synchronous fashion. A quad latch
at the output of each of the three BCD counters permits
storage of any given count. The three sets of BCD outputs
(active high), after going through the latches, are time
division multiplexed, providing one BCD number or digit at
a time. Digit select outputs (active low) are provided for
display control. All outputs are TTL compatible.
An on−chip oscillator provides the low frequency
scanning clock which drives the multiplexer output selector.
The frequency of the oscillator can be controlled externally
by a capacitor between pins 3 and 4, or it can be overridden
and driven with an external clock at pin 4. Multiple devices
can be cascaded using the overflow output, which provides
one pulse for every 1000 counts.
The Master Reset input, when taken high, initializes the
three BCD counters and the multiplexer scanning circuit.
While Master Reset is high the digit scanner is set to digit
one; but all three−digit select outputs are disabled to prolong
display life, and the scan oscillator is inhibited. The Disable
input, when high, prevents the input clock from reaching the
counters, while still retaining the last count. A pulse shaping
circuit at the clock input permits the counters to continue
operating on input pulses with very slow rise times.
Information present in the counters when the latch input
goes high, will be stored in the latches and will be retained
while the latch input is high, independent of other inputs.
Information can be recovered from the latches after the
counters have been reset if Latch Enable remains high
during the entire reset cycle.
Figure 4. Expanded Block Diagram
PULSE
SHAPER
CLOCK
12
11
DISABLE
(ACTIVE
HIGH)
C
R
Q0
Q1
Q2
Q3
÷10
UNITS
C
R
Q0
Q1
Q2
Q3
÷10
TENS
C
R
Q0
Q1
Q2
Q3
÷10
HUNDREDS
10
LATCH ENABLE
QUAD
LATCH
QUAD
LATCH
QUAD
LATCH
R
R
SCAN
OSCILLATOR
SCANNER
PULSE
GENERATOR
C1
4
3
C1A
C1B
MULTIPLEXER
9
7
6
5
Q0
Q1
Q2
Q3
BCD
OUTPUTS
(ACTIVE
HIGH)
13 14
2115
MR
(ACTIVE HIGH)
OVERFLOW
DS1DS2DS3
(LSD) DIGIT SELECT (MSD)
(ACTIVE LOW)
MC14553B
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6
Figure 5. Six−Digit Display
VDD
STROBE
RESET
CLOCK
INPUT
10 13
56791512
14
3
4
12
11
CLK
DIS
Q3 Q2 Q1 Q0 DS3 DS2 DS1
C1A
C1B
O.F.
μ
0.001
F
5
3
2
4
6
1
7
A
B
C
D
Ph
LD
BI
a
b
c
d
e
f
g
9
10
11
12
13
15
14
MC14543B
LSD
VDD
DISPLAYS ARE LOW CURRENT LEDs
(I peak < 10 mA PER SEGMENT)
MSD
VDD
5
3
2
4
6
1
7
A
B
C
D
Ph
LD
BI
a
b
c
d
e
f
g
9
10
11
12
13
15
14
MC14543B
10 13
56791512
14
3
4
12
11
CLK
DIS
Q3 Q2 Q1 Q0 DS3 DS2 DS1
C1A
C1B
O.F.
MC14553B MC14553B
LE MR LE MR
MC14553B
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7
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
PDIP−16
CASE 648−08
ISSUE T
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MC14553B/D
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