ProASIC(R)3 Handbook ProASIC3 Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I - ProASIC3 Datasheet ProASIC3 Flash Family FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I ProASIC3 Device Family Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 ProASIC3 DC and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 Package Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Section II - Core Architecture Low-Power Flash Technology and Flash*Freeze Mode Core Architecture of IGLOO and ProASIC3 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 Low-Power Modes in Actel ProASIC3/E FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 Global Resources and Clock Conditioning Global Resources in Actel Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Embedded Memories FlashROM in Actel's Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 I/O Descriptions and Usage I/O Structures in IGLOO and ProASIC3 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 I/O Software Control in Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 DDR for Actel's Low-Power Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 Packaging and Pin Descriptions Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 Design Migration Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices . . . . . . . . . . .12-1 Migrating Designs from A3P250 to Lower-Logic-Density Devices . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1 Table of Contents Programming and Security Programming Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1 Security in Low-Power Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 . . . . . . . . . . . . .16-1 Microprocessor Programming of Actel's Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 Boundary Scan and UJTAG Boundary Scan in Low-Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1 UJTAG Applications in Actel's Low-Power Flash Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1 Board-Level Requirements Power-Up/-Down Behavior of ProASIC3/E Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1 ProASIC3/E SSO and Pin Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1 Metastability Characterization Report for Actel Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1 Low-Power Flash Device Handbooks Introduction Low-Power Flash Device Handbooks Introduction Device Handbooks contain all the information available to help designers understand and use Actel's devices. Handbook chapters are grouped into sections on the website to simplify navigation. Each chapter of the handbook can be viewed as an individual PDF file. At the top of the handbook web page, you will see a zip file for each product family. This file contains the complete device handbook. Please register for product updates to be notified when a section of the handbook changes. Versions Device handbook chapters may have different version numbers. Actel's goal is to provide customers with the latest information in a timely matter. As a result, the handbook chapters will be updated independently of the handbook. Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production". The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) and contains general product information. This document gives an overview of specific device and family information. Advanced This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Part Number and Revision Date Part Number 51700094-001-0 Revised January 2008 v1.0 i Section I - ProASIC3 Datasheet v1.0 ProASIC3 Flash Family FPGAs (R) with Optional Soft ARM(R) Support Features and Benefits High Capacity * 15 k to 1 M System Gates * Up to 144 kbits of True Dual-Port SRAM * Up to 300 User I/Os Reprogrammable Flash Technology * * * * 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live at Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off High Performance * 350 MHz System Performance * 3.3 V, 66 MHz 64-Bit PCI * 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation * Bank-Selectable I/O Voltages--up to 4 Banks per Chip * Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS 2.5 V / 5.0 V Input * Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS (A3P250 and above) * I/O Registers on Input, Output, and Enable Paths * Hot-Swappable and Cold Sparing I/Os * Programmable Output Slew Rate and Drive Strength * Weak Pull-Up/-Down * IEEE 1149.1 (JTAG) Boundary Scan Test * Pin-Compatible Packages across the ProASIC3 Family Clock Conditioning Circuit (CCC) and PLL In-System Programming (ISP) and Security * Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM(R)-enabled ProASIC(R)3 devices) via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents Low Power * Core Voltage for Low Power * Support for 1.5 V-Only Systems * Low-Impedance Flash Switches * Six CCC Blocks, One with an Integrated PLL * Configurable Phase-Shift, Multiply/Divide, Capabilities and External Feedback * Wide Input Frequency Range (1.5 MHz to 350 MHz) Delay Embedded Memory * 1 kbit of FlashROM User Nonvolatile Memory * SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations) * True Dual-Port SRAM (except x18) ARM Processor Support in ProASIC3 FPGAs High-Performance Routing Hierarchy * M1 and M7 ProASIC3 Devices--Cortex-M1 and CoreMP7 Soft Processor Available with or without Debug * Segmented, Hierarchical Routing and Clock Structure Advanced I/O * 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above) ProASIC3 Product Family ProASIC3 Devices ARM7 Devices1 Cortex-M1 Devices1 System Gates Typical Equivalent Macrocells VersaTiles (D-flip-flops) RAM kbits (1,024 bits) 4,608-Bit Blocks FlashROM Bits Secure (AES) ISP2 Integrated PLL in CCCs VersaNet Globals3 I/O Banks Maximum User I/Os Package Pins QFN VQFP TQFP PQFP FBGA A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 15 k 128 384 - - 1k - - 6 2 49 30 k 256 768 - - 1k - - 6 2 81 60 k 512 1,536 18 4 1k Yes 1 18 2 96 125 k 1,024 3,072 36 8 1k Yes 1 18 2 133 M1A3P250 250 k - 6,144 36 8 1k Yes 1 18 4 157 M1A3P400 400 k - 9,216 54 12 1k Yes 1 18 4 194 M1A3P600 600 k - 13,824 108 24 1k Yes 1 18 4 235 A3P1000 M7A3P1000 M1A3P1000 1M - 24,576 144 32 1k Yes 1 18 4 300 QN68 QN132 VQ100 QN132 VQ100 TQ144 QN132 VQ100 TQ144 PQ208 FG144 PQ208 FG144/256/ 484 PQ208 FG144/256/ 484 PQ208 FG144/256/ 484 FG144 QN1325 VQ100 PQ208 FG144/2565 Notes: 1. Refer to the CoreMP7 datasheet or Cortex-M1 product brief for more information. 2. AES is not available for ARM-enabled ProASIC3 devices. 3. Six chip (main) and three quadrant global networks are available for A3P060 and above. 4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs with Optional ARM Support handbook. 5. The M1A3P250 device does not support this package. A3P015 and A3P030 devices do not support this feature. February 2008 (c) 2008 Actel Corporation Supported only by A3P015 and A3P030 devices. I ProASIC3 Flash Family FPGAs I/Os Per Package1 ProASIC3 Devices A3P015 A3P030 A3P060 A3P250 3 A3P125 A3P400 3 A3P600 A3P1000 M7A3P1000 ARM7 Devices Cortex-M1 Devices M1A3P250 3,6 M1A3P400 3 M1A3P600 M1A3P1000 Single-Ended I/O Single-Ended I/O Single-Ended I/O Single-Ended I/O2 Differential I/O Pairs Single-Ended I/O2 Differential I/O Pairs Differential I/O Pairs Single-Ended I/O2 Differential I/O Pairs QN68 49 - - - - - - - - - - QN132 - 81 80 84 87 19 - - - - - VQ100 - 77 71 71 68 13 - - - - - TQ144 - - 91 100 - - - - - - - - PQ208 - - - 133 151 34 151 34 154 35 154 35 FG144 - - 96 97 97 24 97 25 97 25 97 25 FG256 - - - - 157 38 178 38 177 43 177 44 FG484 - - - - - - 194 38 235 60 300 74 Single-Ended I/O2 Package Single-Ended I/O I/O Type Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 Flash Family FPGAs handbook to ensure complying with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to the ProASIC3 Flash Family FPGAs t handbook for position assignments of the 15 LVPECL pairs. 4. FG256 and FG484 are footprint-compatible packages. 5. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 Ordering Information" on page III for the location of the "G" in the part number. 6. The M1A3P250 device does not support FG256 or QN132 packages. Table 1-1 * ProASIC3 FPGAs Package Sizes Dimensions Package QN68 QN132 VQ100 TQ144 PQ208 FG144 FG256 FG484 Length x Width (mm\mm) 8x8 8x8 14 x 14 20 x 20 28 x 28 13 x 13 17 x 17 23 x 23 Nominal Area (mm2) 64 64 196 400 784 169 289 529 Pitch (mm) 0.4 0.5 0.5 0.5 0.5 1.0 1.0 1.0 Height (mm) 0.90 0.75 1.00 1.40 3.40 1.45 1.60 2.23 II v1.0 ProASIC3 Flash Family FPGAs ProASIC3 Ordering Information A3P1000 _ 1 FG G 144 I Application (Temperature Range) Blank = Commercial (0C to +70C Ambient Temperature) I = Industrial (-40C to +85C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant (Green) Packaging Package Type QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) TQ = Thin Quad Flat Pack (0.5 mm pitch) PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Speed Grade F = 20% Slower than Standard* Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard Part Number ProASIC3 Devices A3P015 = 15,000 System Gates A3P030 = 30,000 System Gates A3P060 = 60,000 System Gates A3P125 = 125,000 System Gates A3P250 = 250,000 System Gates A3P400 = 400,000 System Gates A3P600 = 600,000 System Gates A3P1000 = 1,000,000 System Gates ProASIC3 Devices with ARM7 M7A3P1000 = 1,000,000 System Gates ProASIC3 Devices with Cortex-M1 M1A3P250 = M1A3P400 = M1A3P600 = M1A3P1000 = 250,000 System Gates 400,000 System Gates 600,000 System Gates 1,000,000 System Gates * The DC and switching characteristics for the -F speed grade targets are based only on simulation. The characteristics provided for the -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in the commercial temperature range. v1.0 III ProASIC3 Flash Family FPGAs Temperature Grade Offerings Package A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 ARM7 Devices A3P1000 M7A3P1000 Cortex-M1 Devices M1A3P250 M1A3P400 M1A3P600 M1A3P1000 QN68 C, I - - - - - - - QN132 - C, I C, I C, I C, I - - - VQ100 - C, I C, I C, I C, I - - - TQ144 - - C, I C, I - - - - PQ208 - - - C, I C, I C, I C, I C, I FG144 - - C, I C, I C, I C, I C, I C, I FG256 - - - - C, I C, I C, I C, I FG484 - - - - - C, I C, I C, I Notes: 1. C = Commercial temperature range: 0C to 70C ambient temperature 2. I = Industrial temperature range: -40C to 85C ambient temperature Speed Grade and Temperature Grade Matrix -F 1 Std. -1 -2 C I3 - Temperature Grade 2 Notes: 1. The DC and switching characteristics for the -F speed grade targets are based only on simulation. The characteristics provided for the -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in the commercial temperature range. 2. C = Commercial temperature range: 0C to 70C ambient temperature 3. I = Industrial temperature range: -40C to 85C ambient temperature References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start with M7 (CoreMP7) and M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. A3P015 and A3P030 The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features. IV v1.0 1 - ProASIC3 Device Family Overview General Description ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS(R) family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up (LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. ProASIC3 devices support the ARM7 soft IP core and Cortex-M1 devices. The ARM-enabled devices have Actel ordering numbers that begin with M7A3P (CoreMP7) and M1A3P (Cortex-M1) and do not support AES decryption. Flash Advantages Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, flash-based ProASIC3 devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/ communications, computing, and avionics markets. Security The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3 devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed ProASIC3 device cannot be read back, although secure design verification is possible. ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the ARM core must be protected at all times, AES encryption is always on for the core logic, so bitstreams are always encrypted. There is no user access to encryption for the FlashROM programming data. v1.0 1-1 ProASIC3 Device Family Overview Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. An ProASIC3 device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up The Actel flash-based ProASIC3 devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3 devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. Firm Errors Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 flashbased FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Low Power Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. ProASIC3 devices also have low dynamic power consumption to further maximize power savings. 1 -2 v1.0 ProASIC3 Device Family Overview Advanced Flash Technology The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 and Figure 1-2 on page 1-4): * FPGA VersaTiles * Dedicated FlashROM * Dedicated SRAM/FIFO memory * Extensive CCCs and PLLs * Advanced I/O structure Bank 0 Bank 0 Bank 1 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os ISP AES Decryption* Bank 0 Bank 1 VersaTile User Nonvolatile FlashROM Charge Pumps Bank 1 * Not supported by A3P015 and A3P030 devices Figure 1-1 * ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and A3P125) The A3P015 and A3P030 do not support PLL or SRAM. v1.0 1-3 ProASIC3 Device Family Overview Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption User Nonvolatile FlashROM Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (A3P600 and A3P1000) Bank 2 Figure 1-2 * ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000) The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the ProASIC3 core tile as either a three-input lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of ProASIC3 devices via an IEEE 1532 JTAG interface. VersaTiles The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The ProASIC3 VersaTile supports the following: 1 -4 * All 3-input logic functions--LUT-3 equivalent * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set v1.0 ProASIC3 Device Family Overview Refer to Figure 1-3 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 D-Flip-Flop with Clear or Set Y Data CLK CLR Y Enable D-Flip-Flop with Clear or Set Data CLK D-FF Y D-FF Enable CLR Figure 1-3 * VersaTile Configurations User Nonvolatile FlashROM Actel ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * Internet protocol addressing (wireless or fixed) * System calibration settings * Device serialization and/or inventory control * Subscription-based business models (for example, set-top boxes) * Secure key storage for secure communications algorithms * Asset management/tracking * Date stamping * Version management The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the A3P015 and A3P030 devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-bybyte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel ProASIC3 development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in A3P015 and A3P030 devices). v1.0 1-5 ProASIC3 Device Family Overview In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and A3P030 devices do not have a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: * Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz * Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz * Clock delay adjustment via programmable and fixed delays from -7.56 ns to +11.12 ns * 2 programmable delay types for clock skew minimization * Clock frequency synthesis (for PLL only) Additional CCC specifications: * Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). * Output duty cycle = 50% 1.5% or better (for PLL only) * Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used (for PLL only) * Maximum acquisition time = 300 s (for PLL only) * Low power consumption of 5 mW * Exceptional tolerance to input period jitter-- allowable input jitter is up to 1.5 ns (for PLL only) * Four precise phases; maximum misalignment between adjacent phases of 40 ps x (350 MHz / fOUT_CCC) (for PLL only) Global Clocking ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets. 1 -6 v1.0 ProASIC3 Device Family Overview I/Os with Advanced I/O Standards The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards--single-ended and differential. The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: * Single-Data-Rate applications * Double-Data-Rate applications--DDR LVDS, BLVDS, and M-LVDS I/Os for point-to-point communications ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, BLVDS and M-LVDS. BLVDS and M-LVDS can support up to 20 loads. Part Number and Revision Date Part Number 51700097-001-1 Revised February 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v1.0) 51700097-001-1 This document was divided into two sections and given a version number, starting at v1.0. The first section of the document includes features, benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. 51700097-001-0 (January 2008) This document was updated to include A3P015 device information. QN68 is a new package that was added because it is offered in the A3P015. The following sections were updated: Page N/A "Features and Benefits" "ProASIC3 Ordering Information" "Temperature Grade Offerings" "ProASIC3 Product Family" "A3P015 and A3P030" note "Introduction and Overview" v2.2 (July 2007) The "ProASIC3 FPGAs Package Sizes Dimensions" table is new. II In the "ProASIC3 Ordering Information", the QN package measurements were updated to include both 0.4 mm and 0.5 mm. III In the "General Description" section, the number of I/Os was updated from 288 to 300. 1-1 This document was previously in datasheet v2.2. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is 51700097-001-0. N/A v1.0 1-7 ProASIC3 Device Family Overview Previous Version v2.1 (May 2007) Changes in Current Version (v1.0) Page The M7 and M1 device part numbers have been updated in Table 1 * ProASIC3 Product Family, "I/Os Per Package", "Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings", and "Speed Grade and Temperature Grade Matrix". i, ii, iii, iii, iv The words "ambient temperature" were added to the temperature range in iii, iii, iv the "Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings", and "Speed Grade and Temperature Grade Matrix"sections. v2.0 (April 2007) In the "Clock Conditioning Circuit (CCC) and PLL" section, the Wide Input Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz). i The "Clock Conditioning Circuit (CCC) and PLL" section was updated. i In the "I/Os Per Package" section, the A3P030, A3P060, A3P125, ACP250, and A3P600 device I/Os were updated. ii Advanced v0.7 (January 2007) In the "Packaging Tables", Ambient was deleted. ii Ambient was deleted from the "Speed Grade and Temperature Grade Matrix". iv Advanced v0.6 (April 2006) In the "I/Os Per Package" table, the I/O numbers were added for A3P060, A3P125, and A3P250. The A3P030-VQ100 I/O was changed from 79 to 77. ii Advanced v0.5 (January 2006) BLVDS and M-LDVS are new I/O standards added to the datasheet. N/A The term flow-through was changed to pass-through. N/A Advanced v0.4 (November 2005) Table 1 was updated to include the QN132. ii The "I/Os Per Package" table was updated with the QN132. The footnotes were also updated. The A3P400-FG144 I/O count was updated. ii "Automotive ProASIC3 Ordering Information" was updated with the QN132. iii "Temperature Grade Offerings" was updated with the QN132. iii The "I/Os Per Package" table was updated for the following devices and packages: ii Device A3P250/M7ACP250 A3P250/M7ACP250 A3P1000 Advanced v0.3 Advanced v0.2 1 -8 Package VQ100 FG144 FG256 M7 device information is new. N/A The I/O counts in the "I/Os Per Package" table were updated. ii The "I/Os Per Package" table was updated. ii v1.0 ProASIC3 DC and Switching Characteristics 2 - ProASIC3 DC and Switching Characteristics General Specifications DC and switching characteristics for -F speed grade targets are based only on simulation. The characteristics provided for the -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in the commercial temperature range. Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 * Symbol Absolute Maximum Ratings Parameter Limits Units VCC DC core supply voltage -0.3 to 1.65 V VJTAG JTAG DC voltage -0.3 to 3.75 V VPUMP Programming voltage -0.3 to 3.75 V VCCPLL Analog power supply (PLL) -0.3 to 1.65 V VCCI DC I/O output buffer supply voltage -0.3 to 3.75 V VMV DC I/O input buffer supply voltage -0.3 to 3.75 V VI I/O input voltage -0.3 V to 3.6 V V (when I/O hot insertion mode is enabled) -0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 2 Storage temperature -65 to +150 C 2 Junction temperature +125 C TJ Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2. v1.1 2-1 ProASIC3 DC and Switching Characteristics Table 2-2 * Recommended Operating Conditions Symbol Parameter TA Ambient temperature VCC 1.5 V DC core supply voltage VJTAG JTAG DC voltage VPUMP Programming voltage Commercial Programming Mode Operation 3 Industrial Units 5,6 C 1.425 to 1.575 1.425 to 1.575 V 1.4 to 3.6 1.4 to 3.6 V 3.15 to 3.45 3.15 to 3.45 V 0 to 3.6 0 to 3.6 V 1.4 to 1.6 1.4 to 1.6 V 0 to +70 4,6 -40 to +85 VCCPLL Analog power supply (PLL) VCCI and VMV 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V 2.375 to 2.625 2.375 to 2.625 V 3.0 to 3.6 3.0 to 3.6 V LVDS/BLVDS/M-LVDS differential I/O LVPECL differential I/O Notes: 1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-14 on page 2-17. VMV and VCCI should be at the same voltage within a given I/O bank. 2. All parameters representing voltages are measured with respect to GND unless otherwise specified. 3. VPUMP can be left floating during operation (not programming mode). 4. Maximum TJ = 85C. 5. Maximum TJ = 100C. 6. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel's timing and power simulation tools. Table 2-3 * Flash Programming Limits - Retention, Storage and Operating Temperature1 Product Grade Programming Program Retention Cycles (biased/unbiased) Maximum Storage Temperature TSTG (C) 2 Maximum Operating Junction Temperature TJ (C) 2 Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. 2 -2 v1.1 ProASIC3 DC and Switching Characteristics Table 2-4 * Overshoot and Undershoot Limits (as measured on quiet I/Os)1 VCCI and VMV Average VCCI-GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 10% 1.4 V 5% 1.49 V 2.7 V or less 3V 3.3 V 3.6 V 10% 1.1 V 5% 1.19 V 10% 0.79 V 5% 0.88 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at 85C. 2. The duration is allowed at one out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table refers only to overshoot/undershoot limits for simultaneous switching I/Os and does not provide PCI overshoot/undershoot limits. I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every ProASIC3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4). 2. VCCI > VCC - 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: * During programming, I/Os become tristated and weakly pulled up to VCCI. * JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4 for more details). v1.1 2-3 ProASIC3 DC and Switching Characteristics When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the Power-Up Behavior of ProASIC3/E Devices chapter of the handbook for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V Figure 2-1 * I/O State as a Function of VCCI and VCC Voltage Levels 2 -4 Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. v1.1 VCCI ProASIC3 DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 2-1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 2-1 where: TA = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 110C. EQ 2-2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. * 110C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1.951 W 20.5C/W ja (C/W) EQ 2-2 Table 2-5 * Package Thermal Resistivities ja Package Type Device Pin Count jc Quad Flat No Lead A3P030 132 0.4 21.4 16.8 15.3 C/W A3P060 132 0.3 21.2 16.6 15.0 C/W A3P125 132 0.2 21.1 16.5 14.9 C/W A3P250 132 0.1 21.0 16.4 14.8 C/W Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W Thin Quad Flat Pack (TQFP) All devices 144 11.0 33.5 28.0 25.7 C/W Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W PQFP with embedded heatspreader All devices 208 3.8 16.2 13.3 11.9 C/W Fine Pitch Ball Grid Array (FBGA) See note* 144 3.8 26.9 22.9 21.5 C/W See note* 256 3.8 26.6 22.8 21.5 C/W See note* 484 3.2 20.5 17.0 15.9 C/W A3P1000 144 6.3 31.6 26.2 24.2 C/W A3P1000 256 6.6 28.1 24.4 22.7 C/W A3P1000 484 8.0 23.3 19.0 16.7 C/W Still Air 200 ft./min. 500 ft./min. Units * This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal information will be available in future revisions of the datasheet. v1.1 2-5 ProASIC3 DC and Switching Characteristics Temperature and Voltage Derating Factors Table 2-6 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C, VCC = 1.425 V) Junction Temperature (C) -40C 0C 25C 70C 85C 110C 1.425 Array Voltage VCC (V) 0.87 0.92 0.95 1.00 1.02 1.05 1.500 0.83 0.88 0.90 0.95 0.97 0.99 1.575 0.80 0.85 0.87 0.92 0.93 0.96 Calculating Power Dissipation Quiescent Supply Current Table 2-7 * Quiescent Supply Current Characteristics A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 Typical (25C) 2 mA 2 mA 2 mA 3 mA 3 mA 5 mA 8 mA Maximum (Commercial) 10 mA 10 mA 10 mA 20 mA 20 mA 30 mA 50 mA Maximum (Industrial) 15 mA 15 mA 15 mA 30 mA 30 mA 45 mA 75 mA Notes: 1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 2-8 and Table 2-9 on page 2-7. 2. -F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O leakage. 2 -6 v1.1 ProASIC3 DC and Switching Characteristics Power per I/O Pin Table 2-8 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings1 Applicable to Advanced I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (W/MHz)3 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 - 468.67 2.5 V LVCMOS 35 2.5 - 267.48 1.8 V LVCMOS 35 1.8 - 149.46 1.5 V LVCMOS (JESD8-11) 35 1.5 - 103.12 Single-Ended 3.3 V PCI 10 3.3 - 201.02 3.3 V PCI-X 10 3.3 - 201.02 Differential LVDS - 2.5 7.74 88.92 LVPECL - 3.3 19.54 166.52 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VMV. 3. PAC10 is the total dynamic power measured on VCC and VMV. Table 2-9 * Summary of I/O Input Buffer Power (Per Pin) - Default I/O Software Settings1 Applicable to Standard Plus I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (W/MHz)3 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 - 452.67 2.5 V LVCMOS 35 2.5 - 258.32 1.8 V LVCMOS 35 1.8 - 133.59 1.5 V LVCMOS (JESD8-11) 35 1.5 - 92.84 3.3 V PCI 10 3.3 - 184.92 3.3 V PCI-X 10 3.3 - 184.92 Single-Ended Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VMV. 3. PAC10 is the total dynamic power measured on VCC and VMV. v1.1 2-7 ProASIC3 DC and Switching Characteristics Table 2-10 * Summary of I/O Output Buffer Power (Per Pin) - Default I/O Software Settings1 Applicable to Standard I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (W/MHz)3 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 - 431.08 2.5 V LVCMOS 35 2.5 - 247.36 1.8 V LVCMOS 35 1.8 - 128.46 1.5 V LVCMOS (JESD8-11) 35 1.5 - 89.46 Single-Ended Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCC and VCCI. 2 -8 v1.1 ProASIC3 DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-11 * Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices A3P030 A3P060 A3P125 A3P250 A3P400 Definition A3P600 Parameter A3P1000 Device Specific Dynamic Power (W/MHz) PAC1 Clock contribution of a Global Rib 14.50 12.80 12.80 11.00 11.00 9.30 9.30 PAC2 Clock contribution of a Global Spine 2.48 PAC3 Clock contribution of a VersaTile row 0.81 PAC4 Clock contribution of a VersaTile used as a sequential module 0.12 PAC5 First contribution of a VersaTile used as a sequential module 0.07 PAC6 Second contribution of a VersaTile used as a sequential module 0.29 PAC7 Contribution of a VersaTile used as a combinatorial Module 0.29 PAC8 Average contribution of a routing net 0.70 PAC9 Contribution of an I/O input pin (standarddependent) See Table 2-8 on page 2-7. PAC10 Contribution of an I/O output pin (standarddependent) See Table 2-8 on page 2-7 and Table 2-9 on page 2-7. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Static PLL contribution PAC14 Dynamic contribution for PLL 1.85 1.35 1.58 0.81 0.81 0.41 2.55 mW 2.60 * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Actel Libero(R) Integrated Design Environment (IDE). v1.1 2-9 ProASIC3 DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: * The number of PLLs as well as the number and the frequency of each output clock generated * The number of combinatorial and sequential cells used in the design * The internal clock frequencies * The number and the standard of I/O pins used in the design * The number of RAM blocks used in the design * Toggle rates of I/O pins as well as VersaTiles--guidelines are provided in Table 2-12 on page 2-12. * Enable rates of output buffers--guidelines are provided for typical applications in Table 2-13 on page 2-12. * Read rate and write rate to the memory--guidelines are provided for typical applications in Table 2-13 on page 2-12. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption--PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption--PSTAT PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. Total Dynamic Power Consumption--PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution--PCLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design--guidelines are provided in Table 2-12 on page 2-12. NROW is the number of VersaTile rows used in the design--guidelines are provided in Table 2-12 on page 2-12. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution--PS-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-12 on page 2-12. FCLK is the global clock signal frequency. 2 -1 0 v1.1 ProASIC3 DC and Switching Characteristics Combinatorial Cells Contribution--PC-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-12 on page 2-12. FCLK is the global clock signal frequency. Routing Net Contribution--PNET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-12 on page 2-12. FCLK is the global clock signal frequency. I/O Input Buffer Contribution--PINPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-12 on page 2-12. FCLK is the global clock signal frequency. I/O Output Buffer Contribution--POUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-12 on page 2-12. 1 is the I/O buffer enable rate--guidelines are provided in Table 2-13 on page 2-12. FCLK is the global clock signal frequency. RAM Contribution--PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations--guidelines are provided in Table 2-13 on page 2-12. PLL Contribution--PPLL PPLL = PAC13 + PAC14 *FCLKOUT FCLKOUT is the output clock frequency.1 1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution. v1.1 2 - 11 ProASIC3 DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: * The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. * The average toggle rate of an 8-bit counter is 25%: - Bit 0 (LSB) = 100% - Bit 1 = 50% - Bit 2 = 25% - ... - Bit 7 (MSB) = 0.78125% - Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-12 * Toggle Rate Guidelines Recommended for Power Calculation Component 1 2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 2-13 * Enable Rate Guidelines Recommended for Power Calculation Component 1 2 3 2 -1 2 Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% v1.1 ProASIC3 DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y LVPECL (Applicable to Advanced I/O Banks Only)L Y tPD = 0.56 ns tPD = 0.49 ns tDP = 1.34 ns I/O Module (Non-Registered) Combinational Cell Y LVTTL Output drive strength = 12 mA High slew rate tDP = 2.64 ns (Advanced I/O Banks) tPD = 0.87 ns Combinational Cell I/O Module (Registered) I/O Module (Non-Registered) Y LVTTL Output drive strength = 8 mA High slew rate tDP = 3.66 ns (Advanced I/O Banks) tPY = 1.05 ns LVPECL (Applicable to Advanced I/O Banks only) D tPD = 0.47 ns Q Combinational Cell I/O Module (Non-Registered) Y tICLKQ = 0.24 ns tISUD = 0.26 ns LVCMOS 1.5 V Output drive strength = 4 mA High slew rate tDP = 3.97 ns (Advanced I/O Banks) tPD = 0.47 ns Input LVTTL Clock Register Cell tPY = 0.76 ns (Advanced I/O Banks) D Combinational Cell Y Q I/O Module (Non-Registered) LVDS, BLVDS, M-LVDS (Applicable for Advanced I/O Banks only) D Q D tPD = 0.47 ns tCLKQ = 0.55 ns tSUD = 0.43 ns tPY = 1.20 ns I/O Module (Registered) Register Cell tCLKQ = 0.55 ns tSUD = 0.43 ns Q LVTTL 3.3 V Output drive strength = 12 mA High slew rate tDP = 2.64 ns (Advanced I/O Banks) tOCLKQ = 0.59 ns tOSUD = 0.31 ns Input LVTTL Clock Input LVTTL Clock tPY = 0.76 ns (Advanced I/O Banks) tPY = 0.76 ns (Advanced I/O Banks) Figure 2-2 * Timing Model Operating Conditions: -2 Speed, Commercial Temperature Range (TJ = 70C), Worst Case VCC = 1.425 V v1.1 2 - 13 ProASIC3 DC and Switching Characteristics tPY tDIN D PAD Q DIN Y CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) To Array I/O Interface VIH PAD Vtrip Vtrip VIL VCC 50% 50% Y GND tPY (F) tPY (R) VCC 50% DIN GND 50% tDOUT tDOUT (R) (F) Figure 2-3 * Input Buffer Timing Model and Delays (example) 2 -1 4 v1.1 ProASIC3 DC and Switching Characteristics tDOUT tDP D Q D PAD DOUT Std Load CLK From Array tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) I/O Interface tDOUT (R) D 50% tDOUT VCC (F) 50% 0V VCC DOUT 50% 50% 0V VOH Vtrip Vtrip VOL PAD tDP (R) tDP (F) Figure 2-4 * Output Buffer Model and Delays (example) v1.1 2 - 15 ProASIC3 DC and Switching Characteristics tEOUT D Q CLK E tZL, tZH, tHZ, tLZ, tZLS, tZHS EOUT D Q PAD DOUT CLK D tEOUT = MAX(tEOUT(r), tEOUT(f)) I/O Interface VCC D VCC 50% E 50% tEOUT (F) tEOUT (R) VCC 50% 50% EOUT tZL 50% tZH tHZ Vtrip VCCI 90% VCCI PAD Vtrip VOL VCC D VCC E 50% 50% tEOUT (R) tEOUT (F) VCC EOUT 50% 50% tZLS VOH PAD Vtrip 50% tZHS Vtrip VOL Figure 2-5 * Tristate Output Buffer Timing Model and Delays (example) 2 -1 6 v1.1 50% tLZ 10% VCCI ProASIC3 DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels - Default I/O Software Settings Table 2-14 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Advanced I/O Banks I/O Standard VIL Drive Slew Strength Rate Min, V Max, V VIH VOL VOH Min, V Max, V Max, V Min, V IOL IOH mA mA 3.3 V LVTTL / 3.3 V LVCMOS 12 mA High -0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 V LVCMOS 12 mA High -0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 V LVCMOS 12 mA High -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 12 12 1.5 V LVCMOS 12 mA High -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12 3.3 V PCI Per PCI specifications 3.3 V PCI-X Per PCI-X specifications Note: Currents are measured at 85C junction temperature. Table 2-15 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Standard Plus I/O Banks I/O Standard VIH VIL Drive Slew Max, V Strength Rate Min, V VOL VOH Min, V Max, V Max, V Min, V IOL IOH mA mA 3.3 V LVTTL / 3.3 V LVCMOS 12 mA High -0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 V LVCMOS 12 mA High -0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 V LVCMOS 8 mA High -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 8 8 1.5 V LVCMOS 4 mA High -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 3.3 V PCI Per PCI specifications 3.3 V PCI-X Per PCI-X specifications Note: Currents are measured at 85C junction temperature. Table 2-16 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Standard I/O Banks I/O Standard VIL Drive Slew Max, V Strength Rate Min, V VOL VOH IOL IOH Min, V VIH Max, V Max, V Min, V mA mA 2 3.6 0.4 2.4 8 8 3.3 V LVTTL / 3.3 V LVCMOS 8 mA High -0.3 0.8 2.5 V LVCMOS 8 mA High -0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 V LVCMOS 4 mA High -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 4 4 1.5 V LVCMOS 2 mA High -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 Note: Currents are measured at 85C junction temperature. v1.1 2 - 17 ProASIC3 DC and Switching Characteristics Table 2-17 * Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 Industrial2 IIL IIH IIL IIH DC I/O Standards A A A A 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 1.5 V LVCMOS 10 10 15 15 3.3 V PCI 10 10 15 15 3.3 V PCI-X 10 10 15 15 Notes: 1. Commercial range (0C < TA < 70C) 2. Industrial range (-40C < TA < 85C) Summary of I/O Timing Characteristics - Default I/O Software Settings Table 2-18 * Summary of AC Measuring Points Standard Measuring Trip Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS 1.4 V 2.5 V LVCMOS 1.2 V 1.8 V LVCMOS 0.90 V 1.5 V LVCMOS 0.75 V 0.285 * VCCI (RR) 3.3 V PCI 0.615 * VCCI (FF) 0.285 * VCCI (RR) 3.3 V PCI-X 0.615 * VCCI (FF) Table 2-19 * I/O AC Parameter Definitions Parameter 2 -1 8 Parameter Definition tDP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer--HIGH to Z tZH Enable to Pad delay through the Output Buffer--Z to HIGH tLZ Enable to Pad delay through the Output Buffer--LOW to Z tZL Enable to Pad delay through the Output Buffer--Z to LOW tZHS Enable to Pad delay through the Output Buffer with delayed enable--Z to HIGH tZLS Enable to Pad delay through the Output Buffer with delayed enable--Z to LOW v1.1 ProASIC3 DC and Switching Characteristics - 0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns 1.5 V LVCMOS 12 High 35 - 3.3 V PCI 3.3 V PCI-X Per PCI spec. High 10 25 Units High 35 tZHS (ns) 12 tZLS (ns) 1.8 V LVCMOS tHZ (ns) 0.49 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns tLZ (ns) - tZH (ns) High 35 tZL (ns) 12 tEO UT (ns) 2.5 V LVCMOS tPY (ns) 0.49 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns tDIN (ns) - tDP (ns) High 35 tDOUT (ns) External Resistor () 12 Slew Rate 3.3 V LVTTL / 3.3 V LVCMOS I/O Standard Drive Strength (mA) Capacitive Load (pF) Table 2-20 * Summary of I/O Timing Characteristics--Software Default Settings -2 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Advanced I/O Banks 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns 2 0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns Per PCI-X spec. High 10 25 2 0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns LVDS 24 High - - 0.49 1.37 0.03 1.20 - - - - - - - ns LVPECL 24 High - - 0.49 1.34 0.03 1.05 - - - - - - - ns Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-54 for connectivity. This resistor is not required during normal operation. v1.1 2 - 19 ProASIC3 DC and Switching Characteristics Units tZHS (ns) tZLS (ns) tHZ (ns) tLZ (ns) tZH (ns) tZL (ns) tE OUT (ns) tPY (ns) tDIN (ns) tDP (ns) tDOUT (ns) External Resistor Capacitive Load (pF) Slew Rate I/O Standard Drive Strength (mA) Table 2-21 * Summary of I/O Timing Characteristics--Software Default Settings -2 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 12 mA High 35 pF - 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns 2.5 V LVCMOS 12 mA High 35 pF - 0.49 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns 1.8 V LVCMOS 8 mA High 35 pF - 0.49 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns 1.5 V LVCMOS 4 mA High 35 pF - 3.3 V PCI 3.3 V PCI-X 0.49 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28 ns High 10 pF 25 2 0.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns Per PCI-X spec. High 10 pF 25 2 0.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns Per PCI spec. Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-54 for connectivity. This resistor is not required during normal operation. High 35 pF - 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns 1.8 V LVCMOS 4 mA High 35 pF - 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns 1.5 V LVCMOS 2 mA High 35 pF - 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns Units 8 mA tHZ (ns) 2.5 V LVCMOS tLZ (ns) ns tZH (ns) 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 tZL (ns) - tEO UT (ns) 35 pF tPY (ns) External Resistor High tDIN (ns) Capacitive Load (pF) 8 mA tDP (ns) Slew Rate 3.3 V LVTTL / 3.3 V LVCMOS I/O Standard tDOUT (ns) Drive Strength (mA) Table 2-22 * Summary of I/O Timing Characteristics--Software Default Settings -2 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Standard I/O Banks Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-54 for connectivity. This resistor is not required during normal operation. 2 -2 0 v1.1 ProASIC3 DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-23 * Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF Table 2-24 * I/O Output Buffer Maximum Resistances1 Applicable to Advanced I/O Banks Standard Drive Strength RPULL-DOWN ()2 RPULL-UP ()3 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 17 50 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 11 33 2 mA 100 200 4 mA 100 200 6 mA 50 100 8 mA 50 100 12 mA 25 50 16 mA 20 40 24 mA 11 22 2 mA 200 225 4 mA 100 112 6 mA 50 56 8 mA 50 56 12 mA 20 22 16 mA 20 22 2 mA 200 224 4 mA 100 112 6 mA 67 75 8 mA 33 37 12 mA 33 37 Per PCI/PCI-X specification 25 75 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X 24 mA Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHs pe c v1.1 2 - 21 ProASIC3 DC and Switching Characteristics Table 2-25 * I/O Output Buffer Maximum Resistances1 Applicable to Standard Plus I/O Banks Drive Strength RPULL-DOWN ()2 RPULL-UP ()3 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 25 75 2 mA 100 200 4 mA 100 200 6 mA 50 100 8 mA 50 100 12 mA 25 50 2 mA 200 225 4 mA 100 112 6 mA 50 56 8 mA 50 56 2 mA 200 224 4 mA 100 112 Per PCI/PCI-X specification 0 0 Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHs pe c 2 -2 2 v1.1 ProASIC3 DC and Switching Characteristics Table 2-26 * I/O Output Buffer Maximum Resistances1 Applicable to Standard I/O Banks Standard Drive Strength RPULL-DOWN ()2 RPULL-UP ()3 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 2 mA 100 200 4 mA 100 200 6 mA 50 100 8 mA 50 100 2 mA 200 225 4 mA 100 112 2 mA 200 224 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHs pe c Table 2-27 * I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () R(WEAK PULL-DOWN)2 () VCCI Min. Max. Min. Max. 3.3 V 10 k 45 k 10 k 45 k 2.5 V 11 k 55 k 12 k 74 k 1.8 V 18 k 70 k 17 k 110 k 1.5 V 19 k 90 k 19 k 140 k Notes: 1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULL-UP-MAX) = (VCCImax - VOHspec) / I(WEAK PULL-UP-MIN) v1.1 2 - 23 ProASIC3 DC and Switching Characteristics Table 2-28 * I/O Short Currents IOSH/IOSL Applicable to Advanced I/O Banks Drive Strength IOSL (mA)* IOSH (mA)* 2 mA 27 25 4 mA 27 25 6 mA 54 51 8 mA 54 51 12 mA 109 103 16 mA 127 132 24 mA 181 268 2 mA 27 25 4 mA 27 25 6 mA 54 51 8 mA 54 51 12 mA 109 103 16 mA 127 132 24 mA 181 268 2 mA 18 16 4 mA 18 16 6 mA 37 32 8 mA 37 32 12 mA 74 65 16 mA 87 83 24 mA 124 169 2 mA 11 9 4 mA 22 17 6 mA 44 35 8 mA 51 45 12 mA 74 91 16 mA 74 91 2 mA 16 13 4 mA 33 25 6 mA 39 32 8 mA 55 66 12 mA 55 66 Per PCI/PCI-X specification 109 103 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X * TJ = 100C 2 -2 4 v1.1 ProASIC3 DC and Switching Characteristics Table 2-29 * I/O Short Currents IOSH/IOSL Applicable to Standard Plus I/O Banks Drive Strength IOSL (mA)* IOSH (mA)* 2 mA 27 25 4 mA 27 25 6 mA 54 51 8 mA 54 51 12 mA 109 103 16 mA 109 103 2 mA 18 16 4 mA 18 16 6 mA 37 32 8 mA 37 32 12 mA 74 65 2 mA 11 9 4 mA 22 17 6 mA 44 35 8 mA 44 35 2 mA 16 13 4 mA 33 25 Per PCI/PCI-X specification 109 103 Drive Strength IOSL (mA)* IOSH (mA)* 2 mA 27 25 4 mA 27 25 6 mA 54 51 8 mA 54 51 2 mA 18 16 4 mA 18 16 6 mA 37 32 8 mA 37 32 2 mA 11 9 4 mA 22 17 2 mA 16 13 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X * TJ = 100C Table 2-30 * I/O Short Currents IOSH/IOSL Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS * TJ = 100C v1.1 2 - 25 ProASIC3 DC and Switching Characteristics The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 110C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-31 * Short Current Event Duration before Failure Temperature Time before Failure -40C > 20 years 0C > 20 years 25C > 20 years 70C 5 years 85C 2 years 100C 6 months 110C 3 months Table 2-32 * I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS No requirement 10 ns * 20 years (110C) LVDS/BLVDS/ M-LVDS/LVPECL No requirement 10 ns * 10 years (100C) * The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. 2 -2 6 v1.1 ProASIC3 DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor-Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-33 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength VIH VIL VOL VOH IOL IOH IOSL IOSH 1 Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA Max., mA IIL 1 IIH 2 A A2 2 mA -0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 mA -0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 mA -0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 mA -0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 mA -0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 mA -0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10 24 mA -0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 IIL IIH A2 A2 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Table 2-34 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength VIL VIH VOL VOH IOL IOH IOSL Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 IOSH Max., mA1 2 mA -0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 mA -0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 mA -0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 mA -0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 mA -0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 mA -0.3 0.8 2 3.6 0.4 2.4 16 16 109 103 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. v1.1 2 - 27 ProASIC3 DC and Switching Characteristics Table 2-35 * Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength VIL VIH VOL VOH IOL IOH IOSL IOSH 1 Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA Max., mA IIL 1 IIH 2 A A2 2 mA -0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 mA -0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 mA -0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 mA -0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-6 * AC Loading Table 2-36 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 3.3 1.4 35 * Measuring point = Vtrip. See Table 2-18 on page 2-18 for a complete table of trip points. 2 -2 8 v1.1 ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-37 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 9.20 0.05 1.22 0.51 9.37 7.91 3.18 3.14 12.05 10.60 ns Std. 0.66 7.66 0.04 1.02 0.43 7.80 6.59 2.65 2.61 10.03 8.82 ns -1 0.56 6.51 0.04 0.86 0.36 6.63 5.60 2.25 2.22 8.54 7.51 ns -2 0.49 5.72 0.03 0.76 0.32 5.82 4.92 1.98 1.95 7.49 6.59 ns -F 0.79 5.89 0.05 1.22 0.51 6.00 4.89 3.59 3.85 8.69 7.57 ns Std. 0.66 4.91 0.04 1.02 0.43 5.00 4.07 2.99 3.20 7.23 6.31 ns -1 0.56 4.17 0.04 0.86 0.36 4.25 3.46 2.54 2.73 6.15 5.36 ns -2 0.49 3.66 0.03 0.76 0.32 3.73 3.04 2.23 2.39 5.40 4.71 ns -F 0.79 5.89 0.05 1.22 0.51 6.00 4.89 3.59 3.85 8.69 7.57 ns Std. 0.66 4.91 0.04 1.02 0.43 5.00 4.07 2.99 3.20 7.23 6.31 ns -1 0.56 4.17 0.04 0.86 0.36 4.25 3.46 2.54 2.73 6.15 5.36 ns -2 0.49 3.66 0.03 0.76 0.32 3.73 3.04 2.23 2.39 5.40 4.71 ns -F 0.79 4.24 0.05 1.22 0.51 4.32 3.39 3.86 4.30 7.01 6.08 ns Std. 0.66 3.53 0.04 1.02 0.43 3.60 2.82 3.21 3.58 5.83 5.06 ns -1 0.56 3.00 0.04 0.86 0.36 3.06 2.40 2.73 3.05 4.96 4.30 ns -2 0.49 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns -F 0.79 4.00 0.05 1.22 0.51 4.08 3.08 3.92 4.42 6.76 5.77 ns Std. 0.66 3.33 0.04 1.02 0.43 3.39 2.56 3.26 3.68 5.63 4.80 ns -1 0.56 2.83 0.04 0.86 0.36 2.89 2.18 2.77 3.13 4.79 4.08 ns -2 0.49 2.49 0.03 0.76 0.32 2.53 1.91 2.44 2.75 4.20 3.58 ns -F 0.79 3.69 0.05 1.22 0.51 3.76 2.54 3.99 4.88 6.45 5.23 ns Std. 0.66 3.08 0.04 1.02 0.43 3.13 2.12 3.32 4.06 5.37 4.35 ns -1 0.56 2.62 0.04 0.86 0.36 2.66 1.80 2.83 3.45 4.57 3.70 ns -2 0.49 2.30 0.03 0.76 0.32 2.34 1.58 2.48 3.03 4.01 3.25 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 29 ProASIC3 DC and Switching Characteristics Table 2-38 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 12.32 0.05 1.22 0.51 12.55 10.69 3.18 2.95 15.23 13.37 ns Std. 0.66 10.26 0.04 1.02 0.43 10.45 8.90 2.64 2.46 12.68 11.13 ns -1 0.56 8.72 0.04 0.86 0.36 8.89 7.57 2.25 2.09 10.79 9.47 ns -2 0.49 7.66 0.03 0.76 0.32 7.80 6.64 1.98 1.83 9.47 8.31 ns -F 0.79 8.74 0.05 1.22 0.51 8.90 7.55 3.58 3.65 11.59 10.23 ns Std. 0.66 7.27 0.04 1.02 0.43 7.41 6.28 2.98 3.04 9.65 8.52 ns -1 0.56 6.19 0.04 0.86 0.36 6.30 5.35 2.54 2.59 8.20 7.25 ns -2 0.49 5.43 0.03 0.76 0.32 5.53 4.69 2.23 2.27 7.20 6.36 ns -F 0.79 8.74 0.05 1.22 0.51 8.90 7.55 3.58 3.65 11.59 10.23 ns Std. 0.66 7.27 0.04 1.02 0.43 7.41 6.28 2.98 3.04 9.65 8.52 ns -1 0.56 6.19 0.04 0.86 0.36 6.30 5.35 2.54 2.59 8.20 7.25 ns -2 0.49 5.43 0.03 0.76 0.32 5.53 4.69 2.23 2.27 7.20 6.36 ns -F 0.79 6.70 0.05 1.22 0.51 6.83 5.85 3.85 4.10 9.51 8.54 ns Std. 0.66 5.58 0.04 1.02 0.43 5.68 4.87 3.21 3.42 7.92 7.11 ns -1 0.56 4.75 0.04 0.86 0.36 4.84 4.14 2.73 2.91 6.74 6.05 ns -2 0.49 4.17 0.03 0.76 0.32 4.24 3.64 2.39 2.55 5.91 5.31 ns -F 0.79 6.25 0.05 1.22 0.51 6.37 5.48 3.91 4.22 9.06 8.17 ns Std. 0.66 5.21 0.04 1.02 0.43 5.30 4.56 3.26 3.51 7.54 6.80 ns -1 0.56 4.43 0.04 0.86 0.36 4.51 3.88 2.77 2.99 6.41 5.79 ns -2 0.49 3.89 0.03 0.76 0.32 3.96 3.41 2.43 2.62 5.63 5.08 ns -F 0.79 5.83 0.05 1.22 0.51 5.93 5.46 3.98 4.67 8.62 8.15 ns Std. 0.66 4.85 0.04 1.02 0.43 4.94 4.54 3.32 3.88 7.18 6.78 ns -1 0.56 4.13 0.04 0.86 0.36 4.20 3.87 2.82 3.30 6.10 5.77 ns -2 0.49 3.62 0.03 0.76 0.32 3.69 3.39 2.48 2.90 5.36 5.06 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -3 0 v1.1 ProASIC3 DC and Switching Characteristics Table 2-39 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 8.65 0.05 1.20 0.51 8.81 7.55 2.73 2.81 11.50 10.24 ns Std. 0.66 7.20 0.04 1.00 0.43 7.34 6.29 2.27 2.34 9.57 8.52 ns -1 0.56 6.13 0.04 0.85 0.36 6.24 5.35 1.93 1.99 8.14 7.25 ns -2 0.49 5.38 0.03 0.75 0.32 5.48 4.69 1.70 1.75 7.15 6.36 ns -F 0.79 5.41 0.05 1.20 0.51 5.51 4.58 3.10 3.45 8.19 7.27 ns Std. 0.66 4.50 0.04 1.00 0.43 4.58 3.82 2.58 2.88 6.82 6.05 ns -1 0.56 3.83 0.04 0.85 0.36 3.90 3.25 2.19 2.45 5.80 5.15 ns -2 0.49 3.36 0.03 0.75 0.32 3.42 2.85 1.92 2.15 5.09 4.52 ns -F 0.79 5.41 0.05 1.20 0.51 5.51 4.58 3.10 3.45 8.19 7.27 ns Std. 0.66 4.50 0.04 1.00 0.43 4.58 3.82 2.58 2.88 6.82 6.05 ns -1 0.56 3.83 0.04 0.85 0.36 3.90 3.25 2.19 2.45 5.80 5.15 ns -2 0.49 3.36 0.03 0.75 0.32 3.42 2.85 1.92 2.15 5.09 4.52 ns -F 0.79 3.80 0.05 1.20 0.51 3.87 3.10 3.35 3.87 6.55 5.79 ns Std. 0.66 3.16 0.04 1.00 0.43 3.22 2.58 2.79 3.22 5.45 4.82 ns -1 0.56 2.69 0.04 0.85 0.36 2.74 2.20 2.37 2.74 4.64 4.10 ns -2 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns -F 0.79 3.80 0.05 1.20 0.51 3.87 3.10 3.35 3.87 6.55 5.79 ns Std. 0.66 3.16 0.04 1.00 0.43 3.22 2.58 2.79 3.22 5.45 4.82 ns -1 0.56 2.69 0.04 0.85 0.36 2.74 2.20 2.37 2.74 4.64 4.10 ns -2 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns Notes: 1. Software default selection highlighted in gray. 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 31 ProASIC3 DC and Switching Characteristics Table 2-40 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 11.63 0.05 1.20 0.51 11.84 10.12 2.74 2.65 14.53 12.81 ns Std. 0.66 9.68 0.04 1.00 0.43 9.86 8.42 2.28 2.21 12.09 10.66 ns -1 0.56 8.23 0.04 0.85 0.36 8.39 7.17 1.94 1.88 10.29 9.07 ns -2 0.49 7.23 0.03 0.75 0.32 7.36 6.29 1.70 1.65 9.03 7.96 ns -F 0.79 8.05 0.05 1.20 0.51 8.20 7.07 3.10 3.29 10.88 9.76 ns Std. 0.66 6.70 0.04 1.00 0.43 6.82 5.89 2.58 2.74 9.06 8.12 ns -1 0.56 5.70 0.04 0.85 0.36 5.80 5.01 2.20 2.33 7.71 6.91 ns -2 0.49 5.00 0.03 0.75 0.32 5.10 4.40 1.93 2.05 6.76 6.06 ns -F 0.79 8.05 0.05 1.20 0.51 8.20 7.07 3.10 3.29 10.88 9.76 ns Std. 0.66 6.70 0.04 1.00 0.43 6.82 5.89 2.58 2.74 9.06 8.12 ns -1 0.56 5.70 0.04 0.85 0.36 5.80 5.01 2.20 2.33 7.71 6.91 ns -2 0.49 5.00 0.03 0.75 0.32 5.10 4.40 1.93 2.05 6.76 6.06 ns -F 0.79 6.06 0.05 1.20 0.51 6.18 5.42 3.35 3.70 8.86 8.10 ns Std. 0.66 5.05 0.04 1.00 0.43 5.14 4.51 2.79 3.08 7.38 6.75 ns -1 0.56 4.29 0.04 0.85 0.36 4.37 3.84 2.38 2.62 6.28 5.74 ns -2 0.49 3.77 0.03 0.75 0.32 3.84 3.37 2.09 2.30 5.51 5.04 ns -F 0.79 6.06 0.05 1.20 0.51 6.18 5.42 3.35 3.70 8.86 8.10 ns Std. 0.66 5.05 0.04 1.00 0.43 5.14 4.51 2.79 3.08 7.38 6.75 ns -1 0.56 4.29 0.04 0.85 0.36 4.37 3.84 2.38 2.62 6.28 5.74 ns -2 0.49 3.77 0.03 0.75 0.32 3.84 3.37 2.09 2.30 5.51 5.04 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -3 2 v1.1 ProASIC3 DC and Switching Characteristics Table 2-41 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units -F 0.79 8.49 0.05 1.20 0.51 8.65 7.48 2.49 2.58 ns Std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns -1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns -2 0.49 5.28 0.03 0.75 0.32 5.37 4.65 1.55 1.60 ns -F 0.79 8.49 0.05 1.20 0.51 8.65 7.48 2.49 2.58 ns Std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns -1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns -2 0.49 5.28 0.03 0.75 0.32 5.37 4.65 1.55 1.60 ns -F 0.79 5.30 0.05 1.20 0.51 5.40 4.51 2.88 3.23 ns Std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns -1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns -2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns -F 0.79 5.30 0.05 1.20 0.51 5.40 4.51 2.88 3.23 ns Std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns -1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns -2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 33 ProASIC3 DC and Switching Characteristics Table 2-42 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units -F 0.79 11.37 0.05 1.20 0.51 11.58 10.26 2.49 2.45 ns Std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns -1 0.56 8.05 0.04 0.85 0.36 8.20 7.27 1.76 1.73 ns -2 0.49 7.07 0.03 0.75 0.32 7.20 6.38 1.55 1.52 ns -F 0.79 11.37 0.05 1.20 0.51 11.58 10.26 2.49 2.45 ns Std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns -1 0.56 8.05 0.04 0.85 0.36 8.20 7.27 1.76 1.73 ns -2 0.49 7.07 0.03 0.75 0.32 7.20 6.38 1.55 1.52 ns -F 0.79 7.89 0.05 1.20 0.51 8.04 7.19 2.88 3.09 ns Std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns -1 0.56 5.59 0.04 0.85 0.36 5.69 5.09 2.04 2.19 ns -2 0.49 4.91 0.03 0.75 0.32 5.00 4.47 1.79 1.92 ns -F 0.79 7.89 0.05 1.20 0.51 8.04 7.19 2.88 3.09 ns Std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns -1 0.56 5.59 0.04 0.85 0.36 5.69 5.09 2.04 2.19 ns -2 0.49 4.91 0.03 0.75 0.32 5.00 4.47 1.79 1.92 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -3 4 v1.1 ProASIC3 DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. It uses a 5 V-tolerant input buffer and push-pull output buffer. Table 2-43 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 2.5 V LVCMOS Drive Strength VIL VIH VOL VOH IOL IOH IOSL IOSH 1 Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA Max., mA IIL 1 IIH 2 A A2 2 mA -0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10 4 mA -0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 6 mA -0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10 8 mA -0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 12 mA -0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 16 mA -0.3 0.7 1.7 3.6 0.7 1.7 16 16 87 83 10 10 24 mA -0.3 0.7 1.7 3.6 0.7 1.7 24 24 124 169 10 10 IIL IIH A2 A2 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Table 2-44 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 2.5 V LVCMOS Drive Strength VIL VIH VOL VOH IOL IOH IOSL Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 IOSH Max., mA1 2 mA -0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10 4 mA -0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 6 mA -0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10 8 mA -0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 12 mA -0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. v1.1 2 - 35 ProASIC3 DC and Switching Characteristics Table 2-45 * Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 2.5 V LVCMOS Drive Strength VIL VIH VOL VOH IOL IOH IOSL IOSH 1 Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA Max., mA IIL 1 IIH 2 A A2 2 mA -0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10 4 mA -0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 6 mA -0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10 8 mA -0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-7 * AC Loading Table 2-46 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 2.5 1.2 35 * Measuring point = Vtrip. See Table 2-18 on page 2-18 for a complete table of trip points. 2 -3 6 v1.1 ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-47 * 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.72 10.41 0.05 1.57 0.51 9.41 10.41 3.22 2.77 12.09 13.09 ns Std. 0.60 8.66 0.04 1.31 0.43 7.83 8.66 2.68 2.30 10.07 10.90 ns -1 0.51 7.37 0.04 1.11 0.36 6.66 7.37 2.28 1.96 8.56 9.27 ns -2 0.45 6.47 0.03 0.98 0.32 5.85 6.47 2.00 1.72 7.52 8.14 ns -F 0.72 6.21 0.05 1.57 0.51 6.05 6.21 3.66 3.60 8.74 8.89 ns Std. 0.60 5.17 0.04 1.31 0.43 5.04 5.17 3.05 3.00 7.27 7.40 ns -1 0.51 4.39 0.04 1.11 0.36 4.28 4.39 2.59 2.55 6.19 6.30 ns -2 0.45 3.86 0.03 0.98 0.32 3.76 3.86 2.28 2.24 5.43 5.53 ns -F 0.72 6.21 0.05 1.57 0.51 6.05 6.21 3.66 3.60 8.74 8.89 ns Std. 0.60 5.17 0.04 1.31 0.43 5.04 5.17 3.05 3.00 7.27 7.40 ns -1 0.51 4.39 0.04 1.11 0.36 4.28 4.39 2.59 2.55 6.19 6.30 ns -2 0.45 3.86 0.03 0.98 0.32 3.76 3.86 2.28 2.24 5.43 5.53 ns -F 0.72 4.28 0.05 1.57 0.51 4.36 4.12 3.97 4.13 7.04 6.81 ns Std. 0.60 3.56 0.04 1.31 0.43 3.63 3.43 3.30 3.44 5.86 5.67 ns -1 0.51 3.03 0.04 1.11 0.36 3.08 2.92 2.81 2.92 4.99 4.82 ns -2 0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns -F 0.72 4.03 0.05 1.57 0.51 4.10 3.68 4.04 4.26 6.79 6.36 ns Std. 0.60 3.35 0.04 1.31 0.43 3.41 3.06 3.36 3.55 5.65 5.30 ns -1 0.51 2.85 0.04 1.11 0.36 2.90 2.60 2.86 3.02 4.81 4.51 ns -2 0.45 2.50 0.03 0.98 0.32 2.55 2.29 2.51 2.65 4.22 3.96 ns -F 0.72 3.71 0.05 1.57 0.51 3.78 2.93 4.13 4.80 6.47 5.62 ns Std. 0.60 3.09 0.04 1.31 0.43 3.15 2.44 3.44 4.00 5.38 4.68 ns -1 0.51 2.63 0.04 1.11 0.36 2.68 2.08 2.92 3.40 4.58 3.98 ns -2 0.45 2.31 0.03 0.98 0.32 2.35 1.82 2.57 2.98 4.02 3.49 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 37 ProASIC3 DC and Switching Characteristics Table 2-48 * 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.72 13.69 0.05 1.57 0.51 13.48 13.69 3.22 2.65 16.16 16.38 ns Std. 0.60 11.40 0.04 1.31 0.43 11.22 11.40 2.68 2.20 13.45 13.63 ns -1 0.51 9.69 0.04 1.11 0.36 9.54 9.69 2.28 1.88 11.44 11.60 ns -2 0.45 8.51 0.03 0.98 0.32 8.38 8.51 2.00 1.65 10.05 10.18 ns -F 0.72 9.56 0.05 1.57 0.51 9.74 9.39 3.66 3.47 12.43 12.07 ns Std. 0.60 7.96 0.04 1.31 0.43 8.11 7.81 3.05 2.89 10.34 10.05 ns -1 0.51 6.77 0.04 1.11 0.36 6.90 6.65 2.59 2.46 8.80 8.55 ns -2 0.45 5.94 0.03 0.98 0.32 6.05 5.84 2.28 2.16 7.72 7.50 ns -F 0.72 9.56 0.05 1.57 0.51 9.74 9.39 3.66 3.47 12.43 12.07 ns Std. 0.60 7.96 0.04 1.31 0.43 8.11 7.81 3.05 2.89 10.34 10.05 ns -1 0.51 6.77 0.04 1.11 0.36 6.90 6.65 2.59 2.46 8.80 8.55 ns -2 0.45 5.94 0.03 0.98 0.32 6.05 5.84 2.28 2.16 7.72 7.50 ns -F 0.72 7.42 0.05 1.57 0.51 7.56 7.11 3.97 3.99 10.25 9.80 ns Std. 0.60 6.18 0.04 1.31 0.43 6.29 5.92 3.30 3.32 8.53 8.15 ns -1 0.51 5.26 0.04 1.11 0.36 5.35 5.03 2.81 2.83 7.26 6.94 ns -2 0.45 4.61 0.03 0.98 0.32 4.70 4.42 2.47 2.48 6.37 6.09 ns -F 0.72 6.92 0.05 1.57 0.51 7.05 6.64 4.04 4.13 9.74 9.32 ns Std. 0.60 5.76 0.04 1.31 0.43 5.87 5.53 3.36 3.44 8.11 7.76 ns -1 0.51 4.90 0.04 1.11 0.36 4.99 4.70 2.86 2.92 6.90 6.60 ns -2 0.45 4.30 0.03 0.98 0.32 4.38 4.13 2.51 2.57 6.05 5.80 ns -F 0.72 6.61 0.05 1.57 0.51 6.61 6.61 4.13 4.65 9.30 9.30 ns Std. 0.60 5.51 0.04 1.31 0.43 5.50 5.51 3.43 3.87 7.74 7.74 ns -1 0.51 4.68 0.04 1.11 0.36 4.68 4.68 2.92 3.29 6.58 6.59 ns -2 0.45 4.11 0.03 0.98 0.32 4.11 4.11 2.56 2.89 5.78 5.78 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -3 8 v1.1 ProASIC3 DC and Switching Characteristics Table 2-49 * 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 9.94 0.05 1.56 0.51 8.90 9.94 2.70 2.49 11.58 12.63 ns Std. 0.66 8.28 0.04 1.30 0.43 7.41 8.28 2.25 2.07 9.64 10.51 ns -1 0.56 7.04 0.04 1.10 0.36 6.30 7.04 1.92 1.76 8.20 8.94 ns -2 0.49 6.18 0.03 0.97 0.32 5.53 6.18 1.68 1.55 7.20 7.85 ns -F 0.79 5.83 0.05 1.56 0.51 5.58 5.83 3.11 3.26 8.27 8.52 ns Std. 0.66 4.85 0.04 1.30 0.43 4.65 4.85 2.59 2.71 6.88 7.09 ns -1 0.56 4.13 0.04 1.10 0.36 3.95 4.13 2.20 2.31 5.85 6.03 ns -2 0.49 3.62 0.03 0.97 0.32 3.47 3.62 1.93 2.02 5.14 5.29 ns -F 0.79 5.83 0.05 1.56 0.51 5.58 5.83 3.11 3.26 8.27 8.52 ns Std. 0.66 4.85 0.04 1.30 0.43 4.65 4.85 2.59 2.71 6.88 7.09 ns -1 0.56 4.13 0.04 1.10 0.36 3.95 4.13 2.20 2.31 5.85 6.03 ns -2 0.49 3.62 0.03 0.97 0.32 3.47 3.62 1.93 2.02 5.14 5.29 ns -F 0.79 3.85 0.05 1.56 0.51 3.92 3.77 3.39 3.74 6.61 6.46 ns Std. 0.66 3.21 0.04 1.30 0.43 3.27 3.14 2.82 3.11 5.50 5.38 ns -1 0.56 2.73 0.04 1.10 0.36 2.78 2.67 2.40 2.65 4.68 4.57 ns -2 0.49 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 39 ProASIC3 DC and Switching Characteristics Table 2-50 * 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 13.02 0.05 1.56 0.51 12.78 13.02 2.71 2.39 15.46 15.71 ns Std. 0.66 10.84 0.04 1.30 0.43 10.64 10.84 2.26 1.99 12.87 13.08 ns -1 0.56 9.22 0.04 1.10 0.36 9.05 9.22 1.92 1.69 10.95 11.12 ns -2 0.49 8.10 0.03 0.97 0.32 7.94 8.10 1.68 1.49 9.61 9.77 ns -F 0.79 8.85 0.05 1.56 0.51 9.01 8.84 3.11 3.14 11.70 11.53 ns Std. 0.66 7.37 0.04 1.30 0.43 7.50 7.36 2.59 2.61 9.74 9.60 ns -1 0.56 6.27 0.04 1.10 0.36 6.38 6.26 2.20 2.22 8.29 8.16 ns -2 0.49 5.50 0.03 0.97 0.32 5.60 5.50 1.93 1.95 7.27 7.17 ns -F 0.79 8.85 0.05 1.56 0.51 9.01 8.84 3.11 3.14 11.70 11.53 ns Std. 0.66 7.37 0.04 1.30 0.43 7.50 7.36 2.59 2.61 9.74 9.60 ns -1 0.56 6.27 0.04 1.10 0.36 6.38 6.26 2.20 2.22 8.29 8.16 ns -2 0.49 5.50 0.03 0.97 0.32 5.60 5.50 1.93 1.95 7.27 7.17 ns -F 0.79 6.76 0.05 1.56 0.51 6.89 6.61 3.40 3.62 9.57 9.30 ns Std. 0.66 5.63 0.04 1.30 0.43 5.73 5.51 2.83 3.01 7.97 7.74 ns -1 0.56 4.79 0.04 1.10 0.36 4.88 4.68 2.41 2.56 6.78 6.59 ns -2 0.49 4.20 0.03 0.97 0.32 4.28 4.11 2.11 2.25 5.95 5.78 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -4 0 v1.1 ProASIC3 DC and Switching Characteristics Table 2-51 * 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units -F 0.79 9.86 0.05 1.55 0.51 8.70 9.86 2.44 2.29 ns Std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns -1 0.56 6.98 0.04 1.10 0.36 6.16 6.98 1.73 1.62 ns -2 0.49 6.13 0.03 0.96 0.32 5.41 6.13 1.52 1.43 ns -F 0.79 9.86 0.05 1.55 0.51 8.70 9.86 2.44 2.29 ns Std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns -1 0.56 6.98 0.04 1.10 0.36 6.16 6.98 1.73 1.62 ns -2 0.49 6.13 0.03 0.96 0.32 5.41 6.13 1.52 1.43 ns -F 0.79 5.72 0.05 1.55 0.51 5.47 5.72 2.86 3.07 ns Std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns -1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns -2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns -F 0.79 5.72 0.05 1.55 0.51 5.47 5.72 2.86 3.07 ns Std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns -1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns -2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 41 ProASIC3 DC and Switching Characteristics Table 2-52 * 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units -F 0.79 13.21 0.05 1.55 0.51 12.46 13.21 2.44 2.20 ns Std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns -1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns -2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns -F 0.79 13.21 0.05 1.55 0.51 12.46 13.21 2.44 2.20 ns Std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns -1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns -2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns -F 0.79 9.01 0.05 1.55 0.51 8.84 9.01 2.87 2.96 ns Std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns -1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns -2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns -F 0.79 9.01 0.05 1.55 0.51 8.84 9.01 2.87 2.96 ns Std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns -1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns -2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -4 2 v1.1 ProASIC3 DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-53 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.8 V LVCMOS VIL Drive Strength Min., V VIH Max., V VOL Min., V VOH Max., V Max., V IOL IOH Min., V IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 2 2 11 9 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 4 4 22 17 10 10 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 6 6 44 35 10 10 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 8 8 51 45 10 10 12 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 12 12 74 91 10 10 16 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 16 16 74 91 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Table 2-54 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O I/O Banks 1.8 V LVCMOS Drive Strength VIL Min., V Max., V VIH Min., V VOL Max., V Max., V VOH IOL IOH IOSL Min., V mA mA Max., mA1 IOSH IIL IIH Max., mA1 A2 A2 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 2 2 11 9 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 4 4 22 17 10 10 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 6 6 44 35 10 10 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 8 8 44 35 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. v1.1 2 - 43 ProASIC3 DC and Switching Characteristics Table 2-55 * Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.8 V LVCMOS VIL Drive Strength Min., V Max., V VIH Min., V VOL Max., V Max., V VOH IOL IOH IOSL Min., V mA mA Max., mA1 IOSH IIL IIH Max., mA1 A2 A2 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 2 2 9 11 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 4 4 17 22 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-8 * AC Loading Table 2-56 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.8 0.9 35 * Measuring point = Vtrip. See Table 2-18 on page 2-18 for a complete table of trip points. 2 -4 4 v1.1 ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-57 * 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 14.25 0.05 1.46 0.51 10.97 14.25 3.33 1.99 13.66 16.94 ns Std. 0.66 11.86 0.04 1.22 0.43 9.14 11.86 2.77 1.66 11.37 14.10 ns -1 0.56 10.09 0.04 1.04 0.36 7.77 10.09 2.36 1.41 9.67 11.99 ns -2 0.49 8.86 0.03 0.91 0.32 6.82 8.86 2.07 1.24 8.49 10.53 ns -F 0.79 8.31 0.05 1.46 0.51 7.04 8.31 3.87 3.41 9.73 10.99 ns Std. 0.66 6.91 0.04 1.22 0.43 5.86 6.91 3.22 2.84 8.10 9.15 ns -1 0.56 5.88 0.04 1.04 0.36 4.99 5.88 2.74 2.41 6.89 7.78 ns -2 0.49 5.16 0.03 0.91 0.32 4.38 5.16 2.41 2.12 6.05 6.83 ns -F 0.79 5.34 0.05 1.46 0.51 5.02 5.34 4.24 4.06 7.71 8.03 ns Std. 0.66 4.45 0.04 1.22 0.43 4.18 4.45 3.53 3.38 6.42 6.68 ns -1 0.56 3.78 0.04 1.04 0.36 3.56 3.78 3.00 2.88 5.46 5.69 ns -2 0.49 3.32 0.03 0.91 0.32 3.12 3.32 2.64 2.53 4.79 4.99 ns -F 0.79 4.71 0.05 1.46 0.51 4.72 4.71 4.32 4.23 7.40 7.40 ns Std. 0.66 3.92 0.04 1.22 0.43 3.93 3.92 3.60 3.52 6.16 6.16 ns -1 0.56 3.34 0.04 1.04 0.36 3.34 3.34 3.06 3.00 5.24 5.24 ns -2 0.49 2.93 0.03 0.91 0.32 2.93 2.93 2.69 2.63 4.60 4.60 ns -F 0.79 4.24 0.05 1.46 0.51 4.32 3.65 4.45 4.90 7.01 6.34 ns Std. 0.66 3.53 0.04 1.22 0.43 3.60 3.04 3.70 4.08 5.84 5.28 ns -1 0.56 3.01 0.04 1.04 0.36 3.06 2.59 3.15 3.47 4.96 4.49 ns -2 0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns -F 0.79 4.24 0.05 1.46 0.51 4.32 3.65 4.45 4.90 7.01 6.34 ns Std. 0.66 3.53 0.04 1.22 0.43 3.60 3.04 3.70 4.08 5.84 5.28 ns -1 0.56 3.01 0.04 1.04 0.36 3.06 2.59 3.15 3.47 4.96 4.49 ns -2 0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 45 ProASIC3 DC and Switching Characteristics Table 2-58 * 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 18.66 0.05 1.46 0.51 16.95 18.66 3.34 1.92 19.64 21.34 ns Std. 0.66 15.53 0.04 1.22 0.43 14.11 15.53 2.78 1.60 16.35 17.77 ns -1 0.56 13.21 0.04 1.04 0.36 12.01 13.21 2.36 1.36 13.91 15.11 ns -2 0.49 11.60 0.03 0.91 0.32 10.54 11.60 2.07 1.19 12.21 13.27 ns -F 0.79 12.58 0.05 1.46 0.51 12.51 12.58 3.88 3.28 15.19 15.27 ns Std. 0.66 10.48 0.04 1.22 0.43 10.41 10.48 3.23 2.73 12.65 12.71 ns -1 0.56 8.91 0.04 1.04 0.36 8.86 8.91 2.75 2.33 10.76 10.81 ns -2 0.49 7.82 0.03 0.91 0.32 7.77 7.82 2.41 2.04 9.44 9.49 ns -F 0.79 9.67 0.05 1.46 0.51 9.85 9.42 4.25 3.93 12.53 12.11 ns Std. 0.66 8.05 0.04 1.22 0.43 8.20 7.84 3.54 3.27 10.43 10.08 ns -1 0.56 6.85 0.04 1.04 0.36 6.97 6.67 3.01 2.78 8.88 8.57 ns -2 0.49 6.01 0.03 0.91 0.32 6.12 5.86 2.64 2.44 7.79 7.53 ns -F 0.79 9.01 0.05 1.46 0.51 9.18 8.77 4.33 4.10 11.87 11.45 ns Std. 0.66 7.50 0.04 1.22 0.43 7.64 7.30 3.61 3.41 9.88 9.53 ns -1 0.56 6.38 0.04 1.04 0.36 6.50 6.21 3.07 2.90 8.40 8.11 ns -2 0.49 5.60 0.03 0.91 0.32 5.71 5.45 2.69 2.55 7.38 7.12 ns -F 0.79 8.76 0.05 1.46 0.51 8.69 8.76 4.45 4.74 11.38 11.45 ns Std. 0.66 7.29 0.04 1.22 0.43 7.23 7.29 3.71 3.95 9.47 9.53 ns -1 0.56 6.20 0.04 1.04 0.36 6.15 6.20 3.15 3.36 8.06 8.11 ns -2 0.49 5.45 0.03 0.91 0.32 5.40 5.45 2.77 2.95 7.07 7.12 ns -F 0.79 8.76 0.05 1.46 0.51 8.69 8.76 4.45 4.74 11.38 11.45 ns Std. 0.66 7.29 0.04 1.22 0.43 7.23 7.29 3.71 3.95 9.47 9.53 ns -1 0.56 6.20 0.04 1.04 0.36 6.15 6.20 3.15 3.36 8.06 8.11 ns -2 0.49 5.45 0.03 0.91 0.32 5.40 5.45 2.77 2.95 7.07 7.12 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -4 6 v1.1 ProASIC3 DC and Switching Characteristics Table 2-59 * 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 13.61 0.05 1.44 0.51 10.48 13.61 2.70 1.83 13.17 16.30 ns Std. 0.66 11.33 0.04 1.20 0.43 8.72 11.33 2.24 1.52 10.96 13.57 ns -1 0.56 9.64 0.04 1.02 0.36 7.42 9.64 1.91 1.29 9.32 11.54 ns -2 0.49 8.46 0.03 0.90 0.32 6.51 8.46 1.68 1.14 8.18 10.13 ns -F 0.79 7.79 0.05 1.44 0.51 6.58 7.79 3.18 3.13 9.27 10.47 ns Std. 0.66 6.48 0.04 1.20 0.43 5.48 6.48 2.65 2.60 7.72 8.72 ns -1 0.56 5.51 0.04 1.02 0.36 4.66 5.51 2.25 2.21 6.56 7.42 ns -2 0.49 4.84 0.03 0.90 0.32 4.09 4.84 1.98 1.94 5.76 6.51 ns -F 0.79 4.88 0.05 1.44 0.51 4.61 4.88 3.52 3.73 7.30 7.56 ns Std. 0.66 4.06 0.04 1.20 0.43 3.84 4.06 2.93 3.10 6.07 6.30 ns -1 0.56 3.45 0.04 1.02 0.36 3.27 3.45 2.49 2.64 5.17 5.36 ns -2 0.49 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns -F 0.79 4.88 0.05 1.44 0.51 4.61 4.88 3.52 3.73 7.30 7.56 ns Std. 0.66 4.06 0.04 1.20 0.43 3.84 4.06 2.93 3.10 6.07 6.30 ns -1 0.56 3.45 0.04 1.02 0.36 3.27 3.45 2.49 2.64 5.17 5.36 ns -2 0.49 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 47 ProASIC3 DC and Switching Characteristics Table 2-60 * 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT -F 0.79 17.78 0.05 1.44 0.51 Std. 0.66 14.80 0.04 1.20 -1 0.56 12.59 0.04 -2 0.49 11.05 -F 0.79 Std. tZL tZH tLZ tHZ tZLS tZHS Units 16.21 17.78 2.70 1.76 18.90 20.47 ns 0.43 13.49 14.80 2.25 1.46 15.73 17.04 ns 1.02 0.36 11.48 12.59 1.91 1.25 13.38 14.49 ns 0.03 0.90 0.32 10.08 11.05 1.68 1.09 11.75 12.72 ns 11.89 0.05 1.44 0.51 11.69 11.89 3.19 3.00 14.38 14.58 ns 0.66 9.90 0.04 1.20 0.43 9.73 9.90 2.65 2.50 11.97 12.13 ns -1 0.56 8.42 0.04 1.02 0.36 8.28 8.42 2.26 2.12 10.18 10.32 ns -2 0.49 7.39 0.03 0.90 0.32 7.27 7.39 1.98 1.86 8.94 9.06 ns -F 0.79 8.93 0.05 1.44 0.51 9.10 8.79 3.53 3.59 11.79 11.48 ns Std. 0.66 7.44 0.04 1.20 0.43 7.58 7.32 2.94 2.99 9.81 9.56 ns -1 0.56 6.33 0.04 1.02 0.36 6.44 6.23 2.50 2.54 8.35 8.13 ns -2 0.49 5.55 0.03 0.90 0.32 5.66 5.47 2.19 2.23 7.33 7.14 ns -F 0.79 8.93 0.05 1.44 0.51 9.10 8.79 3.53 3.59 11.79 11.48 ns Std. 0.66 7.44 0.04 1.20 0.43 7.58 7.32 2.94 2.99 9.81 9.56 ns -1 0.56 6.33 0.04 1.02 0.36 6.44 6.23 2.50 2.54 8.35 8.13 ns -2 0.49 5.55 0.03 0.90 0.32 5.66 5.47 2.19 2.23 7.33 7.14 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-61 * 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units -F 0.79 13.47 0.05 1.44 0.51 10.25 13.47 2.39 1.45 ns Std. 0.66 11.21 0.04 1.20 0.43 8.53 11.21 1.99 1.21 ns -1 0.56 9.54 0.04 1.02 0.36 7.26 9.54 1.69 1.03 ns -2 0.49 8.37 0.03 0.90 0.32 6.37 8.37 1.49 0.90 ns -F 0.79 7.62 0.05 1.44 0.51 6.46 7.62 2.89 2.98 ns Std. 0.66 6.34 0.04 1.20 0.43 5.38 6.34 2.41 2.48 ns -1 0.56 5.40 0.04 1.02 0.36 4.58 5.40 2.05 2.11 ns -2 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -4 8 v1.1 ProASIC3 DC and Switching Characteristics Table 2-62 * 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units -F 0.79 18.03 0.05 1.44 0.51 15.80 18.03 2.40 2.40 ns Std. 0.66 15.01 0.04 1.20 0.43 13.15 15.01 1.99 1.99 ns -1 0.56 12.77 0.04 1.02 0.36 11.19 12.77 1.70 1.70 ns -2 0.49 11.21 0.03 0.90 0.32 9.82 11.21 1.49 1.49 ns -F 0.79 12.13 0.05 1.44 0.51 11.48 12.13 2.90 2.85 ns Std. 0.66 10.10 0.04 1.20 0.43 9.55 10.10 2.41 2.37 ns -1 0.56 8.59 0.04 1.02 0.36 8.13 8.59 2.05 2.02 ns -2 0.49 7.54 0.03 0.90 0.32 7.13 7.54 1.80 1.77 ns 2 mA 4 mA Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-63 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.5 V LVCMOS VIL Drive Strength Min., V Max., V VIH Min., V Max., V VOL VOH Max., V Min., V IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 2 mA -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 16 13 10 10 4 mA -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 33 25 10 10 6 mA -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 6 6 39 32 10 10 8 mA -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 8 8 55 66 10 10 12 mA -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12 55 66 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. v1.1 2 - 49 ProASIC3 DC and Switching Characteristics Table 2-64 * Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS VIL Drive Strength Min., V Max., V VIH VOL VOH IOL IOH Min., V Max., V Max., V Min., V IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 2 mA -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 0 0 10 10 4 mA -0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 0 0 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Table 2-65 * Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.5 V LVCMOS VIL Drive Strength Min., V 2 mA -0.3 Max., V VIH Min., V Max., V 0.30 * VCCI 0.7 * VCCI 3.6 VOL VOH IOL IOH Max., V Min., V mA mA 0.25 * VCCI 0.75 * VCCI 2 2 IOSL IOSH IIL Max., Max., mA1 mA1 A2 A2 13 16 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-9 * AC Loading Table 2-66 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.5 0.75 35 * Measuring point = Vtrip. See Table 2-18 on page 2-18 for a complete table of trip points. 2 -5 0 v1.1 IIH 10 ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-67 * 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 10.05 0.05 1.73 0.51 8.20 10.05 4.07 3.32 10.88 12.73 ns Std. 0.66 8.36 0.04 1.44 0.43 6.82 8.36 3.39 2.77 9.06 10.60 ns -1 0.56 7.11 0.04 1.22 0.36 5.80 7.11 2.88 2.35 7.71 9.02 ns -2 0.49 6.24 0.03 1.07 0.32 5.10 6.24 2.53 2.06 6.76 7.91 ns -F 0.79 6.38 0.05 1.73 0.51 5.83 6.38 4.49 4.09 8.51 9.07 ns Std. 0.66 5.31 0.04 1.44 0.43 4.85 5.31 3.74 3.40 7.09 7.55 ns -1 0.56 4.52 0.04 1.22 0.36 4.13 4.52 3.18 2.89 6.03 6.42 ns -2 0.49 3.97 0.03 1.07 0.32 3.62 3.97 2.79 2.54 5.29 5.64 ns -F 0.79 5.61 0.05 1.73 0.51 5.46 5.61 4.59 4.28 8.15 8.29 ns Std. 0.66 4.67 0.04 1.44 0.43 4.55 4.67 3.82 3.56 6.78 6.90 ns -1 0.56 3.97 0.04 1.22 0.36 3.87 3.97 3.25 3.03 5.77 5.87 ns -2 0.49 3.49 0.03 1.07 0.32 3.40 3.49 2.85 2.66 5.07 5.16 ns -F 0.79 4.90 0.05 1.73 0.51 4.99 4.30 4.74 5.05 7.68 6.98 ns Std. 0.66 4.08 0.04 1.44 0.43 4.15 3.58 3.94 4.20 6.39 5.81 ns -1 0.56 3.47 0.04 1.22 0.36 3.53 3.04 3.36 3.58 5.44 4.95 ns -2 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns -F 0.79 4.90 0.05 1.73 0.51 4.99 4.30 4.74 5.05 7.68 6.98 ns Std. 0.66 4.08 0.04 1.44 0.43 4.15 3.58 3.94 4.20 6.39 5.81 ns -1 0.56 3.47 0.04 1.22 0.36 3.53 3.04 3.36 3.58 5.44 4.95 ns -2 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 51 ProASIC3 DC and Switching Characteristics Table 2-68 * 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT -F 0.79 15.36 0.05 1.73 0.51 Std. 0.66 12.78 0.04 1.44 -1 0.56 10.87 0.04 -2 0.49 9.55 -F 0.79 Std. tZL tZH tLZ tHZ tZLS tZHS Units 15.39 15.36 4.08 3.18 18.07 18.04 ns 0.43 12.81 12.78 3.40 2.64 15.05 15.02 ns 1.22 0.36 10.90 10.87 2.89 2.25 12.80 12.78 ns 0.03 1.07 0.32 9.57 9.55 2.54 1.97 11.24 11.22 ns 12.02 0.05 1.73 0.51 12.25 11.47 4.50 3.93 14.93 14.15 ns 0.66 10.01 0.04 1.44 0.43 10.19 9.55 3.75 3.27 12.43 11.78 ns -1 0.56 8.51 0.04 1.22 0.36 8.67 8.12 3.19 2.78 10.57 10.02 ns -2 0.49 7.47 0.03 1.07 0.32 7.61 7.13 2.80 2.44 9.28 8.80 ns -F 0.79 11.21 0.05 1.73 0.51 11.42 10.68 4.60 4.12 14.11 13.37 ns Std. 0.66 9.33 0.04 1.44 0.43 9.51 8.89 3.83 3.43 11.74 11.13 ns -1 0.56 7.94 0.04 1.22 0.36 8.09 7.56 3.26 2.92 9.99 9.47 ns -2 0.49 6.97 0.03 1.07 0.32 7.10 6.64 2.86 2.56 8.77 8.31 ns -F 0.79 10.70 0.05 1.73 0.51 10.90 10.68 4.75 4.86 13.59 13.37 ns Std. 0.66 8.91 0.04 1.44 0.43 9.07 8.89 3.95 4.05 11.31 11.13 ns -1 0.56 7.58 0.04 1.22 0.36 7.72 7.57 3.36 3.44 9.62 9.47 ns -2 0.49 6.65 0.03 1.07 0.32 6.78 6.64 2.95 3.02 8.45 8.31 ns -F 0.79 10.70 0.05 1.73 0.51 10.90 10.68 4.75 4.86 13.59 13.37 ns Std. 0.66 8.91 0.04 1.44 0.43 9.07 8.89 3.95 4.05 11.31 11.13 ns -1 0.56 7.58 0.04 1.22 0.36 7.72 7.57 3.36 3.44 9.62 9.47 ns -2 0.49 6.65 0.03 1.07 0.32 6.78 6.64 2.95 3.02 8.45 8.31 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -5 2 v1.1 ProASIC3 DC and Switching Characteristics Table 2-69 * 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ -F 0.79 9.41 0.05 1.71 0.51 7.71 9.41 3.25 3.06 10.40 12.09 ns Std. 0.66 7.83 0.04 1.42 0.43 6.42 7.83 2.71 2.55 8.65 10.07 ns -1 0.56 6.66 0.04 1.21 0.36 5.46 6.66 2.31 2.17 7.36 8.56 ns -2 0.49 5.85 0.03 1.06 0.32 4.79 5.85 2.02 1.90 6.46 7.52 ns -F 0.79 5.81 0.05 1.71 0.51 5.39 5.81 3.64 3.76 8.08 8.50 ns Std. 0.66 4.84 0.04 1.42 0.43 4.49 4.84 3.03 3.13 6.72 7.08 ns -1 0.56 4.12 0.04 1.21 0.36 3.82 4.12 2.58 2.66 5.72 6.02 ns -2 0.49 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28 ns tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-70 * 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tEOUT -F 0.79 14.51 0.05 1.71 0.51 14.42 14.51 3.26 2.91 17.11 17.20 ns Std. 0.66 12.08 0.04 1.42 0.43 12.01 12.08 2.72 2.43 14.24 14.31 ns -1 0.56 10.27 0.04 1.21 0.36 10.21 10.27 2.31 2.06 12.12 12.18 ns -2 0.49 9.02 0.03 1.06 0.32 8.97 2.03 1.81 10.64 10.69 ns -F 0.79 11.15 0.05 1.71 0.51 11.35 10.71 3.65 3.60 14.04 13.40 ns Std. 0.66 9.28 0.04 1.42 0.43 9.45 8.91 3.04 3.00 11.69 11.15 ns -1 0.56 7.89 0.04 1.21 0.36 8.04 7.58 2.58 2.55 9.94 9.49 ns -2 0.49 6.93 0.03 1.06 0.32 7.06 6.66 2.27 2.24 8.73 8.33 ns tZL tZH 9.02 tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 53 ProASIC3 DC and Switching Characteristics Table 2-71 * 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units -F 0.79 9.18 0.05 1.70 0.51 7.58 9.18 2.94 2.94 ns Std. 0.66 7.65 0.04 1.42 0.43 6.31 7.65 2.45 2.45 ns -1 0.56 6.50 0.04 1.21 0.36 5.37 6.50 2.08 2.08 ns -2 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-72 * 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units -F 0.79 14.81 0.05 1.70 0.51 14.17 14.81 2.94 2.79 ns Std. 0.66 12.33 0.04 1.42 0.43 11.79 12.33 2.45 2.32 ns -1 0.56 10.49 0.04 1.21 0.36 10.03 10.49 2.08 1.98 ns -2 0.49 9.21 0.03 1.06 0.32 8.81 9.21 1.83 1.73 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-73 * Minimum and Maximum DC Input and Output Levels 3.3 V PCI/PCI-X Drive Strength VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 A2 A2 Per PCI specification Per PCI curves 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path characterization are described in Figure 2-10. R = 25 Test Point Datapath R to VCCI for tDP (F) R to GND for tDP (R) R=1k Test Point Enable Path Figure 2-10 * AC Loading 2 -5 4 v1.1 R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 10 pF for tZH /tZHS /tZL /t ZLS 5 pF for tHZ /tLZ ProASIC3 DC and Switching Characteristics AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 2-74. Table 2-74 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF) 3.3 0.285 * VCCI for tDP(R) 10 0 0.615 * VCCI for tDP(F) * Measuring point = Vtrip. See Table 2-18 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-75 * 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 3.22 0.05 1.04 0.51 3.28 2.34 3.86 4.30 5.97 5.03 ns Std. 0.66 2.68 0.04 0.86 0.43 2.73 1.95 3.21 3.58 4.97 4.19 ns -1 0.56 2.28 0.04 0.73 0.36 2.32 1.66 2.73 3.05 4.22 3.56 ns -2 0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-76 * 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units -F 0.79 2.77 0.05 1.02 0.51 2.82 2.05 3.35 3.87 5.51 4.73 ns Std. 0.66 2.31 0.04 0.85 0.43 2.35 1.70 2.79 3.22 4.59 3.94 ns -1 0.56 1.96 0.04 0.72 0.36 2.00 1.45 2.37 2.74 3.90 3.35 ns -2 0.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 55 ProASIC3 DC and Switching Characteristics Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS) configuration (up to 40 nodes). Bourns Part Number: CAT16-LV4F12 OUTBUF_LVDS FPGA P 165 Z0 = 50 165 FPGA INBUF_LVDS + - 100 140 N P Z0 = 50 N Figure 2-11 * LVDS Circuit Diagram and Board-Level Implementation Table 2-77 * Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units 2.375 2.5 2.625 V VCCI Supply Voltage VOL Output LOW Voltage 0.9 1.075 1.25 V VOH Output HIGH Voltage 1.25 1.425 1.6 V VI Input Voltage 0 - 2.925 V VODIFF Differential Output Voltage 250 350 450 mV VOCM Output Common-Mode Voltage 1.125 1.25 1.375 V VICM Input Common-Mode Voltage 0.05 1.25 2.35 V VIDIFF Input Differential Voltage 100 350 - mV Notes: 1. 5% 2. Differential input voltage = 350 mV 2 -5 6 v1.1 ProASIC3 DC and Switching Characteristics Table 2-78 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) 1.325 Cross point 1.075 * Measuring point = Vtrip. See Table 2-18 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-79 * LVDS Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Speed Grade tDOUT tDP tDIN tPY Units -F 0.79 2.20 0.05 1.92 ns Std. 0.66 1.83 0.04 1.60 ns -1 0.56 1.56 0.04 1.36 ns -2 0.49 1.37 0.03 1.20 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. BLVDS/M-LVDS Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive current required by BLVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-12. The input and output buffer delays are available in the LVDS section in Table 2-79. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 and RT = 70 , given Z0 = 50 (2") and Zstub = 50 (~1.5"). Receiver Transceiver EN R + RS Zstub D EN T - + RS Zstub Driver RS Zstub - Zstub RS Zstub EN Transceiver EN R - + RS Receiver + RS RS Zstub Zstub EN T - + RS Zstub RS BIBUF_LVDS - RS ... Z0 Z0 Z0 Z0 Z0 Z0 RT Z 0 Z0 Z0 Z0 Z0 Z0 RT Figure 2-12 * BLVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers v1.1 2 - 57 ProASIC3 DC and Switching Characteristics LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different. Bourns Part Number: CAT16-PC4F12 OUTBUF_LVPECL FPGA P 100 Z0 = 50 100 INBUF_LVPECL + - 100 187 W N FPGA P Z0 = 50 N Figure 2-13 * LVPECL Circuit Diagram and Board-Level Implementation Table 2-80 * Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Max. Min. 3.0 Max. Min. 3.3 Max. Units VCCI Supply Voltage 3.6 VOL Output LOW Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V VOH Output HIGH Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V VIL, VIH Input LOW, Input HIGH Voltages 0 3.3 0 3.6 0 3.9 V VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V VIDIFF Input Differential Voltage 300 300 V 300 mV Table 2-81 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) 1.94 Cross point 1.64 * Measuring point = Vtrip. See Table 2-18 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-82 * LVPECL Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade tDOUT tDP tDIN tPY Units -F 0.79 2.16 0.05 1.69 ns Std. 0.66 1.80 0.04 1.40 ns -1 0.56 1.53 0.04 1.19 ns -2 0.49 1.34 0.03 1.05 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -5 8 v1.1 ProASIC3 DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF Preset L DOUT Data_out E F Y Core Array G PRE D Q DFN1E1P1 TRIBUF CLKBUF CLK INBUF Enable PRE D Q C DFN1E1P1 INBUF Data Pad Out D E E EOUT B H I A J K INBUF INBUF D_Enable CLK CLKBUF Enable Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered PRE D Q DFN1E1P1 E Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered Figure 2-14 * Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset v1.1 2 - 59 ProASIC3 DC and Switching Characteristics Table 2-83 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOSUE Enable Setup Time for the Output Data Register G, H tOHE Enable Hold Time for the Output Data Register G, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOESUE Enable Setup Time for the Output Enable Register K, H tOEHE Enable Hold Time for the Output Enable Register K, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tISUE Enable Setup Time for the Input Data Register B, A tIHE Enable Hold Time for the Input Data Register B, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A * See Figure 2-14 on page 2-59 for more information. 2 -6 0 v1.1 H, DOUT L, DOUT H, EOUT I, EOUT ProASIC3 DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Pad Out DOUT D CC Core Array Q DFN1E1C1 EE Data_out FF D Q DFN1E1C1 TRIBUF INBUF Data Y GG INBUF Enable BB EOUT E E CLR CLR LL INBUF CLR CLKBUF CLK HH AA JJ DD D Q DFN1E1C1 KK Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered E INBUF CLKBUF CLK Enable INBUF D_Enable CLR Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-15 * Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear v1.1 2 - 61 ProASIC3 DC and Switching Characteristics Table 2-84 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOSUE Enable Setup Time for the Output Data Register GG, HH tOHE Enable Hold Time for the Output Data Register GG, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOESUE Enable Setup Time for the Output Enable Register KK, HH tOEHE Enable Hold Time for the Output Enable Register KK, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tISUE Enable Setup Time for the Input Data Register BB, AA tIHE Enable Hold Time for the Input Data Register BB, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA * See Figure 2-15 on page 2-61 for more information. 2 -6 2 v1.1 HH, DOUT LL, DOUT HH, EOUT ProASIC3 DC and Switching Characteristics Input Register tICKMPWH tICKMPWL CLK 50% 50% Enable 50% 1 50% 50% 50% tIHD tISUD Data 50% 50% 50% 0 tIREMPRE tIRECPRE tIWPRE 50% tIHE Preset tISUE 50% 50% 50% tIWCLR 50% Clear tIRECCLR tIREMCLR 50% 50% tIPRE2Q 50% Out_1 50% tICLR2Q 50% tICLKQ Figure 2-16 * Input Register Timing Diagram Timing Characteristics Table 2-85 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 0.38 ns tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 0.42 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.37 0.42 0.50 0.60 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 0.36 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 0.36 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.36 0.41 0.48 0.57 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.32 0.37 0.43 0.52 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 63 ProASIC3 DC and Switching Characteristics Output Register tOCKMPWH tOCKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOSUD tOHD 1 Data_out Enable 50% 50% 0 50% tOWPRE tOHE Preset tOSUE tOREMPRE tORECPRE 50% 50% 50% tOWCLR 50% Clear tOREMCLR tORECCLR 50% 50% tOPRE2Q 50% DOUT 50% tOCLR2Q 50% tOCLKQ Figure 2-17 * Output Register Timing Diagram Timing Characteristics Table 2-86 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 0.95 ns tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 0.50 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.44 0.50 0.59 0.70 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data 0.22 0.25 0.30 0.36 Register ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data 0.22 0.25 0.30 0.36 Register ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.36 0.41 0.48 0.57 ns tOCKMPWL 0.32 0.37 0.43 0.52 ns Clock Minimum Pulse Width LOW for the Output Data Register Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -6 4 v1.1 ProASIC3 DC and Switching Characteristics Output Enable Register tOECKMPWH tOECKMPWL 50% 50% 50% 50% 50% 50% 50% CLK tOESUD tOEHD 1 D_Enable Enable Preset 50% 0 50% 50% tOESUEtOEHE tOEWPRE tOEREMPRE tOERECPRE 50% 50% 50% tOEWCLR 50% tOERECCLR 50% tOEREMCLR 50% Clear EOUT 50% tOEPRE2Q tOECLR2Q 50% 50% tOECLKQ Figure 2-18 * Output Enable Register Timing Diagram v1.1 2 - 65 ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-87 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tOECLKQ Clock-to-Q of the Output Enable Register 0.59 0.67 0.79 0.95 ns tOESUD Data Setup Time for the Output Enable Register 0.31 0.36 0.42 0.50 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.44 0.50 0.58 0.70 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 1.07 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.67 0.76 0.89 1.07 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.22 0.25 0.30 0.36 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 0.36 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable 0.22 0.25 0.30 0.36 Register ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable 0.22 0.25 0.30 0.36 Register ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.36 0.41 0.48 0.57 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.32 0.37 0.43 0.52 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -6 6 v1.1 ProASIC3 DC and Switching Characteristics DDR Module Specifications Input DDR Module Input DDR INBUF Data A D Out_QF (to core) E Out_QR (to core) FF1 B CLK CLKBUF FF2 C CLR INBUF DDR_IN Figure 2-19 * Input DDR Timing Model Table 2-88 * Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup Time of DDR input A, B tDDRIHD Data Hold Time of DDR input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B v1.1 2 - 67 ProASIC3 DC and Switching Characteristics CLK tDDRISUD Data 1 2 3 4 5 tDDRIHD 6 7 8 9 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF 2 6 4 tDDRICLKQ2 tDDRICLR2Q2 Out_QR 3 7 5 Figure 2-20 * Input DDR Timing Diagram Timing Characteristics Table 2-89 * Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.39 0.44 0.52 0.62 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.27 0.31 0.37 0.44 ns tDDRISUD Data Setup for Input DDR 0.28 0.32 0.38 0.45 ns tDDRIHD Data Hold for Input DDR 0.00 0.00 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.57 0.65 0.76 0.92 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.46 0.53 0.62 0.74 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.22 0.25 0.30 0.36 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 0.36 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.36 0.41 0.48 0.57 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.32 0.37 0.43 0.52 ns FDDRIMAX Maximum Frequency for Input DDR TBD TBD TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -6 8 v1.1 ProASIC3 DC and Switching Characteristics Output DDR Module Output DDR A X Data_F (from core) FF1 Out B CLK 0 X CLKBUF C D Data_R (from core) E X 1 X X OUTBUF FF2 B CLR INBUF C X X DDR_OUT Figure 2-21 * Output DDR Timing Model Table 2-90 * Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDROCLKQ Clock-to-Out B, E tDDROCLR2Q Asynchronous Clear-to-Out C, E tDDROREMCLR Clear Removal C, B tDDRORECCLR Clear Recovery C, B tDDROSUD1 Data Setup Data_F A, B tDDROSUD2 Data Setup Data_R D, B tDDROHD1 Data Hold Data_F A, B tDDROHD2 Data Hold Data_R D, B v1.1 2 - 69 ProASIC3 DC and Switching Characteristics CLK tDDROSUD2 tDDROHD2 1 Data_F 2 tDDROREMCLR Data_R 6 4 3 5 tDDROHD1 7 8 9 10 11 tDDRORECCLR tDDROREMCLR CLR tDDROCLR2Q Out tDDROCLKQ 2 7 8 3 9 4 10 Figure 2-22 * Output DDR Timing Diagram Timing Characteristics Table 2-91 * Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 1.13 ns tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 0.61 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 0.61 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 1.29 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 0.36 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 0.36 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.36 0.41 0.48 0.57 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.32 0.37 0.43 0.52 ns FDDOMAX Maximum Frequency for the Output DDR TBD TBD TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -7 0 v1.1 ProASIC3 DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide. A A A OR2 NOR2 Y A AND2 A Y NAND2 B Y B A B C A XOR2 Y A A B C Y B B B Y INV NAND3 Y A MAJ3 B XOR3 0 Y MUX2 B Y 1 C S Figure 2-23 * Sample of Combinatorial Cells v1.1 2 - 71 ProASIC3 DC and Switching Characteristics tPD A NAND2 or Any Combinatorial Logic B Y tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell VCC 50% 50% A, B, C GND VCC 50% 50% OUT GND VCC tPD tPD (FF) (RR) tPD OUT (FR) 50% tPD GND (RF) Figure 2-24 * Timing Model and Waveforms 2 -7 2 v1.1 50% ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-92 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter -2 -1 Std. -F Units Y = !A tPD 0.40 0.46 0.54 0.65 ns Y=A*B tPD 0.47 0.54 0.63 0.76 ns Y = !(A * B) tPD 0.47 0.54 0.63 0.76 ns Y=A+B tPD 0.49 0.55 0.65 0.78 ns NOR2 Y = !(A + B) tPD 0.49 0.55 0.65 0.78 ns XOR2 Y=AB tPD 0.74 0.84 0.99 1.19 ns MAJ3 Y = MAJ(A , B, C) tPD 0.70 0.79 0.93 1.12 ns XOR3 Y=ABC tPD 0.87 1.00 1.17 1.41 ns MUX2 Y = A !S + B S tPD 0.51 0.58 0.68 0.81 ns AND3 Y=A*B*C tPD 0.56 0.64 0.75 0.90 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. VersaTile Specifications as a Sequential Module The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide. Data D Q Out Data Out D En DFN1 Q DFN1E1 CLK CLK PRE Data D Q Out Data En DFN1C1 D Q Out DFI1E1P1 CLK CLK CLR Figure 2-25 * Sample of Sequential Cells v1.1 2 - 73 ProASIC3 DC and Switching Characteristics tCKMPWH tCKMPWL CLK 50% 50% tSUD 50% Data 50% 50% 50% 50% 50% tHD 50% 0 EN 50% PRE tRECPRE tWPRE tSUE tHE 50% tREMPRE 50% 50% 50% CLR tPRE2Q 50% Out tREMCLR tRECCLR tWCLR 50% 50% tCLR2Q 50% 50% tCLKQ Figure 2-26 * Timing Model and Waveforms Timing Characteristics Table 2-93 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tCLKQ Clock-to-Q of the Core Register 0.55 0.63 0.74 0.89 ns tSUD Data Setup Time for the Core Register 0.43 0.49 0.57 0.69 ns tHD Data Hold Time for the Core Register 0.00 0.00 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.45 0.52 0.61 0.73 ns tHE Enable Hold Time for the Core Register 0.00 0.00 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.22 0.25 0.30 0.36 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.22 0.25 0.30 0.36 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 0.36 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.25 0.30 0.36 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.32 0.37 0.43 0.52 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.36 0.41 0.48 0.57 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -7 4 v1.1 ProASIC3 DC and Switching Characteristics Global Resource Characteristics A3P250 Clock Tree Topology Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing. The global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A3P250 device. It is used to drive all D-flip-flops in the device. Central Global Rib CCC VersaTile Rows Global Spine Figure 2-27 * Example of Global Tree Use in an A3P250 Device for Clock Routing v1.1 2 - 75 ProASIC3 DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard-dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-80. Table 2-94 to Table 2-100 on page 2-79 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics Table 2-94 * A3P030 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter 1 -1 1 Std. 2 1 -F Min. Max. Min. Max. Min. Max. Min. Max.2 Units Description 2 2 1 tRCKL Input LOW Delay for Global Clock 0.67 0.81 0.76 0.92 0.89 1.09 1.07 1.31 ns tRCKH Input HIGH Delay for Global Clock 0.68 0.85 0.77 0.97 0.91 1.14 1.09 1.37 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.18 0.21 0.24 0.29 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-95 * A3P060 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter -1 Std. -F 1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Description Min. Units tRCKL Input LOW Delay for Global Clock 0.71 0.93 0.81 1.05 0.95 1.24 1.14 1.49 ns tRCKH Input HIGH Delay for Global Clock 0.70 0.96 0.80 1.09 0.94 1.28 1.13 1.54 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.26 0.29 0.34 0.41 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -7 6 v1.1 ProASIC3 DC and Switching Characteristics Table 2-96 * A3P125 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter 1 -1 1 Std. 2 1 -F Min. Max. Min. Max. Min. Max. Min. Max.2 Units Description 2 2 1 tRCKL Input LOW Delay for Global Clock 0.77 0.99 0.87 1.12 1.03 1.32 1.24 1.58 ns tRCKH Input HIGH Delay for Global Clock 0.76 1.02 0.87 1.16 1.02 1.37 1.23 1.64 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.26 0.29 0.34 0.41 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-97 * A3P250 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter -1 Std. -F 1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Description Min. Units tRCKL Input LOW Delay for Global Clock 0.80 1.01 0.91 1.15 1.07 1.36 1.28 1.63 ns tRCKH Input HIGH Delay for Global Clock 0.78 1.04 0.89 1.18 1.04 1.39 1.25 1.66 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.26 0.29 0.34 0.41 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 77 ProASIC3 DC and Switching Characteristics Table 2-98 * A3P400 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter 1 -1 1 Std. 2 1 -F Min. Max. Min. Max. Min. Max. Min. Max.2 Units Description 2 2 1 tRCKL Input LOW Delay for Global Clock 0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns tRCKH Input HIGH Delay for Global Clock 0.86 1.11 0.98 1.27 1.15 1.49 1.38 1.79 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.26 0.29 0.34 0.41 ns Mhz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-99 * A3P600 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter -1 Std. -F 1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Description Min. Units tRCKL Input LOW Delay for Global Clock 0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns tRCKH Input HIGH Delay for Global Clock 0.86 1.11 0.98 1.27 1.15 1.49 1.38 1.79 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.26 0.29 0.34 0.41 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -7 8 v1.1 ProASIC3 DC and Switching Characteristics Table 2-100 * A3P1000 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter 1 -1 1 Std. 2 1 -F Min. Max. Min. Max. Min. Max. Min. Max.2 Units Description 2 2 1 tRCKL Input LOW Delay for Global Clock 0.94 1.16 1.07 1.32 1.26 1.55 1.51 1.86 ns tRCKH Input HIGH Delay for Global Clock 0.93 1.19 1.06 1.35 1.24 1.59 1.49 1.91 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.26 0.29 0.35 0.41 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 79 ProASIC3 DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-101 * ProASIC3 CCC/PLL Specification Parameter Minimum Typical Maximum Units Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz 125 MHz Serial Clock (SCLK) for Dynamic PLL1 Delay Increments in Programmable Delay Blocks 2, 3 160 Number of Programmable Values in Each Programmable Delay Block ps 32 Input Period Jitter 1.5 CCC Output Peak-to-Peak Period Jitter FCCC_OUT ns Max Peak-to-Peak Period Jitter 0.75 MHz to 24 MHz 1 Global Network Used 3 Global Networks Used 0.50% 0.70% 24 MHz to 100 MHz 1.00% 1.20% 100 MHz to 250 MHz 1.75% 2.00% 250 MHz to 350 MHz 2.50% 5.60% Acquisition Time (A3P250 and A3P1000 only) LockControl = 0 300 s LockControl = 1 300 s (all other dies) LockControl = 0 300 s LockControl = 1 6.0 ms (A3P250 and A3P1000 only) LockControl = 0 1.6 ns LockControl = 1 1.6 ns (all other dies) LockControl = 0 1.6 ns Tracking Jitter5 LockControl = 1 0.8 ns 48.5 51.5 % 2, 3 0.6 5.56 ns 2, 3 0.025 5.56 ns Output Duty Cycle Delay Range in Block: Programmable Delay 1 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay2, 3 2.2 ns Notes: 1. Maximum value obtained for a -2 speed-grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings. 3. TJ = 25C, VCC = 1.5 V 4. The A3P030 device does not contain a PLL. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 2 -8 0 v1.1 ProASIC3 DC and Switching Characteristics Output Signal Tperiod_max Tperiod_min Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max - Tperiod_min. Figure 2-28 * Peak-to-Peak Jitter Definition v1.1 2 - 81 ProASIC3 DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM RAM4K9 RAM512X18 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA PIPE REN RCLK ADDRB11 ADDRB10 DOUTB8 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 DINB0 WW1 WW0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WEN WCLK RESET RESET Figure 2-29 * RAM Models 2 -8 2 v1.1 ProASIC3 DC and Switching Characteristics Timing Waveforms tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS tENH WEN_B tCKQ1 DO Dn D0 D1 D2 tDOH1 Figure 2-30 * RAM Read for Pass-Through Output tCYC tCKH tCKL CLK t AS tAH A1 A0 ADD A2 tBKS tBKH BLK_B tENH tENS WEN_B tCKQ2 DO Dn D0 D1 tDOH2 Figure 2-31 * RAM Read for Pipelined Output v1.1 2 - 83 ProASIC3 DC and Switching Characteristics tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS tENH WEN_B tDS DI0 DI tDH DI1 D2 Dn DO Figure 2-32 * RAM Write, Output Retained (WMODE = 0) tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS WEN_B tDS DI0 DI DO (pass-through) DO (pipelined) tDH DI1 Dn DI1 DI0 Dn Figure 2-33 * RAM Write, Output as Write Data (WMODE = 1) 2 -8 4 DI2 v1.1 DI0 DI1 ProASIC3 DC and Switching Characteristics CLK1 tAS tAH A0 tDH A1 A3 tDS D1 D2 D3 ADD1 DI1 tCCKH CLK2 WEN_B1 WEN_B2 tAS ADD2 A0 DI2 D0 tAH A0 A4 D4 tCKQ1 DO2 (pass-through) Dn D0 tCKQ2 DO2 (pipelined) Dn D0 Figure 2-34 * Write Access after Write onto Same Address v1.1 2 - 85 ProASIC3 DC and Switching Characteristics CLK1 tAS tAH ADD1 DI1 A0 tDS tDH D0 tWRO A2 A3 D2 D3 CLK2 WEN_B1 WEN_B2 tAS tAH A0 ADD2 A1 A4 tCKQ1 DO2 (pass-through) DO2 (pipelined) Dn D0 tCKQ2 Dn D0 Figure 2-35 * Read Access after Write onto Same Address 2 -8 6 D1 v1.1 ProASIC3 DC and Switching Characteristics CLK1 tAS tAH A0 ADD1 A1 A0 WEN_B1 tCKQ1 DO1 (pass-through) tCKQ1 D0 Dn D1 tCKQ2 DO1 (pipelined) D0 Dn tCCKH CLK2 tAS tAH ADD2 A0 A1 A3 DI2 D1 D2 D3 WEN_B2 Figure 2-36 * Write Access after Read onto Same Address tCYC tCKH tCKL CLK RESET_B tRSTBQ DO Dm Dn Figure 2-37 * RAM Reset v1.1 2 - 87 ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-102 * RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tAS Address setup time 0.25 0.28 0.33 0.40 ns tAH Address hold time 0.00 0.00 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.14 0.16 0.19 0.23 ns tENH REN_B, WEN_B hold time 0.10 0.11 0.13 0.16 ns tBKS BLK_B setup time 0.23 0.27 0.31 0.37 ns tBKH BLK_B hold time 0.02 0.02 0.02 0.03 ns tDS Input data (DI) setup time 0.18 0.21 0.25 0.29 ns tDH Input data (DI) hold time 0.00 0.00 0.00 0.00 ns tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 2.36 2.68 3.15 3.79 ns Clock HIGH to new data valid on DO (flow-through, WMODE = 1) 1.79 2.03 2.39 2.87 ns tCKQ2 Clock HIGH to new data valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns tWRO Address collision clk-to-clk delay for reliable read access after write TBD TBD TBD TBD on same address ns tCCKH Address collision clk-to-clk delay for reliable write access after TBD TBD TBD TBD write/read on same address ns tRSTBQ RESET_B LOW to data out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns tREMRSTB RESET_B removal 0.29 0.33 0.38 0.46 ns tRECRSTB RESET_B recovery 1.50 1.71 2.01 2.41 ns tMPWRSTB RESET_B minimum pulse width 0.21 0.24 0.29 0.34 ns tCYC Clock cycle time 3.23 3.68 4.32 5.19 ns FMAX Maximum frequency 310 272 231 193 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -8 8 v1.1 ProASIC3 DC and Switching Characteristics Table 2-103 * RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tAS Address setup time 0.25 0.28 0.33 0.40 ns tAH Address hold time 0.00 0.00 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.13 0.15 0.17 0.21 ns tENH REN_B, WEN_B hold time 0.10 0.11 0.13 0.16 ns tDS Input data (DI) setup time 0.18 0.21 0.25 0.29 ns tDH Input data (DI) hold time 0.00 0.00 0.00 0.00 ns tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 2.16 2.46 2.89 3.47 ns tCKQ2 Clock HIGH to new data valid on DO (pipelined) 0.90 1.02 1.20 1.44 ns tWRO Address collision clk-to-clk delay for reliable read access after write TBD TBD TBD TBD on same address ns tCCKH Address collision clk-to-clk delay for reliable write access after TBD TBD TBD TBD write/read on same address ns tRSTBQ RESET_B LOW to data out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns RESET_B LOW to data out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns tREMRSTB RESET_B removal 0.29 0.33 0.38 0.46 ns tRECRSTB RESET_B recovery 1.50 1.71 2.01 2.41 ns tMPWRSTB RESET_B minimum pulse width 0.21 0.24 0.29 0.34 ns tCYC Clock cycle time 3.23 3.68 4.32 5.19 ns FMAX Maximum frequency 310 272 231 193 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 89 ProASIC3 DC and Switching Characteristics FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-38 * FIFO Model 2 -9 0 v1.1 ProASIC3 DC and Switching Characteristics Timing Waveforms RCLK/ WCLK tMPWRSTB tRSTCK RESET_B tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter) MATCH (A0) Figure 2-39 * FIFO Reset tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY) Figure 2-40 * FIFO EMPTY Flag and AEMPTY Flag Assertion v1.1 2 - 91 ProASIC3 DC and Switching Characteristics tCYC WCLK tWCKFF FULL tCKAF AFULL WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 2-41 * FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA (Address Counter) RCLK MATCH (EMPTY) NO MATCH 1st Rising Edge After 1st Write NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1 2nd Rising Edge After 1st Write tRCKEF EMPTY tCKAF AEMPTY Figure 2-42 * FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA MATCH (FULL) NO MATCH (Address Counter) 1st Rising Edge After 1st WCLK Read NO MATCH NO MATCH NO MATCH Dist = AFF_TH - 1 1st Rising Edge After 2nd Read tWCKF FULL tCKAF AFULL Figure 2-43 * FIFO FULL Flag and AFULL Flag Deassertion 2 -9 2 v1.1 ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-104 * FIFO (for all dies except A3P250) Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tENS REN_B, WEN_B Setup Time 1.34 1.52 1.79 2.15 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.17 2.47 2.90 3.48 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.94 1.07 1.26 1.52 ns tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns FMAX Maximum Frequency for FIFO 310 272 231 193 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. v1.1 2 - 93 ProASIC3 DC and Switching Characteristics Table 2-105 * FIFO (for A3P250 only, aspect-ratio-dependent) Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tENS REN_B, WEN_B Setup Time 3.26 3.71 4.36 5.24 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.17 2.47 2.90 3.48 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.94 1.07 1.26 1.52 ns tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns FMAX Maximum Frequency for FIFO 310 272 231 193 MHz 2 -9 4 v1.1 ProASIC3 DC and Switching Characteristics Table 2-106 * A3P250 FIFO 512x8 Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tENS REN_B, WEN_B Setup Time 3.75 4.27 5.02 6.04 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.17 2.47 2.90 3.48 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.94 1.07 1.26 1.52 ns tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns FMAX Maximum Frequency for FIFO 310 272 231 193 MHz v1.1 2 - 95 ProASIC3 DC and Switching Characteristics Table 2-107 * A3P250 FIFO 1kx4 Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tENS REN_B, WEN_B Setup Time 4.05 4.61 5.42 6.52 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.36 2.68 3.15 3.79 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns FMAX Maximum Frequency for FIFO 310 272 231 193 MHz 2 -9 6 v1.1 ProASIC3 DC and Switching Characteristics Table 2-108 * A3P250 FIFO 2kx2 Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tENS REN_B, WEN_B Setup Time 4.39 5.00 5.88 7.06 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.36 2.68 3.15 3.79 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 1.48 ns RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns FMAX Maximum Frequency for FIFO 310 272 231 193 MHz v1.1 2 - 97 ProASIC3 DC and Switching Characteristics Table 2-109 * A3P250 FIFO 4kx1 Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description -2 -1 Std. -F Units tENS REN_B, WEN_B Setup Time 4.86 5.53 6.50 7.81 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 0.00 0.00 ns tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.36 2.68 3.15 3.79 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (pass-through) 0.92 1.05 1.23 1.48 ns RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns FMAX Maximum Frequency 310 272 231 193 MHz 2 -9 8 v1.1 ProASIC3 DC and Switching Characteristics Embedded FlashROM Characteristics tSU CLK tSU tHOLD Address tSU tHOLD A0 tHOLD A1 tCKQ2 tCKQ2 D0 Data tCKQ2 D0 D1 Figure 2-44 * Timing Diagram Timing Characteristics Table 2-110 * Embedded FlashROM Access Time Parameter Description -2 -1 Std. Units tSU Address Setup Time 0.53 0.61 0.71 ns tHOLD Address Hold Time 0.00 0.00 0.00 ns tCK2Q Clock to Out 21.42 24.40 28.68 ns FMAX Maximum Clock Frequency 15 15 15 MHz v1.1 2 - 99 ProASIC3 DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-13 for more details. Timing Characteristics Table 2-111 * JTAG 1532 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description -2 -1 Std. Units tDISU Test Data Input Setup Time 0.50 0.57 0.67 ns tDIHD Test Data Input Hold Time 1.00 1.13 1.33 ns tTMSSU Test Mode Select Setup Time 0.50 0.57 0.67 ns tTMDHD Test Mode Select Hold Time 1.00 1.13 1.33 ns tTCK2Q Clock to Q (data out) 6.00 6.80 8.00 ns tRSTB2Q Reset to Q (data out) 20.00 22.67 26.67 ns FTCKMAX TCK Maximum Frequency 25.00 22.00 19.00 MHz tTRSTREM ResetB Removal Time 0.00 0.00 0.00 ns tTRSTREC ResetB Recovery Time 0.20 0.23 0.27 ns tTRSTMPW ResetB Minimum Pulse TBD TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -1 0 0 v1.1 ProASIC3 DC and Switching Characteristics Part Number and Revision Date Part Number 51700097-002-1 Revised January 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) Changes in Current Version (v1.1) Page In Table 2-2 * Recommended Operating Conditions, TJ was listed in the symbol column and was incorrect. It was corrected and changed to TA. 2-2 In Table 2-3 * Flash Programming Limits - Retention, Storage and Operating Temperature1, Maximum Operating Junction Temperature was changed from 110C to 100C for both commercial and industrial grades. 2-2 The "PLL Behavior at Brownout Condition" section is new. 2-3 In the "PLL Contribution--PPLL" section, the following was deleted: 2-11 FCLKIN is the input clock frequency. In Table 2-17 * Summary of Maximum and Minimum DC Input Levels, the note was incorrect. It previously said TJ and it was corrected and changed to TA. 2-18 In Table 2-101 * ProASIC3 CCC/PLL Specification, the SCLK parameter and note 1 are new. 2-80 Table 2-111 * JTAG 1532 was populated with the parameter data, which was not in the previous version of the document. 2-100 N/A (July 2007) This document was previously in datasheet v2.2. As a result of moving to the handbook format, Actel restarted the version numbers so the new version number is v1.0. v2.1 (May 2007) The TJ parameter in Table 3-2 * Recommended Operating Conditions was changed to TA, ambient temperature, and table notes 4-6 were added. 3-2 v2.0 (April 2007) Table 3-5 * Package Thermal Resistivities was information. The note below the table is also new. 3-5 v2.2 Advanced v0.7 (January 2007) updated with A3P1000 The timing characteristics tables were updated. N/A The "PLL Macro" section was updated to add information on the VCO and PLL outputs during power-up. 2-15 The "PLL Macro" section was updated to include power-up information. 2-15 Table 2-11 * ProASIC3 CCC/PLL Specification was updated. 2-29 Figure 2-19 * Peak-to-Peak Jitter Definition is new. 2-18 The "SRAM and FIFO" section was updated with operation and timing requirement information. 2-21 The "RESET" section was updated with read and write information. 2-25 The "RESET" section was updated with read and write information. 2-25 The"Introduction" in the "Advanced I/Os" section was updated to include information on input and output buffers being disabled. 2-28 PCI-X 3.3 V was added to Table 2-11 * VCCI Voltages and Compatible Standards. 2-29 In the Table 2-15 * Levels of Hot-Swap Support, the ProASIC3 compliance descriptions were updated for levels 3 and 4. 2-34 v1.1 2 -101 ProASIC3 DC and Switching Characteristics Previous Version Advanced v0.7 (continued) Changes in Current Version (v1.1) Page Table 2-43 * I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices was updated. 2-64 Notes 3, 4, and 5 were added to Table 2-17 * Comparison Table for 5 V- Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum current was updated from 4 x 52.7 to 5 x 52.7. 2-40 The "VCCPLF PLL Supply Voltage" section was updated. 2-50 The "VPUMP Programming Supply Voltage" section was updated. 2-50 The "GL Globals" section was updated to include information about direct input into quadrant clocks. 2-51 VJTAG was deleted from the "TCK Test Clock" section. 2-51 In Table 2-22 * Recommended Tie-Off Values for the TCK and TRST Pins, TSK was changed to TCK in note 2. Note 3 was also updated. 2-51 Ambient was deleted from Table 3-2 * Recommended Operating Conditions. VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45". 3-2 Note 3 is new in Table 3-4 * Overshoot and Undershoot Limits (as measured on quiet I/Os)1. 3-2 In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951. 3-5 Table 3-6 * Temperature and Voltage Derating Factors for Timing Delays was updated. 3-6 Table 3-5 * Package Thermal Resistivities was updated. 3-5 Table 3-14 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings (Advanced) and Table 3-17 * Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were updated. 3-17 to 3-17 Table 3-20 * Summary of I/O Timing Characteristics--Software Default Settings (Advanced) and Table 3-21 * Summary of I/O Timing Characteristics--Software Default Settings (Standard Plus) were updated. 3-20 to 3-20 Table 3-11 * Different Components Contributing Consumption in ProASIC3 Devices was updated. Dynamic Power 3-9 Table 3-24 * I/O Output Buffer Maximum Resistances1 (Advanced) and Table 325 * I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated. 3-22 to 3-22 Table 3-17 * Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions was updated. 3-18 Table 3-28 * I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 * I/O Short Currents IOSH/IOSL (Standard Plus) were updated. 3-24 to 3-26 The note in Table 3-32 * I/O Input Rise Time, Fall Time, and Related I/O Reliability was updated. 3-27 Figure 3-33 * Write Access After Write onto Same Address, Figure 3-34 * Read Access After Write onto Same Address, and Figure 3-35 * Write Access After Read onto Same Address are new. 3-82 to 3-84 Figure 3-43 * Timing Diagram was updated. 2 -1 0 2 to v1.1 3-96 ProASIC3 DC and Switching Characteristics Previous Version Advanced v0.5 (January 2006) Changes in Current Version (v1.1) Page BLVDS and M-LDVS are new I/O standards added to the datasheet. N/A The term flow-through was changed to pass-through. N/A Figure 2-7 * Efficient Long-Line Resources was updated. 2-7 The footnotes in Figure 2-15 * Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT were updated. 2-16 The Delay Increments in the Programmable Delay Blocks specification in Figure 2-24 * ProASIC3E CCC Options. 2-24 The "SRAM and FIFO" section was updated. 2-21 The "RESET" section was updated. 2-25 The "WCLK and RCLK" section was updated. 2-25 The "RESET" section was updated. 2-25 The "RESET" section was updated. 2-27 The "Introduction" of the "Advanced I/Os" section was updated. 2-28 The "I/O Banks" section is new. This section explains the following types of I/Os: 2-29 Advanced Standard+ Standard Table 2-12 * Automotive ProASIC3 Bank Types Definition and Differences is new. This table describes the standards listed above. PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 211 * VCCI Voltages and Compatible Standards 2-29 Table 2-13 * ProASIC3 I/O Features was updated. 2-30 The "Double Data Rate (DDR) Support" section was updated to include information concerning implementation of the feature. 2-32 The "Electrostatic Discharge (ESD) Protection" section was updated to include testing information. 2-35 Level 3 and 4 descriptions were updated in Table 2-43 * I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices. 2-64 The notes in Table 2-43 * I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices were updated. 2-64 The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout" section is new. 2-41 A footnote was added to Table 2-14 * Maximum I/O Frequency for Single-Ended and Differential I/Os in All Banks in Automotive ProASIC3 Devices (maximum drive strength and high slew selected). 2-30 Table 2-18 * Automotive ProASIC3 I/O Attributes vs. I/O Standard Applications 2-45 v1.1 2 -103 ProASIC3 DC and Switching Characteristics Previous Version Advanced v0.5 (January 2006) (continued) Changes in Current Version (v1.1) Page Table 2-50 * ProASIC3 Output Drive (OUT_DRIVE) for Standard I/O Bank Type (A3P030 device) 2-83 Table 2-51 * ProASIC3 Output Drive for Standard+ I/O Bank Type was updated. 2-84 Table 2-54 * ProASIC3 Output Drive for Advanced I/O Bank Type was updated. 2-84 The "x" was updated in the "User I/O Naming Convention" section. 2-48 The "VCC Core Supply Voltage" pin description was updated. 2-50 The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include information concerning leaving the pin unconnected. 2-50 The "VJTAG JTAG Supply Voltage" pin description was updated. 2-50 The "VPUMP Programming Supply Voltage" pin description was updated to include information on what happens when the pin is tied to ground. 2-50 The "I/O User Input/Output" pin description was updated to include information on what happens when the pin is unused. 2-50 The "JTAG Pins" section was updated to include information on what happens when the pin is unused. 2-51 The "Programming" section was updated to include information concerning serialization. 2-53 The "JTAG 1532" information. 2-54 section was updated to include SAMPLE/PRELOAD "DC and Switching Characteristics" chapter was updated with new information. Advanced v0.3 2 -1 0 4 Starting on page 3-1 M7 device information is new. N/A Table 2-4 * ProASIC3 Globals/Spines/Rows by Device was updated to include the number or rows in each top or bottom spine. 2-16 EXTFB was removed from Figure 2-24 * ProASIC3E CCC Options. 2-24 The "PLL Macro" section was updated. EXTFB information was removed from this section. 2-15 The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table 211 * ProASIC3 CCC/PLL Specification 2-29 EXTFB was removed from Figure 2-27 * CCC/PLL Macro. 2-28 Table 2-13 * ProASIC3 I/O Features was updated. 2-30 The "Hot-Swap Support" section was updated. 2-33 The "Cold-Sparing Support" section was updated. 2-34 "Electrostatic Discharge (ESD) Protection" section was updated. 2-35 The LVPECL specification in Table 2-43 * I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices was updated. 2-64 In the Bank 1 area of Figure 2-72, VMV2 was changed to VMV1 and VCCIB2 was changed to VCCIB1. 2-97 The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions" section. 2-50 The "JTAG Pins" section was updated. 2-51 v1.1 ProASIC3 DC and Switching Characteristics Previous Version Advanced v0.3 (continued) Changes in Current Version (v1.1) Page "128-Bit AES Decryption" section was updated to include M7 device information. 2-53 Table 3-6 was updated. 3-6 Table 3-7 was updated. 3-6 In Table 3-11, PAC4 was updated. Advanced v0.2 3-93-8 Table 3-20 was updated. 3-20 The note in Table 3-32 was updated. 3-27 All Timing Characteristics tables were updated from LVTTL to Register Delays 3-31 to 3-73 The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated. 3-85 to 3-90 FTCKMAX was updated in Table 3-110. 3-97 Figure 2-11 was updated. 2-9 The "Clock Resources (VersaNets)" section was updated. 2-9 The "VersaNet Global Networks and Spine Access" section was updated. 2-9 The "PLL Macro" section was updated. 2-15 Figure 2-27 was updated. 2-28 Figure 2-20 was updated. 2-19 Table 2-5 was updated. 2-25 Table 2-6 was updated. 2-25 The "FIFO Flag Usage Considerations" section was updated. 2-27 Table 2-13 was updated. 2-30 Figure 2-24 was updated. 2-31 The "Cold-Sparing Support" section is new. 2-34 Table 2-43 was updated. 2-64 Table 2-18 was updated. 2-45 Pin descriptions in the "JTAG Pins" section were updated. 2-51 The "User I/O Naming Convention" section was updated. 2-48 Table 3-7 was updated. 3-6 The "Methodology" section was updated. 3-10 Table 3-40 and Table 3-39 were updated. 3-33, 3-32 v1.1 2 -105 ProASIC3 DC and Switching Characteristics Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advanced status datasheet may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. 2 -1 0 6 v1.1 ProASIC3 Packaging 3 - Package Pin Assignments 68-Pin QFN 1 Pin A1 Mark 68 Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v1.3 3-1 Package Pin Assignments 68-Pin QFN 68-Pin QFN Pin Number A3P015 Function Pin Number A3P015 Function 1 IO82RSB1 37 TRST 2 IO80RSB1 38 VJTAG 3 IO78RSB1 39 IO40RSB0 4 IO76RSB1 40 IO37RSB0 5 GEC0/IO73RSB1 41 GDB0/IO34RSB0 6 GEA0/IO72RSB1 42 GDA0/IO33RSB0 7 GEB0/IO71RSB1 43 GDC0/IO32RSB0 8 VCC 44 VCCIB0 9 GND 45 GND 10 VCCIB1 46 VCC 11 IO68RSB1 47 IO31RSB0 12 IO67RSB1 48 IO29RSB0 13 IO66RSB1 49 IO28RSB0 14 IO65RSB1 50 IO27RSB0 15 IO64RSB1 51 IO25RSB0 16 IO63RSB1 52 IO24RSB0 17 IO62RSB1 53 IO22RSB0 18 IO60RSB1 54 IO21RSB0 19 IO58RSB1 55 IO19RSB0 20 IO56RSB1 56 IO17RSB0 21 IO54RSB1 57 IO15RSB0 22 IO52RSB1 58 IO14RSB0 23 IO51RSB1 59 VCCIB0 24 VCC 60 GND 25 GND 61 VCC 26 VCCIB1 62 IO12RSB0 27 IO50RSB1 63 IO10RSB0 28 IO48RSB1 64 IO08RSB0 29 IO46RSB1 65 IO06RSB0 30 IO44RSB1 66 IO04RSB0 31 IO42RSB1 67 IO02RSB0 32 TCK 68 IO00RSB0 33 TDI 34 TMS 35 VPUMP 36 TDO 3 -2 v1.3 ProASIC3 Packaging 132-Pin QFN A37 B34 C31 A48 B44 C40 Pin A1Mark D1 D4 A36 B33 C30 C1 C21 B23 A25 C10 B11 A12 D3 A1 B1 D2 C20 B22 A24 C11 B12 A13 Optional Corner Pad (4x) Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v1.3 3-3 Package Pin Assignments 132-Pin QFN 132-Pin QFN 132-Pin QFN Pin Number A3P030 Function Pin Number A3P030 Function Pin Number A3P030 Function A1 IO01RSB1 A37 IO26RSB0 B25 GND A2 IO81RSB1 A38 IO23RSB0 B26 NC A3 NC A39 NC B27 IO41RSB0 A4 IO80RSB1 A40 IO22RSB0 B28 GND A5 GEC0/IO77RSB1 A41 IO20RSB0 B29 GDA0/IO37RSB0 A6 NC A42 IO18RSB0 B30 NC A7 GEB0/IO75RSB1 A43 VCC B31 GND A8 IO73RSB1 A44 IO15RSB0 B32 IO33RSB0 A9 NC A45 IO12RSB0 B33 IO30RSB0 A10 VCC A46 IO10RSB0 B34 IO27RSB0 A11 IO71RSB1 A47 IO09RSB0 B35 IO24RSB0 A12 IO68RSB1 A48 IO06RSB0 B36 GND A13 IO63RSB1 B1 IO02RSB1 B37 IO21RSB0 A14 IO60RSB1 B2 IO82RSB1 B38 IO19RSB0 A15 NC B3 GND B39 GND A16 IO59RSB1 B4 IO79RSB1 B40 IO16RSB0 A17 IO57RSB1 B5 NC B41 IO13RSB0 A18 VCC B6 GND B42 GND A19 IO54RSB1 B7 IO74RSB1 B43 IO08RSB0 A20 IO52RSB1 B8 NC B44 IO05RSB0 A21 IO49RSB1 B9 GND C1 IO03RSB1 A22 IO48RSB1 B10 IO70RSB1 C2 IO00RSB1 A23 IO47RSB1 B11 IO67RSB1 C3 NC A24 TDI B12 IO64RSB1 C4 IO78RSB1 A25 TRST B13 IO61RSB1 C5 GEA0/IO76RSB1 A26 IO44RSB0 B14 GND C6 NC A27 NC B15 IO58RSB1 C7 NC A28 IO43RSB0 B16 IO56RSB1 C8 VCCIB1 A29 IO42RSB0 B17 GND C9 IO69RSB1 A30 IO40RSB0 B18 IO53RSB1 C10 IO66RSB1 A31 IO39RSB0 B19 IO50RSB1 C11 IO65RSB1 A32 GDC0/IO36RSB0 B20 GND C12 IO62RSB1 A33 NC B21 IO46RSB1 C13 NC A34 VCC B22 TMS C14 NC A35 IO34RSB0 B23 TDO C15 IO55RSB1 A36 IO31RSB0 B24 IO45RSB0 C16 VCCIB1 3 -4 v1.3 ProASIC3 Packaging 132-Pin QFN Pin Number A3P030 Function C17 IO51RSB1 C18 NC C19 TCK C20 NC C21 VPUMP C22 VJTAG C23 NC C24 NC C25 NC C26 GDB0/IO38RSB0 C27 NC C28 VCCIB0 C29 IO32RSB0 C30 IO29RSB0 C31 IO28RSB0 C32 IO25RSB0 C33 NC C34 NC C35 VCCIB0 C36 IO17RSB0 C37 IO14RSB0 C38 IO11RSB0 C39 IO07RSB0 C40 IO04RSB0 D1 GND D2 GND D3 GND D4 GND v1.3 3-5 Package Pin Assignments 132-Pin QFN 132-Pin QFN 132-Pin QFN Pin Number A3P060 Function Pin Number A3P060 Function Pin Number A3P060 Function A1 GAB2/IO00RSB1 A37 GBB1/IO25RSB0 B25 GND A2 IO93RSB1 A38 GBC0/IO22RSB0 B26 NC A3 VCCIB1 A39 VCCIB0 B27 GCB2/IO45RSB0 A4 GFC1/IO89RSB1 A40 IO21RSB0 B28 GND A5 GFB0/IO86RSB1 A41 IO18RSB0 B29 GCB0/IO41RSB0 A6 VCCPLF A42 IO15RSB0 B30 GCC1/IO38RSB0 A7 GFA1/IO84RSB1 A43 IO14RSB0 B31 GND A8 GFC2/IO81RSB1 A44 IO11RSB0 B32 GBB2/IO30RSB0 A9 IO78RSB1 A45 GAB1/IO08RSB0 B33 VMV0 A10 VCC A46 NC B34 GBA0/IO26RSB0 A11 GEB1/IO75RSB1 A47 GAB0/IO07RSB0 B35 GBC1/IO23RSB0 A12 GEA0/IO72RSB1 A48 IO04RSB0 B36 GND A13 GEC2/IO69RSB1 B1 IO01RSB1 B37 IO20RSB0 A14 IO65RSB1 B2 GAC2/IO94RSB1 B38 IO17RSB0 A15 VCC B3 GND B39 GND A16 IO64RSB1 B4 GFC0/IO88RSB1 B40 IO12RSB0 A17 IO63RSB1 B5 VCOMPLF B41 GAC0/IO09RSB0 A18 IO62RSB1 B6 GND B42 GND A19 IO61RSB1 B7 GFB2/IO82RSB1 B43 GAA1/IO06RSB0 A20 IO58RSB1 B8 IO79RSB1 B44 GNDQ A21 GDB2/IO55RSB1 B9 GND C1 GAA2/IO02RSB1 A22 NC B10 GEB0/IO74RSB1 C2 IO95RSB1 A23 GDA2/IO54RSB1 B11 VMV1 C3 VCC A24 TDI B12 GEB2/IO70RSB1 C4 GFB1/IO87RSB1 A25 TRST B13 IO67RSB1 C5 GFA0/IO85RSB1 A26 GDC1/IO48RSB0 B14 GND C6 GFA2/IO83RSB1 A27 VCC B15 NC C7 IO80RSB1 A28 IO47RSB0 B16 NC C8 VCCIB1 A29 GCC2/IO46RSB0 B17 GND C9 GEA1/IO73RSB1 A30 GCA2/IO44RSB0 B18 IO59RSB1 C10 GNDQ A31 GCA0/IO43RSB0 B19 GDC2/IO56RSB1 C11 GEA2/IO71RSB1 A32 GCB1/IO40RSB0 B20 GND C12 IO68RSB1 A33 IO36RSB0 B21 GNDQ C13 VCCIB1 A34 VCC B22 TMS C14 NC A35 IO31RSB0 B23 TDO C15 NC A36 GBA2/IO28RSB0 B24 GDC0/IO49RSB0 C16 IO60RSB1 3 -6 v1.3 ProASIC3 Packaging 132-Pin QFN Pin Number A3P060 Function C17 IO57RSB1 C18 NC C19 TCK C20 VMV1 C21 VPUMP C22 VJTAG C23 VCCIB0 C24 NC C25 NC C26 GCA1/IO42RSB0 C27 GCC0/IO39RSB0 C28 VCCIB0 C29 IO29RSB0 C30 GNDQ C31 GBA1/IO27RSB0 C32 GBB0/IO24RSB0 C33 VCC C34 IO19RSB0 C35 IO16RSB0 C36 IO13RSB0 C37 GAC1/IO10RSB0 C38 NC C39 GAA0/IO05RSB0 C40 VMV0 D1 GND D2 GND D3 GND D4 GND v1.3 3-7 Package Pin Assignments 132-Pin QFN 132-Pin QFN 132-Pin QFN Pin Number A3P125 Function Pin Number A3P125 Function Pin Number A3P125 Function A1 GAB2/IO69RSB1 A37 GBB1/IO38RSB0 B25 GND A2 IO130RSB1 A38 GBC0/IO35RSB0 B26 NC A3 VCCIB1 A39 VCCIB0 B27 GCB2/IO58RSB0 A4 GFC1/IO126RSB1 A40 IO28RSB0 B28 GND A5 GFB0/IO123RSB1 A41 IO22RSB0 B29 GCB0/IO54RSB0 A6 VCCPLF A42 IO18RSB0 B30 GCC1/IO51RSB0 A7 GFA1/IO121RSB1 A43 IO14RSB0 B31 GND A8 GFC2/IO118RSB1 A44 IO11RSB0 B32 GBB2/IO43RSB0 A9 IO115RSB1 A45 IO07RSB0 B33 VMV0 A10 VCC A46 VCC B34 GBA0/IO39RSB0 A11 GEB1/IO110RSB1 A47 GAC1/IO05RSB0 B35 GBC1/IO36RSB0 A12 GEA0/IO107RSB1 A48 GAB0/IO02RSB0 B36 GND A13 GEC2/IO104RSB1 B1 IO68RSB1 B37 IO26RSB0 A14 IO100RSB1 B2 GAC2/IO131RSB1 B38 IO21RSB0 A15 VCC B3 GND B39 GND A16 IO99RSB1 B4 GFC0/IO125RSB1 B40 IO13RSB0 A17 IO96RSB1 B5 VCOMPLF B41 IO08RSB0 A18 IO94RSB1 B6 GND B42 GND A19 IO91RSB1 B7 GFB2/IO119RSB1 B43 GAC0/IO04RSB0 A20 IO85RSB1 B8 IO116RSB1 B44 GNDQ A21 IO79RSB1 B9 GND C1 GAA2/IO67RSB1 A22 VCC B10 GEB0/IO109RSB1 C2 IO132RSB1 A23 GDB2/IO71RSB1 B11 VMV1 C3 VCC A24 TDI B12 GEB2/IO105RSB1 C4 GFB1/IO124RSB1 A25 TRST B13 IO101RSB1 C5 GFA0/IO122RSB1 A26 GDC1/IO61RSB0 B14 GND C6 GFA2/IO120RSB1 A27 VCC B15 IO98RSB1 C7 IO117RSB1 A28 IO60RSB0 B16 IO95RSB1 C8 VCCIB1 A29 GCC2/IO59RSB0 B17 GND C9 GEA1/IO108RSB1 A30 GCA2/IO57RSB0 B18 IO87RSB1 C10 GNDQ A31 GCA0/IO56RSB0 B19 IO81RSB1 C11 GEA2/IO106RSB1 A32 GCB1/IO53RSB0 B20 GND C12 IO103RSB1 A33 IO49RSB0 B21 GNDQ C13 VCCIB1 A34 VCC B22 TMS C14 IO97RSB1 A35 IO44RSB0 B23 TDO C15 IO93RSB1 A36 GBA2/IO41RSB0 B24 GDC0/IO62RSB0 C16 IO89RSB1 3 -8 v1.3 ProASIC3 Packaging 132-Pin QFN Pin Number A3P125 Function C17 IO83RSB1 C18 VCCIB1 C19 TCK C20 VMV1 C21 VPUMP C22 VJTAG C23 VCCIB0 C24 NC C25 NC C26 GCA1/IO55RSB0 C27 GCC0/IO52RSB0 C28 VCCIB0 C29 IO42RSB0 C30 GNDQ C31 GBA1/IO40RSB0 C32 GBB0/IO37RSB0 C33 VCC C34 IO24RSB0 C35 IO19RSB0 C36 IO16RSB0 C37 IO10RSB0 C38 VCCIB0 C39 GAB1/IO03RSB0 C40 VMV0 D1 GND D2 GND D3 GND D4 GND v1.3 3-9 Package Pin Assignments 132-Pin QFN 132-Pin QFN 132-Pin QFN Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function A1 GAB2/IO117UPB3 A37 GBB1/IO38RSB0 B25 GND A2 IO117VPB3 A38 GBC0/IO35RSB0 B26 IO54PDB1 A3 VCCIB3 A39 VCCIB0 B27 GCB2/IO52PDB1 A4 GFC1/IO110PDB3 A40 IO28RSB0 B28 GND A5 GFB0/IO109NPB3 A41 IO22RSB0 B29 GCB0/IO49NDB1 A6 VCCPLF A42 IO18RSB0 B30 GCC1/IO48PDB1 A7 GFA1/IO108PPB3 A43 IO14RSB0 B31 GND A8 GFC2/IO105PPB3 A44 IO11RSB0 B32 GBB2/IO42PDB1 A9 IO103NDB3 A45 IO07RSB0 B33 VMV1 A10 VCC A46 VCC B34 GBA0/IO39RSB0 A11 GEA1/IO98PPB3 A47 GAC1/IO05RSB0 B35 GBC1/IO36RSB0 A12 GEA0/IO98NPB3 A48 GAB0/IO02RSB0 B36 GND A13 GEC2/IO95RSB2 B1 IO118VDB3 B37 IO26RSB0 A14 IO91RSB2 B2 GAC2/IO116UDB3 B38 IO21RSB0 A15 VCC B3 GND B39 GND A16 IO90RSB2 B4 GFC0/IO110NDB3 B40 IO13RSB0 A17 IO87RSB2 B5 VCOMPLF B41 IO08RSB0 A18 IO85RSB2 B6 GND B42 GND A19 IO82RSB2 B7 GFB2/IO106PSB3 B43 GAC0/IO04RSB0 A20 IO76RSB2 B8 IO103PDB3 B44 GNDQ A21 IO70RSB2 B9 GND C1 GAA2/IO118UDB3 A22 VCC B10 GEB0/IO99NDB3 C2 IO116VDB3 A23 GDB2/IO62RSB2 B11 VMV3 C3 VCC A24 TDI B12 GEB2/IO96RSB2 C4 GFB1/IO109PPB3 A25 TRST B13 IO92RSB2 C5 GFA0/IO108NPB3 A26 GDC1/IO58UDB1 B14 GND C6 GFA2/IO107PSB3 A27 VCC B15 IO89RSB2 C7 IO105NPB3 A28 IO54NDB1 B16 IO86RSB2 C8 VCCIB3 A29 IO52NDB1 B17 GND C9 GEB1/IO99PDB3 A30 GCA2/IO51PPB1 B18 IO78RSB2 C10 GNDQ A31 GCA0/IO50NPB1 B19 IO72RSB2 C11 GEA2/IO97RSB2 A32 GCB1/IO49PDB1 B20 GND C12 IO94RSB2 A33 IO47NSB1 B21 GNDQ C13 VCCIB2 A34 VCC B22 TMS C14 IO88RSB2 A35 IO41NPB1 B23 TDO C15 IO84RSB2 A36 GBA2/IO41PPB1 B24 GDC0/IO58VDB1 C16 IO80RSB2 3 -1 0 v1.3 ProASIC3 Packaging 132-Pin QFN Pin Number A3P250 Function C17 IO74RSB2 C18 VCCIB2 C19 TCK C20 VMV2 C21 VPUMP C22 VJTAG C23 VCCIB1 C24 IO53NSB1 C25 IO51NPB1 C26 GCA1/IO50PPB1 C27 GCC0/IO48NDB1 C28 VCCIB1 C29 IO42NDB1 C30 GNDQ C31 GBA1/IO40RSB0 C32 GBB0/IO37RSB0 C33 VCC C34 IO24RSB0 C35 IO19RSB0 C36 IO16RSB0 C37 IO10RSB0 C38 VCCIB0 C39 GAB1/IO03RSB0 C40 VMV0 D1 GND D2 GND D3 GND D4 GND v1.3 3 - 11 Package Pin Assignments 100-Pin VQFP 100 1 100-Pin VQFP Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -1 2 v1.3 ProASIC3 Packaging 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A3P030 Function Pin Number A3P030 Function Pin Number A3P030 Function 1 GND 37 VCC 73 IO27RSB0 2 IO82RSB1 38 GND 74 IO26RSB0 3 IO81RSB1 39 VCCIB1 75 IO25RSB0 4 IO80RSB1 40 IO49RSB1 76 IO24RSB0 5 IO79RSB1 41 IO47RSB1 77 IO23RSB0 6 IO78RSB1 42 IO46RSB1 78 IO22RSB0 7 IO77RSB1 43 IO45RSB1 79 IO21RSB0 8 IO76RSB1 44 IO44RSB1 80 IO20RSB0 9 GND 45 IO43RSB1 81 IO19RSB0 10 IO75RSB1 46 IO42RSB1 82 IO18RSB0 11 IO74RSB1 47 TCK 83 IO17RSB0 12 GEC0/IO73RSB1 48 TDI 84 IO16RSB0 13 GEA0/IO72RSB1 49 TMS 85 IO15RSB0 14 GEB0/IO71RSB1 50 NC 86 IO14RSB0 15 IO70RSB1 51 GND 87 VCCIB0 16 IO69RSB1 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB1 54 TDO 90 IO12RSB0 19 IO68RSB1 55 TRST 91 IO10RSB0 20 IO67RSB1 56 VJTAG 92 IO08RSB0 21 IO66RSB1 57 IO41RSB0 93 IO07RSB0 22 IO65RSB1 58 IO40RSB0 94 IO06RSB0 23 IO64RSB1 59 IO39RSB0 95 IO05RSB0 24 IO63RSB1 60 IO38RSB0 96 IO04RSB0 25 IO62RSB1 61 IO37RSB0 97 IO03RSB0 26 IO61RSB1 62 IO36RSB0 98 IO02RSB0 27 IO60RSB1 63 GDB0/IO34RSB0 99 IO01RSB0 28 IO59RSB1 64 GDA0/IO33RSB0 100 IO00RSB0 29 IO58RSB1 65 GDC0/IO32RSB0 30 IO57RSB1 66 VCCIB0 31 IO56RSB1 67 GND 32 IO55RSB1 68 VCC 33 IO54RSB1 69 IO31RSB0 34 IO53RSB1 70 IO30RSB0 35 IO52RSB1 71 IO29RSB0 36 IO51RSB1 72 IO28RSB0 v1.3 3 - 13 Package Pin Assignments 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A3P060 Function Pin Number A3P060 Function Pin Number A3P060 Function 1 GND 37 VCC 73 GBA2/IO25RSB0 2 GAA2/IO51RSB1 38 GND 74 VMV0 3 IO52RSB1 39 VCCIB1 75 GNDQ 4 GAB2/IO53RSB1 40 IO60RSB1 76 GBA1/IO24RSB0 5 IO95RSB1 41 IO59RSB1 77 GBA0/IO23RSB0 6 GAC2/IO94RSB1 42 IO58RSB1 78 GBB1/IO22RSB0 7 IO93RSB1 43 IO57RSB1 79 GBB0/IO21RSB0 8 IO92RSB1 44 GDC2/IO56RSB1 80 GBC1/IO20RSB0 9 GND 45 GDB2/IO55RSB1 81 GBC0/IO19RSB0 10 GFB1/IO87RSB1 46 GDA2/IO54RSB1 82 IO18RSB0 11 GFB0/IO86RSB1 47 TCK 83 IO17RSB0 12 VCOMPLF 48 TDI 84 IO15RSB0 13 GFA0/IO85RSB1 49 TMS 85 IO13RSB0 14 VCCPLF 50 VMV1 86 IO11RSB0 15 GFA1/IO84RSB1 51 GND 87 VCCIB0 16 GFA2/IO83RSB1 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB1 54 TDO 90 IO10RSB0 19 GEC1/IO77RSB1 55 TRST 91 IO09RSB0 20 GEB1/IO75RSB1 56 VJTAG 92 IO08RSB0 21 GEB0/IO74RSB1 57 GDA1/IO49RSB0 93 GAC1/IO07RSB0 22 GEA1/IO73RSB1 58 GDC0/IO46RSB0 94 GAC0/IO06RSB0 23 GEA0/IO72RSB1 59 GDC1/IO45RSB0 95 GAB1/IO05RSB0 24 VMV1 60 GCC2/IO43RSB0 96 GAB0/IO04RSB0 25 GNDQ 61 GCB2/IO42RSB0 97 GAA1/IO03RSB0 26 GEA2/IO71RSB1 62 GCA0/IO40RSB0 98 GAA0/IO02RSB0 27 GEB2/IO70RSB1 63 GCA1/IO39RSB0 99 IO01RSB0 28 GEC2/IO69RSB1 64 GCC0/IO36RSB0 100 IO00RSB0 29 IO68RSB1 65 GCC1/IO35RSB0 30 IO67RSB1 66 VCCIB0 31 IO66RSB1 67 GND 32 IO65RSB1 68 VCC 33 IO64RSB1 69 IO31RSB0 34 IO63RSB1 70 GBC2/IO29RSB0 35 IO62RSB1 71 GBB2/IO27RSB0 36 IO61RSB1 72 IO26RSB0 3 -1 4 v1.3 ProASIC3 Packaging 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A3P125 Function Pin Number A3P125 Function Pin Number A3P125 Function 1 GND 37 VCC 73 GBA2/IO41RSB0 2 GAA2/IO67RSB1 38 GND 74 VMV0 3 IO68RSB1 39 VCCIB1 75 GNDQ 4 GAB2/IO69RSB1 40 IO87RSB1 76 GBA1/IO40RSB0 5 IO132RSB1 41 IO84RSB1 77 GBA0/IO39RSB0 6 GAC2/IO131RSB1 42 IO81RSB1 78 GBB1/IO38RSB0 7 IO130RSB1 43 IO75RSB1 79 GBB0/IO37RSB0 8 IO129RSB1 44 GDC2/IO72RSB1 80 GBC1/IO36RSB0 9 GND 45 GDB2/IO71RSB1 81 GBC0/IO35RSB0 10 GFB1/IO124RSB1 46 GDA2/IO70RSB1 82 IO32RSB0 11 GFB0/IO123RSB1 47 TCK 83 IO28RSB0 12 VCOMPLF 48 TDI 84 IO25RSB0 13 GFA0/IO122RSB1 49 TMS 85 IO22RSB0 14 VCCPLF 50 VMV1 86 IO19RSB0 15 GFA1/IO121RSB1 51 GND 87 VCCIB0 16 GFA2/IO120RSB1 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB1 54 TDO 90 IO15RSB0 19 GEC0/IO111RSB1 55 TRST 91 IO13RSB0 20 GEB1/IO110RSB1 56 VJTAG 92 IO11RSB0 21 GEB0/IO109RSB1 57 GDA1/IO65RSB0 93 IO09RSB0 22 GEA1/IO108RSB1 58 GDC0/IO62RSB0 94 IO07RSB0 23 GEA0/IO107RSB1 59 GDC1/IO61RSB0 95 GAC1/IO05RSB0 24 VMV1 60 GCC2/IO59RSB0 96 GAC0/IO04RSB0 25 GNDQ 61 GCB2/IO58RSB0 97 GAB1/IO03RSB0 26 GEA2/IO106RSB1 62 GCA0/IO56RSB0 98 GAB0/IO02RSB0 27 GEB2/IO105RSB1 63 GCA1/IO55RSB0 99 GAA1/IO01RSB0 28 GEC2/IO104RSB1 64 GCC0/IO52RSB0 100 GAA0/IO00RSB0 29 IO102RSB1 65 GCC1/IO51RSB0 30 IO100RSB1 66 VCCIB0 31 IO99RSB1 67 GND 32 IO97RSB1 68 VCC 33 IO96RSB1 69 IO47RSB0 34 IO95RSB1 70 GBC2/IO45RSB0 35 IO94RSB1 71 GBB2/IO43RSB0 36 IO93RSB1 72 IO42RSB0 v1.3 3 - 15 Package Pin Assignments 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function 1 GND 37 VCC 73 GBA2/IO41PDB1 2 GAA2/IO118UDB3 38 GND 74 VMV1 3 IO118VDB3 39 VCCIB2 75 GNDQ 4 GAB2/IO117UDB3 40 IO77RSB2 76 GBA1/IO40RSB0 5 IO117VDB3 41 IO74RSB2 77 GBA0/IO39RSB0 6 GAC2/IO116UDB3 42 IO71RSB2 78 GBB1/IO38RSB0 7 IO116VDB3 43 GDC2/IO63RSB2 79 GBB0/IO37RSB0 8 IO112PSB3 44 GDB2/IO62RSB2 80 GBC1/IO36RSB0 9 GND 45 GDA2/IO61RSB2 81 GBC0/IO35RSB0 10 GFB1/IO109PDB3 46 GNDQ 82 IO29RSB0 11 GFB0/IO109NDB3 47 TCK 83 IO27RSB0 12 VCOMPLF 48 TDI 84 IO25RSB0 13 GFA0/IO108NPB3 49 TMS 85 IO23RSB0 14 VCCPLF 50 VMV2 86 IO21RSB0 15 GFA1/IO108PPB3 51 GND 87 VCCIB0 16 GFA2/IO107PSB3 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB3 54 TDO 90 IO15RSB0 19 GFC2/IO105PSB3 55 TRST 91 IO13RSB0 20 GEC1/IO100PDB3 56 VJTAG 92 IO11RSB0 21 GEC0/IO100NDB3 57 GDA1/IO60USB1 93 GAC1/IO05RSB0 22 GEA1/IO98PDB3 58 GDC0/IO58VDB1 94 GAC0/IO04RSB0 23 GEA0/IO98NDB3 59 GDC1/IO58UDB1 95 GAB1/IO03RSB0 24 VMV3 60 IO52NDB1 96 GAB0/IO02RSB0 25 GNDQ 61 GCB2/IO52PDB1 97 GAA1/IO01RSB0 26 GEA2/IO97RSB2 62 GCA1/IO50PDB1 98 GAA0/IO00RSB0 27 GEB2/IO96RSB2 63 GCA0/IO50NDB1 99 GNDQ 28 GEC2/IO95RSB2 64 GCC0/IO48NDB1 100 VMV0 29 IO93RSB2 65 GCC1/IO48PDB1 30 IO92RSB2 66 VCCIB1 31 IO91RSB2 67 GND 32 IO90RSB2 68 VCC 33 IO88RSB2 69 IO43NDB1 34 IO86RSB2 70 GBC2/IO43PDB1 35 IO85RSB2 71 GBB2/IO42PSB1 36 IO84RSB2 72 IO41NDB1 3 -1 6 v1.3 ProASIC3 Packaging 144-Pin TQFP 144 1 144-Pin TQFP Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v1.3 3 - 17 Package Pin Assignments 144-Pin TQFP 144-Pin TQFP 144-Pin TQFP Pin Number A3P060 Function Pin Number A3P060 Function Pin Number A3P060 Function 1 GAA2/IO51RSB1 37 NC 73 VPUMP 2 IO52RSB1 38 GEA2/IO71RSB1 74 NC 3 GAB2/IO53RSB1 39 GEB2/IO70RSB1 75 TDO 4 IO95RSB1 40 GEC2/IO69RSB1 76 TRST 5 GAC2/IO94RSB1 41 IO68RSB1 77 VJTAG 6 IO93RSB1 42 IO67RSB1 78 GDA0/IO50RSB0 7 IO92RSB1 43 IO66RSB1 79 GDB0/IO48RSB0 8 IO91RSB1 44 IO65RSB1 80 GDB1/IO47RSB0 9 VCC 45 VCC 81 VCCIB0 10 GND 46 GND 82 GND 11 VCCIB1 47 VCCIB1 83 IO44RSB0 12 IO90RSB1 48 NC 84 GCC2/IO43RSB0 13 GFC1/IO89RSB1 49 IO64RSB1 85 GCB2/IO42RSB0 14 GFC0/IO88RSB1 50 NC 86 GCA2/IO41RSB0 15 GFB1/IO87RSB1 51 IO63RSB1 87 GCA0/IO40RSB0 16 GFB0/IO86RSB1 52 NC 88 GCA1/IO39RSB0 17 VCOMPLF 53 IO62RSB1 89 GCB0/IO38RSB0 18 GFA0/IO85RSB1 54 NC 90 GCB1/IO37RSB0 19 VCCPLF 55 IO61RSB1 91 GCC0/IO36RSB0 20 GFA1/IO84RSB1 56 NC 92 GCC1/IO35RSB0 21 GFA2/IO83RSB1 57 NC 93 IO34RSB0 22 GFB2/IO82RSB1 58 IO60RSB1 94 IO33RSB0 23 GFC2/IO81RSB1 59 IO59RSB1 95 NC 24 IO80RSB1 60 IO58RSB1 96 NC 25 IO79RSB1 61 IO57RSB1 97 NC 26 IO78RSB1 62 NC 98 VCCIB0 27 GND 63 GND 99 GND 28 VCCIB1 64 NC 100 VCC 29 GEC1/IO77RSB1 65 GDC2/IO56RSB1 101 IO30RSB0 30 GEC0/IO76RSB1 66 GDB2/IO55RSB1 102 GBC2/IO29RSB0 31 GEB1/IO75RSB1 67 GDA2/IO54RSB1 103 IO28RSB0 32 GEB0/IO74RSB1 68 GNDQ 104 GBB2/IO27RSB0 33 GEA1/IO73RSB1 69 TCK 105 IO26RSB0 34 GEA0/IO72RSB1 70 TDI 106 GBA2/IO25RSB0 35 VMV1 71 TMS 107 VMV0 36 GNDQ 72 VMV1 108 GNDQ 3 -1 8 v1.3 ProASIC3 Packaging 144-Pin TQFP Pin Number A3P060 Function 109 NC 110 NC 111 GBA1/IO24RSB0 112 GBA0/IO23RSB0 113 GBB1/IO22RSB0 114 GBB0/IO21RSB0 115 GBC1/IO20RSB0 116 GBC0/IO19RSB0 117 VCCIB0 118 GND 119 VCC 120 IO18RSB0 121 IO17RSB0 122 IO16RSB0 123 IO15RSB0 124 IO14RSB0 125 IO13RSB0 126 IO12RSB0 127 IO11RSB0 128 NC 129 IO10RSB0 130 IO09RSB0 131 IO08RSB0 132 GAC1/IO07RSB0 133 GAC0/IO06RSB0 134 NC 135 GND 136 NC 137 GAB1/IO05RSB0 138 GAB0/IO04RSB0 139 GAA1/IO03RSB0 140 GAA0/IO02RSB0 141 IO01RSB0 142 IO00RSB0 143 GNDQ 144 VMV0 v1.3 3 - 19 Package Pin Assignments 144-Pin TQFP 144-Pin TQFP 144-Pin TQFP Pin Number A3P125 Function Pin Number A3P125 Function Pin Number A3P125 Function 1 GAA2/IO67RSB1 37 NC 73 VPUMP 2 IO68RSB1 38 GEA2/IO106RSB1 74 NC 3 GAB2/IO69RSB1 39 GEB2/IO105RSB1 75 TDO 4 IO132RSB1 40 GEC2/IO104RSB1 76 TRST 5 GAC2/IO131RSB1 41 IO103RSB1 77 VJTAG 6 IO130RSB1 42 IO102RSB1 78 GDA0/IO66RSB0 7 IO129RSB1 43 IO101RSB1 79 GDB0/IO64RSB0 8 IO128RSB1 44 IO100RSB1 80 GDB1/IO63RSB0 9 VCC 45 VCC 81 VCCIB0 10 GND 46 GND 82 GND 11 VCCIB1 47 VCCIB1 83 IO60RSB0 12 IO127RSB1 48 IO99RSB1 84 GCC2/IO59RSB0 13 GFC1/IO126RSB1 49 IO97RSB1 85 GCB2/IO58RSB0 14 GFC0/IO125RSB1 50 IO95RSB1 86 GCA2/IO57RSB0 15 GFB1/IO124RSB1 51 IO93RSB1 87 GCA0/IO56RSB0 16 GFB0/IO123RSB1 52 IO92RSB1 88 GCA1/IO55RSB0 17 VCOMPLF 53 IO90RSB1 89 GCB0/IO54RSB0 18 GFA0/IO122RSB1 54 IO88RSB1 90 GCB1/IO53RSB0 19 VCCPLF 55 IO86RSB1 91 GCC0/IO52RSB0 20 GFA1/IO121RSB1 56 IO84RSB1 92 GCC1/IO51RSB0 21 GFA2/IO120RSB1 57 IO83RSB1 93 IO50RSB0 22 GFB2/IO119RSB1 58 IO82RSB1 94 IO49RSB0 23 GFC2/IO118RSB1 59 IO81RSB1 95 NC 24 IO117RSB1 60 IO80RSB1 96 NC 25 IO116RSB1 61 IO79RSB1 97 NC 26 IO115RSB1 62 VCC 98 VCCIB0 27 GND 63 GND 99 GND 28 VCCIB1 64 VCCIB1 100 VCC 29 GEC1/IO112RSB1 65 GDC2/IO72RSB1 101 IO47RSB0 30 GEC0/IO111RSB1 66 GDB2/IO71RSB1 102 GBC2/IO45RSB0 31 GEB1/IO110RSB1 67 GDA2/IO70RSB1 103 IO44RSB0 32 GEB0/IO109RSB1 68 GNDQ 104 GBB2/IO43RSB0 33 GEA1/IO108RSB1 69 TCK 105 IO42RSB0 34 GEA0/IO107RSB1 70 TDI 106 GBA2/IO41RSB0 35 VMV1 71 TMS 107 VMV0 36 GNDQ 72 VMV1 108 GNDQ 3 -2 0 v1.3 ProASIC3 Packaging 144-Pin TQFP Pin Number A3P125 Function 109 GBA1/IO40RSB0 110 GBA0/IO39RSB0 111 GBB1/IO38RSB0 112 GBB0/IO37RSB0 113 GBC1/IO36RSB0 114 GBC0/IO35RSB0 115 IO34RSB0 116 IO33RSB0 117 VCCIB0 118 GND 119 VCC 120 IO29RSB0 121 IO28RSB0 122 IO27RSB0 123 IO25RSB0 124 IO23RSB0 125 IO21RSB0 126 IO19RSB0 127 IO17RSB0 128 IO16RSB0 129 IO14RSB0 130 IO12RSB0 131 IO10RSB0 132 IO08RSB0 133 IO06RSB0 134 VCCIB0 135 GND 136 VCC 137 GAC1/IO05RSB0 138 GAC0/IO04RSB0 139 GAB1/IO03RSB0 140 GAB0/IO02RSB0 141 GAA1/IO01RSB0 142 GAA0/IO00RSB0 143 GNDQ 144 VMV0 v1.3 3 - 21 Package Pin Assignments 208-Pin PQFP 1 208 208-Pin PQFP Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -2 2 v1.3 ProASIC3 Packaging 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP Pin Number A3P125 Function Pin Number A3P125 Function Pin Number A3P125 Function 1 GND 37 IO116RSB1 73 IO92RSB1 2 GAA2/IO67RSB1 38 IO115RSB1 74 IO91RSB1 3 IO68RSB1 39 NC 75 IO90RSB1 4 GAB2/IO69RSB1 40 VCCIB1 76 IO89RSB1 5 IO132RSB1 41 GND 77 IO88RSB1 6 GAC2/IO131RSB1 42 IO114RSB1 78 IO87RSB1 7 NC 43 IO113RSB1 79 IO86RSB1 8 NC 44 GEC1/IO112RSB1 80 IO85RSB1 9 IO130RSB1 45 GEC0/IO111RSB1 81 GND 10 IO129RSB1 46 GEB1/IO110RSB1 82 IO84RSB1 11 NC 47 GEB0/IO109RSB1 83 IO83RSB1 12 IO128RSB1 48 GEA1/IO108RSB1 84 IO82RSB1 13 NC 49 GEA0/IO107RSB1 85 IO81RSB1 14 NC 50 VMV1 86 IO80RSB1 15 NC 51 GNDQ 87 IO79RSB1 16 VCC 52 GND 88 VCC 17 GND 53 NC 89 VCCIB1 18 VCCIB1 54 NC 90 IO78RSB1 19 IO127RSB1 55 GEA2/IO106RSB1 91 IO77RSB1 20 NC 56 GEB2/IO105RSB1 92 IO76RSB1 21 GFC1/IO126RSB1 57 GEC2/IO104RSB1 93 IO75RSB1 22 GFC0/IO125RSB1 58 IO103RSB1 94 IO74RSB1 23 GFB1/IO124RSB1 59 IO102RSB1 95 IO73RSB1 24 GFB0/IO123RSB1 60 IO101RSB1 96 GDC2/IO72RSB1 25 VCOMPLF 61 IO100RSB1 97 GND 26 GFA0/IO122RSB1 62 VCCIB1 98 GDB2/IO71RSB1 27 VCCPLF 63 IO99RSB1 99 GDA2/IO70RSB1 28 GFA1/IO121RSB1 64 IO98RSB1 100 GNDQ 29 GND 65 GND 101 TCK 30 GFA2/IO120RSB1 66 IO97RSB1 102 TDI 31 NC 67 IO96RSB1 103 TMS 32 GFB2/IO119RSB1 68 IO95RSB1 104 VMV1 33 NC 69 IO94RSB1 105 GND 34 GFC2/IO118RSB1 70 IO93RSB1 106 VPUMP 35 IO117RSB1 71 VCC 107 NC 36 NC 72 VCCIB1 108 TDO v1.3 3 - 23 Package Pin Assignments 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP Pin Number A3P125 Function Pin Number A3P125 Function Pin Number A3P125 Function 109 TRST 145 IO46RSB0 181 IO21RSB0 110 VJTAG 146 NC 182 IO20RSB0 111 GDA0/IO66RSB0 147 NC 183 IO19RSB0 112 GDA1/IO65RSB0 148 NC 184 IO18RSB0 113 GDB0/IO64RSB0 149 GBC2/IO45RSB0 185 IO17RSB0 114 GDB1/IO63RSB0 150 IO44RSB0 186 VCCIB0 115 GDC0/IO62RSB0 151 GBB2/IO43RSB0 187 VCC 116 GDC1/IO61RSB0 152 IO42RSB0 188 IO16RSB0 117 NC 153 GBA2/IO41RSB0 189 IO15RSB0 118 NC 154 VMV0 190 IO14RSB0 119 NC 155 GNDQ 191 IO13RSB0 120 NC 156 GND 192 IO12RSB0 121 NC 157 NC 193 IO11RSB0 122 GND 158 GBA1/IO40RSB0 194 IO10RSB0 123 VCCIB0 159 GBA0/IO39RSB0 195 GND 124 NC 160 GBB1/IO38RSB0 196 IO09RSB0 125 NC 161 GBB0/IO37RSB0 197 IO08RSB0 126 VCC 162 GND 198 IO07RSB0 127 IO60RSB0 163 GBC1/IO36RSB0 199 IO06RSB0 128 GCC2/IO59RSB0 164 GBC0/IO35RSB0 200 VCCIB0 129 GCB2/IO58RSB0 165 IO34RSB0 201 GAC1/IO05RSB0 130 GND 166 IO33RSB0 202 GAC0/IO04RSB0 131 GCA2/IO57RSB0 167 IO32RSB0 203 GAB1/IO03RSB0 132 GCA0/IO56RSB0 168 IO31RSB0 204 GAB0/IO02RSB0 133 GCA1/IO55RSB0 169 IO30RSB0 205 GAA1/IO01RSB0 134 GCB0/IO54RSB0 170 VCCIB0 206 GAA0/IO00RSB0 135 GCB1/IO53RSB0 171 VCC 207 GNDQ 136 GCC0/IO52RSB0 172 IO29RSB0 208 VMV0 137 GCC1/IO51RSB0 173 IO28RSB0 138 IO50RSB0 174 IO27RSB0 139 IO49RSB0 175 IO26RSB0 140 VCCIB0 176 IO25RSB0 141 GND 177 IO24RSB0 142 VCC 178 GND 143 IO48RSB0 179 IO23RSB0 144 IO47RSB0 180 IO22RSB0 3 -2 4 v1.3 ProASIC3 Packaging 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function 1 GND 37 IO104PDB3 73 IO83RSB2 2 GAA2/IO118UDB3 38 IO104NDB3 74 IO82RSB2 3 IO118VDB3 39 IO103PSB3 75 IO81RSB2 4 GAB2/IO117UDB3 40 VCCIB3 76 IO80RSB2 5 IO117VDB3 41 GND 77 IO79RSB2 6 GAC2/IO116UDB3 42 IO101PDB3 78 IO78RSB2 7 IO116VDB3 43 IO101NDB3 79 IO77RSB2 8 IO115UDB3 44 GEC1/IO100PDB3 80 IO76RSB2 9 IO115VDB3 45 GEC0/IO100NDB3 81 GND 10 IO114UDB3 46 GEB1/IO99PDB3 82 IO75RSB2 11 IO114VDB3 47 GEB0/IO99NDB3 83 IO74RSB2 12 IO113PDB3 48 GEA1/IO98PDB3 84 IO73RSB2 13 IO113NDB3 49 GEA0/IO98NDB3 85 IO72RSB2 14 IO112PDB3 50 VMV3 86 IO71RSB2 15 IO112NDB3 51 GNDQ 87 IO70RSB2 16 VCC 52 GND 88 VCC 17 GND 53 NC 89 VCCIB2 18 VCCIB3 54 NC 90 IO69RSB2 19 IO111PDB3 55 GEA2/IO97RSB2 91 IO68RSB2 20 IO111NDB3 56 GEB2/IO96RSB2 92 IO67RSB2 21 GFC1/IO110PDB3 57 GEC2/IO95RSB2 93 IO66RSB2 22 GFC0/IO110NDB3 58 IO94RSB2 94 IO65RSB2 23 GFB1/IO109PDB3 59 IO93RSB2 95 IO64RSB2 24 GFB0/IO109NDB3 60 IO92RSB2 96 GDC2/IO63RSB2 25 VCOMPLF 61 IO91RSB2 97 GND 26 GFA0/IO108NPB3 62 VCCIB2 98 GDB2/IO62RSB2 27 VCCPLF 63 IO90RSB2 99 GDA2/IO61RSB2 28 GFA1/IO108PPB3 64 IO89RSB2 100 GNDQ 29 GND 65 GND 101 TCK 30 GFA2/IO107PDB3 66 IO88RSB2 102 TDI 31 IO107NDB3 67 IO87RSB2 103 TMS 32 GFB2/IO106PDB3 68 IO86RSB2 104 VMV2 33 IO106NDB3 69 IO85RSB2 105 GND 34 GFC2/IO105PDB3 70 IO84RSB2 106 VPUMP 35 IO105NDB3 71 VCC 107 NC 36 NC 72 VCCIB2 108 TDO v1.3 3 - 25 Package Pin Assignments 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function 109 TRST 145 IO45PDB1 181 IO21RSB0 110 VJTAG 146 IO44NDB1 182 IO20RSB0 111 GDA0/IO60VDB1 147 IO44PDB1 183 IO19RSB0 112 GDA1/IO60UDB1 148 IO43NDB1 184 IO18RSB0 113 GDB0/IO59VDB1 149 GBC2/IO43PDB1 185 IO17RSB0 114 GDB1/IO59UDB1 150 IO42NDB1 186 VCCIB0 115 GDC0/IO58VDB1 151 GBB2/IO42PDB1 187 VCC 116 GDC1/IO58UDB1 152 IO41NDB1 188 IO16RSB0 117 IO57VDB1 153 GBA2/IO41PDB1 189 IO15RSB0 118 IO57UDB1 154 VMV1 190 IO14RSB0 119 IO56NDB1 155 GNDQ 191 IO13RSB0 120 IO56PDB1 156 GND 192 IO12RSB0 121 IO55RSB1 157 NC 193 IO11RSB0 122 GND 158 GBA1/IO40RSB0 194 IO10RSB0 123 VCCIB1 159 GBA0/IO39RSB0 195 GND 124 NC 160 GBB1/IO38RSB0 196 IO09RSB0 125 NC 161 GBB0/IO37RSB0 197 IO08RSB0 126 VCC 162 GND 198 IO07RSB0 127 IO53NDB1 163 GBC1/IO36RSB0 199 IO06RSB0 128 GCC2/IO53PDB1 164 GBC0/IO35RSB0 200 VCCIB0 129 GCB2/IO52PSB1 165 IO34RSB0 201 GAC1/IO05RSB0 130 GND 166 IO33RSB0 202 GAC0/IO04RSB0 131 GCA2/IO51PSB1 167 IO32RSB0 203 GAB1/IO03RSB0 132 GCA1/IO50PDB1 168 IO31RSB0 204 GAB0/IO02RSB0 133 GCA0/IO50NDB1 169 IO30RSB0 205 GAA1/IO01RSB0 134 GCB0/IO49NDB1 170 VCCIB0 206 GAA0/IO00RSB0 135 GCB1/IO49PDB1 171 VCC 207 GNDQ 136 GCC0/IO48NDB1 172 IO29RSB0 208 VMV0 137 GCC1/IO48PDB1 173 IO28RSB0 138 IO47NDB1 174 IO27RSB0 139 IO47PDB1 175 IO26RSB0 140 VCCIB1 176 IO25RSB0 141 GND 177 IO24RSB0 142 VCC 178 GND 143 IO46RSB1 179 IO23RSB0 144 IO45NDB1 180 IO22RSB0 3 -2 6 v1.3 ProASIC3 Packaging 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function 1 GND 37 IO141PSB3 73 IO112RSB2 2 GAA2/IO155UDB3 38 IO140PDB3 74 IO111RSB2 3 IO155VDB3 39 IO140NDB3 75 IO110RSB2 4 GAB2/IO154UDB3 40 VCCIB3 76 IO109RSB2 5 IO154VDB3 41 GND 77 IO108RSB2 6 GAC2/IO153UDB3 42 IO138PDB3 78 IO107RSB2 7 IO153VDB3 43 IO138NDB3 79 IO106RSB2 8 IO152UDB3 44 GEC1/IO137PDB3 80 IO104RSB2 9 IO152VDB3 45 GEC0/IO137NDB3 81 GND 10 IO151UDB3 46 GEB1/IO136PDB3 82 IO102RSB2 11 IO151VDB3 47 GEB0/IO136NDB3 83 IO101RSB2 12 IO150PDB3 48 GEA1/IO135PDB3 84 IO100RSB2 13 IO150NDB3 49 GEA0/IO135NDB3 85 IO99RSB2 14 IO149PDB3 50 VMV3 86 IO98RSB2 15 IO149NDB3 51 GNDQ 87 IO97RSB2 16 VCC 52 GND 88 VCC 17 GND 53 VMV2 89 VCCIB2 18 VCCIB3 54 NC 90 IO94RSB2 19 IO148PDB3 55 GEA2/IO134RSB2 91 IO92RSB2 20 IO148NDB3 56 GEB2/IO133RSB2 92 IO90RSB2 21 GFC1/IO147PDB3 57 GEC2/IO132RSB2 93 IO88RSB2 22 GFC0/IO147NDB3 58 IO131RSB2 94 IO86RSB2 23 GFB1/IO146PDB3 59 IO130RSB2 95 IO84RSB2 24 GFB0/IO146NDB3 60 IO129RSB2 96 GDC2/IO82RSB2 25 VCOMPLF 61 IO128RSB2 97 GND 26 GFA0/IO145NPB3 62 VCCIB2 98 GDB2/IO81RSB2 27 VCCPLF 63 IO125RSB2 99 GDA2/IO80RSB2 28 GFA1/IO145PPB3 64 IO123RSB2 100 GNDQ 29 GND 65 GND 101 TCK 30 GFA2/IO144PDB3 66 IO121RSB2 102 TDI 31 IO144NDB3 67 IO119RSB2 103 TMS 32 GFB2/IO143PDB3 68 IO117RSB2 104 VMV2 33 IO143NDB3 69 IO115RSB2 105 GND 34 GFC2/IO142PDB3 70 IO113RSB2 106 VPUMP 35 IO142NDB3 71 VCC 107 NC 36 NC 72 VCCIB2 108 TDO v1.3 3 - 27 Package Pin Assignments 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function 109 TRST 145 IO64PDB1 181 IO27RSB0 110 VJTAG 146 IO63NDB1 182 IO26RSB0 111 GDA0/IO79VDB1 147 IO63PDB1 183 IO25RSB0 112 GDA1/IO79UDB1 148 IO62NDB1 184 IO24RSB0 113 GDB0/IO78VDB1 149 GBC2/IO62PDB1 185 IO23RSB0 114 GDB1/IO78UDB1 150 IO61NDB1 186 VCCIB0 115 GDC0/IO77VDB1 151 GBB2/IO61PDB1 187 VCC 116 GDC1/IO77UDB1 152 IO60NDB1 188 IO21RSB0 117 IO76VDB1 153 GBA2/IO60PDB1 189 IO20RSB0 118 IO76UDB1 154 VMV1 190 IO19RSB0 119 IO75NDB1 155 GNDQ 191 IO18RSB0 120 IO75PDB1 156 GND 192 IO17RSB0 121 IO74RSB1 157 VMV0 193 IO16RSB0 122 GND 158 GBA1/IO59RSB0 194 IO15RSB0 123 VCCIB1 159 GBA0/IO58RSB0 195 GND 124 NC 160 GBB1/IO57RSB0 196 IO13RSB0 125 NC 161 GBB0/IO56RSB0 197 IO11RSB0 126 VCC 162 GND 198 IO09RSB0 127 IO72NDB1 163 GBC1/IO55RSB0 199 IO07RSB0 128 GCC2/IO72PDB1 164 GBC0/IO54RSB0 200 VCCIB0 129 GCB2/IO71PSB1 165 IO52RSB0 201 GAC1/IO05RSB0 130 GND 166 IO49RSB0 202 GAC0/IO04RSB0 131 GCA2/IO70PSB1 167 IO46RSB0 203 GAB1/IO03RSB0 132 GCA1/IO69PDB1 168 IO43RSB0 204 GAB0/IO02RSB0 133 GCA0/IO69NDB1 169 IO40RSB0 205 GAA1/IO01RSB0 134 GCB0/IO68NDB1 170 VCCIB0 206 GAA0/IO00RSB0 135 GCB1/IO68PDB1 171 VCC 207 GNDQ 136 GCC0/IO67NDB1 172 IO36RSB0 208 VMV0 137 GCC1/IO67PDB1 173 IO35RSB0 138 IO66NDB1 174 IO34RSB0 139 IO66PDB1 175 IO33RSB0 140 VCCIB1 176 IO32RSB0 141 GND 177 IO31RSB0 142 VCC 178 GND 143 IO65RSB1 179 IO29RSB0 144 IO64NDB1 180 IO28RSB0 3 -2 8 v1.3 ProASIC3 Packaging 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function 1 GND 37 IO152PDB3 73 IO120RSB2 2 GAA2/IO174PDB3 38 IO152NDB3 74 IO119RSB2 3 IO174NDB3 39 IO150PSB3 75 IO118RSB2 4 GAB2/IO173PDB3 40 VCCIB3 76 IO117RSB2 5 IO173NDB3 41 GND 77 IO116RSB2 6 GAC2/IO172PDB3 42 IO147PDB3 78 IO115RSB2 7 IO172NDB3 43 IO147NDB3 79 IO114RSB2 8 IO171PDB3 44 GEC1/IO146PDB3 80 IO112RSB2 9 IO171NDB3 45 GEC0/IO146NDB3 81 GND 10 IO170PDB3 46 GEB1/IO145PDB3 82 IO111RSB2 11 IO170NDB3 47 GEB0/IO145NDB3 83 IO110RSB2 12 IO169PDB3 48 GEA1/IO144PDB3 84 IO109RSB2 13 IO169NDB3 49 GEA0/IO144NDB3 85 IO108RSB2 14 IO168PDB3 50 VMV3 86 IO107RSB2 15 IO168NDB3 51 GNDQ 87 IO106RSB2 16 VCC 52 GND 88 VCC 17 GND 53 VMV2 89 VCCIB2 18 VCCIB3 54 GEA2/IO143RSB2 90 IO104RSB2 19 IO166PDB3 55 GEB2/IO142RSB2 91 IO102RSB2 20 IO166NDB3 56 GEC2/IO141RSB2 92 IO100RSB2 21 GFC1/IO164PDB3 57 IO140RSB2 93 IO98RSB2 22 GFC0/IO164NDB3 58 IO139RSB2 94 IO96RSB2 23 GFB1/IO163PDB3 59 IO138RSB2 95 IO92RSB2 24 GFB0/IO163NDB3 60 IO137RSB2 96 GDC2/IO91RSB2 25 VCOMPLF 61 IO136RSB2 97 GND 26 GFA0/IO162NPB3 62 VCCIB2 98 GDB2/IO90RSB2 27 VCCPLF 63 IO135RSB2 99 GDA2/IO89RSB2 28 GFA1/IO162PPB3 64 IO133RSB2 100 GNDQ 29 GND 65 GND 101 TCK 30 GFA2/IO161PDB3 66 IO131RSB2 102 TDI 31 IO161NDB3 67 IO129RSB2 103 TMS 32 GFB2/IO160PDB3 68 IO127RSB2 104 VMV2 33 IO160NDB3 69 IO125RSB2 105 GND 34 GFC2/IO159PDB3 70 IO123RSB2 106 VPUMP 35 IO159NDB3 71 VCC 107 GNDQ 36 VCC 72 VCCIB2 108 TDO v1.3 3 - 29 Package Pin Assignments 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function 109 TRST 145 IO64PDB1 181 IO27RSB0 110 VJTAG 146 IO63NDB1 182 IO26RSB0 111 GDA0/IO88NDB1 147 IO63PDB1 183 IO25RSB0 112 GDA1/IO88PDB1 148 IO62NDB1 184 IO24RSB0 113 GDB0/IO87NDB1 149 GBC2/IO62PDB1 185 IO23RSB0 114 GDB1/IO87PDB1 150 IO61NDB1 186 VCCIB0 115 GDC0/IO86NDB1 151 GBB2/IO61PDB1 187 VCC 116 GDC1/IO86PDB1 152 IO60NDB1 188 IO20RSB0 117 IO84NDB1 153 GBA2/IO60PDB1 189 IO19RSB0 118 IO84PDB1 154 VMV1 190 IO18RSB0 119 IO82NDB1 155 GNDQ 191 IO17RSB0 120 IO82PDB1 156 GND 192 IO16RSB0 121 IO81PSB1 157 VMV0 193 IO14RSB0 122 GND 158 GBA1/IO59RSB0 194 IO12RSB0 123 VCCIB1 159 GBA0/IO58RSB0 195 GND 124 IO77NDB1 160 GBB1/IO57RSB0 196 IO10RSB0 125 IO77PDB1 161 GBB0/IO56RSB0 197 IO09RSB0 126 NC 162 GND 198 IO08RSB0 127 IO74NDB1 163 GBC1/IO55RSB0 199 IO07RSB0 128 GCC2/IO74PDB1 164 GBC0/IO54RSB0 200 VCCIB0 129 GCB2/IO73PSB1 165 IO52RSB0 201 GAC1/IO05RSB0 130 GND 166 IO50RSB0 202 GAC0/IO04RSB0 131 GCA2/IO72PSB1 167 IO48RSB0 203 GAB1/IO03RSB0 132 GCA1/IO71PDB1 168 IO46RSB0 204 GAB0/IO02RSB0 133 GCA0/IO71NDB1 169 IO44RSB0 205 GAA1/IO01RSB0 134 GCB0/IO70NDB1 170 VCCIB0 206 GAA0/IO00RSB0 135 GCB1/IO70PDB1 171 VCC 207 GNDQ 136 GCC0/IO69NDB1 172 IO36RSB0 208 VMV0 137 GCC1/IO69PDB1 173 IO35RSB0 138 IO67NDB1 174 IO34RSB0 139 IO67PDB1 175 IO33RSB0 140 VCCIB1 176 IO32RSB0 141 GND 177 IO31RSB0 142 VCC 178 GND 143 IO65PSB1 179 IO29RSB0 144 IO64NDB1 180 IO28RSB0 3 -3 0 v1.3 ProASIC3 Packaging 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function 1 GND 37 IO199PDB3 73 IO162RSB2 2 GAA2/IO225PDB3 38 IO199NDB3 74 IO160RSB2 3 IO225NDB3 39 IO197PSB3 75 IO158RSB2 4 GAB2/IO224PDB3 40 VCCIB3 76 IO156RSB2 5 IO224NDB3 41 GND 77 IO154RSB2 6 GAC2/IO223PDB3 42 IO191PDB3 78 IO152RSB2 7 IO223NDB3 43 IO191NDB3 79 IO150RSB2 8 IO222PDB3 44 GEC1/IO190PDB3 80 IO148RSB2 9 IO222NDB3 45 GEC0/IO190NDB3 81 GND 10 IO220PDB3 46 GEB1/IO189PDB3 82 IO143RSB2 11 IO220NDB3 47 GEB0/IO189NDB3 83 IO141RSB2 12 IO218PDB3 48 GEA1/IO188PDB3 84 IO139RSB2 13 IO218NDB3 49 GEA0/IO188NDB3 85 IO137RSB2 14 IO216PDB3 50 VMV3 86 IO135RSB2 15 IO216NDB3 51 GNDQ 87 IO133RSB2 16 VCC 52 GND 88 VCC 17 GND 53 VMV2 89 VCCIB2 18 VCCIB3 54 GEA2/IO187RSB2 90 IO128RSB2 19 IO212PDB3 55 GEB2/IO186RSB2 91 IO126RSB2 20 IO212NDB3 56 GEC2/IO185RSB2 92 IO124RSB2 21 GFC1/IO209PDB3 57 IO184RSB2 93 IO122RSB2 22 GFC0/IO209NDB3 58 IO183RSB2 94 IO120RSB2 23 GFB1/IO208PDB3 59 IO182RSB2 95 IO118RSB2 24 GFB0/IO208NDB3 60 IO181RSB2 96 GDC2/IO116RSB2 25 VCOMPLF 61 IO180RSB2 97 GND 26 GFA0/IO207NPB3 62 VCCIB2 98 GDB2/IO115RSB2 27 VCCPLF 63 IO178RSB2 99 GDA2/IO114RSB2 28 GFA1/IO207PPB3 64 IO176RSB2 100 GNDQ 29 GND 65 GND 101 TCK 30 GFA2/IO206PDB3 66 IO174RSB2 102 TDI 31 IO206NDB3 67 IO172RSB2 103 TMS 32 GFB2/IO205PDB3 68 IO170RSB2 104 VMV2 33 IO205NDB3 69 IO168RSB2 105 GND 34 GFC2/IO204PDB3 70 IO166RSB2 106 VPUMP 35 IO204NDB3 71 VCC 107 GNDQ 36 VCC 72 VCCIB2 108 TDO v1.3 3 - 31 Package Pin Assignments 208-Pin PQFP 208-Pin PQFP 208-Pin PQFP Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function 109 TRST 145 IO84PDB1 181 IO33RSB0 110 VJTAG 146 IO82NDB1 182 IO31RSB0 111 GDA0/IO113NDB1 147 IO82PDB1 183 IO29RSB0 112 GDA1/IO113PDB1 148 IO80NDB1 184 IO27RSB0 113 GDB0/IO112NDB1 149 GBC2/IO80PDB1 185 IO25RSB0 114 GDB1/IO112PDB1 150 IO79NDB1 186 VCCIB0 115 GDC0/IO111NDB1 151 GBB2/IO79PDB1 187 VCC 116 GDC1/IO111PDB1 152 IO78NDB1 188 IO22RSB0 117 IO109NDB1 153 GBA2/IO78PDB1 189 IO20RSB0 118 IO109PDB1 154 VMV1 190 IO18RSB0 119 IO106NDB1 155 GNDQ 191 IO16RSB0 120 IO106PDB1 156 GND 192 IO15RSB0 121 IO104PSB1 157 VMV0 193 IO14RSB0 122 GND 158 GBA1/IO77RSB0 194 IO13RSB0 123 VCCIB1 159 GBA0/IO76RSB0 195 GND 124 IO99NDB1 160 GBB1/IO75RSB0 196 IO12RSB0 125 IO99PDB1 161 GBB0/IO74RSB0 197 IO11RSB0 126 NC 162 GND 198 IO10RSB0 127 IO96NDB1 163 GBC1/IO73RSB0 199 IO09RSB0 128 GCC2/IO96PDB1 164 GBC0/IO72RSB0 200 VCCIB0 129 GCB2/IO95PSB1 165 IO70RSB0 201 GAC1/IO05RSB0 130 GND 166 IO67RSB0 202 GAC0/IO04RSB0 131 GCA2/IO94PSB1 167 IO63RSB0 203 GAB1/IO03RSB0 132 GCA1/IO93PDB1 168 IO60RSB0 204 GAB0/IO02RSB0 133 GCA0/IO93NDB1 169 IO57RSB0 205 GAA1/IO01RSB0 134 GCB0/IO92NDB1 170 VCCIB0 206 GAA0/IO00RSB0 135 GCB1/IO92PDB1 171 VCC 207 GNDQ 136 GCC0/IO91NDB1 172 IO54RSB0 208 VMV0 137 GCC1/IO91PDB1 173 IO51RSB0 138 IO88NDB1 174 IO48RSB0 139 IO88PDB1 175 IO45RSB0 140 VCCIB1 176 IO42RSB0 141 GND 177 IO40RSB0 142 VCC 178 GND 143 IO86PSB1 179 IO38RSB0 144 IO84NDB1 180 IO35RSB0 3 -3 2 v1.3 ProASIC3 Packaging 144-Pin FBGA A1 Ball Pad Corner 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v1.3 3 - 33 Package Pin Assignments 144-Pin FBGA 144-Pin FBGA 144-Pin FBGA Pin Number A3P060 Function Pin Number A3P060 Function Pin Number A3P060 Function A1 GNDQ D1 IO91RSB1 G1 GFA1/IO84RSB1 A2 VMV0 D2 IO92RSB1 G2 GND A3 GAB0/IO04RSB0 D3 IO93RSB1 G3 VCCPLF A4 GAB1/IO05RSB0 D4 GAA2/IO51RSB1 G4 GFA0/IO85RSB1 A5 IO08RSB0 D5 GAC0/IO06RSB0 G5 GND A6 GND D6 GAC1/IO07RSB0 G6 GND A7 IO11RSB0 D7 GBC0/IO19RSB0 G7 GND A8 VCC D8 GBC1/IO20RSB0 G8 GDC1/IO45RSB0 A9 IO16RSB0 D9 GBB2/IO27RSB0 G9 IO32RSB0 A10 GBA0/IO23RSB0 D10 IO18RSB0 G10 GCC2/IO43RSB0 A11 GBA1/IO24RSB0 D11 IO28RSB0 G11 IO31RSB0 A12 GNDQ D12 GCB1/IO37RSB0 G12 GCB2/IO42RSB0 B1 GAB2/IO53RSB1 E1 VCC H1 VCC B2 GND E2 GFC0/IO88RSB1 H2 GFB2/IO82RSB1 B3 GAA0/IO02RSB0 E3 GFC1/IO89RSB1 H3 GFC2/IO81RSB1 B4 GAA1/IO03RSB0 E4 VCCIB1 H4 GEC1/IO77RSB1 B5 IO00RSB0 E5 IO52RSB1 H5 VCC B6 IO10RSB0 E6 VCCIB0 H6 IO34RSB0 B7 IO12RSB0 E7 VCCIB0 H7 IO44RSB0 B8 IO14RSB0 E8 GCC1/IO35RSB0 H8 GDB2/IO55RSB1 B9 GBB0/IO21RSB0 E9 VCCIB0 H9 GDC0/IO46RSB0 B10 GBB1/IO22RSB0 E10 VCC H10 VCCIB0 B11 GND E11 GCA0/IO40RSB0 H11 IO33RSB0 B12 VMV0 E12 IO30RSB0 H12 VCC C1 IO95RSB1 F1 GFB0/IO86RSB1 J1 GEB1/IO75RSB1 C2 GFA2/IO83RSB1 F2 VCOMPLF J2 IO78RSB1 C3 GAC2/IO94RSB1 F3 GFB1/IO87RSB1 J3 VCCIB1 C4 VCC F4 IO90RSB1 J4 GEC0/IO76RSB1 C5 IO01RSB0 F5 GND J5 IO79RSB1 C6 IO09RSB0 F6 GND J6 IO80RSB1 C7 IO13RSB0 F7 GND J7 VCC C8 IO15RSB0 F8 GCC0/IO36RSB0 J8 TCK C9 IO17RSB0 F9 GCB0/IO38RSB0 J9 GDA2/IO54RSB1 C10 GBA2/IO25RSB0 F10 GND J10 TDO C11 IO26RSB0 F11 GCA1/IO39RSB0 J11 GDA1/IO49RSB0 C12 GBC2/IO29RSB0 F12 GCA2/IO41RSB0 J12 GDB1/IO47RSB0 3 -3 4 v1.3 ProASIC3 Packaging 144-Pin FBGA Pin Number A3P060 Function K1 GEB0/IO74RSB1 K2 GEA1/IO73RSB1 K3 GEA0/IO72RSB1 K4 GEA2/IO71RSB1 K5 IO65RSB1 K6 IO64RSB1 K7 GND K8 IO57RSB1 K9 GDC2/IO56RSB1 K10 GND K11 GDA0/IO50RSB0 K12 GDB0/IO48RSB0 L1 GND L2 VMV1 L3 GEB2/IO70RSB1 L4 IO67RSB1 L5 VCCIB1 L6 IO62RSB1 L7 IO59RSB1 L8 IO58RSB1 L9 TMS L10 VJTAG L11 VMV1 L12 TRST M1 GNDQ M2 GEC2/IO69RSB1 M3 IO68RSB1 M4 IO66RSB1 M5 IO63RSB1 M6 IO61RSB1 M7 IO60RSB1 M8 NC M9 TDI M10 VCCIB1 M11 VPUMP M12 GNDQ v1.3 3 - 35 Package Pin Assignments 144-Pin FBGA 144-Pin FBGA 144-Pin FBGA Pin Number A3P125 Function Pin Number A3P125 Function Pin Number A3P125 Function A1 GNDQ D1 IO128RSB1 G1 GFA1/IO121RSB1 A2 VMV0 D2 IO129RSB1 G2 GND A3 GAB0/IO02RSB0 D3 IO130RSB1 G3 VCCPLF A4 GAB1/IO03RSB0 D4 GAA2/IO67RSB1 G4 GFA0/IO122RSB1 A5 IO11RSB0 D5 GAC0/IO04RSB0 G5 GND A6 GND D6 GAC1/IO05RSB0 G6 GND A7 IO18RSB0 D7 GBC0/IO35RSB0 G7 GND A8 VCC D8 GBC1/IO36RSB0 G8 GDC1/IO61RSB0 A9 IO25RSB0 D9 GBB2/IO43RSB0 G9 IO48RSB0 A10 GBA0/IO39RSB0 D10 IO28RSB0 G10 GCC2/IO59RSB0 A11 GBA1/IO40RSB0 D11 IO44RSB0 G11 IO47RSB0 A12 GNDQ D12 GCB1/IO53RSB0 G12 GCB2/IO58RSB0 B1 GAB2/IO69RSB1 E1 VCC H1 VCC B2 GND E2 GFC0/IO125RSB1 H2 GFB2/IO119RSB1 B3 GAA0/IO00RSB0 E3 GFC1/IO126RSB1 H3 GFC2/IO118RSB1 B4 GAA1/IO01RSB0 E4 VCCIB1 H4 GEC1/IO112RSB1 B5 IO08RSB0 E5 IO68RSB1 H5 VCC B6 IO14RSB0 E6 VCCIB0 H6 IO50RSB0 B7 IO19RSB0 E7 VCCIB0 H7 IO60RSB0 B8 IO22RSB0 E8 GCC1/IO51RSB0 H8 GDB2/IO71RSB1 B9 GBB0/IO37RSB0 E9 VCCIB0 H9 GDC0/IO62RSB0 B10 GBB1/IO38RSB0 E10 VCC H10 VCCIB0 B11 GND E11 GCA0/IO56RSB0 H11 IO49RSB0 B12 VMV0 E12 IO46RSB0 H12 VCC C1 IO132RSB1 F1 GFB0/IO123RSB1 J1 GEB1/IO110RSB1 C2 GFA2/IO120RSB1 F2 VCOMPLF J2 IO115RSB1 C3 GAC2/IO131RSB1 F3 GFB1/IO124RSB1 J3 VCCIB1 C4 VCC F4 IO127RSB1 J4 GEC0/IO111RSB1 C5 IO10RSB0 F5 GND J5 IO116RSB1 C6 IO12RSB0 F6 GND J6 IO117RSB1 C7 IO21RSB0 F7 GND J7 VCC C8 IO24RSB0 F8 GCC0/IO52RSB0 J8 TCK C9 IO27RSB0 F9 GCB0/IO54RSB0 J9 GDA2/IO70RSB1 C10 GBA2/IO41RSB0 F10 GND J10 TDO C11 IO42RSB0 F11 GCA1/IO55RSB0 J11 GDA1/IO65RSB0 C12 GBC2/IO45RSB0 F12 GCA2/IO57RSB0 J12 GDB1/IO63RSB0 3 -3 6 v1.3 ProASIC3 Packaging 144-Pin FBGA Pin Number A3P125 Function K1 GEB0/IO109RSB1 K2 GEA1/IO108RSB1 K3 GEA0/IO107RSB1 K4 GEA2/IO106RSB1 K5 IO100RSB1 K6 IO98RSB1 K7 GND K8 IO73RSB1 K9 GDC2/IO72RSB1 K10 GND K11 GDA0/IO66RSB0 K12 GDB0/IO64RSB0 L1 GND L2 VMV1 L3 GEB2/IO105RSB1 L4 IO102RSB1 L5 VCCIB1 L6 IO95RSB1 L7 IO85RSB1 L8 IO74RSB1 L9 TMS L10 VJTAG L11 VMV1 L12 TRST M1 GNDQ M2 GEC2/IO104RSB1 M3 IO103RSB1 M4 IO101RSB1 M5 IO97RSB1 M6 IO94RSB1 M7 IO86RSB1 M8 IO75RSB1 M9 TDI M10 VCCIB1 M11 VPUMP M12 GNDQ v1.3 3 - 37 Package Pin Assignments 144-Pin FBGA 144-Pin FBGA 144-Pin FBGA Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function A1 GNDQ D1 IO112NDB3 G1 GFA1/IO108PPB3 A2 VMV0 D2 IO112PDB3 G2 GND A3 GAB0/IO02RSB0 D3 IO116VDB3 G3 VCCPLF A4 GAB1/IO03RSB0 D4 GAA2/IO118UPB3 G4 GFA0/IO108NPB3 A5 IO16RSB0 D5 GAC0/IO04RSB0 G5 GND A6 GND D6 GAC1/IO05RSB0 G6 GND A7 IO29RSB0 D7 GBC0/IO35RSB0 G7 GND A8 VCC D8 GBC1/IO36RSB0 G8 GDC1/IO58UPB1 A9 IO33RSB0 D9 GBB2/IO42PDB1 G9 IO53NDB1 A10 GBA0/IO39RSB0 D10 IO42NDB1 G10 GCC2/IO53PDB1 A11 GBA1/IO40RSB0 D11 IO43NPB1 G11 IO52NDB1 A12 GNDQ D12 GCB1/IO49PPB1 G12 GCB2/IO52PDB1 B1 GAB2/IO117UDB3 E1 VCC H1 VCC B2 GND E2 GFC0/IO110NDB3 H2 GFB2/IO106PDB3 B3 GAA0/IO00RSB0 E3 GFC1/IO110PDB3 H3 GFC2/IO105PSB3 B4 GAA1/IO01RSB0 E4 VCCIB3 H4 GEC1/IO100PDB3 B5 IO14RSB0 E5 IO118VPB3 H5 VCC B6 IO19RSB0 E6 VCCIB0 H6 IO79RSB2 B7 IO22RSB0 E7 VCCIB0 H7 IO65RSB2 B8 IO30RSB0 E8 GCC1/IO48PDB1 H8 GDB2/IO62RSB2 B9 GBB0/IO37RSB0 E9 VCCIB1 H9 GDC0/IO58VPB1 B10 GBB1/IO38RSB0 E10 VCC H10 VCCIB1 B11 GND E11 GCA0/IO50NDB1 H11 IO54PSB1 B12 VMV1 E12 IO51NDB1 H12 VCC C1 IO117VDB3 F1 GFB0/IO109NPB3 J1 GEB1/IO99PDB3 C2 GFA2/IO107PPB3 F2 VCOMPLF J2 IO106NDB3 C3 GAC2/IO116UDB3 F3 GFB1/IO109PPB3 J3 VCCIB3 C4 VCC F4 IO107NPB3 J4 GEC0/IO100NDB3 C5 IO12RSB0 F5 GND J5 IO88RSB2 C6 IO17RSB0 F6 GND J6 IO81RSB2 C7 IO24RSB0 F7 GND J7 VCC C8 IO31RSB0 F8 GCC0/IO48NDB1 J8 TCK C9 IO34RSB0 F9 GCB0/IO49NPB1 J9 GDA2/IO61RSB2 C10 GBA2/IO41PDB1 F10 GND J10 TDO C11 IO41NDB1 F11 GCA1/IO50PDB1 J11 GDA1/IO60UDB1 C12 GBC2/IO43PPB1 F12 GCA2/IO51PDB1 J12 GDB1/IO59UDB1 3 -3 8 v1.3 ProASIC3 Packaging 144-Pin FBGA Pin Number A3P250 Function K1 GEB0/IO99NDB3 K2 GEA1/IO98PDB3 K3 GEA0/IO98NDB3 K4 GEA2/IO97RSB2 K5 IO90RSB2 K6 IO84RSB2 K7 GND K8 IO66RSB2 K9 GDC2/IO63RSB2 K10 GND K11 GDA0/IO60VDB1 K12 GDB0/IO59VDB1 L1 GND L2 VMV3 L3 GEB2/IO96RSB2 L4 IO91RSB2 L5 VCCIB2 L6 IO82RSB2 L7 IO80RSB2 L8 IO72RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO95RSB2 M3 IO92RSB2 M4 IO89RSB2 M5 IO87RSB2 M6 IO85RSB2 M7 IO78RSB2 M8 IO76RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ v1.3 3 - 39 Package Pin Assignments 144-Pin FBGA 144-Pin FBGA 144-Pin FBGA Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function A1 GNDQ D1 IO149NDB3 G1 GFA1/IO145PPB3 A2 VMV0 D2 IO149PDB3 G2 GND A3 GAB0/IO02RSB0 D3 IO153VDB3 G3 VCCPLF A4 GAB1/IO03RSB0 D4 GAA2/IO155UPB3 G4 GFA0/IO145NPB3 A5 IO16RSB0 D5 GAC0/IO04RSB0 G5 GND A6 GND D6 GAC1/IO05RSB0 G6 GND A7 IO30RSB0 D7 GBC0/IO54RSB0 G7 GND A8 VCC D8 GBC1/IO55RSB0 G8 GDC1/IO77UPB1 A9 IO34RSB0 D9 GBB2/IO61PDB1 G9 IO72NDB1 A10 GBA0/IO58RSB0 D10 IO61NDB1 G10 GCC2/IO72PDB1 A11 GBA1/IO59RSB0 D11 IO62NPB1 G11 IO71NDB1 A12 GNDQ D12 GCB1/IO68PPB1 G12 GCB2/IO71PDB1 B1 GAB2/IO154UDB3 E1 VCC H1 VCC B2 GND E2 GFC0/IO147NDB3 H2 GFB2/IO143PDB3 B3 GAA0/IO00RSB0 E3 GFC1/IO147PDB3 H3 GFC2/IO142PSB3 B4 GAA1/IO01RSB0 E4 VCCIB3 H4 GEC1/IO137PDB3 B5 IO14RSB0 E5 IO155VPB3 H5 VCC B6 IO19RSB0 E6 VCCIB0 H6 IO75PDB1 B7 IO23RSB0 E7 VCCIB0 H7 IO75NDB1 B8 IO31RSB0 E8 GCC1/IO67PDB1 H8 GDB2/IO81RSB2 B9 GBB0/IO56RSB0 E9 VCCIB1 H9 GDC0/IO77VPB1 B10 GBB1/IO57RSB0 E10 VCC H10 VCCIB1 B11 GND E11 GCA0/IO69NDB1 H11 IO73PSB1 B12 VMV1 E12 IO70NDB1 H12 VCC C1 IO154VDB3 F1 GFB0/IO146NPB3 J1 GEB1/IO136PDB3 C2 GFA2/IO144PPB3 F2 VCOMPLF J2 IO143NDB3 C3 GAC2/IO153UDB3 F3 GFB1/IO146PPB3 J3 VCCIB3 C4 VCC F4 IO144NPB3 J4 GEC0/IO137NDB3 C5 IO12RSB0 F5 GND J5 IO125RSB2 C6 IO17RSB0 F6 GND J6 IO116RSB2 C7 IO25RSB0 F7 GND J7 VCC C8 IO32RSB0 F8 GCC0/IO67NDB1 J8 TCK C9 IO53RSB0 F9 GCB0/IO68NPB1 J9 GDA2/IO80RSB2 C10 GBA2/IO60PDB1 F10 GND J10 TDO C11 IO60NDB1 F11 GCA1/IO69PDB1 J11 GDA1/IO79UDB1 C12 GBC2/IO62PPB1 F12 GCA2/IO70PDB1 J12 GDB1/IO78UDB1 3 -4 0 v1.3 ProASIC3 Packaging 144-Pin FBGA Pin Number A3P400 Function K1 GEB0/IO136NDB3 K2 GEA1/IO135PDB3 K3 GEA0/IO135NDB3 K4 GEA2/IO134RSB2 K5 IO127RSB2 K6 IO121RSB2 K7 GND K8 IO104RSB2 K9 GDC2/IO82RSB2 K10 GND K11 GDA0/IO79VDB1 K12 GDB0/IO78VDB1 L1 GND L2 VMV3 L3 GEB2/IO133RSB2 L4 IO128RSB2 L5 VCCIB2 L6 IO119RSB2 L7 IO114RSB2 L8 IO110RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO132RSB2 M3 IO129RSB2 M4 IO126RSB2 M5 IO124RSB2 M6 IO122RSB2 M7 IO117RSB2 M8 IO115RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ v1.3 3 - 41 Package Pin Assignments 144-Pin FBGA 144-Pin FBGA 144-Pin FBGA Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function A1 GNDQ D1 IO169PDB3 G1 GFA1/IO162PPB3 A2 VMV0 D2 IO169NDB3 G2 GND A3 GAB0/IO02RSB0 D3 IO172NDB3 G3 VCCPLF A4 GAB1/IO03RSB0 D4 GAA2/IO174PPB3 G4 GFA0/IO162NPB3 A5 IO10RSB0 D5 GAC0/IO04RSB0 G5 GND A6 GND D6 GAC1/IO05RSB0 G6 GND A7 IO34RSB0 D7 GBC0/IO54RSB0 G7 GND A8 VCC D8 GBC1/IO55RSB0 G8 GDC1/IO86PPB1 A9 IO50RSB0 D9 GBB2/IO61PDB1 G9 IO74NDB1 A10 GBA0/IO58RSB0 D10 IO61NDB1 G10 GCC2/IO74PDB1 A11 GBA1/IO59RSB0 D11 IO62NPB1 G11 IO73NDB1 A12 GNDQ D12 GCB1/IO70PPB1 G12 GCB2/IO73PDB1 B1 GAB2/IO173PDB3 E1 VCC H1 VCC B2 GND E2 GFC0/IO164NDB3 H2 GFB2/IO160PDB3 B3 GAA0/IO00RSB0 E3 GFC1/IO164PDB3 H3 GFC2/IO159PSB3 B4 GAA1/IO01RSB0 E4 VCCIB3 H4 GEC1/IO146PDB3 B5 IO13RSB0 E5 IO174NPB3 H5 VCC B6 IO19RSB0 E6 VCCIB0 H6 IO80PDB1 B7 IO31RSB0 E7 VCCIB0 H7 IO80NDB1 B8 IO39RSB0 E8 GCC1/IO69PDB1 H8 GDB2/IO90RSB2 B9 GBB0/IO56RSB0 E9 VCCIB1 H9 GDC0/IO86NPB1 B10 GBB1/IO57RSB0 E10 VCC H10 VCCIB1 B11 GND E11 GCA0/IO71NDB1 H11 IO84PSB1 B12 VMV1 E12 IO72NDB1 H12 VCC C1 IO173NDB3 F1 GFB0/IO163NPB3 J1 GEB1/IO145PDB3 C2 GFA2/IO161PPB3 F2 VCOMPLF J2 IO160NDB3 C3 GAC2/IO172PDB3 F3 GFB1/IO163PPB3 J3 VCCIB3 C4 VCC F4 IO161NPB3 J4 GEC0/IO146NDB3 C5 IO16RSB0 F5 GND J5 IO129RSB2 C6 IO25RSB0 F6 GND J6 IO131RSB2 C7 IO28RSB0 F7 GND J7 VCC C8 IO42RSB0 F8 GCC0/IO69NDB1 J8 TCK C9 IO45RSB0 F9 GCB0/IO70NPB1 J9 GDA2/IO89RSB2 C10 GBA2/IO60PDB1 F10 GND J10 TDO C11 IO60NDB1 F11 GCA1/IO71PDB1 J11 GDA1/IO88PDB1 C12 GBC2/IO62PPB1 F12 GCA2/IO72PDB1 J12 GDB1/IO87PDB1 3 -4 2 v1.3 ProASIC3 Packaging 144-Pin FBGA Pin Number A3P600 Function K1 GEB0/IO145NDB3 K2 GEA1/IO144PDB3 K3 GEA0/IO144NDB3 K4 GEA2/IO143RSB2 K5 IO119RSB2 K6 IO111RSB2 K7 GND K8 IO94RSB2 K9 GDC2/IO91RSB2 K10 GND K11 GDA0/IO88NDB1 K12 GDB0/IO87NDB1 L1 GND L2 VMV3 L3 GEB2/IO142RSB2 L4 IO136RSB2 L5 VCCIB2 L6 IO115RSB2 L7 IO103RSB2 L8 IO97RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO141RSB2 M3 IO138RSB2 M4 IO123RSB2 M5 IO126RSB2 M6 IO134RSB2 M7 IO108RSB2 M8 IO99RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ v1.3 3 - 43 Package Pin Assignments 144-Pin FBGA 144-Pin FBGA 144-Pin FBGA Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function A1 GNDQ D1 IO213PDB3 G1 GFA1/IO207PPB3 A2 VMV0 D2 IO213NDB3 G2 GND A3 GAB0/IO02RSB0 D3 IO223NDB3 G3 VCCPLF A4 GAB1/IO03RSB0 D4 GAA2/IO225PPB3 G4 GFA0/IO207NPB3 A5 IO10RSB0 D5 GAC0/IO04RSB0 G5 GND A6 GND D6 GAC1/IO05RSB0 G6 GND A7 IO44RSB0 D7 GBC0/IO72RSB0 G7 GND A8 VCC D8 GBC1/IO73RSB0 G8 GDC1/IO111PPB1 A9 IO69RSB0 D9 GBB2/IO79PDB1 G9 IO96NDB1 A10 GBA0/IO76RSB0 D10 IO79NDB1 G10 GCC2/IO96PDB1 A11 GBA1/IO77RSB0 D11 IO80NPB1 G11 IO95NDB1 A12 GNDQ D12 GCB1/IO92PPB1 G12 GCB2/IO95PDB1 B1 GAB2/IO224PDB3 E1 VCC H1 VCC B2 GND E2 GFC0/IO209NDB3 H2 GFB2/IO205PDB3 B3 GAA0/IO00RSB0 E3 GFC1/IO209PDB3 H3 GFC2/IO204PSB3 B4 GAA1/IO01RSB0 E4 VCCIB3 H4 GEC1/IO190PDB3 B5 IO13RSB0 E5 IO225NPB3 H5 VCC B6 IO26RSB0 E6 VCCIB0 H6 IO105PDB1 B7 IO35RSB0 E7 VCCIB0 H7 IO105NDB1 B8 IO60RSB0 E8 GCC1/IO91PDB1 H8 GDB2/IO115RSB2 B9 GBB0/IO74RSB0 E9 VCCIB1 H9 GDC0/IO111NPB1 B10 GBB1/IO75RSB0 E10 VCC H10 VCCIB1 B11 GND E11 GCA0/IO93NDB1 H11 IO101PSB1 B12 VMV1 E12 IO94NDB1 H12 VCC C1 IO224NDB3 F1 GFB0/IO208NPB3 J1 GEB1/IO189PDB3 C2 GFA2/IO206PPB3 F2 VCOMPLF J2 IO205NDB3 C3 GAC2/IO223PDB3 F3 GFB1/IO208PPB3 J3 VCCIB3 C4 VCC F4 IO206NPB3 J4 GEC0/IO190NDB3 C5 IO16RSB0 F5 GND J5 IO160RSB2 C6 IO29RSB0 F6 GND J6 IO157RSB2 C7 IO32RSB0 F7 GND J7 VCC C8 IO63RSB0 F8 GCC0/IO91NDB1 J8 TCK C9 IO66RSB0 F9 GCB0/IO92NPB1 J9 GDA2/IO114RSB2 C10 GBA2/IO78PDB1 F10 GND J10 TDO C11 IO78NDB1 F11 GCA1/IO93PDB1 J11 GDA1/IO113PDB1 C12 GBC2/IO80PPB1 F12 GCA2/IO94PDB1 J12 GDB1/IO112PDB1 3 -4 4 v1.3 ProASIC3 Packaging 144-Pin FBGA Pin Number A3P1000 Function K1 GEB0/IO189NDB3 K2 GEA1/IO188PDB3 K3 GEA0/IO188NDB3 K4 GEA2/IO187RSB2 K5 IO169RSB2 K6 IO152RSB2 K7 GND K8 IO117RSB2 K9 GDC2/IO116RSB2 K10 GND K11 GDA0/IO113NDB1 K12 GDB0/IO112NDB1 L1 GND L2 VMV3 L3 GEB2/IO186RSB2 L4 IO172RSB2 L5 VCCIB2 L6 IO153RSB2 L7 IO144RSB2 L8 IO140RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO185RSB2 M3 IO173RSB2 M4 IO168RSB2 M5 IO161RSB2 M6 IO156RSB2 M7 IO145RSB2 M8 IO141RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ v1.3 3 - 45 Package Pin Assignments 256-Pin FBGA A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -4 6 v1.3 ProASIC3 Packaging 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function A1 GND C5 GAC0/IO04RSB0 E9 IO24RSB0 A2 GAA0/IO00RSB0 C6 GAC1/IO05RSB0 E10 VCCIB0 A3 GAA1/IO01RSB0 C7 IO13RSB0 E11 VCCIB0 A4 GAB0/IO02RSB0 C8 IO17RSB0 E12 VMV1 A5 IO07RSB0 C9 IO22RSB0 E13 GBC2/IO43PDB1 A6 IO10RSB0 C10 IO27RSB0 E14 IO46RSB1 A7 IO11RSB0 C11 IO31RSB0 E15 NC A8 IO15RSB0 C12 GBC0/IO35RSB0 E16 IO45PDB1 A9 IO20RSB0 C13 IO34RSB0 F1 IO113NDB3 A10 IO25RSB0 C14 NC F2 IO112PPB3 A11 IO29RSB0 C15 IO42NPB1 F3 NC A12 IO33RSB0 C16 IO44PDB1 F4 IO115VDB3 A13 GBB1/IO38RSB0 D1 IO114VDB3 F5 VCCIB3 A14 GBA0/IO39RSB0 D2 IO114UDB3 F6 GND A15 GBA1/IO40RSB0 D3 GAC2/IO116UDB3 F7 VCC A16 GND D4 NC F8 VCC B1 GAB2/IO117UDB3 D5 GNDQ F9 VCC B2 GAA2/IO118UDB3 D6 IO08RSB0 F10 VCC B3 NC D7 IO14RSB0 F11 GND B4 GAB1/IO03RSB0 D8 IO18RSB0 F12 VCCIB1 B5 IO06RSB0 D9 IO23RSB0 F13 IO43NDB1 B6 IO09RSB0 D10 IO28RSB0 F14 NC B7 IO12RSB0 D11 IO32RSB0 F15 IO47PPB1 B8 IO16RSB0 D12 GNDQ F16 IO45NDB1 B9 IO21RSB0 D13 NC G1 IO111NDB3 B10 IO26RSB0 D14 GBB2/IO42PPB1 G2 IO111PDB3 B11 IO30RSB0 D15 NC G3 IO112NPB3 B12 GBC1/IO36RSB0 D16 IO44NDB1 G4 GFC1/IO110PPB3 B13 GBB0/IO37RSB0 E1 IO113PDB3 G5 VCCIB3 B14 NC E2 NC G6 VCC B15 GBA2/IO41PDB1 E3 IO116VDB3 G7 GND B16 IO41NDB1 E4 IO115UDB3 G8 GND C1 IO117VDB3 E5 VMV0 G9 GND C2 IO118VDB3 E6 VCCIB0 G10 GND C3 NC E7 VCCIB0 G11 VCC C4 NC E8 IO19RSB0 G12 VCCIB1 v1.3 3 - 47 Package Pin Assignments 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA Pin Number A3P250 Function Pin Number A3P250 Function Pin Number A3P250 Function G13 GCC1/IO48PPB1 K1 GFC2/IO105PDB3 M5 VMV3 G14 IO47NPB1 K2 IO107NPB3 M6 VCCIB2 G15 IO54PDB1 K3 IO104PPB3 M7 VCCIB2 G16 IO54NDB1 K4 NC M8 NC H1 GFB0/IO109NPB3 K5 VCCIB3 M9 IO74RSB2 H2 GFA0/IO108NDB3 K6 VCC M10 VCCIB2 H3 GFB1/IO109PPB3 K7 GND M11 VCCIB2 H4 VCOMPLF K8 GND M12 VMV2 H5 GFC0/IO110NPB3 K9 GND M13 NC H6 VCC K10 GND M14 GDB1/IO59UPB1 H7 GND K11 VCC M15 GDC1/IO58UDB1 H8 GND K12 VCCIB1 M16 IO56NDB1 H9 GND K13 IO52NPB1 N1 IO103NDB3 H10 GND K14 IO55RSB1 N2 IO101PPB3 H11 VCC K15 IO53NPB1 N3 GEC1/IO100PPB3 H12 GCC0/IO48NPB1 K16 IO51NDB1 N4 NC H13 GCB1/IO49PPB1 L1 IO105NDB3 N5 GNDQ H14 GCA0/IO50NPB1 L2 IO104NPB3 N6 GEA2/IO97RSB2 H15 NC L3 NC N7 IO86RSB2 H16 GCB0/IO49NPB1 L4 IO102RSB3 N8 IO82RSB2 J1 GFA2/IO107PPB3 L5 VCCIB3 N9 IO75RSB2 J2 GFA1/IO108PDB3 L6 GND N10 IO69RSB2 J3 VCCPLF L7 VCC N11 IO64RSB2 J4 IO106NDB3 L8 VCC N12 GNDQ J5 GFB2/IO106PDB3 L9 VCC N13 NC J6 VCC L10 VCC N14 VJTAG J7 GND L11 GND N15 GDC0/IO58VDB1 J8 GND L12 VCCIB1 N16 GDA1/IO60UDB1 J9 GND L13 GDB0/IO59VPB1 P1 GEB1/IO99PDB3 J10 GND L14 IO57VDB1 P2 GEB0/IO99NDB3 J11 VCC L15 IO57UDB1 P3 NC J12 GCB2/IO52PPB1 L16 IO56PDB1 P4 NC J13 GCA1/IO50PPB1 M1 IO103PDB3 P5 IO92RSB2 J14 GCC2/IO53PPB1 M2 NC P6 IO89RSB2 J15 NC M3 IO101NPB3 P7 IO85RSB2 J16 GCA2/IO51PDB1 M4 GEC0/IO100NPB3 P8 IO81RSB2 3 -4 8 v1.3 ProASIC3 Packaging 256-Pin FBGA 256-Pin FBGA Pin Number A3P250 Function Pin Number A3P250 Function P9 IO76RSB2 T13 IO67RSB2 P10 IO71RSB2 T14 GDA2/IO61RSB2 P11 IO66RSB2 T15 TMS P12 NC T16 GND P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO60VDB1 R1 GEA1/IO98PDB3 R2 GEA0/IO98NDB3 R3 NC R4 GEC2/IO95RSB2 R5 IO91RSB2 R6 IO88RSB2 R7 IO84RSB2 R8 IO80RSB2 R9 IO77RSB2 R10 IO72RSB2 R11 IO68RSB2 R12 IO65RSB2 R13 GDB2/IO62RSB2 R14 TDI R15 NC R16 TDO T1 GND T2 IO94RSB2 T3 GEB2/IO96RSB2 T4 IO93RSB2 T5 IO90RSB2 T6 IO87RSB2 T7 IO83RSB2 T8 IO79RSB2 T9 IO78RSB2 T10 IO73RSB2 T11 IO70RSB2 T12 GDC2/IO63RSB2 v1.3 3 - 49 Package Pin Assignments 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function A1 GND C5 GAC0/IO04RSB0 E9 IO31RSB0 A2 GAA0/IO00RSB0 C6 GAC1/IO05RSB0 E10 VCCIB0 A3 GAA1/IO01RSB0 C7 IO20RSB0 E11 VCCIB0 A4 GAB0/IO02RSB0 C8 IO24RSB0 E12 VMV1 A5 IO16RSB0 C9 IO33RSB0 E13 GBC2/IO62PDB1 A6 IO17RSB0 C10 IO39RSB0 E14 IO65RSB1 A7 IO22RSB0 C11 IO45RSB0 E15 IO52RSB0 A8 IO28RSB0 C12 GBC0/IO54RSB0 E16 IO66PDB1 A9 IO34RSB0 C13 IO48RSB0 F1 IO150NDB3 A10 IO37RSB0 C14 VMV0 F2 IO149NPB3 A11 IO41RSB0 C15 IO61NPB1 F3 IO09RSB0 A12 IO43RSB0 C16 IO63PDB1 F4 IO152UDB3 A13 GBB1/IO57RSB0 D1 IO151VDB3 F5 VCCIB3 A14 GBA0/IO58RSB0 D2 IO151UDB3 F6 GND A15 GBA1/IO59RSB0 D3 GAC2/IO153UDB3 F7 VCC A16 GND D4 IO06RSB0 F8 VCC B1 GAB2/IO154UDB3 D5 GNDQ F9 VCC B2 GAA2/IO155UDB3 D6 IO10RSB0 F10 VCC B3 IO12RSB0 D7 IO19RSB0 F11 GND B4 GAB1/IO03RSB0 D8 IO26RSB0 F12 VCCIB1 B5 IO13RSB0 D9 IO30RSB0 F13 IO62NDB1 B6 IO14RSB0 D10 IO40RSB0 F14 IO49RSB0 B7 IO21RSB0 D11 IO46RSB0 F15 IO64PPB1 B8 IO27RSB0 D12 GNDQ F16 IO66NDB1 B9 IO32RSB0 D13 IO47RSB0 G1 IO148NDB3 B10 IO38RSB0 D14 GBB2/IO61PPB1 G2 IO148PDB3 B11 IO42RSB0 D15 IO53RSB0 G3 IO149PPB3 B12 GBC1/IO55RSB0 D16 IO63NDB1 G4 GFC1/IO147PPB3 B13 GBB0/IO56RSB0 E1 IO150PDB3 G5 VCCIB3 B14 IO44RSB0 E2 IO08RSB0 G6 VCC B15 GBA2/IO60PDB1 E3 IO153VDB3 G7 GND B16 IO60NDB1 E4 IO152VDB3 G8 GND C1 IO154VDB3 E5 VMV0 G9 GND C2 IO155VDB3 E6 VCCIB0 G10 GND C3 IO11RSB0 E7 VCCIB0 G11 VCC C4 IO07RSB0 E8 IO25RSB0 G12 VCCIB1 3 -5 0 v1.3 ProASIC3 Packaging 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function G13 GCC1/IO67PPB1 K1 GFC2/IO142PDB3 M5 VMV3 G14 IO64NPB1 K2 IO144NPB3 M6 VCCIB2 G15 IO73PDB1 K3 IO141PPB3 M7 VCCIB2 G16 IO73NDB1 K4 IO120RSB2 M8 IO108RSB2 H1 GFB0/IO146NPB3 K5 VCCIB3 M9 IO101RSB2 H2 GFA0/IO145NDB3 K6 VCC M10 VCCIB2 H3 GFB1/IO146PPB3 K7 GND M11 VCCIB2 H4 VCOMPLF K8 GND M12 VMV2 H5 GFC0/IO147NPB3 K9 GND M13 IO83RSB2 H6 VCC K10 GND M14 GDB1/IO78UPB1 H7 GND K11 VCC M15 GDC1/IO77UDB1 H8 GND K12 VCCIB1 M16 IO75NDB1 H9 GND K13 IO71NPB1 N1 IO140NDB3 H10 GND K14 IO74RSB1 N2 IO138PPB3 H11 VCC K15 IO72NPB1 N3 GEC1/IO137PPB3 H12 GCC0/IO67NPB1 K16 IO70NDB1 N4 IO131RSB2 H13 GCB1/IO68PPB1 L1 IO142NDB3 N5 GNDQ H14 GCA0/IO69NPB1 L2 IO141NPB3 N6 GEA2/IO134RSB2 H15 NC L3 IO125RSB2 N7 IO117RSB2 H16 GCB0/IO68NPB1 L4 IO139RSB3 N8 IO111RSB2 J1 GFA2/IO144PPB3 L5 VCCIB3 N9 IO99RSB2 J2 GFA1/IO145PDB3 L6 GND N10 IO94RSB2 J3 VCCPLF L7 VCC N11 IO87RSB2 J4 IO143NDB3 L8 VCC N12 GNDQ J5 GFB2/IO143PDB3 L9 VCC N13 IO93RSB2 J6 VCC L10 VCC N14 VJTAG J7 GND L11 GND N15 GDC0/IO77VDB1 J8 GND L12 VCCIB1 N16 GDA1/IO79UDB1 J9 GND L13 GDB0/IO78VPB1 P1 GEB1/IO136PDB3 J10 GND L14 IO76VDB1 P2 GEB0/IO136NDB3 J11 VCC L15 IO76UDB1 P3 VMV2 J12 GCB2/IO71PPB1 L16 IO75PDB1 P4 IO129RSB2 J13 GCA1/IO69PPB1 M1 IO140PDB3 P5 IO128RSB2 J14 GCC2/IO72PPB1 M2 IO130RSB2 P6 IO122RSB2 J15 NC M3 IO138NPB3 P7 IO115RSB2 J16 GCA2/IO70PDB1 M4 GEC0/IO137NPB3 P8 IO110RSB2 v1.3 3 - 51 Package Pin Assignments 256-Pin FBGA 256-Pin FBGA Pin Number A3P400 Function Pin Number A3P400 Function P9 IO98RSB2 T13 IO86RSB2 P10 IO95RSB2 T14 GDA2/IO80RSB2 P11 IO88RSB2 T15 TMS P12 IO84RSB2 T16 GND P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO79VDB1 R1 GEA1/IO135PDB3 R2 GEA0/IO135NDB3 R3 IO127RSB2 R4 GEC2/IO132RSB2 R5 IO123RSB2 R6 IO118RSB2 R7 IO112RSB2 R8 IO106RSB2 R9 IO100RSB2 R10 IO96RSB2 R11 IO89RSB2 R12 IO85RSB2 R13 GDB2/IO81RSB2 R14 TDI R15 NC R16 TDO T1 GND T2 IO126RSB2 T3 GEB2/IO133RSB2 T4 IO124RSB2 T5 IO116RSB2 T6 IO113RSB2 T7 IO107RSB2 T8 IO105RSB2 T9 IO102RSB2 T10 IO97RSB2 T11 IO92RSB2 T12 GDC2/IO82RSB2 3 -5 2 v1.3 ProASIC3 Packaging 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function A1 GND C5 GAC0/IO04RSB0 E9 IO31RSB0 A2 GAA0/IO00RSB0 C6 GAC1/IO05RSB0 E10 VCCIB0 A3 GAA1/IO01RSB0 C7 IO20RSB0 E11 VCCIB0 A4 GAB0/IO02RSB0 C8 IO24RSB0 E12 VMV1 A5 IO11RSB0 C9 IO33RSB0 E13 GBC2/IO62PDB1 A6 IO16RSB0 C10 IO39RSB0 E14 IO67PPB1 A7 IO18RSB0 C11 IO44RSB0 E15 IO64PPB1 A8 IO28RSB0 C12 GBC0/IO54RSB0 E16 IO66PDB1 A9 IO34RSB0 C13 IO51RSB0 F1 IO166NDB3 A10 IO37RSB0 C14 VMV0 F2 IO168NPB3 A11 IO41RSB0 C15 IO61NPB1 F3 IO167PPB3 A12 IO43RSB0 C16 IO63PDB1 F4 IO169PDB3 A13 GBB1/IO57RSB0 D1 IO171NDB3 F5 VCCIB3 A14 GBA0/IO58RSB0 D2 IO171PDB3 F6 GND A15 GBA1/IO59RSB0 D3 GAC2/IO172PDB3 F7 VCC A16 GND D4 IO06RSB0 F8 VCC B1 GAB2/IO173PDB3 D5 GNDQ F9 VCC B2 GAA2/IO174PDB3 D6 IO10RSB0 F10 VCC B3 GNDQ D7 IO19RSB0 F11 GND B4 GAB1/IO03RSB0 D8 IO26RSB0 F12 VCCIB1 B5 IO13RSB0 D9 IO30RSB0 F13 IO62NDB1 B6 IO14RSB0 D10 IO40RSB0 F14 IO64NPB1 B7 IO21RSB0 D11 IO45RSB0 F15 IO65PPB1 B8 IO27RSB0 D12 GNDQ F16 IO66NDB1 B9 IO32RSB0 D13 IO50RSB0 G1 IO165NDB3 B10 IO38RSB0 D14 GBB2/IO61PPB1 G2 IO165PDB3 B11 IO42RSB0 D15 IO53RSB0 G3 IO168PPB3 B12 GBC1/IO55RSB0 D16 IO63NDB1 G4 GFC1/IO164PPB3 B13 GBB0/IO56RSB0 E1 IO166PDB3 G5 VCCIB3 B14 IO52RSB0 E2 IO167NPB3 G6 VCC B15 GBA2/IO60PDB1 E3 IO172NDB3 G7 GND B16 IO60NDB1 E4 IO169NDB3 G8 GND C1 IO173NDB3 E5 VMV0 G9 GND C2 IO174NDB3 E6 VCCIB0 G10 GND C3 VMV3 E7 VCCIB0 G11 VCC C4 IO07RSB0 E8 IO25RSB0 G12 VCCIB1 v1.3 3 - 53 Package Pin Assignments 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function G13 GCC1/IO69PPB1 K1 GFC2/IO159PDB3 M5 VMV3 G14 IO65NPB1 K2 IO161NPB3 M6 VCCIB2 G15 IO75PDB1 K3 IO156PPB3 M7 VCCIB2 G16 IO75NDB1 K4 IO129RSB2 M8 IO117RSB2 H1 GFB0/IO163NPB3 K5 VCCIB3 M9 IO110RSB2 H2 GFA0/IO162NDB3 K6 VCC M10 VCCIB2 H3 GFB1/IO163PPB3 K7 GND M11 VCCIB2 H4 VCOMPLF K8 GND M12 VMV2 H5 GFC0/IO164NPB3 K9 GND M13 IO94RSB2 H6 VCC K10 GND M14 GDB1/IO87PPB1 H7 GND K11 VCC M15 GDC1/IO86PDB1 H8 GND K12 VCCIB1 M16 IO84NDB1 H9 GND K13 IO73NPB1 N1 IO150NDB3 H10 GND K14 IO80NPB1 N2 IO147PPB3 H11 VCC K15 IO74NPB1 N3 GEC1/IO146PPB3 H12 GCC0/IO69NPB1 K16 IO72NDB1 N4 IO140RSB2 H13 GCB1/IO70PPB1 L1 IO159NDB3 N5 GNDQ H14 GCA0/IO71NPB1 L2 IO156NPB3 N6 GEA2/IO143RSB2 H15 IO67NPB1 L3 IO151PPB3 N7 IO126RSB2 H16 GCB0/IO70NPB1 L4 IO158PSB3 N8 IO120RSB2 J1 GFA2/IO161PPB3 L5 VCCIB3 N9 IO108RSB2 J2 GFA1/IO162PDB3 L6 GND N10 IO103RSB2 J3 VCCPLF L7 VCC N11 IO99RSB2 J4 IO160NDB3 L8 VCC N12 GNDQ J5 GFB2/IO160PDB3 L9 VCC N13 IO92RSB2 J6 VCC L10 VCC N14 VJTAG J7 GND L11 GND N15 GDC0/IO86NDB1 J8 GND L12 VCCIB1 N16 GDA1/IO88PDB1 J9 GND L13 GDB0/IO87NPB1 P1 GEB1/IO145PDB3 J10 GND L14 IO85NDB1 P2 GEB0/IO145NDB3 J11 VCC L15 IO85PDB1 P3 VMV2 J12 GCB2/IO73PPB1 L16 IO84PDB1 P4 IO138RSB2 J13 GCA1/IO71PPB1 M1 IO150PDB3 P5 IO136RSB2 J14 GCC2/IO74PPB1 M2 IO151NPB3 P6 IO131RSB2 J15 IO80PPB1 M3 IO147NPB3 P7 IO124RSB2 J16 GCA2/IO72PDB1 M4 GEC0/IO146NPB3 P8 IO119RSB2 3 -5 4 v1.3 ProASIC3 Packaging 256-Pin FBGA 256-Pin FBGA Pin Number A3P600 Function Pin Number A3P600 Function P9 IO107RSB2 T13 IO93RSB2 P10 IO104RSB2 T14 GDA2/IO89RSB2 P11 IO97RSB2 T15 TMS P12 VMV1 T16 GND P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO88NDB1 R1 GEA1/IO144PDB3 R2 GEA0/IO144NDB3 R3 IO139RSB2 R4 GEC2/IO141RSB2 R5 IO132RSB2 R6 IO127RSB2 R7 IO121RSB2 R8 IO114RSB2 R9 IO109RSB2 R10 IO105RSB2 R11 IO98RSB2 R12 IO96RSB2 R13 GDB2/IO90RSB2 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO137RSB2 T3 GEB2/IO142RSB2 T4 IO134RSB2 T5 IO125RSB2 T6 IO123RSB2 T7 IO118RSB2 T8 IO115RSB2 T9 IO111RSB2 T10 IO106RSB2 T11 IO102RSB2 T12 GDC2/IO91RSB2 v1.3 3 - 55 Package Pin Assignments 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function A1 GND C7 IO25RSB0 E13 GBC2/IO80PDB1 A2 GAA0/IO00RSB0 C8 IO36RSB0 E14 IO83PPB1 A3 GAA1/IO01RSB0 C9 IO42RSB0 E15 IO86PPB1 A4 GAB0/IO02RSB0 C10 IO49RSB0 E16 IO87PDB1 A5 IO16RSB0 C11 IO56RSB0 F1 IO217NDB3 A6 IO22RSB0 C12 GBC0/IO72RSB0 F2 IO218NDB3 A7 IO28RSB0 C13 IO62RSB0 F3 IO216PDB3 A8 IO35RSB0 C14 VMV0 F4 IO216NDB3 A9 IO45RSB0 C15 IO78NDB1 F5 VCCIB3 A10 IO50RSB0 C16 IO81NDB1 F6 GND A11 IO55RSB0 D1 IO222NDB3 F7 VCC A12 IO61RSB0 D2 IO222PDB3 F8 VCC A13 GBB1/IO75RSB0 D3 GAC2/IO223PDB3 F9 VCC A14 GBA0/IO76RSB0 D4 IO223NDB3 F10 VCC A15 GBA1/IO77RSB0 D5 GNDQ F11 GND A16 GND D6 IO23RSB0 F12 VCCIB1 B1 GAB2/IO224PDB3 D7 IO29RSB0 F13 IO83NPB1 B2 GAA2/IO225PDB3 D8 IO33RSB0 F14 IO86NPB1 B3 GNDQ D9 IO46RSB0 F15 IO90PPB1 B4 GAB1/IO03RSB0 D10 IO52RSB0 F16 IO87NDB1 B5 IO17RSB0 D11 IO60RSB0 G1 IO210PSB3 B6 IO21RSB0 D12 GNDQ G2 IO213NDB3 B7 IO27RSB0 D13 IO80NDB1 G3 IO213PDB3 B8 IO34RSB0 D14 GBB2/IO79PDB1 G4 GFC1/IO209PPB3 B9 IO44RSB0 D15 IO79NDB1 G5 VCCIB3 B10 IO51RSB0 D16 IO82NSB1 G6 VCC B11 IO57RSB0 E1 IO217PDB3 G7 GND B12 GBC1/IO73RSB0 E2 IO218PDB3 G8 GND B13 GBB0/IO74RSB0 E3 IO221NDB3 G9 GND B14 IO71RSB0 E4 IO221PDB3 G10 GND B15 GBA2/IO78PDB1 E5 VMV0 G11 VCC B16 IO81PDB1 E6 VCCIB0 G12 VCCIB1 C1 IO224NDB3 E7 VCCIB0 G13 GCC1/IO91PPB1 C2 IO225NDB3 E8 IO38RSB0 G14 IO90NPB1 C3 VMV3 E9 IO47RSB0 G15 IO88PDB1 C4 IO11RSB0 E10 VCCIB0 G16 IO88NDB1 C5 GAC0/IO04RSB0 E11 VCCIB0 H1 GFB0/IO208NPB3 C6 GAC1/IO05RSB0 E12 VMV1 H2 GFA0/IO207NDB3 3 -5 6 v1.3 ProASIC3 Packaging 256-Pin FBGA 256-Pin FBGA 256-Pin FBGA Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function H3 GFB1/IO208PPB3 K9 GND M15 GDC1/IO111PDB1 H4 VCOMPLF K10 GND M16 IO107NDB1 H5 GFC0/IO209NPB3 K11 VCC N1 IO194PSB3 H6 VCC K12 VCCIB1 N2 IO192PPB3 H7 GND K13 IO95NPB1 N3 GEC1/IO190PPB3 H8 GND K14 IO100NPB1 N4 IO192NPB3 H9 GND K15 IO102NDB1 N5 GNDQ H10 GND K16 IO102PDB1 N6 GEA2/IO187RSB2 H11 VCC L1 IO202NDB3 N7 IO161RSB2 H12 GCC0/IO91NPB1 L2 IO202PDB3 N8 IO155RSB2 H13 GCB1/IO92PPB1 L3 IO196PPB3 N9 IO141RSB2 H14 GCA0/IO93NPB1 L4 IO193PPB3 N10 IO129RSB2 H15 IO96NPB1 L5 VCCIB3 N11 IO124RSB2 H16 GCB0/IO92NPB1 L6 GND N12 GNDQ J1 GFA2/IO206PSB3 L7 VCC N13 IO110PDB1 J2 GFA1/IO207PDB3 L8 VCC N14 VJTAG J3 VCCPLF L9 VCC N15 GDC0/IO111NDB1 J4 IO205NDB3 L10 VCC N16 GDA1/IO113PDB1 J5 GFB2/IO205PDB3 L11 GND P1 GEB1/IO189PDB3 J6 VCC L12 VCCIB1 P2 GEB0/IO189NDB3 J7 GND L13 GDB0/IO112NPB1 P3 VMV2 J8 GND L14 IO106NDB1 P4 IO179RSB2 J9 GND L15 IO106PDB1 P5 IO171RSB2 J10 GND L16 IO107PDB1 P6 IO165RSB2 J11 VCC M1 IO197NSB3 P7 IO159RSB2 J12 GCB2/IO95PPB1 M2 IO196NPB3 P8 IO151RSB2 J13 GCA1/IO93PPB1 M3 IO193NPB3 P9 IO137RSB2 J14 GCC2/IO96PPB1 M4 GEC0/IO190NPB3 P10 IO134RSB2 J15 IO100PPB1 M5 VMV3 P11 IO128RSB2 J16 GCA2/IO94PSB1 M6 VCCIB2 P12 VMV1 K1 GFC2/IO204PDB3 M7 VCCIB2 P13 TCK K2 IO204NDB3 M8 IO147RSB2 P14 VPUMP K3 IO203NDB3 M9 IO136RSB2 P15 TRST K4 IO203PDB3 M10 VCCIB2 P16 GDA0/IO113NDB1 K5 VCCIB3 M11 VCCIB2 R1 GEA1/IO188PDB3 K6 VCC M12 VMV2 R2 GEA0/IO188NDB3 K7 GND M13 IO110NDB1 R3 IO184RSB2 K8 GND M14 GDB1/IO112PPB1 R4 GEC2/IO185RSB2 v1.3 3 - 57 Package Pin Assignments 256-Pin FBGA Pin Number A3P1000 Function R5 IO168RSB2 R6 IO163RSB2 R7 IO157RSB2 R8 IO149RSB2 R9 IO143RSB2 R10 IO138RSB2 R11 IO131RSB2 R12 IO125RSB2 R13 GDB2/IO115RSB2 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO183RSB2 T3 GEB2/IO186RSB2 T4 IO172RSB2 T5 IO170RSB2 T6 IO164RSB2 T7 IO158RSB2 T8 IO153RSB2 T9 IO142RSB2 T10 IO135RSB2 T11 IO130RSB2 T12 GDC2/IO116RSB2 T13 IO120RSB2 T14 GDA2/IO114RSB2 T15 TMS T16 GND 3 -5 8 v1.3 ProASIC3 Packaging 484-Pin FBGA A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v1.3 3 - 59 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function A1 GND B15 NC D7 GAB0/IO02RSB0 A2 GND B16 NC D8 IO16RSB0 A3 VCCIB0 B17 NC D9 IO17RSB0 A4 NC B18 NC D10 IO22RSB0 A5 NC B19 NC D11 IO28RSB0 A6 IO15RSB0 B20 NC D12 IO34RSB0 A7 IO18RSB0 B21 VCCIB1 D13 IO37RSB0 A8 NC B22 GND D14 IO41RSB0 A9 NC C1 VCCIB3 D15 IO43RSB0 A10 IO23RSB0 C2 NC D16 GBB1/IO57RSB0 A11 IO29RSB0 C3 NC D17 GBA0/IO58RSB0 A12 IO35RSB0 C4 NC D18 GBA1/IO59RSB0 A13 IO36RSB0 C5 GND D19 GND A14 NC C6 NC D20 NC A15 NC C7 NC D21 NC A16 IO50RSB0 C8 VCC D22 NC A17 IO51RSB0 C9 VCC E1 NC A18 NC C10 NC E2 NC A19 NC C11 NC E3 GND A20 VCCIB0 C12 NC E4 GAB2/IO154UDB3 A21 GND C13 NC E5 GAA2/IO155UDB3 A22 GND C14 VCC E6 IO12RSB0 B1 GND C15 VCC E7 GAB1/IO03RSB0 B2 VCCIB3 C16 NC E8 IO13RSB0 B3 NC C17 NC E9 IO14RSB0 B4 NC C18 GND E10 IO21RSB0 B5 NC C19 NC E11 IO27RSB0 B6 NC C20 NC E12 IO32RSB0 B7 NC C21 NC E13 IO38RSB0 B8 NC C22 VCCIB1 E14 IO42RSB0 B9 NC D1 NC E15 GBC1/IO55RSB0 B10 NC D2 NC E16 GBB0/IO56RSB0 B11 NC D3 NC E17 IO44RSB0 B12 NC D4 GND E18 GBA2/IO60PDB1 B13 NC D5 GAA0/IO00RSB0 E19 IO60NDB1 B14 NC D6 GAA1/IO01RSB0 E20 GND 3 -6 0 v1.3 ProASIC3 Packaging 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function E21 NC G13 IO40RSB0 J5 IO149NPB3 E22 NC G14 IO46RSB0 J6 IO09RSB0 F1 NC G15 GNDQ J7 IO152UDB3 F2 NC G16 IO47RSB0 J8 VCCIB3 F3 NC G17 GBB2/IO61PPB1 J9 GND F4 IO154VDB3 G18 IO53RSB0 J10 VCC F5 IO155VDB3 G19 IO63NDB1 J11 VCC F6 IO11RSB0 G20 NC J12 VCC F7 IO07RSB0 G21 NC J13 VCC F8 GAC0/IO04RSB0 G22 NC J14 GND F9 GAC1/IO05RSB0 H1 NC J15 VCCIB1 F10 IO20RSB0 H2 NC J16 IO62NDB1 F11 IO24RSB0 H3 VCC J17 IO49RSB0 F12 IO33RSB0 H4 IO150PDB3 J18 IO64PPB1 F13 IO39RSB0 H5 IO08RSB0 J19 IO66NDB1 F14 IO45RSB0 H6 IO153VDB3 J20 NC F15 GBC0/IO54RSB0 H7 IO152VDB3 J21 NC F16 IO48RSB0 H8 VMV0 J22 NC F17 VMV0 H9 VCCIB0 K1 NC F18 IO61NPB1 H10 VCCIB0 K2 NC F19 IO63PDB1 H11 IO25RSB0 K3 NC F20 NC H12 IO31RSB0 K4 IO148NDB3 F21 NC H13 VCCIB0 K5 IO148PDB3 F22 NC H14 VCCIB0 K6 IO149PPB3 G1 NC H15 VMV1 K7 GFC1/IO147PPB3 G2 NC H16 GBC2/IO62PDB1 K8 VCCIB3 G3 NC H17 IO65RSB1 K9 VCC G4 IO151VDB3 H18 IO52RSB0 K10 GND G5 IO151UDB3 H19 IO66PDB1 K11 GND G6 GAC2/IO153UDB3 H20 VCC K12 GND G7 IO06RSB0 H21 NC K13 GND G8 GNDQ H22 NC K14 VCC G9 IO10RSB0 J1 NC K15 VCCIB1 G10 IO19RSB0 J2 NC K16 GCC1/IO67PPB1 G11 IO26RSB0 J3 NC K17 IO64NPB1 G12 IO30RSB0 J4 IO150NDB3 K18 IO73PDB1 v1.3 3 - 61 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function K19 IO73NDB1 M11 GND P3 NC K20 NC M12 GND P4 IO142NDB3 K21 NC M13 GND P5 IO141NPB3 K22 NC M14 VCC P6 IO125RSB2 L1 NC M15 GCB2/IO71PPB1 P7 IO139RSB3 L2 NC M16 GCA1/IO69PPB1 P8 VCCIB3 L3 NC M17 GCC2/IO72PPB1 P9 GND L4 GFB0/IO146NPB3 M18 NC P10 VCC L5 GFA0/IO145NDB3 M19 GCA2/IO70PDB1 P11 VCC L6 GFB1/IO146PPB3 M20 NC P12 VCC L7 VCOMPLF M21 NC P13 VCC L8 GFC0/IO147NPB3 M22 NC P14 GND L9 VCC N1 NC P15 VCCIB1 L10 GND N2 NC P16 GDB0/IO78VPB1 L11 GND N3 NC P17 IO76VDB1 L12 GND N4 GFC2/IO142PDB3 P18 IO76UDB1 L13 GND N5 IO144NPB3 P19 IO75PDB1 L14 VCC N6 IO141PPB3 P20 NC L15 GCC0/IO67NPB1 N7 IO120RSB2 P21 NC L16 GCB1/IO68PPB1 N8 VCCIB3 P22 NC L17 GCA0/IO69NPB1 N9 VCC R1 NC L18 NC N10 GND R2 NC L19 GCB0/IO68NPB1 N11 GND R3 VCC L20 NC N12 GND R4 IO140PDB3 L21 NC N13 GND R5 IO130RSB2 L22 NC N14 VCC R6 IO138NPB3 M1 NC N15 VCCIB1 R7 GEC0/IO137NPB3 M2 NC N16 IO71NPB1 R8 VMV3 M3 NC N17 IO74RSB1 R9 VCCIB2 M4 GFA2/IO144PPB3 N18 IO72NPB1 R10 VCCIB2 M5 GFA1/IO145PDB3 N19 IO70NDB1 R11 IO108RSB2 M6 VCCPLF N20 NC R12 IO101RSB2 M7 IO143NDB3 N21 NC R13 VCCIB2 M8 GFB2/IO143PDB3 N22 NC R14 VCCIB2 M9 VCC P1 NC R15 VMV2 M10 GND P2 NC R16 IO83RSB2 3 -6 2 v1.3 ProASIC3 Packaging 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P400 Function Pin Number A3P400 Function Pin Number A3P400 Function R17 GDB1/IO78UPB1 U9 IO122RSB2 W1 NC R18 GDC1/IO77UDB1 U10 IO115RSB2 W2 NC R19 IO75NDB1 U11 IO110RSB2 W3 NC R20 VCC U12 IO98RSB2 W4 GND R21 NC U13 IO95RSB2 W5 IO126RSB2 R22 NC U14 IO88RSB2 W6 GEB2/IO133RSB2 T1 NC U15 IO84RSB2 W7 IO124RSB2 T2 NC U16 TCK W8 IO116RSB2 T3 NC U17 VPUMP W9 IO113RSB2 T4 IO140NDB3 U18 TRST W10 IO107RSB2 T5 IO138PPB3 U19 GDA0/IO79VDB1 W11 IO105RSB2 T6 GEC1/IO137PPB3 U20 NC W12 IO102RSB2 T7 IO131RSB2 U21 NC W13 IO97RSB2 T8 GNDQ U22 NC W14 IO92RSB2 T9 GEA2/IO134RSB2 V1 NC W15 GDC2/IO82RSB2 T10 IO117RSB2 V2 NC W16 IO86RSB2 T11 IO111RSB2 V3 GND W17 GDA2/IO80RSB2 T12 IO99RSB2 V4 GEA1/IO135PDB3 W18 TMS T13 IO94RSB2 V5 GEA0/IO135NDB3 W19 GND T14 IO87RSB2 V6 IO127RSB2 W20 NC T15 GNDQ V7 GEC2/IO132RSB2 W21 NC T16 IO93RSB2 V8 IO123RSB2 W22 NC T17 VJTAG V9 IO118RSB2 Y1 VCCIB3 T18 GDC0/IO77VDB1 V10 IO112RSB2 Y2 NC T19 GDA1/IO79UDB1 V11 IO106RSB2 Y3 NC T20 NC V12 IO100RSB2 Y4 NC T21 NC V13 IO96RSB2 Y5 GND T22 NC V14 IO89RSB2 Y6 NC U1 NC V15 IO85RSB2 Y7 NC U2 NC V16 GDB2/IO81RSB2 Y8 VCC U3 NC V17 TDI Y9 VCC U4 GEB1/IO136PDB3 V18 NC Y10 NC U5 GEB0/IO136NDB3 V19 TDO Y11 NC U6 VMV2 V20 GND Y12 NC U7 IO129RSB2 V21 NC Y13 NC U8 IO128RSB2 V22 NC Y14 VCC v1.3 3 - 63 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA Pin Number A3P400 Function Pin Number A3P400 Function Y15 VCC AB7 IO119RSB2 Y16 NC AB8 IO114RSB2 Y17 NC AB9 IO109RSB2 Y18 GND AB10 NC Y19 NC AB11 NC Y20 NC AB12 IO104RSB2 Y21 NC AB13 IO103RSB2 Y22 VCCIB1 AB14 NC AA1 GND AB15 NC AA2 VCCIB3 AB16 IO91RSB2 AA3 NC AB17 IO90RSB2 AA4 NC AB18 NC AA5 NC AB19 NC AA6 NC AB20 VCCIB2 AA7 NC AB21 GND AA8 NC AB22 GND AA9 NC AA10 NC AA11 NC AA12 NC AA13 NC AA14 NC AA15 NC AA16 NC AA17 NC AA18 NC AA19 NC AA20 NC AA21 VCCIB1 AA22 GND AB1 GND AB2 GND AB3 VCCIB2 AB4 NC AB5 NC AB6 IO121RSB2 3 -6 4 v1.3 ProASIC3 Packaging 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function A1 GND B15 NC D7 GAB0/IO02RSB0 A2 GND B16 IO47RSB0 D8 IO11RSB0 A3 VCCIB0 B17 IO49RSB0 D9 IO16RSB0 A4 NC B18 NC D10 IO18RSB0 A5 NC B19 NC D11 IO28RSB0 A6 IO09RSB0 B20 NC D12 IO34RSB0 A7 IO15RSB0 B21 VCCIB1 D13 IO37RSB0 A8 NC B22 GND D14 IO41RSB0 A9 NC C1 VCCIB3 D15 IO43RSB0 A10 IO22RSB0 C2 NC D16 GBB1/IO57RSB0 A11 IO23RSB0 C3 NC D17 GBA0/IO58RSB0 A12 IO29RSB0 C4 NC D18 GBA1/IO59RSB0 A13 IO35RSB0 C5 GND D19 GND A14 NC C6 NC D20 NC A15 NC C7 NC D21 NC A16 IO46RSB0 C8 VCC D22 NC A17 IO48RSB0 C9 VCC E1 NC A18 NC C10 NC E2 NC A19 NC C11 NC E3 GND A20 VCCIB0 C12 NC E4 GAB2/IO173PDB3 A21 GND C13 NC E5 GAA2/IO174PDB3 A22 GND C14 VCC E6 GNDQ B1 GND C15 VCC E7 GAB1/IO03RSB0 B2 VCCIB3 C16 NC E8 IO13RSB0 B3 NC C17 NC E9 IO14RSB0 B4 NC C18 GND E10 IO21RSB0 B5 NC C19 NC E11 IO27RSB0 B6 IO08RSB0 C20 NC E12 IO32RSB0 B7 IO12RSB0 C21 NC E13 IO38RSB0 B8 NC C22 VCCIB1 E14 IO42RSB0 B9 NC D1 NC E15 GBC1/IO55RSB0 B10 IO17RSB0 D2 NC E16 GBB0/IO56RSB0 B11 NC D3 NC E17 IO52RSB0 B12 NC D4 GND E18 GBA2/IO60PDB1 B13 IO36RSB0 D5 GAA0/IO00RSB0 E19 IO60NDB1 B14 NC D6 GAA1/IO01RSB0 E20 GND v1.3 3 - 65 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function E21 NC G13 IO40RSB0 J5 IO168NPB3 E22 NC G14 IO45RSB0 J6 IO167PPB3 F1 NC G15 GNDQ J7 IO169PDB3 F2 NC G16 IO50RSB0 J8 VCCIB3 F3 NC G17 GBB2/IO61PPB1 J9 GND F4 IO173NDB3 G18 IO53RSB0 J10 VCC F5 IO174NDB3 G19 IO63NDB1 J11 VCC F6 VMV3 G20 NC J12 VCC F7 IO07RSB0 G21 NC J13 VCC F8 GAC0/IO04RSB0 G22 NC J14 GND F9 GAC1/IO05RSB0 H1 NC J15 VCCIB1 F10 IO20RSB0 H2 NC J16 IO62NDB1 F11 IO24RSB0 H3 VCC J17 IO64NPB1 F12 IO33RSB0 H4 IO166PDB3 J18 IO65PPB1 F13 IO39RSB0 H5 IO167NPB3 J19 IO66NDB1 F14 IO44RSB0 H6 IO172NDB3 J20 NC F15 GBC0/IO54RSB0 H7 IO169NDB3 J21 IO68PDB1 F16 IO51RSB0 H8 VMV0 J22 IO68NDB1 F17 VMV0 H9 VCCIB0 K1 IO157PDB3 F18 IO61NPB1 H10 VCCIB0 K2 IO157NDB3 F19 IO63PDB1 H11 IO25RSB0 K3 NC F20 NC H12 IO31RSB0 K4 IO165NDB3 F21 NC H13 VCCIB0 K5 IO165PDB3 F22 NC H14 VCCIB0 K6 IO168PPB3 G1 IO170NDB3 H15 VMV1 K7 GFC1/IO164PPB3 G2 IO170PDB3 H16 GBC2/IO62PDB1 K8 VCCIB3 G3 NC H17 IO67PPB1 K9 VCC G4 IO171NDB3 H18 IO64PPB1 K10 GND G5 IO171PDB3 H19 IO66PDB1 K11 GND G6 GAC2/IO172PDB3 H20 VCC K12 GND G7 IO06RSB0 H21 NC K13 GND G8 GNDQ H22 NC K14 VCC G9 IO10RSB0 J1 NC K15 VCCIB1 G10 IO19RSB0 J2 NC K16 GCC1/IO69PPB1 G11 IO26RSB0 J3 NC K17 IO65NPB1 G12 IO30RSB0 J4 IO166NDB3 K18 IO75PDB1 3 -6 6 v1.3 ProASIC3 Packaging 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function K19 IO75NDB1 M11 GND P3 IO153NDB3 K20 NC M12 GND P4 IO159NDB3 K21 IO76NDB1 M13 GND P5 IO156NPB3 K22 IO76PDB1 M14 VCC P6 IO151PPB3 L1 NC M15 GCB2/IO73PPB1 P7 IO158PPB3 L2 IO155PDB3 M16 GCA1/IO71PPB1 P8 VCCIB3 L3 NC M17 GCC2/IO74PPB1 P9 GND L4 GFB0/IO163NPB3 M18 IO80PPB1 P10 VCC L5 GFA0/IO162NDB3 M19 GCA2/IO72PDB1 P11 VCC L6 GFB1/IO163PPB3 M20 IO79PPB1 P12 VCC L7 VCOMPLF M21 IO78PPB1 P13 VCC L8 GFC0/IO164NPB3 M22 NC P14 GND L9 VCC N1 IO154NDB3 P15 VCCIB1 L10 GND N2 IO154PDB3 P16 GDB0/IO87NPB1 L11 GND N3 NC P17 IO85NDB1 L12 GND N4 GFC2/IO159PDB3 P18 IO85PDB1 L13 GND N5 IO161NPB3 P19 IO84PDB1 L14 VCC N6 IO156PPB3 P20 NC L15 GCC0/IO69NPB1 N7 IO129RSB2 P21 IO81PDB1 L16 GCB1/IO70PPB1 N8 VCCIB3 P22 NC L17 GCA0/IO71NPB1 N9 VCC R1 NC L18 IO67NPB1 N10 GND R2 NC L19 GCB0/IO70NPB1 N11 GND R3 VCC L20 IO77PDB1 N12 GND R4 IO150PDB3 L21 IO77NDB1 N13 GND R5 IO151NPB3 L22 IO78NPB1 N14 VCC R6 IO147NPB3 M1 NC N15 VCCIB1 R7 GEC0/IO146NPB3 M2 IO155NDB3 N16 IO73NPB1 R8 VMV3 M3 IO158NPB3 N17 IO80NPB1 R9 VCCIB2 M4 GFA2/IO161PPB3 N18 IO74NPB1 R10 VCCIB2 M5 GFA1/IO162PDB3 N19 IO72NDB1 R11 IO117RSB2 M6 VCCPLF N20 NC R12 IO110RSB2 M7 IO160NDB3 N21 IO79NPB1 R13 VCCIB2 M8 GFB2/IO160PDB3 N22 NC R14 VCCIB2 M9 VCC P1 NC R15 VMV2 M10 GND P2 IO153PDB3 R16 IO94RSB2 v1.3 3 - 67 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P600 Function Pin Number A3P600 Function Pin Number A3P600 Function R17 GDB1/IO87PPB1 U9 IO131RSB2 W1 NC R18 GDC1/IO86PDB1 U10 IO124RSB2 W2 IO148PDB3 R19 IO84NDB1 U11 IO119RSB2 W3 NC R20 VCC U12 IO107RSB2 W4 GND R21 IO81NDB1 U13 IO104RSB2 W5 IO137RSB2 R22 IO82PDB1 U14 IO97RSB2 W6 GEB2/IO142RSB2 T1 IO152PDB3 U15 VMV1 W7 IO134RSB2 T2 IO152NDB3 U16 TCK W8 IO125RSB2 T3 NC U17 VPUMP W9 IO123RSB2 T4 IO150NDB3 U18 TRST W10 IO118RSB2 T5 IO147PPB3 U19 GDA0/IO88NDB1 W11 IO115RSB2 T6 GEC1/IO146PPB3 U20 NC W12 IO111RSB2 T7 IO140RSB2 U21 IO83NDB1 W13 IO106RSB2 T8 GNDQ U22 NC W14 IO102RSB2 T9 GEA2/IO143RSB2 V1 NC W15 GDC2/IO91RSB2 T10 IO126RSB2 V2 NC W16 IO93RSB2 T11 IO120RSB2 V3 GND W17 GDA2/IO89RSB2 T12 IO108RSB2 V4 GEA1/IO144PDB3 W18 TMS T13 IO103RSB2 V5 GEA0/IO144NDB3 W19 GND T14 IO99RSB2 V6 IO139RSB2 W20 NC T15 GNDQ V7 GEC2/IO141RSB2 W21 NC T16 IO92RSB2 V8 IO132RSB2 W22 NC T17 VJTAG V9 IO127RSB2 Y1 VCCIB3 T18 GDC0/IO86NDB1 V10 IO121RSB2 Y2 IO148NDB3 T19 GDA1/IO88PDB1 V11 IO114RSB2 Y3 NC T20 NC V12 IO109RSB2 Y4 NC T21 IO83PDB1 V13 IO105RSB2 Y5 GND T22 IO82NDB1 V14 IO98RSB2 Y6 NC U1 IO149PDB3 V15 IO96RSB2 Y7 NC U2 IO149NDB3 V16 GDB2/IO90RSB2 Y8 VCC U3 NC V17 TDI Y9 VCC U4 GEB1/IO145PDB3 V18 GNDQ Y10 NC U5 GEB0/IO145NDB3 V19 TDO Y11 NC U6 VMV2 V20 GND Y12 NC U7 IO138RSB2 V21 NC Y13 NC U8 IO136RSB2 V22 NC Y14 VCC 3 -6 8 v1.3 ProASIC3 Packaging 484-Pin FBGA 484-Pin FBGA Pin Number A3P600 Function Pin Number A3P600 Function Y15 VCC AB7 IO128RSB2 Y16 NC AB8 IO122RSB2 Y17 NC AB9 IO116RSB2 Y18 GND AB10 NC Y19 NC AB11 NC Y20 NC AB12 IO113RSB2 Y21 NC AB13 IO112RSB2 Y22 VCCIB1 AB14 NC AA1 GND AB15 NC AA2 VCCIB3 AB16 IO100RSB2 AA3 NC AB17 IO95RSB2 AA4 NC AB18 NC AA5 NC AB19 NC AA6 IO135RSB2 AB20 VCCIB2 AA7 IO133RSB2 AB21 GND AA8 NC AB22 GND AA9 NC AA10 NC AA11 NC AA12 NC AA13 NC AA14 NC AA15 NC AA16 IO101RSB2 AA17 NC AA18 NC AA19 NC AA20 NC AA21 VCCIB1 AA22 GND AB1 GND AB2 GND AB3 VCCIB2 AB4 NC AB5 NC AB6 IO130RSB2 v1.3 3 - 69 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function A1 GND B15 IO63RSB0 D7 GAB0/IO02RSB0 A2 GND B16 IO66RSB0 D8 IO16RSB0 A3 VCCIB0 B17 IO68RSB0 D9 IO22RSB0 A4 IO07RSB0 B18 IO70RSB0 D10 IO28RSB0 A5 IO09RSB0 B19 NC D11 IO35RSB0 A6 IO13RSB0 B20 NC D12 IO45RSB0 A7 IO18RSB0 B21 VCCIB1 D13 IO50RSB0 A8 IO20RSB0 B22 GND D14 IO55RSB0 A9 IO26RSB0 C1 VCCIB3 D15 IO61RSB0 A10 IO32RSB0 C2 IO220PDB3 D16 GBB1/IO75RSB0 A11 IO40RSB0 C3 NC D17 GBA0/IO76RSB0 A12 IO41RSB0 C4 NC D18 GBA1/IO77RSB0 A13 IO53RSB0 C5 GND D19 GND A14 IO59RSB0 C6 IO10RSB0 D20 NC A15 IO64RSB0 C7 IO14RSB0 D21 NC A16 IO65RSB0 C8 VCC D22 NC A17 IO67RSB0 C9 VCC E1 IO219NDB3 A18 IO69RSB0 C10 IO30RSB0 E2 NC A19 NC C11 IO37RSB0 E3 GND A20 VCCIB0 C12 IO43RSB0 E4 GAB2/IO224PDB3 A21 GND C13 NC E5 GAA2/IO225PDB3 A22 GND C14 VCC E6 GNDQ B1 GND C15 VCC E7 GAB1/IO03RSB0 B2 VCCIB3 C16 NC E8 IO17RSB0 B3 NC C17 NC E9 IO21RSB0 B4 IO06RSB0 C18 GND E10 IO27RSB0 B5 IO08RSB0 C19 NC E11 IO34RSB0 B6 IO12RSB0 C20 NC E12 IO44RSB0 B7 IO15RSB0 C21 NC E13 IO51RSB0 B8 IO19RSB0 C22 VCCIB1 E14 IO57RSB0 B9 IO24RSB0 D1 IO219PDB3 E15 GBC1/IO73RSB0 B10 IO31RSB0 D2 IO220NDB3 E16 GBB0/IO74RSB0 B11 IO39RSB0 D3 NC E17 IO71RSB0 B12 IO48RSB0 D4 GND E18 GBA2/IO78PDB1 B13 IO54RSB0 D5 GAA0/IO00RSB0 E19 IO81PDB1 B14 IO58RSB0 D6 GAA1/IO01RSB0 E20 GND 3 -7 0 v1.3 ProASIC3 Packaging 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function E21 NC G13 IO52RSB0 J5 IO218NDB3 E22 IO84PDB1 G14 IO60RSB0 J6 IO216PDB3 F1 NC G15 GNDQ J7 IO216NDB3 F2 IO215PDB3 G16 IO80NDB1 J8 VCCIB3 F3 IO215NDB3 G17 GBB2/IO79PDB1 J9 GND F4 IO224NDB3 G18 IO79NDB1 J10 VCC F5 IO225NDB3 G19 IO82NPB1 J11 VCC F6 VMV3 G20 IO85PDB1 J12 VCC F7 IO11RSB0 G21 IO85NDB1 J13 VCC F8 GAC0/IO04RSB0 G22 NC J14 GND F9 GAC1/IO05RSB0 H1 NC J15 VCCIB1 F10 IO25RSB0 H2 NC J16 IO83NPB1 F11 IO36RSB0 H3 VCC J17 IO86NPB1 F12 IO42RSB0 H4 IO217PDB3 J18 IO90PPB1 F13 IO49RSB0 H5 IO218PDB3 J19 IO87NDB1 F14 IO56RSB0 H6 IO221NDB3 J20 NC F15 GBC0/IO72RSB0 H7 IO221PDB3 J21 IO89PDB1 F16 IO62RSB0 H8 VMV0 J22 IO89NDB1 F17 VMV0 H9 VCCIB0 K1 IO211PDB3 F18 IO78NDB1 H10 VCCIB0 K2 IO211NDB3 F19 IO81NDB1 H11 IO38RSB0 K3 NC F20 IO82PPB1 H12 IO47RSB0 K4 IO210PPB3 F21 NC H13 VCCIB0 K5 IO213NDB3 F22 IO84NDB1 H14 VCCIB0 K6 IO213PDB3 G1 IO214NDB3 H15 VMV1 K7 GFC1/IO209PPB3 G2 IO214PDB3 H16 GBC2/IO80PDB1 K8 VCCIB3 G3 NC H17 IO83PPB1 K9 VCC G4 IO222NDB3 H18 IO86PPB1 K10 GND G5 IO222PDB3 H19 IO87PDB1 K11 GND G6 GAC2/IO223PDB3 H20 VCC K12 GND G7 IO223NDB3 H21 NC K13 GND G8 GNDQ H22 NC K14 VCC G9 IO23RSB0 J1 IO212NDB3 K15 VCCIB1 G10 IO29RSB0 J2 IO212PDB3 K16 GCC1/IO91PPB1 G11 IO33RSB0 J3 NC K17 IO90NPB1 G12 IO46RSB0 J4 IO217NDB3 K18 IO88PDB1 v1.3 3 - 71 Package Pin Assignments 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function K19 IO88NDB1 M11 GND P3 IO199NDB3 K20 IO94NPB1 M12 GND P4 IO202NDB3 K21 IO98NDB1 M13 GND P5 IO202PDB3 K22 IO98PDB1 M14 VCC P6 IO196PPB3 L1 NC M15 GCB2/IO95PPB1 P7 IO193PPB3 L2 IO200PDB3 M16 GCA1/IO93PPB1 P8 VCCIB3 L3 IO210NPB3 M17 GCC2/IO96PPB1 P9 GND L4 GFB0/IO208NPB3 M18 IO100PPB1 P10 VCC L5 GFA0/IO207NDB3 M19 GCA2/IO94PPB1 P11 VCC L6 GFB1/IO208PPB3 M20 IO101PPB1 P12 VCC L7 VCOMPLF M21 IO99PPB1 P13 VCC L8 GFC0/IO209NPB3 M22 NC P14 GND L9 VCC N1 IO201NDB3 P15 VCCIB1 L10 GND N2 IO201PDB3 P16 GDB0/IO112NPB1 L11 GND N3 NC P17 IO106NDB1 L12 GND N4 GFC2/IO204PDB3 P18 IO106PDB1 L13 GND N5 IO204NDB3 P19 IO107PDB1 L14 VCC N6 IO203NDB3 P20 NC L15 GCC0/IO91NPB1 N7 IO203PDB3 P21 IO104PDB1 L16 GCB1/IO92PPB1 N8 VCCIB3 P22 IO103NDB1 L17 GCA0/IO93NPB1 N9 VCC R1 NC L18 IO96NPB1 N10 GND R2 IO197PPB3 L19 GCB0/IO92NPB1 N11 GND R3 VCC L20 IO97PDB1 N12 GND R4 IO197NPB3 L21 IO97NDB1 N13 GND R5 IO196NPB3 L22 IO99NPB1 N14 VCC R6 IO193NPB3 M1 NC N15 VCCIB1 R7 GEC0/IO190NPB3 M2 IO200NDB3 N16 IO95NPB1 R8 VMV3 M3 IO206NDB3 N17 IO100NPB1 R9 VCCIB2 M4 GFA2/IO206PDB3 N18 IO102NDB1 R10 VCCIB2 M5 GFA1/IO207PDB3 N19 IO102PDB1 R11 IO147RSB2 M6 VCCPLF N20 NC R12 IO136RSB2 M7 IO205NDB3 N21 IO101NPB1 R13 VCCIB2 M8 GFB2/IO205PDB3 N22 IO103PDB1 R14 VCCIB2 M9 VCC P1 NC R15 VMV2 M10 GND P2 IO199PDB3 R16 IO110NDB1 3 -7 2 v1.3 ProASIC3 Packaging 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number A3P1000 Function Pin Number A3P1000 Function Pin Number A3P1000 Function R17 GDB1/IO112PPB1 U9 IO165RSB2 W1 NC R18 GDC1/IO111PDB1 U10 IO159RSB2 W2 IO191PDB3 R19 IO107NDB1 U11 IO151RSB2 W3 NC R20 VCC U12 IO137RSB2 W4 GND R21 IO104NDB1 U13 IO134RSB2 W5 IO183RSB2 R22 IO105PDB1 U14 IO128RSB2 W6 GEB2/IO186RSB2 T1 IO198PDB3 U15 VMV1 W7 IO172RSB2 T2 IO198NDB3 U16 TCK W8 IO170RSB2 T3 NC U17 VPUMP W9 IO164RSB2 T4 IO194PPB3 U18 TRST W10 IO158RSB2 T5 IO192PPB3 U19 GDA0/IO113NDB1 W11 IO153RSB2 T6 GEC1/IO190PPB3 U20 NC W12 IO142RSB2 T7 IO192NPB3 U21 IO108NDB1 W13 IO135RSB2 T8 GNDQ U22 IO109PDB1 W14 IO130RSB2 T9 GEA2/IO187RSB2 V1 NC W15 GDC2/IO116RSB2 T10 IO161RSB2 V2 NC W16 IO120RSB2 T11 IO155RSB2 V3 GND W17 GDA2/IO114RSB2 T12 IO141RSB2 V4 GEA1/IO188PDB3 W18 TMS T13 IO129RSB2 V5 GEA0/IO188NDB3 W19 GND T14 IO124RSB2 V6 IO184RSB2 W20 NC T15 GNDQ V7 GEC2/IO185RSB2 W21 NC T16 IO110PDB1 V8 IO168RSB2 W22 NC T17 VJTAG V9 IO163RSB2 Y1 VCCIB3 T18 GDC0/IO111NDB1 V10 IO157RSB2 Y2 IO191NDB3 T19 GDA1/IO113PDB1 V11 IO149RSB2 Y3 NC T20 NC V12 IO143RSB2 Y4 IO182RSB2 T21 IO108PDB1 V13 IO138RSB2 Y5 GND T22 IO105NDB1 V14 IO131RSB2 Y6 IO177RSB2 U1 IO195PDB3 V15 IO125RSB2 Y7 IO174RSB2 U2 IO195NDB3 V16 GDB2/IO115RSB2 Y8 VCC U3 IO194NPB3 V17 TDI Y9 VCC U4 GEB1/IO189PDB3 V18 GNDQ Y10 IO154RSB2 U5 GEB0/IO189NDB3 V19 TDO Y11 IO148RSB2 U6 VMV2 V20 GND Y12 IO140RSB2 U7 IO179RSB2 V21 NC Y13 NC U8 IO171RSB2 V22 IO109NDB1 Y14 VCC v1.3 3 - 73 ProASIC3 Packaging 484-Pin FBGA 484-Pin FBGA Pin Number A3P1000 Function Pin Number A3P1000 Function Y15 VCC AB7 IO167RSB2 Y16 NC AB8 IO162RSB2 Y17 NC AB9 IO156RSB2 Y18 GND AB10 IO150RSB2 Y19 NC AB11 IO145RSB2 Y20 NC AB12 IO144RSB2 Y21 NC AB13 IO132RSB2 Y22 VCCIB1 AB14 IO127RSB2 AA1 GND AB15 IO126RSB2 AA2 VCCIB3 AB16 IO123RSB2 AA3 NC AB17 IO121RSB2 AA4 IO181RSB2 AB18 IO118RSB2 AA5 IO178RSB2 AB19 NC AA6 IO175RSB2 AB20 VCCIB2 AA7 IO169RSB2 AB21 GND AA8 IO166RSB2 AB22 GND AA9 IO160RSB2 AA10 IO152RSB2 AA11 IO146RSB2 AA12 IO139RSB2 AA13 IO133RSB2 AA14 NC AA15 NC AA16 IO122RSB2 AA17 IO119RSB2 AA18 IO117RSB2 AA19 NC AA20 NC AA21 VCCIB1 AA22 GND AB1 GND AB2 GND AB3 VCCIB2 AB4 IO180RSB2 AB5 IO176RSB2 AB6 IO173RSB2 v1.3 3 - 74 ProASIC3 Packaging Part Number and Revision Date Part Number 51700097-003-3 Revised June 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v1.3) Page v1.2 (February 2008) Pin numbers were added to the "68-Pin QFN" package diagram. Note 2 was added below the diagram. 3-1 The "132-Pin QFN" package diagram was updated to include D1 to D4. In addition, note 1 was changed from top view to bottom view, and note 2 is new. 3-3 v1.1 (January 2008) The "68-Pin QFN" section is new. 3-1 v1.0 (January 2008) In the "100-Pin VQFP" A3P030 pin table, the function of pin 63 was incorrect and changed from IO39RSB0 to GDB0/IO38RSB0. 3-12 v2.2 (July 2007) This document was previously in datasheet v2.2. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is v1.0. N/A v2.0 (April 2007) The following pin tables were updated for A3P600: "208-Pin PQFP", "256-Pin 4-27 - 4-63 FBGA", and "484-Pin FBGA". The "144-Pin FBGA" table for A3P600 is new. Advanced v0.7 (January 2007) Notes were added to the package diagrams identifying if they were top or bottom view. N/A The A3P030 "132-Pin QFN" table is new. 4-2 The A3P060 "132-Pin QFN" table is new. 4-4 The A3P125 "132-Pin QFN" table is new. 4-6 The A3P250 "132-Pin QFN" table is new. 4-8 The A3P030 "100-Pin VQFP" table is new. 4-11 The A3P060 "100-Pin VQFP" pin table was updated. 4-13 The A3P125 "100-Pin VQFP" pin table was updated. 4-13 The A3P060 "144-Pin TQFP" pin table was updated. 4-16 The A3P125 "144-Pin TQFP" pin table was updated. 4-18 The A3P125 "208-Pin PQFP" pin table was updated. 4-21 The A3P400 "208-Pin PQFP" pin table was updated. 4-25 The A3P060 "144-Pin FBGA" pin table was updated. 4-32 The A3P125 "144-Pin FBGA" pin table is new. 4-34 The A3P400 "144-Pin FBGA" is new. 4-38 The A3P400 "256-Pin FBGA" was updated. 4-48 The A3P1000 "256-Pin FBGA" was updated. 4-54 The A3P400 "484-Pin FBGA" was updated. 4-58 The A3P1000 "484-Pin FBGA" was updated. 4-68 Advanced v0.5 (January 2006) v1.3 3 - 75 ProASIC3 Packaging Previous Version Advanced v0.2 (continued) Changes in Current Version (v1.3) Page The A3P250 "100-Pin VQFP*" pin table was updated. 4-14 The A3P250 "208-Pin PQFP*" pin table was updated. 4-23 The A3P1000 "208-Pin PQFP*" pin table was updated. 4-29 The A3P250 "144-Pin FBGA*" pin table was updated. 4-36 The A3P1000 "144-Pin FBGA*" pin table was updated. 4-32 The A3P250 "256-Pin FBGA*" pin table was updated. 4-45 The A3P1000 "256-Pin FBGA*" pin table was updated. 4-54 The A3P1000 "484-Pin FBGA*" pin table was updated. 4-68 v1.3 3 - 76 ProASIC3 Packaging Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production". The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) and contains general product information. This document gives an overview of specific device and family information. Advanced This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advanced status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. v1.3 3 - 77 Section II - Core Architecture Low-Power Flash Technology and Flash*Freeze Mode Core Architecture of IGLOO and ProASIC3 Devices 1 - Core Architecture of IGLOO and ProASIC3 Devices Device Architecture Advanced Flash Switch Unlike SRAM FPGAs, the low-power flash devices use a live-at-power-up ISP flash switch as their programming element. Flash cells are distributed throughout the device to provide nonvolatile, reconfigurable programming to connect signal lines to the appropriate VersaTile inputs and outputs. In the flash switch, two transistors share the floating gate, which stores the programming information (Figure 1-1). One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor. The latter is used to connect or separate routing nets, or to configure VersaTile logic. It is also used to erase the floating gate. Dedicated high-performance lines are connected as required using the flash switch for fast, low-skew, global signal distribution throughout the device core. Maximum core utilization is possible for virtually any design. The use of the flash switch technology also removes the possibility of firm errors, which are increasingly common in SRAM-based FPGAs. Floating Gate Sensing Switch In Switching Word Switch Out Figure 1-1 * Flash-Based Switch v1.1 1-1 Core Architecture of IGLOO and ProASIC3 Devices IGLOO(R) and ProASIC(R)3 Core Architecture Support The low-power flash families listed in Table 1-1 support the architecture features described in this document. Table 1-1 * Low-Power Flash Families Family1 IGLOO Timing Numbers2 Description Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*FreezeTM IGLOO DC and technology Characteristics Switching IGLOO PLUS Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO PLUS DC and technology and enhanced I/O capabilities Switching Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional PLLs, IGLOOe DC and Switching and additional I/O standards Characteristics ProASIC3L Low-power, high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and Switching technology Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, and ProASIC3E DC and Switching additional I/O standards Characteristics ProASIC3 DC and Switching Characteristics ProASIC3 Low-power, high-performance FPGAs qualified for automotive Automotive ProASIC3 DC and Automotive applications Switching Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 1-1) provide a selection of low-power, secure, live-atpower-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 1-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 1-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 1 -2 v1.1 Core Architecture of IGLOO and ProASIC3 Devices Device Overview The low-power flash devices consist of multiple distinct programmable architectural features (Figure 1-2 on page 1-3 through Figure 1-4 on page 1-4): * FPGA fabric/core (VersaTiles) * Routing and clock resources (VersaNets) * FlashROM * Dedicated SRAM and/or FIFO - 15 k and 30 k gate devices do not support SRAM or FIFO. - Automotive devices do not support FIFO operation * I/O Structures * Flash*Freeze technology and low-power modes Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 2 Note: Flash*Freeze technology only applies to IGLOO and ProASIC3L families. Figure 1-2 * IGLOO and ProASIC3/L Device Architecture Overview with Four I/O Banks (AGL600 device is shown) v1.1 1-3 Core Architecture of IGLOO and ProASIC3 Devices Bank 0 Bank 1 Bank 3 CCC* RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os Bank 1 Bank 3 VersaTile ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps Bank 2 Figure 1-3 * IGLOO PLUS Device Architecture Overview with Four I/O Banks CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile ISP AES Decryption User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Note: Flash*Freeze technology only applies to IGLOOe devices. Figure 1-4 * IGLOOe and ProASIC3E Device Architecture Overview (AGLE600 device is shown) 1 -4 v1.1 Core Architecture of IGLOO and ProASIC3 Devices Core Architecture VersaTile The proprietary IGLOO and ProASIC3 device architectures provide granularity comparable to gate arrays. The device core consists of a sea-of-VersaTiles architecture. As illustrated in Figure 1-5, there are four inputs in a logic VersaTile cell, and each VersaTile can be configured using the appropriate flash switch connections: * Any 3-input logic function * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set (on a 4th input) VersaTiles can flexibly map the logic and sequential gates of a design. The inputs of the VersaTile can be inverted (allowing bubble pushing), and the output of the tile can connect to high-speed, very-long-line routing resources. VersaTiles and larger functions can be connected with any of the four levels of routing hierarchy. When the VersaTile is used as an enable D-flip-flop, SET/CLR is supported by a fourth input. The SET/CLR signal can only be routed to this fourth input over the VersaNet (global) network. However, if, in the user's design, the SET/CLR signal is not routed over the VersaNet network, a compile warning message will be given, and the intended logic function will be implemented by two VersaTiles instead of one. The output of the VersaTile is F2 when the connection is to the ultra-fast local lines, or YL when the connection is to the efficient long-line or very-long-line resources. 0 1 Y Pin 1 Data X3 0 1 0 1 F2 YL 0 1 CLK X2 CLR/ Enable X1 CLR XC* Legend: Via (hard connection) Switch (flash connection) Ground * This input can only be connected to the global clock distribution network. Figure 1-5 * Low-Power Flash Device Core VersaTile v1.1 1-5 Core Architecture of IGLOO and ProASIC3 Devices Array Coordinates During many place-and-route operations in the Actel Designer software tool, it is possible to set constraints that require array coordinates. Table 1-2 provides array coordinates of core cells and memory blocks for ProASIC3 and IGLOO devices. Table 1-3 provides the information for IGLOO PLUS devices. The array coordinates are measured from the lower left (0, 0) They can be used in region constraints for specific logic groups/blocks, designated by a wildcard, and can contain core cells, memories, and I/Os. I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a one-to-one correspondence between I/O cells and core cells. In addition, the I/O coordinate system changes depending on the die/package combination. It is not listed in Table 1-2. The Designer ChipPlanner tool provides the array coordinates of all I/O locations. I/O and cell coordinates are used for placement constraints. However, I/O placement is easier by package pin assignment. Figure 1-6 on page 1-7 illustrates the array coordinates of a 600 k gate device. For more information on how to use array coordinates for region/placement constraints, see the Designer User's Guide or online help (available in the software) for software tools. Table 1-2 * IGLOO and ProASIC3 Array Coordinates VersaTiles Device Min. Max. Entire Die Bottom Top Min. Max. ProASIC3/ ProASIC3L IGLOO x y x y (x, y) (x, y) (x, y) (x, y) A3P015 AGL015 3 2 34 13 None None (0, 0) (37, 15) A3P030 AGL030 3 3 66 13 None None (0, 0) (69, 15) A3P060 AGL060 3 2 66 25 None (3, 26) (0, 0) (69, 29) A3P125 AGL125 3 2 130 25 None (3, 26) (0, 0) (133, 29) A3P250/L AGL250 3 2 130 49 None (3, 50) (0, 0) (133, 53) 3 2 194 49 None (3, 50) (0, 0) (197, 53) A3P400 A3P600/L AGL600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) A3P1000/L AGL1000 3 4 258 99 (3, 2) (3, 100) (0, 0) (261, 103) A3PE600 AGLE600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) 3 4 322 123 (3, 2) (3, 124) (0, 0) (325, 127) 3 6 450 173 (3, 2) or (3, 4) (3, 174) or (3, 176) (0, 0) (453, 179) A3PE1500 A3PE3000/L Table 1-3 * AGLE3000 IGLOO PLUS Array Coordinates VersaTiles Device 1 -6 Memory Rows Min. Memory Rows Max. Entire Die Bottom Top Min. Max. IGLOO PLUS x y x y (x, y) (x, y) (x, y) (x, y) AGLP030 2 3 67 13 None None (0, 0) (69, 15) AGLP060 2 2 67 25 None (3, 26) (0, 0) (69, 29) AGLP125 2 2 131 25 None (3, 26) (0, 0) (133, 29) v1.1 Core Architecture of IGLOO and ProASIC3 Devices Top Row (7, 79) to (189, 79) Bottom Row (5, 78) to (192, 78) (0, 79) I/O Tile (197, 79) Memory (3, 77) Blocks (3, 76) (194, 77) Memory (194, 76) Blocks VersaTile (Core) (3, 75) (194, 75) VersaTile (Core) (194, 4) VersaTile (Core) VersaTile (Core) (3, 4) (194, 3) Memory (194, 2) Blocks Memory (3, 3) Blocks (3, 2) (197, 1) (0, 0) I/O Tile UJTAG FlashROM Top Row (5, 1) to (168, 1) Bottom Row (7, 0) to (165, 0) (197, 0) Top Row (169, 1) to (192, 1) Note: The vertical I/O tile coordinates are not shown. West-side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east-side coordinates are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}. Figure 1-6 * Array Coordinates for AGL600, AGLE600, A3P600, and A3PE600 v1.1 1-7 Core Architecture of IGLOO and ProASIC3 Devices Routing Architecture The routing structure of low-power flash devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast local resources; efficient long-line resources; high-speed, very-long-line resources; and the high-performance VersaNet networks. The ultra-fast local resources are dedicated lines that allow the output of each VersaTile to connect directly to every input of the eight surrounding VersaTiles (Figure 1-7 on page 1-8). The exception to this is that the SET/CLR input of a VersaTile configured as a D-flip-flop is driven only by the VersaTile global network. The efficient long-line resources provide routing for longer distances and higher-fanout connections. These resources vary in length (spanning one, two, or four VersaTiles), run both vertically and horizontally, and cover the entire device (Figure 1-8 on page 1-9). Each VersaTile can drive signals onto the efficient long-line resources, which can access every input of every VersaTile. Routing software automatically inserts active buffers to limit loading effects. The high-speed, very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: length 12 VersaTiles in the vertical direction and length 16 in the horizontal direction from a given core VersaTile (Figure 1-9 on page 1-9). Very long lines in low-power flash devices have been enhanced over those in previous ProASIC families. This provides a significant performance boost for long-reach signals. The high-performance VersaNet global networks are low-skew, high-fanout nets that are accessible from external pins or internal logic. These nets are typically used to distribute clocks, resets, and other high-fanout nets requiring minimum skew. The VersaNet networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically, with signals accessing every input of every VersaTile. For more details on VersaNets, refer to Global Resources in Actel Low-Power Flash Devices. Long Lines L Inputs L L L Ultra-Fast Local Lines (connects a VersaTile to the adjacent VersaTile, I/O buffer, or memory block) Output L L L L L Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection. Figure 1-7 * Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors 1 -8 v1.1 Core Architecture of IGLOO and ProASIC3 Devices Spans 4 VersaTiles Spans 1 VersaTile Spans 2 VersaTiles VersaTile L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L Spans 1 VersaTile Spans 2 VersaTiles Spans 4 VersaTiles Figure 1-8 * Efficient Long-Line Resources High-Speed, Very-Long-Line Resources Pad Ring SRAM I/O Ring Pad Ring I/O Ring 16x12 Block of VersaTiles Pad Ring Figure 1-9 * Very-Long-Line Resources v1.1 1-9 Core Architecture of IGLOO and ProASIC3 Devices Related Documents Handbook Documents Global Resources in Actel Low-Power Flash Devices http://www.actel.com/documents/LPD_Glorbal_HBs.pdf User's Guides Designer User's Guide http://www.actel.com/documents/designer_ug.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet. To improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage information. No technical changes were made to the content unless explicitly listed. Part Number 51700094-002-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) 1 -1 0 Changes in Current Version (v1.1) Page Table 1-1 * Low-Power Flash Families and the accompanying text was updated to include the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 1-2 The "Device Overview" section was updated to note that 15 k devices do not support SRAM or FIFO. 1-3 Figure 1-3 * IGLOO PLUS Device Architecture Overview with Four I/O Banks is new. 1-4 Table 1-2 * IGLOO and ProASIC3 Array Coordinates was updated to add A3P015 and AGL015. 1-6 Table 1-3 * IGLOO PLUS Array Coordinates is new. 1-6 v1.1 Low-Power Modes in Actel ProASIC3/E FPGAs 2 - Low-Power Modes in Actel ProASIC3/E FPGAs Introduction The demand for low-power systems and semiconductors, combined with the strong growth observed for value-based FPGAs, is driving growing demand for low-power FPGAs. For portable and battery-operated applications, power consumption has always been the greatest challenge. The battery life of a system and on-board devices has a direct impact on the success of the product. As a result, FPGAs used in these applications should meet low-power consumption requirements. Actel ProASIC(R)3/E FPGAs offer low power consumption capability inherited from their nonvolatile and live-at-power-up (LAPU) flash technology. This application note describes the power consumption and how to use different power saving modes to further reduce power consumption for power-conscious electronics design. Power Consumption Overview In evaluating the power consumption of FPGA technologies, it is important to consider it from a system point of view. Generally, the overall power consumption should be based on static, dynamic, inrush, and configuration power. Few FPGAs implement ways to reduce static power consumption utilizing sleep modes. SRAM-based FPGAs use volatile memory for their configuration, so the device must be reconfigured after each power-up cycle. Moreover, during this initialization state, the logic could be in an indeterminate state, which might cause inrush current and power spikes. More complex power supplies are required to eliminate potential system power-up failures, resulting in higher costs. For portable electronics requiring frequent power-up and -down cycles, this directly affects battery life, requiring more frequent recharging or replacement. SRAM-Based FPGA Total Power Consumption = Pstatic + Pdynamic + Pinrush + Pconfig EQ 2-1 ProASIC3/E Total Power Consumption = Pstatic + Pdynamic EQ 2-2 Unlike SRAM-based FPGAs, Actel flash-based FPGAs are nonvolatile and do not require power-up configuration. Additionally, Actel nonvolatile flash FPGAs are live at power-up and do not require additional support components. Total power consumption is reduced as the inrush current and configuration power components are eliminated. Note that the static power component can be reduced in flash FPGAs (such as the ProASIC3/E devices) by entering User Low Static mode or Sleep mode. This leads to an extremely low static power component contribution to the total system power consumption. The following sections describe the usage of Static (Idle) mode to reduce the power component, User Low Static mode to reduce the static power component, and Sleep mode and Shutdown mode to achieve a range of power consumption when the FPGA or system is idle. Table 2-1 on page 2-2 summarizes the different low-power modes offered by ProASIC3/E devices. v1.1 2-1 Low-Power Modes in Actel ProASIC3/E FPGAs Table 2-1 * ProASIC3/E Low-Power Modes Summary Mode Active Power Supplies / Clock Status On - All, clock Needed to Start Up N/A (already active) Off - None Static (Idle) On - All Initiate clock source. Off - No active clock in FPGA No need contents. to initialize volatile Optional: Enter User Low Static (Idle) Mode by enabling ULSICC macro to further reduce power consumption by powering down FlashROM. Sleep On - VCCI Need to turn on core. Off - VCC core voltage Load states from external memory. LAPU enables immediate operation when power returns. As needed, restore volatile contents from external memory. Optional: Save state of volatile contents in external memory. Shutdown On - None Need to turn on VCC, VCCI. Off - All power supplies Applicable to PA3E and A3P030; cold-sparing and hotinsertion allow the device to be powered down without bringing down the system. LAPU enables immediate operation when power returns. Static (Idle) Mode In Static (Idle) mode, the clock inputs are not switching and the static power consumption is the minimum power required to keep the device powered up. In this mode, I/Os are only drawing the minimum leakage current specified in the datasheet. Also, in Static (Idle) mode, embedded SRAM, I/Os, and registers retain their values, so the device can enter and exit this mode without any penalty. If the embedded PLLs are used as the clock source, Static (Idle) mode can be entered easily by pulling LOW the PLL POWERDOWN pin (active-low). By pulling the PLL POWERDOWN pin to LOW, the PLL is turned off. Refer to Figure 2-1 on page 2-3 for more information. 2 -2 v1.1 Low-Power Modes in Actel ProASIC3/E FPGAs CLKA POWERDOWN GLA GLB YB GLC YC LOCK OADIV[4:0]* OAMUX[2:0]* DLYGLA[4:0]* OBDIV[4:0]* OBMUX[2:0]* DLYYB[4:0]* DLYGLB[4:0]* OCDIV[4:0]* OCMUX[2:0]* DLYYC[4:0]* DLYGLC[4:0]* FINDIV[6:0]* FBDIV[6:0]* FBDLY[4:0]* FBSEL[1:0]* XDLYSEL* VCOSEL[2:0]* Figure 2-1 * CCC/PLL Macro User Low Static (Idle) Mode User Low Static (Idle) mode is an advanced feature supported by ProASIC3/E devices to reduce static (idle) power consumption. Entering and exiting this mode is made possible using the ULSICC macro by setting its value to disable/enable the User Low Static (Idle) mode. Under typical operating conditions, characterization results show up to 25% reduction of the static (idle) power consumption. The greatest power savings in terms of percentage are seen in the smaller members of the ProASIC3 family. The active-high control signal for User Low Static (Idle) mode can be generated by internal or external logic. When the device is operating in User Low Static (Idle) mode, FlashROM functionality is temporarily disabled to save power. If FlashROM functionality is needed, the device can exit User Low Static mode temporarily and re-enter the mode once the functionality is no longer needed. To utilize User Low Static (Idle) mode, simply instantiate the ULSICC macro (Table 2-2 on page 2-4) in your design, and connect the input port to either an internal logic signal or a device package pin, as illustrated in Figure 2-2 on page 2-4 or Figure 2-3 on page 2-5, respectively. The attribute is used so the Synplify(R) synthesis tool will not optimize the instance with no output port. This mode can be used to lower standard static (idle) power consumption when the FlashROM feature is not needed. Configuring the device to enter User Low Static (Idle) mode is beneficial when the FPGA enters and exits static mode frequently and lowering power consumption as much as possible is desired. The device is still functional, and data is retained in this state so the device can enter and exit this mode quickly, resulting in reduced total power consumption. The device can also stay in User Low Static mode when the FlashROM feature is not used in the device. v1.1 2-3 Low-Power Modes in Actel ProASIC3/E FPGAs Table 2-2 * Using ULSICC Macro* VHDL COMPONENT ULSICC port ( LSICC END COMPONENT; Verilog : in module ULSICC(LSICC); input LSICC; STD_ULOGIC); endmodule Example: Example: COMPONENT ULSICC port ( LSICC END COMPONENT; ULSICC U1(.LSICC(myInputSignal)) /* synthesis syn_noprune=1 */; : in STD_ULOGIC); attribute syn_noprune : boolean; attribute syn_noprune of u1 : label is true; u1: ULSICC port map(myInputSignal); * Supported in Libero IDE v7.2 and newer versions. ProASIC3/E Device Internal Signal Programming Circuitry ULSICC Macro FlashROM Figure 2-2 * User Low Static (Idle) Mode Application--Internal Control Signal 2 -4 v1.1 Low-Power Modes in Actel ProASIC3/E FPGAs ProASIC3/E Device External Signal Programming Circuitry ULSICC Macro FlashROM Any User's I/O Figure 2-3 * User Low Static (Idle) Mode Application--External Control Signal Normal Operation User Low Static Mode Normal Operation ULSICC Signal 1 s 1 s Figure 2-4 * User Low Static (Idle) Mode Timing Diagram Sleep Mode Actel ProASIC3/E FPGAs support Sleep mode when device functionality is not required. In Sleep mode, the VCC (FPGA core voltage) supply is turned off, either grounded or left floating, resulting in the FPGA core being turned off to reduce power consumption. While the ProASIC3/E device is in Sleep mode, the rest of the system is still operating and driving the input buffers of the ProASIC3/E device. The driven inputs do not pull up power planes, and the current draw is limited to a minimal leakage current. Table 2-3 shows the status of the power supplies in Sleep mode. When a power supply is powered off, the corresponding power pin can be left floating or grounded. Table 2-3 * Sleep Mode--Power Supply Requirements for ProASIC3/E Devices Power Supplies ProASIC3/E VCC Powered off VCCI = VMV Powered on VJTAG Powered on VPUMP Powered on v1.1 2-5 Low-Power Modes in Actel ProASIC3/E FPGAs Table 2-4 shows the current draw in Sleep mode for an A3P250 device with the following test conditions: VCCI = VMV; VCC = floating or GND; VJTAG = floating or GND; VPUMP = floating or GND. Table 2-4 * A3P250 Current Draw in Sleep Mode A3P250 Typical Conditions ICCI (A) ICCI (A) per Bank VCCI = 3.3 V 31.57 7.89 VCCI = 2.5 V 23.96 5.99 VCCI = 1.8 V 17.32 4.33 VCCI = 1.5 V 14.46 3.62 ICC FPGA Core 0.0 0.0 Leakage Current per I/O 0.1 0.1 VPUMP 0.0 0.0 Note: The data in this table were taken under typical conditions and are based on characterization. The data is not guaranteed. Table 2-5 shows the current draw in Sleep mode for an A3PE600 device with the following test conditions: VCCI = VMV; VCC = floating or GND; VJTAG = floating or GND; VPUMP = floating or GND. Table 2-5 * A3PE600 Current Draw in Sleep Mode A3PE600 Typical Conditions ICCI (A) ICCI (A) per Bank VCCI = 3.3 V 59.85 7.48 VCCI = 2.5 V 45.50 5.69 VCCI = 1.8 V 32.98 4.12 VCCI = 1.5 V 27.66 3.46 VCCI = 0 V or Floating 0.0 0.0 ICC FPGA Core 0.0 0.0 Leakage Current per I/O 0.1 0.1 IPUMP 0.0 0.0 Note: The data in this table were taken under typical conditions and are based on characterization. The data is not guaranteed. ProASIC3/E devices were designed such that before device power-up, all I/Os are in tristate mode. The I/Os will remain tristated during power-up until the last voltage supply (VCC or VCCI) is powered to its functional level. After the last supply reaches the functional level, the outputs will exit the tristate mode and drive the logic at the input of the output buffer. The behavior of user I/Os is independent of the VCC and VCCI sequence or the state of other FPGA voltage supplies (VPUMP and VJTAG). During power-down, device I/Os become tristated once the first power supply (VCC or VCCI) drops below its brownout voltage level. The I/O behavior during power-down is also independent of voltage supply sequencing. Figure 2-5 on page 2-7 shows a timing diagram for the FPGA core entering the activation and deactivation trip points for a typical application when the VCC power supply ramp rate is 100 s (ramping from 0 V to 1.5 V). This is, in fact, the timing diagram for the FPGA entering and exiting Sleep mode, as it is dependent on powering down or powering up VCC. Depending on the ramp rate of the power supply and board-level configurations, the user can easily calculate how long it takes for the core to become active or inactive. For more information, refer to the Power-Up/-Down Behavior of ProASIC3/E Devices application note. 2 -6 v1.1 Low-Power Modes in Actel ProASIC3/E FPGAs VCC Deactivation Trip Point Vd = 0.75 0.25 V VCC = 1.5 V Activation Trip Point Va = 0.85 0.25 V t Sleep Mode Figure 2-5 * Entering and Exiting Sleep Mode--Typical Timing Diagram Shutdown Mode For ProASIC3E and A3P030, shutdown mode can be entered by turning off all power supplies when device functionality is not needed. Cold-sparing and hot-insertion features enable the device to be powered down without turning off the entire system. When power returns, the live at power-up feature enables immediate operation of the device. Using Sleep Mode or Shutdown Mode in the System Depending on the power supply and components used in an application, there are many ways to turn the power supplies connected to the device on or off. For example, Figure 2-6 shows how a microprocessor is used to control a power FET. It is recommended that power FETs with low on resistance be used to perform the switching action. 1.5 V Power Supply P-Channel Power FET Microprocessor Power On/Off Control Signal VCC Pin ProASIC3/E Figure 2-6 * Controlling Power On/Off State Using Microprocessor and Power FET v1.1 2-7 Low-Power Modes in Actel ProASIC3/E FPGAs Alternatively, Figure 2-7 shows how a microprocessor can be used with a voltage regulator's shutdown pin to turn the power supplies connected to the device on or off. Microprocessor Showdown Control Signal for VCCI Showdown Control Signal for VCC VCC Power Pin Power Supply ProASIC3/E Voltage Regulator VCC Power Pin Figure 2-7 * Controlling Power On/Off State Using Microprocessor and Voltage Regulator Though Sleep mode or Shutdown mode can be used to save power, the content of the SRAM and the state of the registers is lost when power is turned off if no other measure is taken. To keep the original contents of the device, a low-cost external serial EEPROM can be used to save and restore the device contents when entering and exiting Sleep mode. In the Embedded SRAM Initialization Using External Serial EEPROM application note, detailed information and a reference design are provided to initialize the embedded SRAM using an external serial EEPROM. The user can easily customize the reference design to save and restore the FPGA state when entering and exiting Sleep mode. The microcontroller will need to manage this activity, so before powering down VCC, the data must be read from the FPGA and stored externally. Similarly, after the FPGA is powered up, the microcontroller must allow the FPGA to load the data from external memory and restore its original state. Conclusion Actel ProASIC3/E FPGAs inherit low-power consumption capability from their nonvolatile and liveat-power-up flash-based technology. Power consumption can be reduced further using the Static (Idle), User Low Static (Idle), Sleep, or Shutdown power modes. All these features result in a low-power, cost-effective, single-chip solution designed specifically for power-sensitive electronics applications. 2 -8 v1.1 Low-Power Modes in Actel ProASIC3/E FPGAs Related Documents Application Notes Power-Up/Down Behavior of ProASIC3/E Devices http://www.actel.com/documents/ProASIC3_E_PowerUp_HBs.pdf Embedded SRAM Initialization Using External Serial EEPROM http://www.actel.com/documents/EmbeddedSRAMInit_AN.pdf Handbook Documents SRAM and FIFO Memories in Actel's in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_SRAMFIFO_HBs.pdf Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content Part Number 51700094-003-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.1) Page v1.0 (January 2008) The part number for this document was changed from 51700094-002-0 to 51700094-003-1. N/A 51900138-2/10.06 The Power Supplies / Clock Status description was updated for Static (Idle) in Table 2-1 * ProASIC3/E Low-Power Modes Summary. 2-2 Programming information was updated in the "User Low Static (Idle) Mode" section. 2-3 The "User Low Static (Idle) Mode" section was updated to include information about allowing programming in the ULSICC mode. 2-3 Figure 2-2 * User Low Static (Idle) Mode Application--Internal Control Signal was updated. 2-4 Figure 2-3 * User Low Static (Idle) Mode Application--External Control Signal was updated. 2-5 In Table 2-4 * A3P250 Current Draw in Sleep Mode, "VCCI = 1.5 V" was changed from 3.6158 to 3.62. 2-6 In Table 2-5 * A3PE600 Current Draw in Sleep Mode, "VCCI = 2.5 V" was changed from 5.6875 to 3.69. 2-6 51900138-1/6.06 51900138-0/6.05 v1.1 2-9 Global Resources and Clock Conditioning Global Resources in Actel Low-Power Flash Devices 3 - Global Resources in Actel Low-Power Flash Devices Introduction Actel IGLOO,(R) Fusion, and ProASIC(R)3 FPGA devices offer a powerful, low-delay VersaNet global network scheme and have extensive support for multiple clock domains. In addition to the Clock Conditioning Circuits (CCCs) and phase-locked loops (PLLs), there is a comprehensive global clock distribution network called a VersaNet global network. Each logical element (VersaTile) input and output port has access to these global networks. The VersaNet global networks can be used to distribute low-skew clock signals or high-fanout nets. In addition, these highly segmented VersaNet global networks offer users the flexibility to create low-skew local networks using spines. This document describes VersaNet global networks and discusses how to assign signals to these global networks and spines in a design flow. Details concerning low-power flash device PLLs are described in Clock Conditioning Circuits in IGLOO and ProASIC3 Devices. This document describes the low-power flash devices' global architecture and uses of these global networks in designs. Global Architecture Low-power flash devices offer powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has up to six CCCs, some with PLLs. * In IGLOOe, ProASIC3EL, and ProASIC3E devices, all CCCs have PLLs--hence, 6 PLLs per device. * In IGLOO, IGLOO PLUS, ProASIC3L, and ProASIC3 devices, the west CCC contains a PLL core (except in 15 k and 30 k devices). Each PLL includes delay lines, a phase shifter (0, 90, 180, 270), and clock multipliers/dividers. Each CCC has all the circuitry needed for the selection and interconnection of inputs to the VersaNet global network. The east and west CCCs each have access to three VersaNet global lines on each side of the chip (six global lines total). The CCCs at the four corners each have access to three quadrant global lines in each quadrant of the chip (except in 15 k gate and 30 k gate devices). In 15 k and 30 k gate devices, all six VersaNet global lines are driven from three southern I/Os, located toward the east and west sides. Each of these tiles can be configured to select a central I/O on its respective side or an internal routed signal as the input signal. 15 k and 30 k gate devices do not support any clock conditioning circuitry, nor do they contain the VersaNet global network concept of top and bottom spines. The flexible use of the VersaNet global network allows the designer to address several design requirements. User applications that are clock-resource-intensive can easily route external or gated internal clocks using VersaNet global routing networks. Designers can also drastically reduce delay penalties and minimize resource usage by mapping critical, high-fanout nets to the VersaNet global network. The following sections give an overview of the VersaNet global network, the structure of the global network, and the clock aggregation feature that enables a design to have very low clock skew using spines. v1.1 3-1 Global Resources in Actel Low-Power Flash Devices Global Resource Support in Low-Power Devices The low-power flash families listed in Table 3-1 support the global resources and the functions described in this document. Table 3-1 * Low-Power Flash Families Family1 Timing Numbers2 Description IGLOO Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*FreezeTM IGLOO DC and Switching technology Characteristics IGLOO PLUS Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO PLUS DC and technology and enhanced I/O capabilities Switching Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional PLLs, IGLOOe DC and Switching and additional I/O standards Characteristics ProASIC3L Low-power, high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and Switching technology Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, and ProASIC3E DC and Switching additional I/O standards Characteristics ProASIC3 Automotive Low-power, high-performance FPGAs qualified for Automotive Automotive ProASIC3 DC and applications Switching Characteristics Fusion Low-power mixed-signal Programmable System Chip (PSC) ProASIC3 DC and Switching Characteristics Fusion DC and Power Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 3-1) provide a selection of low-power, secure, live-atpower-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. The Actel Fusion(R) family, based on the highly successful ProASIC3 flash FPGA architecture, has been designed as a high-performance, mixed-signal Programmable System Chip. Fusion supports many peripherals, including embedded flash memory, analog-to-digital converter (ADC), high-drive outputs, RC and crystal oscillators, and real-time counter (RTC). The total available on-chip memory, including the flash array blocks, is greater than that found in SRAM FPGAs. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 3-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 3-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 3 -2 v1.1 Global Resources in Actel Low-Power Flash Devices VersaNet Global Network Distribution One of the architectural benefits of low-power flash architecture is the set of powerful, low-delay VersaNet global networks that can access the VersaTiles, SRAM, and I/O tiles of the device. Each device offers a chip global network with six global lines that are distributed from the center of the FPGA array. In addition, each device, (except the 15 k and 30 k gate device), has four quadrant global networks, each with three regional global line resources. These quadrant global networks can only drive a signal inside their own quadrant. Each core VersaTile has access to nine global line resources--three quadrant and six chip-wide (main) global networks--and a total of 18 globals are available on the device (3 x 4 regional from each quadrant and 6 global). Figure 3-1 shows simplified device architecture, and Figure 3-2 on page 3-4 shows an overview of the VersaNet global networks. The VersaNet global networks are segmented and consist of VersaNet global networks, spines, global ribs, and global multiplexers (MUXes), as shown in Figure 3-1. The global networks are driven from the global rib at the center of the die or quadrant global networks at the north or south side of the die. The global network uses the MUX trees to access the spine, and the spine uses the clock ribs to access the VersaTile. Access is available to the chip or quadrant global networks and the spines through the global MUXes. Access to the spine using the global MUXes is explained in the "Spine Architecture" section on page 3-4. These VersaNet global networks offer fast, low-skew routing resources for high-fanout nets, including clock signals. In addition, these highly segmented global networks offer users the flexibility to create low-skew local networks using spines for up to 252 internal/external clocks or other high-fanout nets in low-power flash devices. Optimal usage of these low-skew networks can result in significant improvement in design performance. Quadrant Global Pads T1 T2 High-Performance Global Network T3 I/ORing Pad Ring Pad Ring Top Spine Global Pads Chip (main) Global Pads Global Spine Global Ribs I/O Ring Bottom Spine Scope of Spine (shaded area plus local RAMs and I/Os) Spine-Selection MUX Embedded RAM Blocks Pad Ring B1 B2 B3 Logic Tiles Note: Not applicable to 15 k and 30 k gate devices Figure 3-1 * Overview of VersaNet Global Network and Device Architecture v1.1 3-3 Global Resources in Actel Low-Power Flash Devices North Quadrant Global Network Quadrant Global Spine CCC CCC 3 3 3 3 Chip (main) Global Network 6 6 3 6 6 3 CCC 6 Global Spine 6 3 CCC 3 6 3 South Quadrant Global Network CCC 6 3 CCC Note: Not applicable to 15 k and 30 k gate devices. Figure 3-2 * Simplified VersaNet Global Network Spine Architecture The low-power flash device architecture allows the VersaNet global networks to be segmented. Each of these networks contains spines (the vertical branches of the global network tree) and ribs that can reach all the VersaTiles inside its region. The nine spines available in a vertical column reside in global networks with two separate regions of scope: the quadrant global network, which has three spines, and the chip (main) global network, which has six spines. Note that there are three quadrant spines in each quadrant of the device (except in 15 k and 30 k gate devices). There are four quadrant global network regions per device. In 15 k and 30 k gate devices, there is no quadrant clock network, so there are only six spines in each spine tree. The spines are the vertical branches of the global network tree, shown in Figure 3-2. Each spine in a vertical column of a chip (main) global network is further divided into two equallength spine segments: one in the top and one in the bottom half of the die (except in 15 k and 30 k gate devices). Top and bottom spine segments radiating from the center of a device have the same height. However, just as in the ProASICPLUS(R) family, signals assigned only to the top and bottom spine cannot access the middle two rows of the die. The spines for quadrant clock networks do not cross the middle of the die and cannot access the middle two rows of the architecture. Each spine and its associated ribs cover a certain area of the device (the "scope" of the spine; see Figure 3-2). Each spine is accessed by the dedicated global network MUX tree architecture, which defines how a particular spine is driven--either by the signal on the global network from a CCC, for example, or by another net defined by the user. Details of the chip (main) global network spineselection MUX are presented in Figure 3-4 on page 3-7. The spine drivers for each spine are located in the middle of the die. Quadrant spines can be driven from user I/Os on the north and south sides of the die. The ability to drive spines in the quadrant global networks can have a significant effect on system performance for high-fanout inputs to a design. Access to the top quadrant spine regions is from the top of the die, and access to the bottom quadrant spine regions is from the bottom of the die. The A3PE3000 device has 28 clock trees and each tree has nine spines; this flexible global network architecture enables users to map up to 252 different internal/external clocks in an A3PE3000 device. 3 -4 v1.1 Global Resources in Actel Low-Power Flash Devices Table 3-2 * Globals/Spines/Rows for IGLOO and ProASIC3 Devices Quadrant Chip Globals Clock Globals (4x3) Trees Globals/ Total Rows Spines Spines VersaTiles Total in per per in Each VersaTile Each Tree Device Tree s Spine ProASIC3/ ProASIC3L Devices IGLOO Devices A3P015 AGL015 6 0 1 9 9 384 384 12 A3P030 AGL030 6 0 2 9 18 384 768 12 A3P060 AGL060 6 12 4 9 36 384 1,536 12 A3P125 AGL125 6 12 8 9 72 384 3,072 12 A3P250/L AGL250 6 12 8 9 72 768 6,144 24 6 12 12 9 108 768 9,216 24 A3P400 A3P600/L AGL600 6 12 12 9 108 1,152 13,824 36 A3P1000/L AGL1000 6 12 16 9 144 1,536 24,576 48 A3PE600 AGLE600 6 12 12 9 108 1,120 13,440 35 6 12 20 9 180 1,888 37,760 59 6 12 28 9 252 2,656 74,368 83 A3PE1500 A3PE3000/L Table 3-3 * AGLE3000 Globals/Spines/Rows for IGLOO PLUS Devices IGLOO PLUS Chip Devices Globals Quadrant Globals Clock (4x3) Trees Globals/ Total Spines Spines VersaTiles per Tree per Device in Each Tree Rows Total in Each VersaTiles Spine AGLP030 6 0 2 9 18 384* 792 12 AGLP060 6 12 4 9 36 384* 1,584 12 AGLP125 6 12 8 9 72 384* 3,120 12 Note: *Clock trees that are located at far left and far right will support more VersaTiles. Table 3-4 * Globals/Spines/Rows for Fusion Devices Clock Trees Globals/ Spines per Tree Total Spines per Device VersaTiles in Each Tree Total VersaTiles Rows in Each Spine Fusion Device Chip Globals Quadrant Globals (4x3) AFS090 6 12 6 9 54 384 2,304 12 AFS250 6 12 8 9 72 768 6,144 24 AFS600 6 12 12 9 108 1,152 13,824 36 AFS1500 6 12 20 9 180 1,920 38,400 60 Spine Access The physical location of each spine is identified by the letter 'T' (top) or 'B' (bottom) and an accompanying number (Tn or Bn). The number n indicates the horizontal location of the spine; 1 refers to the first spine on the left side of the die. Since there are six chip spines in each spine tree, there are up to six spines available for each combination of 'T' (or 'B') and n (for example, six T1 spines). Similarly, there are three quadrant spines available for each combination of 'T' (or 'B') and n (for example, four T1 spines), as shown in Figure 3-3 on page 3-6. v1.1 3-5 Global Resources in Actel Low-Power Flash Devices A B Global Network C Tn Tn+1 Tn+2 Tn+3 Tn+4 Figure 3-3 * Chip Global Aggregation Spines are also called local clocks, and are accessed by the dedicated global MUX architecture. These MUXes define how a particular spine is driven. Refer to Figure 3-4 on page 3-7 for the global MUX architecture. The MUXes for each chip global spine are located in the middle of the die. Access to the top and bottom chip global spine is available from the middle of the die. There is no control dependency between the top and bottom spines. If a top spine, T1, of a chip global network is assigned to a net, B1 is not wasted and can be used by the global clock network. The signal assigned only to the top or bottom spine cannot access the middle two rows of the architecture. However, if a spine is using the top and bottom at the same time (T1 and B1, for instance), the previous restriction is lifted. The MUXes for each quadrant global spine are located in the north and south sides of the die. Access to the top and bottom quadrant global spines is available from the north and south sides of the die. Since the MUXes for quadrant spines are located in the north and south sides of the die, you should not try to drive T1 and B1 quadrant spines from the same signal. 3 -6 v1.1 Global Resources in Actel Low-Power Flash Devices Using Clock Aggregation Clock aggregation allows for multi-spine clock domains to be assigned using hardwired connections, without adding any extra skew. A MUX tree, shown in Figure 3-4, provides the necessary flexibility to allow long lines, local resources, or I/Os to access domains of one, two, or four global spines. Signal access to the clock aggregation system is achieved through long-line resources in the central rib in the center of the die, and also through local resources in the north and south ribs, allowing I/Os to feed directly into the clock system. As Figure 3-5 indicates, this access system is contiguous. There is no break in the middle of the chip for the north and south I/O VersaNet access. This is different from the quadrant clocks located in these ribs, which only reach the middle of the rib. Internal/External Signals Internal/External Signals Tree Node MUX Tree Node MUX Internal/External Signal Tree Node MUX Global Rib Internal/External Signal Global Driver MUX Spine Figure 3-4 * Spine Selection MUX of Global Tree Global Spine Global Rib Global Driver and MUX Tree Node MUX I/O Access Internal Signal Access Global Signal Access I/O Tiles Figure 3-5 * Clock Aggregation Tree Architecture v1.1 3-7 Global Resources in Actel Low-Power Flash Devices Clock Aggregation Architecture This clock aggregation feature allows a balanced clock tree, which improves clock skew. The physical regions for clock aggregation are defined from left to right and shift by one spine. For chip global networks, there are three types of clock aggregation available, as shown in Figure 3-6: * Long lines that can drive up to four adjacent spines * Long lines that can drive up to two adjacent spines * Long lines that can drive one spine There are three types of clock aggregation available for the quadrant spines, as shown in Figure 3-6: * I/Os or local resources that can drive up to four adjacent spines * I/Os or local resources that can drive up to two adjacent spines * I/Os or local resources that can drive one spine * As an example, A3PE600 and AFS600 devices have twelve spine locations: T1, T2, T3, T4, T5, T6, B1, B2, B3, B4, B5, and B6. Table 3-5 shows the clock aggregation you can have in A3PE600 and AFS600. A B C Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Figure 3-6 * Four Spines Aggregation Table 3-5 * Spine Aggregation in A3PE600 or AFS600 Clock Aggregation Spine 1 spine T1, T2, T3, T4, T5, T6, B1, B2, B3, B4, B5, B6 2 spines T1:T2, T2:T3, T3:T4, T4:T5, T5:T6, B1:B2, B2:B3, B3:B4, B4:B5, B5:B6 4 spines B1:B4, B2:B5, B3:B6, T1:T4, T2:T5, T3:T6 The clock aggregation for the quadrant spines can cross over from the left to right quadrant, but not from top to bottom. The quadrant spine assignment T1:T4 is legal, but the quadrant spine assignment T1:B1 is not legal. Note that this clock aggregation is hardwired. You can always assign signals to spine T1 and B2 by instantiating a buffer, but this may add skew in the signal. 3 -8 v1.1 Global Resources in Actel Low-Power Flash Devices I/O Banks and Global I/Os The following sections give an overview of naming conventions and other related I/O information. Naming of Global I/Os In low-power flash devices, the global I/Os have access to certain clock conditioning circuitry and have direct access to the global network. Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities to those of regular I/Os. Due to the comprehensive and flexible nature of the I/Os in low-power flash devices, a naming scheme is used to show the details of the I/O. The global I/O uses the generic name Gmn/IOuxwByVz. Refer to the I/O Structure section of the handbook for the device that you are using for more information on this naming convention. Figure 3-7 represents the global input pins connection to the northwest CCC or northwest quadrant global networks for a low-power flash device. Each global buffer, as well as the PLL reference clock, can be driven from one of the following: * 3 dedicated single-ended I/Os using a hardwired connection * 2 dedicated differential I/Os using a hardwired connection * The FPGA core Since each bank can have a different I/O standard, the user should be careful to choose the correct global I/O for the design. There are 54 global pins available to access 18 global networks. For the single-ended and voltage-referenced I/O standards, you can use any of these three available I/Os to access the global network. For differential I/O standards such as LVDS and LVPECL, the I/O macro needs to be placed on GAA0 and GAA1 or a similar location. The unassigned global I/Os can be used as regular I/Os. Note that pin names starting with GF and GC are associated with the chip global networks, and GA, GB, GD, and GE are used for quadrant global networks. Each shaded box represents an INBUF or INBUF_LVDS/LVPECL macro, as appropriate. To Core Sample Pin Names 1 GAA0/IO0NDB0V0 1 GAA1/IO00PDB0V0 + Source for CCC (CLKA or CLKB or CLKC) 1 GAA2/IO13PDB7V1 Routed Clock 2 (from FPGA core) + GAA[0:2]: GA represents global in the northwest corner of the device. A[0:2]: designates specific A clock source. Figure 3-7 * Global I/O Overview v1.1 3-9 Global Resources in Actel Low-Power Flash Devices Unused Global I/O Configuration The unused clock inputs behave similarly to the unused Pro I/Os. The Actel Designer software automatically configures the unused global pins as inputs with pull-up resistors if they are not used as regular I/O. I/O Banks and Global I/O Standards In low-power flash devices, any I/O or internal logic can be used to drive the global network. However, only the global macro placed at the global pins will use the hardwired connection between the I/O and global network. Global signal (signal driving a global macro) assignment to I/O banks is no different from regular I/O assignment to I/O banks with the exception that you are limited to the pin placement location available. Only global signals compatible with both the VCCI and VREF standards can be assigned to the same bank. Design Recommendations The following sections provide design flow recommendations for using a global network in a design. * "Global Macros and I/O Standards" * "Using Global Macros in Synplicity" on page 3-12 * "Global Promotion and Demotion Using PDC" on page 3-13 * "Spine Assignment" on page 3-14 * "Designer Flow for Global Assignment" on page 3-15 * "Simple Design Example" on page 3-17 * "Global Management in PLL Design" on page 3-19 * "Using Spines of Occupied Global Networks" on page 3-20 Global Macros and I/O Standards Low-power flash devices have six chip global networks and four quadrant clock networks. However, the same clock macros are used for assigning signals to chip globals and quadrant globals. Depending on the clock macro placement or assignment in the Physical Design Constraint (PDC) file or MultiView Navigator (MVN), the signal will use the chip global network or quadrant network. Table 3-6 on page 3-11 lists the clock macros available for low-power flash devices. Refer to the IGLOO, Fusion and ProASIC3 Macro Library Guide for details. 3 -1 0 v1.1 Global Resources in Actel Low-Power Flash Devices Table 3-6 * Clock Macros Macro Name Description CLKBUF Symbol Input macro for Clock Network CLKBUF Y PAD CLKBUF_x Input macro for Clock Network with specific I/O standard CLKBUF_LVDS/ LVPECL LVDS or LVPECL input macro for Clock Network CLKBUF_X Y PAD PADP PADP Y CLKBIBUF_LVDS PADN CLKINT CLKBIBUF_LVPECL Y PADN Internal clock interface A Y CLKINT CLKBIBUF Bidirectional macro with input dedicated to routed Clock Network D E Y PAD CLKBIBUF Use these available macros to assign a signal to the global network. In addition to these global macros, PLL and CLKDLY macros can also drive the global networks. Use I/O-standard-specific clock macros (CLKBUF_x) to instantiate a specific I/O standard for the global signals. Table 3-7 shows the list of these I/O-standard-specific macros. Note that if you use these I/O-standard-specific clock macros, you cannot change the I/O standard later in the design stage. If you use the regular CLKBUF macro, you can use MVN or the PDC file in Designer to change the I/O standard. The default I/O standard for CLKBUF is LVTTL in the current Actel Libero(R) Integrated Design Environment (IDE) and Designer software. Table 3-7 * I/O Standards within CLKBUF Name Description CLKBUF_LVCMOS5 LVCMOS clock buffer with 5.0 V CMOS voltage level CLKBUF_LVCMOS33 LVCMOS clock buffer with 3.3 V CMOS voltage level CLKBUF_LVCMOS25 LVCMOS clock buffer with 2.5 V CMOS voltage level1 CLKBUF_LVCMOS18 LVCMOS clock buffer with 1.8 V CMOS voltage level CLKBUF_LVCMOS15 LVCMOS clock buffer with 1.5 V CMOS voltage level CLKBUF_LVCMOS12 LVCMOS clock buffer with 1.2 V CMOS voltage level CLKBUF_PCI PCI clock buffer CLKBUF_PCIX PCIX clock buffer CLKBUF_GTL25 GTL clock buffer with 2.5 V CMOS voltage level1 CLKBUF_GTL33 GTL clock buffer with 3.3 V CMOS voltage level1 Notes: 1. Supported in only the IGLOOe and ProASIC3E devices 2. By default, the CLKBUF macro uses the 3.3 V LVTTL I/O technology. v1.1 3 - 11 Global Resources in Actel Low-Power Flash Devices Table 3-7 * I/O Standards within CLKBUF (continued) Name Description CLKBUF_GTLP25 GTL+ clock buffer with 2.5 V CMOS voltage level1 CLKBUF_GTLP33 GTL+ clock buffer with 3.3 V CMOS voltage level1 CLKBUF_ HSTL _I HSTL Class I clock buffer1 CLKBUF_ HSTL _II HSTL Class II clock buffer1 CLKBUF_SSTL2_I SSTL2 Class I clock buffer1 CLKBUF_SSTL2_II SSTL2 Class II clock buffer1 CLKBUF_SSTL3_I SSTL3 Class I clock buffer1 CLKBUF_SSTL3_II SSTL3 Class II clock buffer1 Notes: 1. Supported in only the IGLOOe and ProASIC3E devices 2. By default, the CLKBUF macro uses the 3.3 V LVTTL I/O technology. The current synthesis tool libraries only infer the CLKBUF or CLKINT macros in the netlist. All other global macros must be instantiated manually into your HDL code. The following is an example of CLKBUF_LVCMOS25 global macro instantiations that you can copy and paste into your code: VHDL component clkbuf_lvcmos25 port (pad : in std_logic; y : out std_logic); end component begin -- concurrent statements u2 : clkbuf_lvcmos25 port map (pad => end ext_clk, y => int_clk); Verilog module design (______); input _____; output ______; clkbuf_lvcmos25 u2 (.y(int_clk), .pad(ext_clk); endmodule Using Global Macros in Synplicity The Synplify(R) synthesis tool automatically inserts global buffers for nets with high fanout during synthesis. By default, Synplicity(R) puts six global macros (CLKBUF or CLKINT) in the netlist, including any global instantiation or PLL macro. Synplify always honors your global macro instantiation. If you have a PLL (only primary output is used) in the design, Synplify adds five more global buffers in the netlist. Synplify uses the following global counting rule to add global macros in the netlist: 1. CLKBUF: 1 global buffer 2. CLKINT: 1 global buffer 3. CLKDLY: 1 global buffer 4. PLL: 1 to 3 global buffers 3 -1 2 - GLA, GLB, GLC, YB, and YC are counted as 1 buffer. - GLB or YB is used or both are counted as 1 buffer. - GLC or YC is used or both are counted as 1 buffer. v1.1 Global Resources in Actel Low-Power Flash Devices CLKA EXTFB POWERDOWN OADIVRST GLA LOCK GLB YB GLC YC Note: OAVDIVRST exists only in the Fusion PLL. Figure 3-8 * PLLs in Low-Power Flash Devices You can use the syn_global_buffers attribute in Synplify to specify a maximum number of global macros to be inserted in the netlist. This can also be used to restrict the number of global buffers inserted. In the Synplicity 8.1 version, a new attribute, syn_global_minfanout, has been added for low-power flash devices. This enables you to promote only the high-fanout signal to global. However, be aware that you can only have six signals assigned to chip global networks, and the rest of the global signals should be assigned to quadrant global networks. So, if the netlist has 18 global macros, the remaining 12 global macros should have fanout that allows the instances driven by these globals to be placed inside a quadrant. Global Promotion and Demotion Using PDC The HDL source file or schematic is the preferred place for defining which signals should be assigned to a clock network using clock macro instantiation. This method is preferred because it is guaranteed to be honored by the synthesis tools and Designer software and stop any replication on this net by the synthesis tool. Note that a signal with fanout may have logic replication if it is not promoted to global during synthesis. In that case, the user cannot promote that signal to global using PDC. See Synplicity Help for details on using this attribute. To help you with global management, Designer allows you to promote a signal to a global network or demote a global macro to a regular macro from the user netlist using the compile options and/or PDC commands. The following are the PDC constraints you can use to promote a signal to a global network: 1. PDC syntax to promote a regular net to a chip global clock: assign_global_clock -net netname The following will happen during promotion of a regular signal to a global network: - If the net is external, the net will be driven by a CLKINT inserted automatically by Compile. - The I/O macro will not be changed to CLKBUF macros. - If the net is an internal net, the net will be driven by a CLKINT inserted automatically by Compile. 2. PDC syntax to promote a net to a quadrant clock: assign_local_clock -net netname -type quadrant UR|UL|LR|LL This follows the same rule as the chip global clock network. The following PDC command demotes the clock nets to regular nets. unassign_global_clock -net netname v1.1 3 - 13 Global Resources in Actel Low-Power Flash Devices The following will happen during demotion of a global signal to regular nets: * CLKBUF_x becomes INBUF_x; CLKINT is removed from the netlist. * The essential global macro, such as the output of the Clock Conditioning Circuit, cannot be demoted. * No automatic buffering will happen. Since no automatic buffering happens when a signal is demoted, this net may have a high delay due to large fanout. This may have a negative effect on the quality of the results. Actel recommends that the automatic global demotion only be used on small-fanout nets. Use clock networks for high-fanout nets to improve timing and routability. Spine Assignment The low-power flash device architecture allows the global networks to be segmented and used as clock spines. These spines, also called local clocks, enable the use of PDC or MVN to assign a signal to a spine. PDC syntax to promote a net to a spine/local clock: assign_local_clock -net netname -type [quadrant|chip] Tn|Bn|Tn:Bm If the net is driven by a clock macro, Designer automatically demotes the clock net to a regular net before it is assigned to a spine. Nets driven by a PLL or CLKDLY macro cannot be assigned to a local clock. When assigning a signal to a spine or quadrant global network using PDC (pre-compile), the Designer software will legalize the shared instances. The number of shared instances to be legalized can be controlled by compile options. If these networks are created in MVN (only quadrant globals can be created), no legalization is done (as it is post-compile). Designer does not do legalization between non-clock nets. As an example, consider two nets, net_clk and net_reset, driving the same flip-flop. The following PDC constraints are used: assign_local_clock -net net_clk -type chip T3 assign_local_clock -net net_reset -type chip T1:T2 During Compile, Designer adds a buffer in the reset net and places it in the T1 or T2 region, and places the flip-flop in the T3 spine region (Figure 3-9). After Compile Before Compile D net_clk D CLK CLK net_clk CLR net_reset CLR net_reset T1 T2 Added buffer T3 assign_local_clock -net net_clk -type chip T3 assign_local_clock -net net_reset -type chip T1:T2 Figure 3-9 * Adding a Buffer for Shared Instances 3 -1 4 v1.1 Global Resources in Actel Low-Power Flash Devices You can control the maximum number of shared instances allowed for the legalization to take place using the Compile Option dialog box shown in Figure 3-10. Refer to Libero IDE / Designer online help for details on the Compile Option dialog box. A large number of shared instances most likely indicates a floorplanning problem that you should address. Figure 3-10 * Shared Instances in the Compile Option Dialog Box Designer Flow for Global Assignment To achieve the desired result, pay special attention to global management during synthesis and place-and-route. The current Synplify tool does not insert more than six global buffers in the netlist by default. Thus, the default flow will not assign any signal to the quadrant global network. However, you can use attributes in Synplify and increase the default global macro assignment in the netlist. Designer v6.2 supports automatic quadrant global assignment, which was not available in Designer v6.1. Layout will make the choice to assign the correct signals to global. However, you can also utilize PDC and perform manual global assignment to overwrite any automatic assignment. The following step-by-step suggestions guide you in the layout of your design and help you improve timing in Designer: 1. Run Compile and check the Compile report. The Compile report has global information in the "Device Utilization" section that describes the number of chip and quadrant signals in the design. A "Net Report" section describes chip global nets, quadrant global nets, local clock nets, a list of nets listed by fanout, and net candidates for local clock assignment. Review this information. Note that YB or YC are counted as global only when they are used in isolation; if you use YB only and not GLB, this net is not shown in the global/quadrant nets report. Instead, it appears in the Global Utilization report. 2. If some signals have a very high fanout and are candidates for global promotion, promote those signals to global using the compile options or PDC commands. Figure 3-11 on page 3-16 shows the Globals Management section of the compile options. Select Promote regular nets whose fanout is greater than and enter a reasonable value for fanouts. v1.1 3 - 15 Global Resources in Actel Low-Power Flash Devices Figure 3-11 * Globals Management GUI in Designer 3. Occasionally, the synthesis tool assigns a global macro to clock nets, even though the fanout is significantly less than other asynchronous signals. Select Demote global nets whose fanout is less than and enter a reasonable value for fanouts. This frees up some global networks from the signals that have very low fanouts. This can also be done using PDC. 4. Use local clocks for the signals that do not need to go to the whole chip but should have low skew. This local clocks assignment can only be done using PDC. 5. Assign the I/O buffer using MVN if you have fixed I/O assignment. As shown in Figure 3-6 on page 3-8, there are three sets of global pins that have a hardwired connection to each global network. Do not try to put multiple CLKBUF macros in these three sets of global pins. For example, do not assign two CLKBUFs to GAA0x and GAA2x pins. 6. You must click Commit at the end of MVN assignment. This runs the pre-layout checker and checks the validity of global assignment. 7. Always run Compile with the Keep existing physical constraints option on. This uses the quadrant clock network assignment in the MVN assignment and checks if you have the desired signals on the global networks. 8. Run Layout and check the timing. 3 -1 6 v1.1 Global Resources in Actel Low-Power Flash Devices Simple Design Example Consider a design consisting of six building blocks (shift registers) and targeted for an A3PE600PQ208 (Figure 3-9 on page 3-14). The example design consists of two PLLs (PLL1 has GLA only; PLL2 has both GLA and GLB), a global reset (ACLR), an enable (EN_ALL), and three external clock domains (QCLK1, QCLK2, and QCLK3) driving the different blocks of the design. Note that the PQ208 package only has two PLLs (which access the chip global network). Because of fanout, the global reset and enable signals need to be assigned to the chip global resources. There is only one free chip global for the remaining global (QCLK1, QCLK2, QCLK3). Place two of these signals on the quadrant global resource. The design example demonstrates manually assignment of QCLK1 and QCLK2 to the quadrant global using the PDC command. PDOWN PLLZ_CLKA PLL2 POWER-DOWN CLKA reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock LOCK GLA GLB REG_PLLCLK2GLA_OUT REG_PLLCLK2GLA \$116 reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock DATA_QCLK1 QCLK1 REG_QCLK1_OUT REG_QCLK1 DATA_PLLCQCLK2 EN_ALL DATA_QCLK2 ACLR QCLK2 reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock REG_QCLK2 REG_QCLK2_OUT reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock REG_PLLCLK2GLB_OUT REG_PLLCLK2GLB reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock DATA_QCLK3 QCLK3 REG_QCLK3_OUT REG_QCLK3 DATA_PLLCLK1 PLL1_CLKA PLL1 POWER-DOWN CLKA \$115 reg256_behave Shhl_In Shhl_In Shhl_out Adr Clock LOCK GLA REG_PLLCLK1_OUT REG_PLLCLK1 Figure 3-12 * Block Diagram of the Global Management Example Design v1.1 3 - 17 Global Resources in Actel Low-Power Flash Devices Step 1 Run Synthesis with default options. The Synplicity log shows the following device utilization: Cell usage: cell count area count*area DFN1E1C1 1536 2.0 3072.0 BUFF 278 1.0 278.0 INBUF 10 0.0 0.0 VCC 9 0.0 0.0 GND 9 0.0 0.0 OUTBUF 6 0.0 0.0 CLKBUF 3 0.0 0.0 PLL 2 0.0 0.0 TOTAL 3350.0 1853 Step 2 Run Compile with the Promote regular nets whose fanout is greater than option selected in Designer; you will see the following in the Compile report: Device utilization report: ========================== CORE Used: 1536 Total: 13824 (11.11%) IO (W/ clocks) Used: 19 Total: 147 (12.93%) Differential IO Used: 0 Total: 65 (0.00%) GLOBAL Used: 8 Total: 18 (44.44%) PLL Used: 2 Total: 2 (100.00%) RAM/FIFO Used: 0 Total: 24 (0.00%) FlashROM Used: 0 Total: 1 (0.00%) ........................ The following nets have been assigned to a global resource: Fanout Type Name -------------------------1536 INT_NET Net : EN_ALL_c Driver: EN_ALL_pad_CLKINT Source: AUTO PROMOTED 1536 SET/RESET_NET Net : ACLR_c Driver: ACLR_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : QCLK1_c Driver: QCLK1_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : QCLK2_c Driver: QCLK2_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : QCLK3_c Driver: QCLK3_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : $1N14 Driver: $1I5/Core Source: ESSENTIAL 256 CLK_NET Net : $1N12 Driver: $1I6/Core Source: ESSENTIAL 256 CLK_NET Net : $1N10 Driver: $1I6/Core Source: ESSENTIAL Designer will promote five more signals to global due to high fanout. There are eight signals assigned to global networks. 3 -1 8 v1.1 Global Resources in Actel Low-Power Flash Devices During Layout, Designer will assign two of the signals to quadrant global locations. Step 3 (optional) You can also assign the QCLK1_c and QCLK2_c nets to quadrant regions using the following PDC commands: assign_local_clock -net QCLK1_c assign_local_clock -net QCLK2_c -type quadrant UL -type quadrant LL Step 4 Import this PDC with the netlist and run Compile again. You will see the following in the Compile report: The following nets have been assigned to a global resource: Fanout Type Name -------------------------1536 INT_NET Net : EN_ALL_c Driver: EN_ALL_pad_CLKINT Source: AUTO PROMOTED 1536 SET/RESET_NET Net : ACLR_c Driver: ACLR_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : QCLK3_c Driver: QCLK3_pad_CLKINT Source: AUTO PROMOTED 256 CLK_NET Net : $1N14 Driver: $1I5/Core Source: ESSENTIAL 256 CLK_NET Net : $1N12 Driver: $1I6/Core Source: ESSENTIAL 256 CLK_NET Net : $1N10 Driver: $1I6/Core Source: ESSENTIAL The following nets have been assigned to a quadrant clock resource using PDC: Fanout Type Name -------------------------256 CLK_NET Net : QCLK1_c Driver: QCLK1_pad_CLKINT Region: quadrant_UL 256 CLK_NET Net : QCLK2_c Driver: QCLK2_pad_CLKINT Region: quadrant_LL Step 5 Run Layout. Global Management in PLL Design This section describes the legal global network connections to PLLs in the low-power flash devices. For detailed information on using PLLs, refer to Clock Conditioning Circuits in IGLOO and ProASIC3 Devices. Actel recommends that you use the dedicated global pins to directly drive the reference clock input of the associated PLL for reduced propagation delays and clock distortion. However, low-power flash devices offer the flexibility to connect other signals to reference clock inputs. Each PLL is associated with three global networks (Figure 3-7 on page 3-9). There are some limitations, such as when trying to use the global and PLL at the same time: * If you use a PLL with only primary output, you can still use the remaining two free global networks. * If you use three globals associated with a PLL location, you cannot use the PLL on that location. * If the YB or YC output is used standalone, it will occupy one global, even though this signal does not go to the global network. v1.1 3 - 19 Global Resources in Actel Low-Power Flash Devices Using Spines of Occupied Global Networks When a signal is assigned to a global network, the flash switches are programmed to set the MUX select lines (explained in the "Clock Aggregation Architecture" section on page 3-8) to drive the spines of that network with the global net. However, if the global net is restricted from reaching into the scope of a spine, the MUX drivers of that spine are available for other high-fanout or critical signals (Figure 3-13). For example, if you want to limit the CLK1_c signal to the left half of the chip and want use the right side of the same global network for CLK2_c, you can add the following PDC commands: define_region -name region1 -type inclusive 0 0 34 29 assign_net_macros region1 CLK1_c assign_local_clock -net CLK2_c -type chip B2 Figure 3-13 * Design Example Using Spines of Occupied Global Networks Conclusion IGLOO, Fusion, and ProASIC3 devices contain 18 global networks: 6 chip global networks and 12 quadrant global networks. These global networks can be segmented into local low-skew networks called spines. The spines provide low-skew networks for the high-fanout signals of a design. These allow you up to 252 different internal/external clocks in an A3PE3000 device. This document describes the architecture for the global network, plus guidelines and methodologies in assigning signals to globals and spines. 3 -2 0 v1.1 Global Resources in Actel Low-Power Flash Devices Related Documents Handbook Documents Clock Conditioning Circuits in IGLOO and ProASIC3 Devices http://www.actel.com/LPD_CCC_HBs.pdf I/O Structures in IGLOO PLUS Devices http://www.actel.com/documents/IGLOOPLUS_IO_HBs.pdf I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/IGLOO_PA3_IO_HBs.pdf I/O Structures in IGLOOe and ProASIC3E Devices http://www.actel.com/documents/IGLOOe_PA3E_IO_HBs.pdf User's Guides IGLOO, Fusion, and ProASIC3 Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-005-1 Revised March 2008 v1.1 3 - 21 Global Resources in Actel Low-Power Flash Devices List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) 51900087-1/3.05 51900087-0/1.05 3 -2 2 Changes in Current Version (v1.1) Page The "Global Architecture" section was updated to include the IGLOO PLUS family. The bullet was revised to include that the west CCC does not contain a PLL core in 15 k and 30 k devices. Instances of "A3P030 and AGL030 devices" were replaced with "15 k and 30 k gate devices." 3-1 Table 3-1 * Low-Power Flash Families and the accompanying text was updated to include the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 3-2 The "VersaNet Global Network Distribution" section, "Spine Architecture" section, the note in Figure 3-1 * Overview of VersaNet Global Network and Device Architecture, and the note in Figure 3-2 * Simplified VersaNet Global Network were updated to include mention of 15 k gate devices. 3-3, 3-4 Table 3-2 * Globals/Spines/Rows for IGLOO and ProASIC3 Devices was updated to add the A3P015 device, and to revise the values for clock trees, globals/spines per tree, and globals/spines per device for the A3P030 and AGL030 devices. 3-5 Table 3-3 * Globals/Spines/Rows for IGLOO PLUS Devices is new. 3-5 CLKBUF_LVCMOS12 was added to Table 3-7 * I/O Standards within CLKBUF. 3-11 The "Handbook Documents" section was updated to include the three different I/O Structures chapters for ProASIC3 and IGLOO device families. 3-21 Figure 3-2 * Simplified VersaNet Global Network was updated. 3-4 The "Naming of Global I/Os" section was updated. 3-9 The "Using Global Macros in Synplicity" section was updated. 3-12 The "Global Promotion and Demotion Using PDC" section was updated. 3-13 The "Designer Flow for Global Assignment" section was updated. 3-15 The "Simple Design Example" section was updated. 3-17 Table 3-2 * Globals/Spines/Rows for IGLOO and ProASIC3 Devices was updated. 3-5 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices 4 - Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Introduction This document outlines the following device information: CCC features, PLL core specifications, functional descriptions, software configuration information, detailed usage information, recommended board-level considerations, and other considerations concerning clock conditioning circuits and global networks in low-power flash devices. Overview of Clock Conditioning Circuitry In IGLOO(R) and ProASIC(R)3 devices, the CCCs are used to implement frequency division, frequency multiplication, phase shifting, and delay operations. The CCCs are available in six chip locations-- each of the four chip corners and the middle of the east and west chip sides. For device-specific variations, refer to the "Device-Specific Layout" section on page 4-13. The CCC is composed of the following: * PLL core * 3 phase selectors * 6 programmable delays and 1 fixed delay that advances/delays phase * 5 programmable frequency dividers that provide frequency multiplication/division (not shown in Figure 4-5 on page 4-8 because they are automatically configured based on the user's required frequencies) * 1 dynamic shift register that provides CCC dynamic reconfiguration capability Figure 4-1 provides a simplified block diagram of the physical implementation of the building blocks in each of the CCCs. 3 Global I/Os To Core Multiplexer Tree CLKA To Global Network A From Core 3 Global I/Os To Core CLKB From Core 3 Global I/Os To Core CCC Function Block (with or without PLL) CLKC To Global Network B To Global Network C From Core Multiple Signals Single Signals Figure 4-1 * Overview of the CCCs Offered in IGLOO and ProASIC3 Each CCC can implement up to three independent global buffers (with or without programmable delay) or a PLL function (programmable frequency division/multiplication, phase shift, and delays) v1.1 4-1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices with up to three global outputs. Unused global outputs of a PLL can be used to implement independent global buffers, up to a maximum of three global outputs for a given CCC. CCC Programming The CCC block is fully configurable, either via flash configuration bits set in the programming bitstream or through an asynchronous interface. This asynchronous dedicated shift register interface is dynamically accessible from inside the low-power flash devices to permit parameter changes, such as PLL divide ratios and delays, during device operation. To increase the versatility and flexibility of the clock conditioning system, the CCC configuration is determined either by the user during the design process, with configuration data being stored in flash memory as part of the device programming procedure, or by writing data into a dedicated shift register during normal device operation. This latter mode allows the user to dynamically reconfigure the CCC without the need for core programming. The shift register is accessed through a simple serial interface. Refer to UJTAG Applications in Actel's Low-Power Flash Devices. Global Resources Low-power flash devices provide three global routing networks (GLA, GLB, and GLC) for each of the CCC locations. There are potentially many I/O locations; each global I/O location can be chosen from only one of three possibilities. This is controlled by the multiplexer tree circuitry in each global network. Once the I/O location is selected, the user has the option to utilize the CCCs before the signals are connected to the global networks. The CCC in each location (up to six) has the same structure, so generating the CCC macros is always done with an identical software GUI. The CCCs in the corner locations drive the quadrant global networks, and the CCCs in the middle of the east and west locations drive the chip global networks. The quadrant global networks span only a quarter of the device, while the chip global networks span the entire device. For more details on global resources offered in low-power flash devices, refer to Global Resources in Actel Low-Power Flash Devices. A global buffer can be placed in any of the three global locations (CLKA-GLA, CLKB-GLB, or CLKC-GLC) of a given CCC. A PLL macro uses the CLKA CCC input to drive its reference clock. It uses the GLA and, optionally, the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global output cannot be reused if the YB (or YC) output is used. Refer to the "PLL Macro Signal Descriptions" section on page 4-7 for more information. Each global buffer, as well as the PLL reference clock, can be driven from one of the following: 4 -2 * 3 dedicated single-ended I/Os using a hardwired connection * 2 dedicated differential I/Os using a hardwired connection * The FPGA core v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices CCC Support in Low-Power Devices The low-power flash families listed in Table 4-1 support the CCC feature and the functions described in this document. Table 4-1 * Family Low-Power Flash Families 1 IGLOO Timing Numbers2 Description Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*FreezeTM IGLOO DC and Switching technology Characteristics IGLOO PLUS Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO PLUS DC and Switching technology and enhanced I/O capabilities. Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional IGLOOe DC and Switching PLLs, and additional I/O standards Characteristics ProASIC3L Low-power, high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and Switching technology Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, ProASIC3E DC and Switching and additional I/O standards Characteristics ProASIC3 Automotive Low-power, high-performance FPGAs qualified for automotive Automotive ProASIC3 DC and applications Switching Characteristics ProASIC3 DC and Switching Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 4-1) provide a selection of low-power, secure, live-atpower-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 4-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 4-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. v1.1 4-3 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Global Buffers with No Programmable Delays Access to the global / quadrant global networks can be configured directly from the global I/O buffer, bypassing the CCC functional block (as indicated by the dotted lines in Figure 4-2). Internal signals driven by the FPGA core can use the global / quadrant global networks by connecting via the routed clock input of the multiplexer tree. There are many specific CLKBUF macros supporting the wide variety of single-ended I/O inputs (CLKBUF) and differential I/O standards (CLKBUF_LVDS/LVPECL) in the low-power flash families. They are used when connecting global I/Os directly to the global/quadrant networks. When an internal signal needs to be connected to the global/quadrant network, the CLKINT macro is used to connect the signal to the routed clock input of the network's MUX tree. To utilize direct connection from global I/Os or from internal signals to the global/quadrant networks, CLKBUF, CLKBUF_LVPECL/LVDS, and CLKINT macros are used. * The CLKBUF and CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS macros are composite macros that include an I/O macro driving a global buffer, which uses a hardwired connection. * The CLKBUF, CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS, and CLKINT macros are pass-through clock sources and do not use the PLL or provide any programmable delay functionality. * The CLKINT macro provides a global buffer function driven internally by the FPGA core. The available CLKBUF macros are described in the IGLOO, Fusion, and ProASIC3 Macro Library Guide. Clock Source Clock Conditioning Output GLA CLKBUF_LVDS/LVPECL Macro CLKBUF Macro CLKINT Macro PADP or None PADN Y PAD Y A Y GLB or GLC Note: The CLKDLY macro uses programmable delay element type 2. Figure 4-2 * CCC Options: Global Buffers with No Programmable Delay Global Buffer with Programmable Delay Clocks requiring clock adjustments can utilize the programmable delay cores before connecting to the global / quadrant global networks. A maximum of 18 CCC global buffers can be instantiated in a device--three per CCC times up to six CCCs per device. Each CCC functional block contains a programmable delay element for each of the global networks (up to three). 4 -4 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Clock Source Clock Conditioning Output Input LVDS/LVPECL Macro PADN GLA CLK Y GL PADP or GLB or DLYGL[4:0] INBUF* Macro Y PAD GLC Note: For INBUF* driving a PLL macro or CLKDLY macro, the I/O will be hard-routed to the CCC; i.e., will be placed by software to a dedicated Global I/O. Figure 4-3 * CCC Options: Global Buffers with Programmable Delay The CLKDLY macro is a pass-through clock source that does not use the PLL, but provides the ability to delay the clock input using a programmable delay. The CLKDLY macro takes the selected clock input and adds a user-defined delay element. This macro generates an output clock phase shift from the input clock. The CLKDLY macro can be driven by an INBUF* macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards supported by the low-power flash family. The available INBUF macros are described in the IGLOO, Fusion, and ProASIC3 Macro Library Guide. The CLKDLY macro can be driven directly from the FPGA core. The CLKDLY macro can also be driven from an I/O that is routed through the FPGA regular routing fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate from the hardwired I/O connection described earlier. The visual CLKDLY configuration in the SmartGen part of the Actel Libero(R) Integrated Design Environment (IDE) and Designer tools allows the user to select the desired amount of delay and configures the delay elements appropriately. SmartGen also allows the user to select the input clock source. SmartGen will automatically instantiate the special macro, PLLINT, when needed. CLKDLY Macro Signal Descriptions The CLKDLY macro supports one input and one output. Each signal is described in Table 4-2. Table 4-2 * Signal CLK Input and Output Description of the CLKDLY Macro Name I/O Reference Clock Input Description Reference clock input for PLL core Input clock for primary output clock, GLA GL Global Output Output Primary output clock to respective global/quadrant clock networks CLKDLY Macro Usage When a CLKDLY macro is used in a CCC location, the programmable delay element is used to allow the clock delays to go to the global network. In addition, the user can bypass the PLL in a CCC location integrated with a PLL, but use the programmable delay that is associated with the global network by instantiating the CLKDLY macro. The same is true when using programmable delay elements in a CCC location with no PLLs (the user needs to instantiate the CLKDLY macro). There is no difference between the programmable delay elements used for the PLL and the CLKDLY macro. v1.1 4-5 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices The CCC will be configured to use the programmable delay elements in accordance with the macro instantiated by the user. As an example, if the PLL is not used in a particular CCC location, the designer is free to specify up to three CLKDLY macros in the CCC, each of which can have its own input frequency and delay adjustment options. If the PLL core is used, assuming output to only one global clock network, the other two global clock networks are free to be used by either connecting directly from the global inputs or connecting from one or two CLKDLY macros for programmable delay. The programmable delay elements are shown in the block diagram of the PLL block shown in Figure 4-5 on page 4-8. Note that any CCC locations with no PLL present contain only the programmable delay blocks going to the global networks (labeled "Programmable Delay Type 2"). Refer to the "Clock Delay Adjustment" section on page 4-19 for a description of the programmable delay types used for the PLL. Also refer to Table 4-13 on page 4-24 for Programmable Delay Type 1 step delay values, and Table 4-14 on page 4-25 for Programmable Delay Type 2 step delay values. CCC locations with a PLL present can be configured to utilize only the programmable delay blocks (Programmable Delay Type 2) going to the global networks A, B, and C. Global network A can be configured to use only the programmable delay element (bypassing the PLL) if the PLL is not used in the design. Figure 4-5 on page 4-8 shows a block diagram of the PLL, where the programmable delay elements are used for the global networks (Programmable Delay Type 2). Global Buffers with PLL function Clocks requiring frequency synthesis or clock adjustments can utilize the PLL core before connecting to the global / quadrant global networks. A maximum of 18 CCC global buffers can be instantiated in a device--three per CCC times up to six CCCs per device. Each PLL core can generate up to three global/quadrant clocks, while a clock delay element provides one. The PLL functionality of the clock conditioning block is supported by the PLL macro. Clock Source Clock Conditioning Input LVDS/LVPECL Macro Output PLL Macro GLA PADN Y PADP INBUF* Macro PAD Y For INBUF* driving a PLL macro or CLKDLY macro, the I/O will be hard-routed to the CCC; i.e., will be placed by software to a dedicated Global I/O. CLKA EXTFB POWERDOWN OADIV[4:0]* OAMUX[2:0]* DLYGLA[4:0]* OBDIV[4:0]* OBMUX[2:0]* DLYYB[4:0]* DLYGLB[4:0]* OCDIV[4:0]* OCMUX[2:0]* DLYYC[4:0]* DLYGLC[4:0]* FINDIV[6:0]* FBDIV[6:0]* FBDLY[4:0]* FBSEL[1:0]* XDLYSEL* VCOSEL[2:0]* GLA LOCK GLB YB GLC YC or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) Note: Refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide for more information. Figure 4-4 * CCC Options: Global Buffers with PLL The PLL macro provides five derived clocks (three independent) from a single reference clock. The PLL macro also provides power-down input and lock output signals. The additional inputs shown 4 -6 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices on the macro are configuration settings, which are configured through the use of SmartGen. For manual setting of these bits refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide for details. Figure 4-5 on page 4-8 illustrates the various clock output options and delay elements. PLL Macro Signal Descriptions The PLL macro supports two inputs and up to six outputs. Table 4-3 gives a description of each signal. Table 4-3 * Input and Output Signals of the PLL Block Signal Name I/O Description CLKA Reference Clock Input Reference clock input for PLL core; Input clock for primary output clock, GLA EXTFB External Feedback Input Allows an external signal to be compared to a reference clock in the PLL core's phase detector Input Active low input that selects power-down mode and disables the PLL. With the POWERDOWN signal asserted, the PLL core sends 0 V signals on all of the outputs. POWERDOWN Power Down GLA Primary Output Output Primary output clock to respective global/quadrant clock networks GLB Secondary 1 Output Output Secondary 1 output clock to respective global/quadrant clock networks YB Core 1 Output GLC Secondary 2 Output Output Secondary 2 output clock to respective global/quadrant clock networks Output Core 1 output clock to local routing network YC Core 2 Output Output Core 2 output clock to local routing network LOCK PLL Lock Indicator Output Active-high signal indicating that steady-state lock has been achieved between CLKA and the PLL feedback signal Input Clock As discussed above, the inputs to the input reference clock (CLKA) of the PLL can come from global input pins, regular I/O pins, or internally from the core. Global Output Clocks GLA (Primary), GLB (Secondary 1), and GLC (Secondary 2) are the outputs of Global Multiplexer 1, Global Multiplexer 2, and Global Multiplexer 3, respectively. These signals (GLx) can be used to drive the high-speed global and quadrant networks of the low-power flash devices. A global multiplexer block consists of the input routing for selecting the input signal for the GLx clock and the output multiplexer, as well as delay elements associated with that clock. Core Output Clocks YB and YC are known as Core Outputs and can be used to drive internal logic without using global network resources. This is especially helpful when global network resources must be conserved and utilized for other timing-critical paths. YB and YC are identical to GLB and GLC, respectively, with the possible exception of a higher selectable final output delay. The SmartGen PLL Wizard will configure these outputs according to user specifications and can enable these signals with or without the enabling of Global Output Clocks. The above signals can be enabled in the following output groupings in both internal and external feedback configurations of the static PLL: * One output - GLA only * Two outputs - GLA + (GLB and/or YB) * Three outputs - GLA + (GLB and/or YB) + (GLC and/or YC) v1.1 4-7 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices PLL Macro Block Diagram As illustrated, the PLL supports three distinct output frequencies from a given input clock. Two of these (GLB and GLC) can be routed to the B and C global network access, respectively, and/or routed to the device core (YB and YC). There are five delay elements to support phase control on all five outputs (GLA, GLB, GLC, YB, and YC). There is also a delay element in the feedback loop that can be used to advance the clock relative to the reference clock. The PLL macro reference clock can be driven by an INBUF* macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations. The PLL macro reference clock can be driven directly from the FPGA core. The PLL macro reference clock can also be driven from an I/O that is routed through the FPGA regular routing fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate from the hardwired I/O connection described earlier. During power-up, the PLL outputs will toggle around the maximum frequency of the voltagecontrolled oscillator (VCO) gear selected. Toggle frequencies can range from 40 MHz to 250 MHz. This will continue as long as the clock input (CLKA) is constant (HIGH or LOW). This can be prevented by LOW assertion of the POWERDOWN signal. The visual PLL configuration in SmartGen, part of the Libero IDE and Designer tools, will derive the necessary internal divider ratios based on the input frequency and desired output frequencies selected by the user. SmartGen also allows the user to select the various delays and phase shift values necessary to adjust the phases between the reference clock (CLKA) and the derived clocks (GLA, GLB, GLC, YB, and YC). SmartGen also allows the user to select the input clock source. SmartGen automatically instantiates the special macro, PLLINT, when needed. CLKA PLL Core Fixed Delay Four-Phase Output Phase Select Programmable Delay Type 2 GLA Programmable Delay Type 2 GLB Programmable Delay Type 1 YB Programmable Delay Type 2 GLC Programmable Delay Type 1 YC Programmable Delay Type 1 EXTFB Phase Select Phase Select Note: Clock divider and clock multiplier blocks are not shown in this figure or in SmartGen. They are automatically configured based on the user's required frequencies. Figure 4-5 * CCC with PLL Block 4 -8 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Global Input Selections Low-power flash devices provide the flexibility of choosing one of the three global input pad locations available to connect to a CCC functional block or to a global / quadrant global network. Figure 4-6 shows the detailed architecture of each global input structure. If the single-ended I/O standard is chosen, there is flexibility to choose one of the global input pads (the first, second, and fourth input). Once chosen, the other I/O locations are used as regular I/Os. If the differential I/O standard is chosen, the first and second inputs are considered as paired, and the third input is paired with a regular I/O. The user then has the choice of selecting one of the two sets to be used as the clock input source to the CCC functional block. There is also the option to allow an internal clock signal to feed the global network or the CCC functional block. A multiplexer tree selects the appropriate global input for routing to the desired location. Note that the global I/O pads do not need to feed the global network; they can also be used as regular I/O pads. Each shaded box represents an INBUF or INBUF_LVDS/LVPECL macro, as appropriate. To Core Sample Pin Names 1 GAA0/IO0NDB0V0 1 GAA1/IO00PDB0V0 + Source for CCC (CLKA or CLKB or CLKC) 1 GAA2/IO13PDB7V1 Routed Clock 2 (from FPGA core) + GAA[0:2]: GA represents global in the northwest corner of the device. A[0:2]: designates specific A clock source. Notes: 1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric. Refer to User I/O Naming Conventions in I/O Structures in IGLOO and ProASIC3 Devices. 2. Instantiate the routed clock source input as follows: a) Connect the output of a logic element to the clock input of a PLL, CLKDLY, or CLKINT macro. b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS/BLVDS/M-LVDS/DDR) in a relevant global pin location. Figure 4-6 * Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT Each global buffer, as well as the PLL reference clock, can be driven from one of the following: * 3 dedicated single-ended I/Os using a hardwired connection * 2 dedicated differential I/Os using a hardwired connection * The FPGA core v1.1 4-9 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Since the architecture of the devices varies as size increases, the following list details I/O types supported for globals: * LVDS-, BLVDS-, and M-LVDS-based clock sources are only available on 250 k gate devices and above. * 65 k and 125 k gate devices support single-ended clock sources only. * 15 k and 30 k gate devices support these inputs for CCC only and do not contain a PLL. Clock Sources for PLL and CLKDLY Macros The input reference clock (CLKA for a PLL macro, CLK for a CLKDLY macro) can be accessed from different sources via the associated clock multiplexer tree. Each CCC has the option of choosing the source of the input clock from one of the following: * Hardwired I/O * External I/O * Core Logic The SmartGen macro builder tool allows users to easily create the PLL and CLKDLY macros with the desired settings. It is strongly recommended that SmartGen be used to generate the CCC macros. Hardwired I/O Clock Source Hardwired I/O refers to global input pins that are hardwired to the multiplexer tree, which directly accesses the CCC global buffers. These global input pins have designated pin locations and are indicated with the I/O naming convention Gmn (m refers to any one of the positions where the PLL core is available, and n refers to any one of the three global input MUXes and the pin number of the associated global location, m). Choosing this option provides the benefit of directly connecting to the CCC reference clock input, which provides less delay. See Figure 4-7 for an example illustration of the connections, shown in red. If a CLKDLY macro is initiated to utilize the programmable delay element of the CCC, the clock input can be placed at one of nine dedicated global input pin locations. In other words, if Hardwired I/O is chosen as the input source, the user can decide to place the input pin in one of the GmA0, GmA1, GmA2, GmB0, GmB1, GmB2, GmC0, GmC1, or GmC2 locations of the low-power flash devices. When a PLL macro is used to utilize the PLL core in a CCC location, the clock input of the PLL can only be connected to one of three GmA* global pin locations: GmA0, GmA1, or GmA2. To Core Gmn0 Gmn1 Multiplexer Tree _ + PLL or CLKDLY Macro CLKA To Global (or local) Routing Network IOuxwByVz Gmn2 _ + Routed Clock (from FPGA core) PLLINT Figure 4-7 * Illustration of Hardwired I/O (global input pins) Usage 4 -1 0 v1.1 Gmn* = Global Input Pin IOuxwByVz = Regular I/O Pin Clock Conditioning Circuits in IGLOO and ProASIC3 Devices External I/O Clock Source External I/O refers to regular I/O pins. The clock source is instantiated with one of the various INBUF options and accesses the CCCs via internal routing. The user has the option of assigning this input to any of the I/Os labeled with the I/O convention IOuxwByVz. Refer to User I/O Naming Conventions in I/O Structures in IGLOO and ProASIC3 Devices for more information. Figure 4-8 gives a brief explanation of external I/O usage. Choosing this option provides the freedom of selecting any user I/O location but introduces additional delay because the signal connects to the routed clock input through internal routing before connecting to the CCC reference clock input. For the External I/O option, the routed signal would be instantiated with a PLLINT macro before connecting to the CCC reference clock input. This instantiation is conveniently done automatically by SmartGen when this option is selected. Using the SmartGen tool to generate the CCC macro is the recommended approach. The instantiation of the PLLINT macro results in the use of the routed clock input of the I/O to connect to the PLL clock input. If not using SmartGen, manually instantiate a PLLINT macro before the PLL reference clock to indicate that the regular I/O driving the PLL reference clock should be used (see Figure 4-8 for an example illustration of the connections, shown in red). In the above two options, the clock source must be instantiated with one of the various INBUF macros. The reference clock pins of the CCC functional block core macros must be driven by regular input macros (INBUFs), not clock input macros. To Core Gmn* Gmn* Multiplexer Tree _ + PLL or CLKDLY Macro CLKA To Global (or Local) Routing Network IOuxwByVz* Gmn* _ + Routed Clock (from FPGA Core) PLLINT Gmn* = Global Input Pin IOuxwByVz = Regular I/O Pin IOuxwByVz* Figure 4-8 * Illustration of External I/O Usage v1.1 4 - 11 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Core Logic Clock Source Core logic refers to internal routed nets. Internal routed signals access the CCC via the FPGA Core Fabric. Similar to the external I/O option, whenever the clock source comes internally from the core itself, the routed signal is instantiated with a PLLINT macro before connecting to the CCC clock input (see Figure 4-9 for an example illustration of the connections, shown in red). To Core Gmn* Multiplexer Tree _ + Gmn* PLL or CLKDLY Macro CLKA To Global (or Local) Routing Network IOuxwByVz* Routed Clock (from FPGA Core) _ + Gmn* PLLINT Gmn* = Global Input Pin IOuxwByVz = Regular I/O Pin From Internal Signals Figure 4-9 * Illustration of Core Logic Usage Available I/O Standards Table 4-4 * Available I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros CLKBUF_LVCMOS5 CLKBUF_LVCMOS33 1 CLKBUF_LVCMOS25 2 CLKBUF_LVCMOS18 CLKBUF_LVCMOS15 CLKBUF_PCI CLKBUF_PCIX 2 CLKBUF_GTL25 2 CLKBUF_GTL33 2 CLKBUF_GTLP25 2 CLKBUF_GTLP33 2 CLKBUF_HSTL_I 2 CLKBUF_HSTL_II 2 CLKBUF_SSTL3_I 2 CLKBUF_SSTL3_II 2 CLKBUF_SSTL2_I 2 CLKBUF_SSTL2_II 2 CLKBUF_LVDS 3 CLKBUF_LVPECL Notes: 1. By default, the CLKBUF macro uses the 3.3 V LVTTL I/O technology. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. 2. I/O standards only supported in ProASIC3E and IGLOOe families. 3. BLVDS and M-LVDS standards are supported by CLKBUF_LVDS. 4 -1 2 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Global Synthesis Constraints The Synplify(R) synthesis tool, by default, allows six clocks in a design for IGLOO and ProASIC3. When more than six clocks are needed in the design, a user synthesis constraint attribute, syn_global_buffers, can be used to control the maximum number of clocks (up to 18) that can be inferred by the synthesis engine. High-fanout nets will be inferred with clock buffers and/or internal clock buffers. If the design consists of CCC global buffers, they are included in the count of clocks in the design. The subsections below discuss the clock input source (global buffers with no programmable delays) and the clock conditioning functional block (global buffers with programmable delays and/or PLL function) in detail. Device-Specific Layout Two kinds of CCCs are offered in low-power flash devices: CCCs with integrated PLLs, and CCCs without integrated PLLs (simplified CCCs). Table 4-5 lists the number of CCCs in various devices. Table 4-5 * Number of CCCs by Device Size and Package Device ProASIC3/ProASIC3L IGLOO/IGLOO PLUS Package CCCs with CCCs without Integrated Integrated PLLs PLLs (simplified CCC) A3P015 AGL015 All 0 2 A3P030 AGL030/AGLP030 All 0 2 A3P060 AGL060/AGLP060 All 1 5 A3P125 AGL125/AGLP125 All 1 5 AGL250 All 1 5 All 1 5 A3P600/L AGL600 All 1 5 A3P1000/L AGL1000 All 1 5 A3PE600 AGLE600 PQ208 2 4 A3PE600 All other packages 6 0 A3PE1500 PQ208 2 4 A3PE1500 All other packages 6 0 PQ208 2 4 All other packages 6 0 A3P250/L A3P400 A3PE3000/L A3PE3000/L AGLE3000 This document outlines the following device information: CCC features, PLL core specifications, functional descriptions, software configuration information, detailed usage information, recommended board-level considerations, and other considerations concerning global networks in low-power flash devices. Clock Conditioning Circuits with Integrated PLLs Each of the CCCs with integrated PLLs includes the following: * 1 PLL core, which consists of a phase detector, a low-pass filter, and a four-phase voltagecontrolled oscillator * 3 global multiplexer blocks that steer signals from the global pads and the PLL core onto the global networks * 6 programmable delays and 1 fixed delay for time advance/delay adjustments v1.1 4 - 13 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices * 5 programmable frequency divider blocks to provide frequency synthesis (automatically configured by the SmartGen macro builder tool) Clock Conditioning Circuits without Integrated PLLs Each of the simplified CCCs without integrated PLLs in the low-power flash families is composed of the following: * 3 global multiplexer blocks that steer signals from the global pads and the programmable delay elements onto the global networks * 3 programmable delay elements to provide time delay adjustments CCC Locations CCCs located in the middle of the east and west sides of the device access the three VersaNet global networks on each side (six total networks), while the four CCCs located in the four corners access three quadrant global networks (twelve total networks). See Figure 4-10. Northwest Quadrant Global Networks CCC Location B Quadrant Global Spine CCC Location A 3 3 3 Chip-Wide (main) Global Networks 6 6 3 6 6 3 CCC Location C CCC Location F 3 Global Spine 3 CCC Location E 6 6 3 6 3 6 3 CCC Location D Southeast Quadrant Global Networks Figure 4-10 * Global Network Architecture The following explains the locations of the CCCs in IGLOO and ProASIC3 devices: In Figure 4-13 on page 4-16 through Figure 4-14 on page 4-16, CCCs with integrated PLLs are indicated in red, and simplified CCCs are indicated in yellow. There is a letter associated with each location of the CCC, in clockwise order. The upper left corner CCC is named "A," the upper right is named "B," and so on. These names finish up at the middle left with letter "F." IGLOO and ProASIC3 CCC Locations In all IGLOO and ProASIC3 devices (except 15 k and 30 k gate devices, which do not contain PLLs), six CCCs are located in the same positions as the IGLOOe and ProASIC3E CCCs. Only one of the CCCs has an integrated PLL and is located in the middle of the west (middle left) side of the device. The 4 -1 4 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices other five CCCs are simplified CCCs and are located in the four corners and the middle of the east side of the device (Figure 4-11). A B Bank 0 CCC Bank 3 Bank 1 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os C F VersaTile Bank 3 Bank 1 ISP AES Decryption User Nonvolatile FlashROM (FROM) RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Charge Pumps D E Bank 2 = CCC with integrated PLL = Simplified CCC with programmable delay elements (no PLL) Figure 4-11 * CCC Locations in IGLOO and ProASIC3 Family Devices (except 15 k and 30 k gate devices) Note that the 15 k and 30 k gate devices do not support PLL features. This device has only six global I/O buffers, three each located in the middle of the east and west sides of the device. A CCC functional block is available in each of the two locations, for a total of two CCCs. No quadrant global networks are present in the four corners of this device (Figure 4-12). Bank 0 A B Bank 1 Bank 0 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os CCC F C E ISP AES Decryption User Nonvolatile FlashROM (FROM) Bank 0 Bank 1 VersaTile Charge Pumps D Bank 1 = Simplified CCC with programmable delay elements (no PLL) Figure 4-12 * CCC Locations in the 15 k and 30 k Gate Devices v1.1 4 - 15 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices IGLOOe and ProASIC3E CCC Locations IGLOOe and ProASIC3E devices have six CCCs - one in each of the four corners and one each in the middle of the east and west sides of the device (Figure 4-13). All six CCCs are integrated with PLLs, except in PQFP-208 package devices. PQFP-208 package devices also have six CCCs, of which two include PLLs and four are simplified CCCs. The CCCs with PLLs are implemented in the middle of the east and west (middle right and middle left) sides of the device. The simplified CCCs without PLLs are located in the four corners of the device (Figure 4-14). CCC A B RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os C F VersaTile ISP AES Decryption User Nonvolatile FlashRom Flash*Freeze Technology RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Charge Pumps E D = CCC with integrated PLL Figure 4-13 * CCC Locations in IGLOOe and ProASIC3E Family Devices (except PQFP-208 package) Bank 0 A B RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 1 Bank 3 CCC I/Os C F Bank 1 Bank 3 VersaTile ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology D E Bank 2 = CCC with integrated PLL = Simplified CCC with programmable delay elements (no PLL) Figure 4-14 * CCC Locations in ProASIC3E Family Devices (PQFP-208 package) 4 -1 6 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Charge Pumps v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices PLL Core Specifications PLL Core Specifications can be found in the DC and Switching Characteristics chapter of the appropriate family datasheet. Loop Bandwidth Common design practice for systems with a low-noise input clock is the need to have PLLs with small loop bandwidths to reduce the effects of noise sources at the output. Table 4-6 shows the PLL loop bandwidth, providing a measure of the PLL's ability to track the input clock and jitter. Table 4-6 * -3dB Frequency of the PLL Typical Maximum Minimum (Ta = +125C, VCCA = 1.4 V) (Ta = +25C, VCCA = 1.5 V) (Ta = -55C, VCCA = 1.6 V) -3 dB Frequency 15 kHz 25 kHz 45 kHz PLL Core Operating Principles This section briefly describes the basic principles of PLL operation. The PLL core is composed of a phase detector (PD), a low-pass filter (LPF), and a four-phase voltage-controlled oscillator (VCO). Figure 4-15 illustrates a basic single-phase PLL core with a divider and delay in the feedback path. Frequency Reference Input FIN Phase Detector Voltage Controlled Oscillator Low-Pass Filter Divide by M Counter Frequency Output M x FIN Delay Figure 4-15 * Simplified PLL Core with Feedback Divider and Delay The PLL is an electronic servo loop that phase-aligns the PD feedback signal with the reference input. To achieve this, the PLL dynamically adjusts the VCO output signal according to the average phase difference between the input and feedback signals. The first element is the PD, which produces a voltage proportional to the phase difference between its inputs. A simple example of a digital phase detector is an Exclusive-OR gate. The second element, the LPF, extracts the average voltage from the phase detector and applies it to the VCO. This applied voltage alters the resonant frequency of the VCO, thus adjusting its output frequency. Consider Figure 4-15 with the feedback path bypassing the divider and delay elements. If the LPF steadily applies a voltage to the VCO such that the output frequency is identical to the input frequency, this steady-state condition is known as lock. Note that the input and output phases are also identical. The PLL core sets a LOCK output signal HIGH to indicate this condition. Should the input frequency increase slightly, the PD detects the frequency/phase difference between its reference and feedback input signals. Since the PD output is proportional to the phase difference, the change causes the output from the LPF to increase. This voltage change increases the resonant frequency of the VCO and increases the feedback frequency as a result. The PLL dynamically adjusts in this manner until the PD senses two phase-identical signals and steady-state lock is achieved. The opposite (decreasing PD output signal) occurs when the input frequency decreases. v1.1 4 - 17 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Now suppose the feedback divider is inserted in the feedback path. As the division factor N is increased, the average phase difference increases. The average phase difference will cause the VCO to increase its frequency until the output signal is phase-identical to the input after undergoing division. In other words, lock in both frequency and phase is achieved when the output frequency is M times the input. Thus, clock division in the feedback path results in multiplication at the output. A similar argument can be made when the delay element is inserted into the feedback path. To achieve steady-state lock, the VCO output signal will be delayed by the input period less the feedback delay. For periodic signals, this is equivalent to time-advancing the output clock by the feedback delay. Another key parameter of a PLL system is the acquisition time. Acquisition time is the amount of time it takes for the PLL to achieve lock (i.e., phase-align the feedback signal with the input reference clock). For example, suppose there is no voltage applied to the VCO, allowing it to operate at its free-running frequency. Should an input reference clock suddenly appear, a lock would be established within the maximum acquisition time. Functional Description This section provides detailed descriptions of PLL block functionality: clock dividers and multipliers, clock delay adjustment, phase adjustment, and dynamic PLL configuration. Clock Dividers and Multipliers The PLL block contains five programmable dividers. Figure 4-16 shows a simplified PLL block. n CLKA PLL CORE m Fixed Delay System Delay 270 180 90 0 u D1 Feedback Delay Output Delay D2 Output Delay D2 v w 4 -1 8 v1.1 YB GLC Secondary 2 D1 Output Delay Figure 4-16 * PLL Block Diagram GLB Secondary 1 D1 Output Delay Output Delay D2 D1 = Programmable Delay Type 1 D2 = Programmable Delay Type 2 GLA Primary YC Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Dividers n and m (the input divider and feedback divider, respectively) provide integer frequency division factors from 1 to 128. The output dividers u, v, and w provide integer division factors from 1 to 32. Frequency scaling of the reference clock CLKA is performed according to the following formulas: fGLA = fCLKA x m / (n x u) - GLA Primary PLL Output Clock EQ 4-1 fGLB = fYB = fCLKA x m / (n x v) - GLB Secondary 1 PLL Output Clock(s) EQ 4-2 fGLC = fYC = fCLKA x m / (n x w) - GLC Secondary 2 PLL Output Clock(s) EQ 4-3 SmartGen provides a user-friendly method of generating the configured PLL netlist, which includes automatically setting the division factors to achieve the closest possible match to the requested frequencies. Since the five output clocks share the n and m dividers, the achievable output frequencies are interdependent and related according to the following formula: fGLA = fGLB x (v / u) = fGLC x (w / u) EQ 4-4 Clock Delay Adjustment There are a total of seven configurable delay elements implemented in the PLL architecture. Two of the delays are located in the feedback path, entitled System Delay and Feedback Delay. System Delay provides a fixed delay of 2 ns (typical), and Feedback Delay provides selectable delay values from 0.6 ns to 5.56 ns in 160 ps increments (typical). For PLLs, delays in the feedback path will effectively advance the output signal from the PLL core with respect to the reference clock. Thus, the System and Feedback delays generate negative delay on the output clock. Additionally, each of these delays can be independently bypassed if necessary. The remaining five delays perform traditional time delay and are located at each of the outputs of the PLL. Besides the fixed global driver delay of 0.755 ns for each of the global networks, the global multiplexer outputs (GLA, GLB, and GLC) each feature an additional selectable delay value from 0.025 ns to 0.76 ns in the first step, and then to 5.56 ns in 160 ps increments. The additional YB and YC signals have access to a selectable delay from 0.6 ns to 5.56 ns in 160 ps increments (typical). This is the same delay value as the CLKDLY macro. It is similar to CLKDLY, which bypasses the PLL core just to take advantage of the phase adjustment option with the delay value. The following parameters must be taken into consideration to achieve minimum delay at the outputs (GLA, GLB, GLC, YB, and YC) relative to the reference clock: routing delays from the PLL core to CCC outputs, core outputs and global network output delays, and the feedback path delay. The feedback path delay acts as a time advance of the input clock and will offset any delays introduced beyond the PLL core output. The routing delays are determined from back-annotated simulation and are configuration-dependent. Phase Adjustment The output from the PLL core can be phase-adjusted with respect to the reference input clock, CLKA. The user can select a 0, 90, 180, or 270 phase shift independently for each of the outputs YA, GLB/YB, and GLC/YC. Note that each of these phase-adjusted signals may also undergo further frequency division and/or time adjustment via the remaining dividers and delays located at the outputs of the PLL. Dynamic PLL Configuration The CCCs can be configured both statically and dynamically. In addition to the ports available in the Static CCC, the Dynamic CCC has the dynamic shift register signals that enable dynamic reconfiguration of the CCC. With the Dynamic CCC, the ports CLKB and CLKC are also exposed. All three clocks (CLKA, CLKB, and CLKC) can be configured independently. v1.1 4 - 19 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices The CCC block is fully configurable. The following two sources can act as the CCC configuration bits. Flash Configuration Bits The flash configuration bits are the configuration bits associated with programmed flash switches. These bits are used when the CCC is in static configuration mode. Once the device is programmed, these bits cannot be modified. They provide the default operating state of the CCC. Dynamic Shift Register Outputs This source does not require core reprogramming and allows core-driven dynamic CCC reconfiguration. When the dynamic register drives the configuration bits, the user-defined core circuit takes full control over SDIN, SDOUT, SCLK, SSHIFT, and SUPDATE. The configuration bits can consequently be dynamically changed through shift and update operations in the serial register interface. Access to the logic core is accomplished via the dynamic bits in the specific tiles assigned to the PLLs. Figure 4-17 illustrates a simplified block diagram of the MUX architecture in the CCCs. SDIN SDOUT SCLK SSHIFT SUPDATE <80:0> Dynamic Shift Register RESET_ENABLE <80> <79:0> Flash Programming Configuration Bits <79:0> MODE Configuration Bits Figure 4-17 * The CCC Configuration MUX Architecture The selection between the flash configuration bits and the bits from the configuration register is made using the MODE signal shown in Figure 4-17. If the MODE signal is logic HIGH, the dynamic shift register configuration bits are selected. There are 81 control bits to configure the different functions of the CCC. Each group of control bits is assigned a specific location in the configuration shift register. For a list of the 81 configuration bits (C[80:0]) in the CCC and a description of each, refer to "PLL Configuration Bits Description" on page 4-22. The configuration register can be serially loaded with the new configuration data and programmed into the CCC using the following ports: * SDIN: The configuration bits are serially loaded into a shift register through this port. The LSB of the configuration data bits should be loaded first. * SDOUT: The shift register contents can be shifted out (LSB first) through this port using the shift operation. * SCLK: This port should be driven by the shift clock. * SSHIFT: The active-high shift enable signal should drive this port. The configuration data will be shifted into the shift register if this signal is HIGH. Once SSHIFT goes LOW, the data shifting will be halted. * SUPDATE: The SUPDATE signal is used to configure the CCC with the new configuration bits when shifting is complete. To access the configuration ports of the shift register (SDIN, SDOUT, SSHIFT, etc.), the user should instantiate the CCC macro in his design with appropriate ports. Actel recommends that users choose SmartGen to generate the CCC macros with the required ports for dynamic reconfiguration. 4 -2 0 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Users must familiarize themselves with the architecture of the CCC core and its input, output, and configuration ports to implement the desired delay and output frequency in the CCC structure. Figure 4-18 shows a model of the CCC with configurable blocks and switches. CLKA /n C<6:0> 270 180 90 0 PLL CORE (7) (6) (5) (4) M U X A /m GLA D /u C<50:46> (2) Internal C<13:7> C<18:14> (1) C<31:29> (0) (2) D (1) M U X B D C<44:40> C<45> D /v YB C<39:38> C<23:19> C<34:32> D GLB CLKB C<55:51> M U X C Internal D /w YC C<70:66> C<28:24> C<37:35> D GLC CLKC C<60:56> Internal Figure 4-18 * CCC Block Control Bits - Graphical Representation of Assignments Loading the Configuration Register The most important part of CCC dynamic configuration is to load the shift register properly with the configuration bits. There are different ways to access and load the configuration shift register: * JTAG Interface * Logic Core * Specific I/O Tiles v1.1 4 - 21 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices JTAG Interface The JTAG interface requires no additional I/O pins. The JTAG TAP controller is used to control the loading of the CCC configuration shift register. Low-power flash devices provide a user interface macro between the JTAG pins and the device core logic. This macro is called UJTAG. A user should instantiate the UJTAG macro in his design to access the configuration register ports via the JTAG pins. For more information on CCC dynamic reconfiguration using UJTAG, refer to UJTAG Applications in Actel's Low-Power Flash Devices. Logic Core If the logic core is employed, the user must design a module to provide the configuration data and control the shifting and updating of the CCC configuration shift register. In effect, this is a userdesigned TAP controller, which requires additional chip resources. Specific I/O Tiles If specific I/O tiles are used for configuration, the user must provide the external equivalent of a TAP controller. This does not require additional core resources but does use pins. Shifting the Configuration Data To enter a new configuration, all 81 bits must shift in via SDIN. After all bits are shifted, SSHIFT must go LOW and SUPDATE HIGH to enable the new configuration. For simulation purposes, bits <71:73> and <77:80> are "don't cares." The SUPDATE signal must be LOW during any clock cycle where SSHIFT is active. After SUPDATE is asserted, it must go back to the LOW state until a new update is required. PLL Configuration Bits Description Table 4-7 * Config. Bits Configuration Bit Descriptions for the CCC Blocks Signal Name Description 80 RESETEN Reset Enable Enables (active high) the synchronization of PLL output dividers after dynamic reconfiguration (SUPDATE). The Reset Enable signal is READ-ONLY and should not be modified via dynamic reconfiguration. 79 DYNCSEL Clock Input C Dynamic Select Configures clock input C to be sent to GLC for dynamic control.* 78 DYNBSEL Clock Input B Dynamic Select Configures clock input B to be sent to GLB for dynamic control.* 77 DYNASEL Clock Input A Dynamic Select Configures clock configuration.* input A for dynamic PLL <76:74> VCOSEL[2:0] VCO Gear Control Three-bit VCO Gear Control for four frequency ranges 73 STATCSEL MUX Select on Input C MUX selection for clock input C* 72 STATBSEL MUX Select on Input B MUX selection for clock input B* 71 STATASEL MUX Select on Input A MUX selection for clock input A* <70:66> DLYC[4:0] YC Output Delay Sets the output delay value for YC. <65:61> DLYB[4:0] YB Output Delay Sets the output delay value for YB. <60:56> DLYGLC[4:0] GLC Output Delay Sets the output delay value for GLC. <55:51> DLYGLB[4:0] GLB Output Delay Sets the output delay value for GLB. <50:46> DLYGLA[4:0] Primary Output Delay Primary, GLA Output Delay * This value depends on the input clock source, so Layout must complete before these bits can be set. After completing Layout in Designer, generate the "CCC_Configuration" report by choosing Tools > Report > CCC_Configuration. The report contains the appropriate settings for these bits. 4 -2 2 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Table 4-7 * Config. Bits 45 Configuration Bit Descriptions for the CCC Blocks (continued) Signal XDLYSEL Name Description System Delay Select When selected, inserts System Delay in the feedback path in Figure 4-16 on page 4-18. Sets the feedback delay value for the feedback element in Figure 4-16 on page 4-18. <44:40> FBDLY[4:0] Feedback Delay <39:38> FBSEL[1:0] Primary Feedback Delay Select Controls the feedback MUX: no delay, include programmable delay element, or use external feedback. <37:35> OCMUX[2:0] Secondary 2 Output Select Selects from the VCO's four phase outputs for GLC/YC. <34:32> OBMUX[2:0] Secondary 1 Output Select Selects from the VCO's four phase outputs for GLB/YB. <31:29> OAMUX[2:0] GLA Output Select Selects from the VCO's four phase outputs for GLA. <28:24> OCDIV[4:0] Secondary 2 Output Divider Sets the divider value for the GLC/YC outputs. Also known as divider w in Figure 4-16 on page 4-18. The divider value will be OCDIV[4:0] + 1. <23:19> OBDIV[4:0] Secondary 1 Output Divider Sets the divider value for the GLB/YB outputs. Also known as divider v in Figure 4-16 on page 4-18. The divider value will be OBDIV[4:0] + 1. <18:14> OADIV[4:0] Primary Output Divider Sets the divider value for the GLA output. Also known as divider u in Figure 4-16 on page 4-18. The divider value will be OADIV[4:0] + 1. <13:7> FBDIV[6:0] Feedback Divider Sets the divider value for the PLL core feedback. Also known as divider m in Figure 4-16 on page 4-18. The divider value will be FBDIV[6:0] + 1. <6:0> FINDIV[6:0] Input Divider Input Clock Divider (/n). Sets the divider value for the input delay on CLKA. The divider value will be FINDIV[6:0] + 1. * This value depends on the input clock source, so Layout must complete before these bits can be set. After completing Layout in Designer, generate the "CCC_Configuration" report by choosing Tools > Report > CCC_Configuration. The report contains the appropriate settings for these bits. Table 4-8 to Table 4-14 on page 4-25 provide descriptions of the configuration data for the configuration bits. Table 4-8 * Input Clock (fin) Divider, (/n) (used as frequency divider) FINDIV<6:0> State Divisor New Frequency Factor 0 1 1.00000 1 2 0.50000 ... ... ... 127 128 0.0078125 Table 4-9 * Feedback Signal (fbin) Divider, (/m) (used as frequency multiplier) FBDIV<6:0> State Divisor New Frequency Factor 0 1 1 1 2 2 ... ... ... 127 128 128 v1.1 4 - 23 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Table 4-10 * Output Frequency Dividers A Output Divider, OADIV <4:0> (/u); B Output Divider, OBDIV <4:0> (/v); C Output Divider, OCDIV <4:0> (/w) OADIV<4:0>; OBDIV<4:0>; CDIV<4:0> State Divisor New Frequency Factor 0 1 1.00000 1 2 0.50000 ... ... ... 31 32 0.03125 Table 4-11 * MUXA, MUXB, MUXC OAMUX<2:0>; OBMUX<2:0>; OCMUX<2:0> State MUX Input Selected 0 None. Six-input MUX and PLL are bypassed. Clock passes only through global MUX and goes directly into HC ribs. 1 Not available 2 PLL feedback delay line output 3 Not used 4 PLL VCO 0 phase shift 5 PLL VCO 90 phase shift 6 PLL VCO 180 phase shift 7 PLL VCO 270 phase shift Table 4-12 * 2-Bit Feedback MUX FBSEL<1:0> State MUX Input Selected 0 Ground. Used for power-down mode in power-down logic block. 1 PLL VCO 0 phase shift 2 PLL delayed VCO 0 phase shift 3 N/A Table 4-13 * Programmable Delay Selection for Feedback Delay and Secondary Core Output Delays FBDLY<4:0>; DLYYB<4:0>; DLYYC<4:0> State Delay Value 0 Typical delay = 600 ps 1 Typical delay = 760 ps 2 Typical delay = 920 ps ... ... 31 Typical delay = 5.56 ns 4 -2 4 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Table 4-14 * Programmable Delay Selection for Global Clock Output Delays DLYGLA<4:0>; DLYGLB<4:0>; DLYGLC<4:0> State Delay Value 0 Typical delay = 225 ps 1 Typical delay = 760 ps 2 Typical delay = 920 ps ... ... 31 Typical delay = 5.56 ns Software Configuration SmartGen automatically generates the desired CCC functional block by configuring the control bits, and allows the user to select two CCC modes: Static PLL and Delayed Clock (CLKDLY). Static PLL Configuration The newly implemented Visual PLL Configuration Wizard feature provides the user a quick and easy way to configure the PLL with the desired settings (Figure 4-19 on page 4-26). The user can invoke SmartGen to set the parameters and generate the netlist file with the appropriate flash configuration bits set for the CCCs. As mentioned in "PLL Macro Block Diagram" on page 4-8, the input reference clock CLKA can be configured to be driven by Hardwired I/O, External I/O, or Core Logic. The user enters the desired settings for all the parameters (output frequency, output selection, output phase adjustment, clock delay, feedback delay, and system delay). Notice that the actual values (divider values, output frequency, delay values, and phase) are shown to aid the user in reaching the desired design frequency in real time. These values are typical-case data. Best- and worst-case data can be observed through static timing analysis in SmartTime within Designer. For dynamic configuration, the CCC parameters are defined using either the external JTAG port or an internally defined serial interface via the built-in dynamic shift register. This feature provides the ability to compensate for changes in the external environment. v1.1 4 - 25 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices VCO Clock Frequency Programmable Output Delay Elements Input Selection Fixed System Delay Output Selection Feedback Selection (Feedback MUX) Figure 4-19 * Visual PLL Configuration Wizard Feedback Configuration The PLL provides both internal and external feedback delays. Depending on the configuration, various combinations of feedback delays can be achieved. Internal Feedback Configuration This configuration essentially sets the feedback multiplexer to route the VCO output of the PLL Core as the input to the feedback of the PLL. The feedback signal may be processed with the fixed system and the adjustable feedback delay, as shown in Figure 4-20. The dividers are automatically configured by SmartGen based on the user input. Indicated below is the System Delay pull-down menu. The System Delay can be bypassed by setting it to 0. When set, it adds a 2 ns delay to the feedback path (which results in delay advancement of the output clock by 2 ns). Figure 4-20 * Internal Feedback with Selectable System Delay 4 -2 6 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Figure 4-21 shows the controllable Feedback Delay. If set properly in conjunction with the fixed System Delay, the total output delay can be advanced significantly. Figure 4-21 * Internal Feedback with Selectable Feedback Delay External Feedback Configuration For certain applications, such as those requiring generation of PCB clocks that must be matched with existing board delays, it is useful to implement an external feedback EXTFB. The Phase Detector of the PLL core will receive CLKA and EXTFB as inputs. EXTFB may be processed by the fixed System Delay element as well as the M divider element. The EXTFB option is currently not supported. After setting all the required parameters, users can generate one or more PLL configurations with HDL or EDIF descriptions by clicking the Generate button. SmartGen enables them to save the session results and messages in a log file: **************** Macro Parameters **************** Name Family Output Format Type Input Freq(MHz) CLKA Source Feedback Delay Value Index Feedback Mux Select XDLY Mux Select Primary Freq(MHz) Primary PhaseShift Primary Delay Value Index Primary Mux Select Secondary1 Freq(MHz) Use GLB Use YB GLB Delay Value Index YB Delay Value Index Secondary1 PhaseShift Secondary1 Mux Select Secondary2 Freq(MHz) Use GLC Use YC GLC Delay Value Index YC Delay Value Index Secondary2 PhaseShift Secondary2 Mux Select : : : : : : : : : : : : : : : : : : : : : : : : : : : test_pll ProASIC3E VHDL Static PLL 10.000 Hardwired I/O 1 2 No 33.000 0 1 4 66.000 YES YES 1 1 0 4 101.000 YES NO 1 1 0 4 v1.1 4 - 27 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices ... ... ... Primary Clock frequency 33.333 Primary Clock Phase Shift 0.000 Primary Clock Output Delay from CLKA 0.180 Secondary1 Secondary1 Secondary1 Secondary1 Clock Clock Clock Clock frequency 66.667 Phase Shift 0.000 Global Output Delay from CLKA 0.180 Core Output Delay from CLKA 0.625 Secondary2 Clock frequency 100.000 Secondary2 Clock Phase Shift 0.000 Secondary2 Clock Global Output Delay from CLKA 0.180 Below is an example Verilog HDL description of a legal PLL core configuration generated by SmartGen: module test_pll(POWERDOWN,CLKA,LOCK,GLA); input POWERDOWN, CLKA; output LOCK, GLA; wire VCC, GND; VCC VCC_1_net(.Y(VCC)); GND GND_1_net(.Y(GND)); PLL Core(.CLKA(CLKA), .EXTFB(GND), .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .GLB(), .YB(), .GLC(), .YC(), .OADIV0(GND), .OADIV1(GND), .OADIV2(GND), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND), .OAMUX1(GND), .OAMUX2(VCC), .DLYGLA0(GND), .DLYGLA1(GND), .DLYGLA2(GND), .DLYGLA3(GND) , .DLYGLA4(GND), .OBDIV0(GND), .OBDIV1(GND), .OBDIV2(GND), .OBDIV3(GND), .OBDIV4(GND), .OBMUX0(GND), .OBMUX1(GND), .OBMUX2(GND), .DLYYB0(GND), .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND), .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(GND), .OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(GND), .OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), .DLYGLC2(GND), .DLYGLC3(GND) , .DLYGLC4(GND), .FINDIV0(VCC), .FINDIV1(GND), .FINDIV2( VCC), .FINDIV3(GND), .FINDIV4(GND), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(VCC), .FBDIV1(GND), .FBDIV2(VCC), .FBDIV3(GND), .FBDIV4(GND), .FBDIV5(GND), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2(GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1(GND), .XDLYSEL(GND), .VCOSEL0(GND), .VCOSEL1(GND), .VCOSEL2(GND)); defparam Core.VCOFREQUENCY = 33.000; endmodule The "PLL Configuration Bits Description" section on page 4-22 provides descriptions of the PLL configuration bits and is provided only for completeness. The configuration bits are shown as busses only for purposes of illustration. They will actually be broken up into individual pins in compilation libraries and all simulation models. For example, the FBSEL[1:0] bus will actually appear as pins FBSEL1 and FBSEL0. The setting of these select lines for the static PLL configuration is performed by the software and is completely transparent to the user. 4 -2 8 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Dynamic PLL Configuration To generate a dynamically reconfigurable CCC, the user should select Dynamic CCC in the configuration section of the SmartGen GUI (Figure 4-22). This will generate both the CCC core and the configuration shift register / control bit MUX. Figure 4-22 * SmartGen GUI Even if dynamic configuration is selected in SmartGen, the user still must specify the static configuration data for the CCC (Figure 4-23). The specified static configuration is used whenever the MODE signal is set to LOW and the CCC is required to function in the static mode. The static configuration data can be used as the default behavior of the CCC where required. Figure 4-23 * Dynamic CCC Configuration in SmartGen v1.1 4 - 29 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices When SmartGen is used to define the configuration that will be shifted in via the serial interface, SmartGen prints out the values of the 81 configuration bits. For ease of use, several configuration bits are automatically inferred by SmartGen when the dynamic PLL core is generated; however, <71:73> (STATASEL, STATBSEL, STATCSEL) and <77:79> (DYNASEL, DYNBSEL, DYNCSEL) depend on the input clock source of the corresponding CCC. Users must first run Layout in Designer to determine the exact setting for these ports. After Layout is complete, generate the "CCC_Configuration" report by choosing Tools > Reports > CCC_Configuration in the Designer software. Refer to "PLL Configuration Bits Description" on page 4-22 for descriptions of the PLL configuration bits. For simulation purposes, bits <71:73> and <78:80> are "don't cares." Therefore, it is strongly suggested that SmartGen be used to generate the correct configuration bit settings for the dynamic PLL core. After setting all the required parameters, users can generate one or more PLL configurations with HDL or EDIF descriptions by clicking the Generate button. SmartGen enables them to save the session results and messages in a log file: **************** Macro Parameters **************** Name Family Output Format Type Input Freq(MHz) CLKA Source Feedback Delay Value Index Feedback Mux Select XDLY Mux Select Primary Freq(MHz) Primary PhaseShift Primary Delay Value Index Primary Mux Select Secondary1 Freq(MHz) Use GLB Use YB GLB Delay Value Index YB Delay Value Index Secondary1 PhaseShift Secondary1 Mux Select Secondary1 Input Freq(MHz) CLKB Source Secondary2 Freq(MHz) Use GLC Use YC GLC Delay Value Index YC Delay Value Index Secondary2 PhaseShift Secondary2 Mux Select Secondary2 Input Freq(MHz) CLKC Source : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : dyn_pll_hardio ProASIC3E VERILOG Dynamic CCC 30.000 Hardwired I/O 1 1 No 33.000 0 1 4 40.000 YES NO 1 1 0 0 40.000 Hardwired I/O 50.000 YES NO 1 1 0 0 50.000 Hardwired I/O Configuration Bits: FINDIV[6:0] 0000101 FBDIV[6:0] 0100000 OADIV[4:0] 00100 OBDIV[4:0] 00000 OCDIV[4:0] 00000 OAMUX[2:0] 100 OBMUX[2:0] 000 OCMUX[2:0] 000 FBSEL[1:0] 01 FBDLY[4:0] 00000 XDLYSEL 0 DLYGLA[4:0] 00000 4 -3 0 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices DLYGLB[4:0] DLYGLC[4:0] DLYYB[4:0] DLYYC[4:0] VCOSEL[2:0] 00000 00000 00000 00000 100 Primary Clock Frequency 33.000 Primary Clock Phase Shift 0.000 Primary Clock Output Delay from CLKA 1.695 Secondary1 Clock Frequency 40.000 Secondary1 Clock Phase Shift 0.000 Secondary1 Clock Global Output Delay from CLKB 0.200 Secondary2 Clock Frequency 50.000 Secondary2 Clock Phase Shift 0.000 Secondary2 Clock Global Output Delay from CLKC 0.200 ###################################### # Dynamic Stream Data ###################################### -------------------------------------|NAME |SDIN |VALUE |TYPE | -------------------------------------|FINDIV |[6:0] |0000101 |EDIT | |FBDIV |[13:7] |0100000 |EDIT | |OADIV |[18:14] |00100 |EDIT | |OBDIV |[23:19] |00000 |EDIT | |OCDIV |[28:24] |00000 |EDIT | |OAMUX |[31:29] |100 |EDIT | |OBMUX |[34:32] |000 |EDIT | |OCMUX |[37:35] |000 |EDIT | |FBSEL |[39:38] |01 |EDIT | |FBDLY |[44:40] |00000 |EDIT | |XDLYSEL |[45] |0 |EDIT | |DLYGLA |[50:46] |00000 |EDIT | |DLYGLB |[55:51] |00000 |EDIT | |DLYGLC |[60:56] |00000 |EDIT | |DLYYB |[65:61] |00000 |EDIT | |DLYYC |[70:66] |00000 |EDIT | |STATASEL|[71] |X |MASKED | |STATBSEL|[72] |X |MASKED | |STATCSEL|[73] |X |MASKED | |VCOSEL |[76:74] |100 |EDIT | |DYNASEL |[77] |X |MASKED | |DYNBSEL |[78] |X |MASKED | |DYNCSEL |[79] |X |MASKED | |RESETEN |[80] |1 |READONLY | The resultant Verilog HDL description of a legal dynamic PLL core configuration generated by SmartGen is as follows: module dyn_pll_macro(POWERDOWN, CLKA, LOCK, GLA, GLB, GLC, SDIN, SCLK, SSHIFT, SUPDATE, MODE, SDOUT, CLKB, CLKC); input POWERDOWN, CLKA; output LOCK, GLA, GLB, GLC; input SDIN, SCLK, SSHIFT, SUPDATE, MODE; output SDOUT; input CLKB, CLKC; wire VCC, GND; VCC VCC_1_net(.Y(VCC)); GND GND_1_net(.Y(GND)); v1.1 4 - 31 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices DYNCCC Core(.CLKA(CLKA), .EXTFB(GND), .POWERDOWN(POWERDOWN), .GLA(GLA), .LOCK(LOCK), .CLKB(CLKB), .GLB(GLB), .YB(), .CLKC(CLKC), .GLC(GLC), .YC(), .SDIN(SDIN), .SCLK(SCLK), .SSHIFT(SSHIFT), .SUPDATE(SUPDATE), .MODE(MODE), .SDOUT(SDOUT), .OADIV0(GND), .OADIV1(GND), .OADIV2(VCC), .OADIV3(GND), .OADIV4(GND), .OAMUX0(GND), .OAMUX1(GND), .OAMUX2(VCC), .DLYGLA0(GND), .DLYGLA1(GND), .DLYGLA2(GND), .DLYGLA3(GND), .DLYGLA4(GND), .OBDIV0(GND), .OBDIV1(GND), .OBDIV2(GND), .OBDIV3(GND), .OBDIV4(GND), .OBMUX0(GND), .OBMUX1(GND), .OBMUX2(GND), .DLYYB0(GND), .DLYYB1(GND), .DLYYB2(GND), .DLYYB3(GND), .DLYYB4(GND), .DLYGLB0(GND), .DLYGLB1(GND), .DLYGLB2(GND), .DLYGLB3(GND), .DLYGLB4(GND), .OCDIV0(GND), .OCDIV1(GND), .OCDIV2(GND), .OCDIV3(GND), .OCDIV4(GND), .OCMUX0(GND), .OCMUX1(GND), .OCMUX2(GND), .DLYYC0(GND), .DLYYC1(GND), .DLYYC2(GND), .DLYYC3(GND), .DLYYC4(GND), .DLYGLC0(GND), .DLYGLC1(GND), .DLYGLC2(GND), .DLYGLC3(GND), .DLYGLC4(GND), .FINDIV0(VCC), .FINDIV1(GND), .FINDIV2(VCC), .FINDIV3(GND), .FINDIV4(GND), .FINDIV5(GND), .FINDIV6(GND), .FBDIV0(GND), .FBDIV1(GND), .FBDIV2(GND), .FBDIV3(GND), .FBDIV4(GND), .FBDIV5(VCC), .FBDIV6(GND), .FBDLY0(GND), .FBDLY1(GND), .FBDLY2(GND), .FBDLY3(GND), .FBDLY4(GND), .FBSEL0(VCC), .FBSEL1(GND), .XDLYSEL(GND), .VCOSEL0(GND), .VCOSEL1(GND), .VCOSEL2(VCC)); defparam Core.VCOFREQUENCY = 165.000; endmodule Delayed Clock Configuration The CLKDLY macro can be generated with the desired delay and input clock source (Hardwired I/O, External I/O, or Core Logic), as in Figure 4-24. Figure 4-24 * Delayed Clock Configuration Dialog Box After setting all the required parameters, users can generate one or more PLL configurations with HDL or EDIF descriptions by clicking the Generate button. SmartGen enables them to save the session results and messages in a log file: **************** Macro Parameters **************** Name Family Output Format Type Delay Index CLKA Source : : : : : : delay_macro ProASIC3 Verilog Delayed Clock 2 Hardwired I/O Total Clock Delay = 0.935 ns. The resultant CLKDLY macro Verilog netlist is as follows: module delay_macro(GL,CLK); output GL; input CLK; 4 -3 2 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices wire VCC, GND; VCC VCC_1_net(.Y(VCC)); GND GND_1_net(.Y(GND)); CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(VCC), .DLYGL1(GND), .DLYGL2(VCC), .DLYGL3(GND), .DLYGL4(GND)); endmodule Detailed Usage Information Clock Frequency Synthesis Deriving clocks of various frequencies from a single reference clock is known as frequency synthesis. The PLL has an input frequency range from 1.5 to 350 MHz. This frequency is automatically divided down to a range between 1.5 MHz and 5.5 MHz by input dividers (not shown) between PLL macro inputs and PLL phase detector inputs. The VCO output is capable of an output range from 24 to 350 MHz. With dividers before the input to the PLL core and following the VCO outputs, the VCO output frequency can be divided to provide the final frequency range from 0.75 to 350 MHz. Using SmartGen, the dividers are automatically set to achieve the closest possible matches to the specified output frequencies. Users should be cautious when selecting the desired PLL input and output frequencies and the I/O buffer standard used to connect to the PLL input and output clocks. Depending on the I/O standards used for the PLL input and output clocks, the I/O frequencies have different maximum limits. Refer to the family datasheets for specifications of maximum I/O frequencies for supported I/O standards. Desired PLL input or output frequencies will not be achieved if the selected frequencies are higher than the maximum I/O frequencies allowed by the selected I/O standards. Users should be careful when selecting the I/O standards used for PLL input and output clocks. Performing post-layout simulation can help detect this type of error, which will be identified with pulse width violation errors. Users are strongly encouraged to perform post-layout simulation to ensure the I/O standard used can provide the desired PLL input or output frequencies. Users can also choose to cascade PLLs together to achieve the high frequencies needed for their applications. Details of cascading PLLs are discussed in the "Cascading CCCs" section on page 4-38. In SmartGen, the actual generated frequency (under typical operating conditions) will be displayed beside the requested output frequency value. This provides the ability to determine the exact frequency that can be generated by SmartGen, in real time. The log file generated by SmartGen is a useful tool in determining how closely the requested clock frequencies match the user specifications. For example, assume a user specifies 101 MHz as one of the secondary output frequencies. If the best output frequency that could be achieved were 100 MHz, the log file generated by SmartGen would indicate the actual generated frequency. Simulation Verification The integration of the generated PLL and CLKDLY modules is similar to any VHDL component or Verilog module instantiation in a larger design; i.e., there is no special requirement that users need to take into account to successfully synthesize their designs. For simulation purposes, users need to refer to the VITAL or Verilog library that includes the functional description and associated timing parameters. Refer to the Software Tools section of the Actel website to obtain the family simulation libraries. If Actel Designer is installed, these libraries are stored in the following locations: <Designer_Installation_Directory>\lib\vtl\95\proasic3.vhd <Designer_Installation_Directory>\lib\vtl\95\proasic3e.vhd <Designer_Installation_Directory>\lib\vlog\ proasic3.v <Designer_Installation_Directory>\lib\vlog\ proasic3e.v v1.1 4 - 33 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices For Libero IDE users, there is no need to compile the simulation libraries, as they are conveniently pre-compiled in the ModelSim(R) Actel simulation tool. The following is an example of a PLL configuration utilizing the clock frequency synthesis and clock delay adjustment features. The steps include generating the PLL core with SmartGen, performing simulation for verification with ModelSim, and performing static timing analysis with SmartTime in Designer. Parameters of the example PLL configuration: Input Frequency - 20 MHz Primary Output Requirement - 20 MHz with clock advancement of 3.02 ns Secondary 1 Output Requirement - 40 MHz with clock delay of 2.515 ns Figure 4-25 shows the SmartGen settings. Notice that the overall delays are calculated automatically, allowing the user to adjust the delay elements appropriately to obtain the desired delays. Figure 4-25 * SmartGen Settings After confirming the correct settings, generate a structural netlist of the PLL and verify PLL core settings by checking the log file: Name Family Output Format Type Input Freq(MHz) CLKA Source Feedback Delay Value Index Feedback Mux Select XDLY Mux Select Primary Freq(MHz) Primary PhaseShift Primary Delay Value Index Primary Mux Select Secondary1 Freq(MHz) Use GLB Use YB 4 -3 4 : : : : : : : : : : : : : : : : test_pll_delays ProASIC3E VHDL Static PLL 20.000 Hardwired I/O 21 2 No 20.000 0 1 4 40.000 YES NO v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices ... ... ... Primary Clock frequency 20.000 Primary Clock Phase Shift 0.000 Primary Clock Output Delay from CLKA -3.020 Secondary1 Clock frequency 40.000 Secondary1 Clock Phase Shift 0.000 Secondary1 Clock Global Output Delay from CLKA 2.515 Next, perform simulation in ModelSim to verify the correct delays. Figure 4-26 shows the simulation results. The delay values match those reported in the SmartGen PLL wizard. Primary Clock Output Time Advancement from CLKA Secondary1 Clock Global Output Delay from CLKA Figure 4-26 * ModelSim Simulation Results The timing can also be analyzed using SmartTime in Designer. The user should import the synthesized netlist to Designer, perform Compile and Layout, and then invoke SmartTime. Go to Tools > Options and change the maximum delay operating conditions to Typical Case. Then expand the Clock-to-Out paths of GLA and GLB and the individual components of the path delays are shown. The path of GLA is shown in Figure 4-27 on page 4-36 displaying the same delay value. v1.1 4 - 35 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Figure 4-27 * Static Timing Analysis Using SmartTime Place-and-Route Stage Considerations Several considerations must be noted to properly place the CCC macros for layout. For CCCs with clock inputs configured with the Hardwired I/O-Driven option: * PLL macros must have the clock input pad coming from one of the GmA* locations. * CLKDLY macros must have the clock input pad coming from one of the Global I/Os. If a PLL with a Hardwired I/O input is used at a CCC location and a Hardwired I/O-Driven CLKDLY macro is used at the same CCC location, the clock input of the CLKDLY macro must be chosen from one of the GmB* or GmC* pin locations. If the PLL is not used or is an External I/O-Driven or Core Logic-Driven PLL, the clock input of the CLKDLY macro can be sourced from the GmA*, GmB*, or GmC* pin locations. For CCCs with clock inputs configured with the External I/O-Driven option, the clock input pad can be assigned to any regular I/O location (IO******** pins). Note that since global I/O pins can also be used as regular I/Os, regardless of CCC function (CLKDLY or PLL), clock inputs can also be placed in any of these I/O locations. By default, the Designer layout engine will place global nets in the design at one of the six chip globals. When the number of globals in the design is greater than six, the Designer layout engine will automatically assign additional globals to the quadrant global networks of the low-power flash devices. If the user wishes to decide which global signals should be assigned to chip globals (six available) and which to the quadrant globals (three per quadrant for a total of 12 available), the assignment can be achieved with PinEditor, ChipPlanner, or by importing a placement 4 -3 6 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices constraint file. Layout will fail if the global assignments are not allocated properly. See the "Physical Constraints for Quadrant Clocks" section for information on assigning global signals to the quadrant clock networks. Promoted global signals will be instantiated with CLKINT macros to drive these signals onto the global network. This is automatically done by Designer when the Auto-Promotion option is selected. If the user wishes to assign the signals to the quadrant globals instead of the default chip globals, this can done by using ChipPlanner, by declaring a physical design constraint (PDC), or by importing a PDC file. Physical Constraints for Quadrant Clocks If it is necessary to promote global clocks (CLKBUF, CLKINT, PLL, CLKDLY) to quadrant clocks, the user can define PDCs to execute the promotion. PDCs can be created using PDC commands (precompile) or the MVN interface (post-compile). The advantage of using the PDC flow over the MVN flow is that the Compile stage is able to automatically promote any regular net to a global net before assigning it to a quadrant. There are three options to place a quadrant clock using PDC commands: * Place a clock core (not hardwired to an I/O) into a quadrant clock location. * Place a clock core (hardwired to an I/O) into an I/O location (set_io) or an I/O module location (set_location) that drives a quadrant clock location. * Assign a net driven by a regular net or a clock net to a quadrant clock using the following command: assign_local_clock -net <net name> -type quadrant <quadrant clock region> where <net name> is the name of the net assigned to the local user clock region. <quadrant clock region> defines which quadrant the net should be assigned to. Quadrant clock regions are defined as UL (upper left), UR (upper right), LL (lower left), and LR (lower right). Note: If the net is a regular net, the software inserts a CLKINT buffer on the net. For example: assign_local_clock -net localReset -type quadrant UR Keep in mind the following when placing quadrant clocks using MultiView Navigator: Hardwired I/O-Driven CCCs * Find the associated clock input port under the Ports tab, and place the input port at one of the Gmn* locations using PinEditor or I/O Attribute Editor, as shown in Figure 4-28. Figure 4-28 * Port Assignment for a CCC with Hardwired I/O Clock Input v1.1 4 - 37 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices * Use quadrant global region assignments by finding the clock net associated with the CCC macro under the Nets tab and creating a quadrant global region for the net, as shown in Figure 4-29. Figure 4-29 * Quadrant Clock Assignment for a Global Net External I/O-Driven CCCs The above-mentioned recommendation for proper layout techniques will ensure the correct assignment. It is possible that, especially with External I/O-Driven CCC macros, placement of the CCC macro in a desired location may not be achieved. For example, assigning an input port of an External I/O-Driven CCC near a particular CCC location does not guarantee global assignments to the desired location. This is because the clock inputs of External I/O-Driven CCCs can be assigned to any I/O location; therefore, it is possible that the CCC connected to the clock input will be routed to a location other than the one closest to the I/O location, depending on resource availability and placement constraints. Clock Placer The clock placer is a placement engine for low-power flash devices that places global signals on the chip global and quadrant global networks. Based on the clock assignment constraints for the chip global and quadrant global clocks, it will try to satisfy all constraints, as well as creating quadrant clock regions when necessary. If the clock placer fails to create the quadrant clock regions for the global signals, it will report an error and stop Layout. The user must ensure that the constraints set to promote clock signals to quadrant global networks are valid. Cascading CCCs The CCCs in low-power flash devices can be cascaded. Cascading CCCs can help achieve more accurate PLL output frequency results than those achievable with a single CCC. In addition, this technique is useful when the user application requires the output clock of the PLL to be a multiple of the reference clock by an integer greater than the maximum feedback divider value of the PLL (divide by 128) to achieve the desired frequency. For example, the user application may require a 280 MHz output clock using a 2 MHz input reference clock, as shown in Figure 4-30 on page 4-39. 4 -3 8 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Figure 4-30 * Cascade PLL Configuration Using internal feedback, we know from EQ 4-1 on page 4-19 that the maximum achievable output frequency from the primary output is fGLA = fCLKA x m / (n x u) = 2 MHz x 128 / (1 x 1) = 256 MHz EQ 4-5 Figure 4-31 shows the settings of the initial PLL. When configuring the initial PLL, specify the input to be either Hardwired I/O-Driven or External I/O-Driven. This generates a netlist with the initial PLL routed from an I/O. Do not specify the input to be Core Logic-Driven, as this prohibits the connection from the I/O pin to the input of the PLL. Figure 4-31 * First-Stage PLL Showing Input of 2 MHz and Output of 256 MHz A second PLL can be connected serially to achieve the required frequency. EQ 4-1 on page 4-19 to EQ 4-3 on page 4-19 are extended as follows: fGLA2 = fGLA x m2 / (n2 x u2) = fCLKA1 x m1 x m2 / (n1 x u1 x n2 x u2) - Primary PLL Output Clock EQ 4-6 fGLB2 = fYB2 = fCLKA1 x m1 x m2 / (n1 x n2 x v1 x v2) - Secondary 1 PLL Output Clock(s) EQ 4-7 fGLC2 = fYC2 = fCLKA1 x m1 x m2 / (n1 x n2 x w1 x w2) - Secondary 2 PLL Output Clock(s) EQ 4-8 In the example, the final output frequency (foutput) from the primary output of the second PLL will be as follows (EQ 4-9): foutput = fGLA2 = fGLA x m2 / (n2 x u2) = 256 MHz x 70 / (64 x 1) = 280 MHz EQ 4-9 Figure 4-32 on page 4-40 shows the settings of the second PLL. When configuring the second PLL (or any subsequent-stage PLLs), specify the input to be Core Logic-Driven. This generates a netlist with the second PLL routed internally from the core. Do not specify the input to be Hardwired I/O- Driven or External I/O-Driven, as these options prohibit the connection from the output of the first PLL to the input of the second PLL. v1.1 4 - 39 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Figure 4-32 * Second-Stage PLL Showing Input of 256 MHz from First Stage and Final Output of 280 MHz Figure 4-33 shows the simulation results, where the first PLL's output period is 3.9 ns (~256 MHz), and the stage 2 (final) output period is 3.56 ns (~280 MHz). Stage 1 Output Clock Period Figure 4-33 * ModelSim Simulation Results 4 -4 0 v1.1 Stage 2 Output Clock Period Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Recommended Board-Level Considerations The power to the PLL core is supplied by VCCPLA/B/C/D/E/F (VCCPLx) , and the associated ground connections are supplied by VCOMPLA/B/C/D/E/F (VCOMPLx). When the PLLs are not used, the Actel Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Optionally, the PLL can be turned on/off during normal device operation via the POWERDOWN port (see Table 4-3 on page 4-7). PLL Power Supply Decoupling Scheme The PLL core is designed to tolerate noise levels on the PLL power supply as specified in the datasheets. When operated within the noise limits, the PLL will meet the output peak-to-peak jitter specifications specified in the datasheets. User applications should always ensure the PLL power supply is powered from a noise-free or low-noise power source. However, in situations where the PLL power supply noise level is higher than the tolerable limits, various decoupling schemes can be designed to suppress noise to the PLL power supply. An example is provided in Figure 4-34. The VCCPLx and VCOMPLx pins correspond to the PLL analog power supply and ground. Actel strongly recommends that two ceramic capacitors (10 nF in parallel with 100 nF) be placed close to the power pins (less than 1 inch away). A third generic 10 F electrolytic capacitor is recommended for low-frequency noise and should be placed farther away due to its large physical size. Actel recommends that a 6.8 H inductor be placed between the supply source and the capacitors to filter out any low-/medium- and high-frequency noise. In addition, the PCB layers should be controlled so the VCCPLx and VCOMPLx planes have the minimum separation possible, thus generating a good-quality RF capacitor. For more recommendations, refer to the Board-Level Considerations application note. Recommended 100 nF capacitor: * Producer BC Components, type X7R, 100 nF, 16 V * BC Components part number: 0603B104K160BT * Digi-Key part number: BC1254CT-ND * Digi-Key part number: BC1254TR-ND Recommended 10 nF capacitor: * Surface-mount ceramic capacitor * Producer BC Components, type X7R, 10 nF, 50 V * BC Components part number: 0603B103K500BT * Digi-Key part number: BC1252CT-ND * Digi-Key part number: BC1252TR-ND VCCPLx IGLOO/e or ProASIC3/E Device 10 nF 100 nF 10 F Power Supply VCOMPLx Figure 4-34 * Decoupling Scheme for One PLL (should be replicated for each PLL used) v1.1 4 - 41 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices Conclusion The advanced CCCs of the IGLOO and ProASIC3 families are ideal for applications requiring precise clock management. They integrate easily with the internal low-skew clock networks and provide flexible frequency synthesis, clock de-skewing, and/or time shifting operations. Related Documents Application Notes Board-Level Considerations http://www.actel.com/documents/BoardLevelCons_AN.pdf Handbook Documents UJTAG Applications in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_UJTAG_HBs.pdf Global Resources in Actel Low-Power Flash Devices http://www.actel.com/documents/LPD_Global_HBs.pdf User I/O Naming Conventions in I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/LPD_IO_HBs.pdf User's Guides IGLOO, Fusion, and ProASIC3 Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-006-1 Revised March 2008 4 -4 2 v1.1 Clock Conditioning Circuits in IGLOO and ProASIC3 Devices List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) 51900133-0/5.06 Changes in the Current Version (v1.1) Page Table 4-1 * Low-Power Flash Families and the associated text were updated to include the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 4-3 The "Global Input Selections" section was updated to include 15 k gate devices as supported I/O types for globals, for CCC only. 4-9 Table 4-5 * Number of CCCs by Device Size and Package was revised to include ProASIC3L, IGLOO PLUS, A3P015, AGL015, AGLP030, AGLP060, and AGLP125. 4-13 The "IGLOO and ProASIC3 CCC Locations" section was revised to include 15 k gate devices in the exception statements, as they do not contain PLLs. 4-14 Information about unlocking the PLL was removed from the "Dynamic PLL Configuration" section. 4-19 In the "Dynamic PLL Configuration" section, information was added about running Layout and determining the exact setting of the ports. 4-29 In Table 4-7 * Configuration Bit Descriptions for the CCC Blocks, the following bits were updated to delete "transport to the user" and reference the footnote at the bottom of the table: 79 to 71. 4-22 v1.1 4 - 43 Embedded Memories FlashROM in Actel's Low-Power Flash Devices 5 - FlashROM in Actel's Low-Power Flash Devices Introduction The IGLOO,(R) ProASIC(R)3, and Fusion families of low-power flash-based FPGAs have a dedicated nonvolatile FlashROM memory of 1,024 bits, which provides a unique feature in the FPGA market. The FlashROM can be read, modified, and written using the JTAG (or UJTAG) interface. It can be read but not modified from the FPGA core. Only low-power flash FPGAs contain on-chip user nonvolatile memory (NVM). Architecture of User Nonvolatile FlashROM Low-power flash devices have 1 kbit of user-accessible nonvolatile flash memory on-chip that can be read from the FPGA core fabric. The FlashROM is arranged in eight banks of 128 bits (16 bytes) during programming. The 128 bits in each bank are addressable as 16 bytes during the read-back of the FlashROM from the FPGA core. Figure 5-1 shows the FlashROM logical structure. The FlashROM can only be programmed via the IEEE 1532 JTAG port. It cannot be programmed directly from the FPGA core. When programming, each of the eight 128-bit banks can be selectively reprogrammed. The FlashROM can only be reprogrammed on a bank boundary. Programming involves an automatic, on-chip bank erase prior to reprogramming the bank. The FlashROM supports synchronous read. The address is latched on the rising edge of the clock, and the new output data is stable after the falling edge of the same clock cycle. For more information, refer to the timing diagrams in the appropriate family datasheet DC and Switching Characteristics chapter. The FlashROM can be read on byte boundaries. The upper three bits of the FlashROM address from the FPGA core define the bank being accessed. The lower four bits of the FlashROM address from the FPGA core define which of the 16 bytes in the bank is being accessed. Byte Number in Bank Bank Number 3 MSB of ADDR (READ) 15 14 13 12 11 4 LSB of ADDR (READ) 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 5-1 * FlashROM Architecture v1.1 5-1 FlashROM in Actel's Low-Power Flash Devices FlashROM Support in Low-Power Devices The low-power flash families listed in Table 5-1 support the FlashROM feature and the functions described in this document. Table 5-1 * Family Low-Power Flash Families 1 IGLOO Timing Numbers2 Description Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*FreezeTM IGLOO DC and Switching technology Characteristics IGLOO PLUS Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO PLUS DC and technology and enhanced I/O capabilities. Switching Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional PLLs, IGLOOe DC and Switching and additional I/O standards Characteristics ProASIC3L Low-power, high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and Switching technology Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, and ProASIC3E DC and Switching additional I/O standards Characteristics ProASIC3 Automotive Low-power, high-performance FPGAs qualified for automotive Automotive ProASIC3 DC and applications Switching Characteristics Fusion Low-power mixed-signal Programmable System Chip (PSC) ProASIC3 DC and Switching Characteristics Fusion DC and Power Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 5-1) provide a selection of low-power, secure, live-atpower-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. The Actel Fusion(R) family, based on the highly successful ProASIC3 flash FPGA architecture, has been designed as a high-performance, mixed-signal Programmable System Chip. Fusion supports many peripherals, including embedded flash memory, analog-to-digital converter (ADC), high-drive outputs, RC and crystal oscillators, and real-time counter (RTC). The total available on-chip memory, including the flash array blocks, is greater than that found in SRAM FPGAs. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 5-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 5-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 5 -2 v1.1 FlashROM in Actel's Low-Power Flash Devices CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block ISP AES Decryption Nonvolatile Memory FlashROM (FROM) Charge Pumps Figure 5-2 * Fusion Device Architecture Overview (AFS600) CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block ISP AES Decryption Nonvolatile Memory FlashROM (FROM) Charge Pumps Figure 5-3 * ProASIC3 and IGLOO Device Architecture v1.1 5-3 FlashROM in Actel's Low-Power Flash Devices FlashROM Applications The SmartGen core generator is used to configure FlashROM content. You can configure each page independently. SmartGen enables you to create and modify regions within a page; these regions can be 1 to 16 bytes long (Figure 5-4). Page Number 15 14 13 12 Byte Number in Page 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 5-4 * FlashROM Configuration The FlashROM content can be changed independently of the FPGA core content. It can be easily accessed and programmed via JTAG, depending on the security settings of the device. The SmartGen core generator enables each region to be independently updated (described in the "Programming and Accessing FlashROM" section on page 5-6). This enables you to change the FlashROM content on a per-part basis while keeping some regions "constant" for all parts. These features allow the FlashROM to be used in diverse system applications. Consider the following possible uses of FlashROM: 5 -4 * Internet protocol (IP) addressing (wireless or fixed) * System calibration settings * Restoring configuration after unpredictable system power-down * Device serialization and/or inventory control * Subscription-based business models (e.g., set-top boxes) * Secure key storage * Asset management tracking * Date stamping * Version management v1.1 FlashROM in Actel's Low-Power Flash Devices FlashROM Security Low-power flash devices have an on-chip Advanced Encryption Standard (AES) decryption core, combined with an enhanced version of the Actel flash-based lock technology (FlashLock(R)). Together, they provide unmatched levels of security in a programmable logic device. This security applies to both the FPGA core and FlashROM content. These devices use the 128-bit AES (Rijndael) algorithm to encrypt programming files for secure transmission to the on-chip AES decryption core. The same algorithm is then used to decrypt the programming file. This key size provides approximately 3.4 x 1038 possible 128-bit keys. A computing system that could find a DES key in a second would take approximately 149 trillion years to crack a 128-bit AES key. The 128-bit FlashLock feature in low-power flash devices works via a FlashLock security Pass Key mechanism, where the user locks or unlocks the device with a user-defined key. Refer to Security in Low-Power Flash Devices. If the device is locked with certain security settings, functions such as device read, write, and erase are disabled. This unique feature helps to protect against invasive and noninvasive attacks. Without the correct Pass Key, access to the FPGA is denied. To gain access to the FPGA, the device first must be unlocked using the correct Pass Key. During programming of the FlashROM or the FPGA core, you can generate the security header programming file, which is used to program the AES key and/or FlashLock Pass Key. The security header programming file can also be generated independently of the FlashROM and FPGA core content. The FlashLock Pass Key is not stored in the FlashROM. Low-power flash devices with AES-based security allow for secure remote field updates over public networks such as the Internet, and ensure that valuable intellectual property (IP) remains out of the hands of IP thieves. Figure 5-5 shows this flow diagram. Programming Data Fusion FlashROM FPGA Core AES Encryption Same AES Key AES-128 Decryption Core Untrusted Medium Encrypted Data Encrypted Data Figure 5-5 * Programming FlashROM Using AES v1.1 5-5 FlashROM in Actel's Low-Power Flash Devices Programming and Accessing FlashROM The FlashROM content can only be programmed via JTAG, but it can be read back selectively through the JTAG programming interface, the UJTAG interface, or via direct FPGA core addressing. The pages of the FlashROM can be made secure to prevent read-back via JTAG. In that case, readback on these secured pages is only possible by the FPGA core fabric or via UJTAG. A 7-bit address from the FPGA core defines which of the eight pages (three MSBs) is being read, and which of the 16 bytes within the selected page (four LSBs) are being read. The FlashROM content can be read on a random basis; the access time is 10 ns for a device supporting commercial specifications. The FPGA core will be powered down during writing of the FlashROM content. FPGA power-down during FlashROM programming is managed on-chip, and FPGA core functionality is not available during programming of the FlashROM. Table 5-2 summarizes various FlashROM access scenarios. Table 5-2 * FlashROM Read/Write Capabilities by Access Mode Access Mode FlashROM Read FlashROM Write JTAG Yes Yes UJTAG Yes No FPGA core Yes No Figure 5-6 shows the accessing of the FlashROM using the UJTAG macro. This is similar to FPGA core access, where the 7-bit address defines which of the eight pages (three MSBs) is being read and which of the 16 bytes within the selected page (four LSBs) are being read. Refer to UJTAG Applications in Actel's Low-Power Flash Devices for details on using the UJTAG macro to read the FlashROM. Figure 5-7 on page 5-7 and Figure 5-8 on page 5-7 show the FlashROM access from the JTAG port. The FlashROM content can be read on a random basis. The three-bit address defines which page is being read or updated. UJTAG Address Generation and Data Serialization UIREG [7:0] Enable FlashROM RESET TDO TDI URSTB UDRUPD UDRCK TMS TCK TRST UDRCAP UDRSH Control CLK SDI Addr [6:0] Addr [6:0] Data [7:0] Data[7:0] SDO UTDI UTDO Figure 5-6 * Block Diagram of Using UJTAG to Read FlashROM Contents 5 -6 v1.1 FlashROM in Actel's Low-Power Flash Devices 7-Bit Address from Core 1110000 7 6 5 3 MSB of ADDR (READ) 3-Bit Page Address Word Number in Page Page Number 111 4-Bit Word Address 0000 4 3 2 1 0 15 14 13 12 11 4 LSB of ADDR (READ) 10 9 8 7 6 5 4 3 2 1 0 8-Bit Data 8-Bit Data to FPGA Core 8-Bit Data from Page 7 Word 0 Figure 5-7 * Accessing FlashROM Using FPGA Core ...........................00001:128 Bit Data To/From JTAG Interface 4-Bit Page Address from JTAG Interface Page Number Word Number in Page 15 14 13 12 11 4 LSB of ADDR (READ) 10 9 8 7 6 5 4 3 2 1 0 3 MSB of ADDR (READ) 7 6 5 4 3 2 1 0 Figure 5-8 * Accessing FlashROM Using JTAG Port v1.1 5-7 FlashROM in Actel's Low-Power Flash Devices FlashROM Design Flow The Actel Libero(R) Integrated Design Environment (IDE) software has extensive FlashROM support, including FlashROM generation, instantiation, simulation, and programming. Figure 5-9 shows the user flow diagram. In the design flow, there are three main steps: 1. FlashROM generation and instantiation in the design 2. Simulation of FlashROM design 3. Programming file generation for FlashROM design SmartGen UFC File FlashROM Netlist User Design MEM File Simulator Synthesis User Netlist BackAnnotated Netlist Designer Core Map Security Header Options FlashPoint Programmer Programming Files Figure 5-9 * FlashROM Design Flow FlashROM Generation and Instantiation in the Design The SmartGen core generator, available in Libero IDE and Designer, is the only tool that can be used to generate the FlashROM content. SmartGen has several user-friendly features to help generate the FlashROM contents. Instead of selecting each byte and assigning values, you can create a region within a page, modify the region, and assign properties to that region. The FlashROM user interface, shown in Figure 5-10 on page 5-9, includes the configuration grid, existing regions list, and properties field. The properties field specifies the region-specific information and defines the data used for that region. You can assign values to the following properties: 1. Static Fixed Data--Enables you to fix the data so it cannot be changed during programming time. This option is useful when you have fixed data stored in this region, which is required for the operation of the design in the FPGA. Key storage is one example. 2. Static Modifiable Data--Select this option when the data in a particular region is expected to be static data (such as a version number, which remains the same for a long duration but could conceivably change in the future). This option enables you to avoid changing the value every time you enter new data. 5 -8 v1.1 FlashROM in Actel's Low-Power Flash Devices 3. Read from File--This provides the full flexibility of FlashROM usage to the customer. If you have a customized algorithm for generating the FlashROM data, you can specify this setting. You can then generate a text file with data for as many devices as you wish to program, and load that into the FlashPoint programming file generation software to get programming files that include all the data. SmartGen will optionally pass the location of the file where the data is stored if the file is specified in SmartGen. Each text file has only one type of data format (binary, decimal, hex, or ASCII text). The length of each data file must be shorter than or equal to the selected region length. If the data is shorter than the selected region length, the most significant bits will be padded with 0s. For multiple text files for multiple regions, the first lines are for the first device. In SmartGen, Load Sim. Value From File allows you to load the first device data in the MEM file for simulation. 4. Auto Increment/Decrement--This scenario is useful when you specify the contents of FlashROM for a large number of devices in a series. You can specify the step value for the serial number and a maximum value for inventory control. During programming file generation, the actual number of devices to be programmed is specified and a start value is fed to the software. Figure 5-10 * SmartGen GUI of the FlashROM SmartGen allows you to generate the FlashROM netlist in VHDL, Verilog, or EDIF format. After the FlashROM netlist is generated, the core can be instantiated in the main design like other SmartGen cores. Note that the macro library name for FlashROM is UFROM. The following is a sample FlashROM VHDL netlist that can be instantiated in the main design: library ieee; use ieee.std_logic_1164.all; library fusion; entity FROM_a is port( ADDR : in std_logic_vector(6 downto 0); DOUT : out std_logic_vector(7 downto 0)); end FROM_a; architecture DEF_ARCH of FROM_a is component UFROM generic (MEMORYFILE:string); port(DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7 : out std_logic; ADDR0, ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR6 : in std_logic := 'U') ; v1.1 5-9 FlashROM in Actel's Low-Power Flash Devices end component; component GND port( Y : out std_logic); end component; signal U_7_PIN2 : std_logic ; begin GND_1_net : GND port map(Y => U_7_PIN2); UFROM0 : UFROM generic map(MEMORYFILE => "FROM_a.mem") port map(DO0 => DOUT(0), DO1 => DOUT(1), DO2 => DOUT(2), DO3 => DOUT(3), DO4 => DOUT(4), DO5 => DOUT(5), DO6 => DOUT(6), DO7 => DOUT(7), ADDR0 => ADDR(0), ADDR1 => ADDR(1), ADDR2 => ADDR(2), ADDR3 => ADDR(3), ADDR4 => ADDR(4), ADDR5 => ADDR(5), ADDR6 => ADDR(6)); end DEF_ARCH; SmartGen generates the following files along with the netlist. These are located in the SmartGen folder for the Libero IDE project. 1. MEM (Memory Initialization) file 2. UFC (User Flash Configuration) file 3. Log file The MEM file is used for simulation, as explained in the "Simulation of FlashROM Design" section. The UFC file, generated by SmartGen, has the FlashROM configuration for single or multiple devices and is used during STAPL generation. It contains the region properties and simulation values. Note that any changes in the MEM file will not be reflected in the UFC file. Do not modify the UFC to change FlashROM content. Instead, use the SmartGen GUI to modify the FlashROM content. See the "Programming File Generation for FlashROM Design" section on page 5-11 for a description of how the UFC file is used during the programming file generation. The log file has information regarding the file type and file location. Simulation of FlashROM Design The MEM file has 128 rows of 8 bits, each representing the contents of the FlashROM used for simulation. For example, the first row represents page 0, byte 0; the next row is page 0, byte 1; and so the pattern continues. Note that the three MSBs of the address define the page number, and the four LSBs define the byte number. So, if you send address 0000100 to FlashROM, this corresponds to the page 0 and byte 4 location, which is the fifth row in the MEM file. SmartGen defaults to 0s for any unspecified location of the FlashROM. Besides using the MEM file generated by SmartGen, you can create a binary file with 128 rows of 8 bits each and use this as a MEM file. Actel recommends that you use different file names if you plan to generate multiple MEM files. During simulation, Libero IDE passes the MEM file used as the generic file in the netlist, along with the design files and testbench. If you want to use different MEM files during simulation, you need to modify the generic file reference in the netlist. ..................... UFROM0: UFROM --generic map(MEMORYFILE => "F:\Appsnotes\FROM\test_designs\testa\smartgen\FROM_a.mem") --generic map(MEMORYFILE => "F:\Appsnotes\FROM\test_designs\testa\smartgen\FROM_b.mem") ......................... The VITAL and Verilog simulation models accept the generics passed by the netlist, read the MEM file, and perform simulation with the data in the file. 5 -1 0 v1.1 FlashROM in Actel's Low-Power Flash Devices Programming File Generation for FlashROM Design FlashPoint is the programming software used to generate the programming files for flash devices. Depending on the applications, you can use the FlashPoint software to generate a STAPL file with different FlashROM contents. In each case, optional AES decryption is available. To generate a STAPL file that contains the same FPGA core content and different FlashROM contents, the FlashPoint software needs an Array Map file for the core and UFC file(s) for the FlashROM. This final STAPL file represents the combination of the logic of the FPGA core and FlashROM content. FlashPoint generates the STAPL files you can use to program the desired FlashROM page and/or FPGA core of the FPGA device contents. FlashPoint supports the encryption of the FlashROM content and/or FPGA Array configuration data. In the case of using the FlashROM for device serialization, a sequence of unique FlashROM contents will be generated. When generating a programming file with multiple unique FlashROM contents, you can specify in FlashPoint whether to include all FlashROM content in a single STAPL file or generate a different STAPL file for each FlashROM (Figure 5-11). The programming software (FlashPro) handles the single STAPL file that contains the FlashROM content from multiple devices. It enables you to program the FlashROM content into a series of devices sequentially (Figure 5-11). See the FlashPro User's Guide for information on serial programming. UFC File for Single FlashROM Content FPGA Arrary Map File UFC File for Multiple FlashROM Content FPGA Arrary Map File FlashPoint FlashPoint Security Settings Security Settings Single STAPL File Single STAPL File Single STAPL File Figure 5-11 * Single or Multiple Programming File Generation Figure 5-12 on page 5-12 shows the programming file generator, which enables different STAPL file generation methods. When you select Program FlashROM and choose the UFC file, the FlashROM Settings window appears, as shown in Figure 5-13 on page 5-12. In this window, you can select the FlashROM page you want to program and the data value for the configured regions. This enables you to use a different page for different programming files. v1.1 5 - 11 FlashROM in Actel's Low-Power Flash Devices Figure 5-12 * Programming File Generator Figure 5-13 * Setting FlashROM during Programming File Generation The programming hardware and software can load the FlashROM with the appropriate STAPL file. Programming software handles the single STAPL file that contains multiple FlashROM contents for multiple devices, and programs the FlashROM in sequential order (e.g., for device serialization). This feature is supported in the programming software. After programming with the STAPL file, you can run DEVICE_INFO to check the FlashROM content. 5 -1 2 v1.1 FlashROM in Actel's Low-Power Flash Devices DEVICE_INFO displays the FlashROM content, serial number, Design Name, and checksum as shown below: EXPORT IDCODE[32] = 123261CF EXPORT SILSIG[32] = 00000000 User information : CHECKSUM: 61A0 Design Name: TOP Programming Method: STAPL Algorithm Version: 1 Programmer: UNKNOWN ========================================= FlashROM Information : EXPORT Region_7_0[128] = FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ========================================= Security Setting : Encrypted FlashROM Programming Enabled. Encrypted FPGA Array Programming Enabled. ========================================= The Libero IDE file manager recognizes the UFC and MEM files and displays them in the appropriate view. Libero IDE also recognizes the multiple programming files, if you choose the option to generate multiple files for multiple FlashROM content in Designer. These features enable a user-friendly flow for the FlashROM generation and programming in Libero IDE. Custom Serialization Using FlashROM You can use FlashROM for device serialization or inventory control by using the Auto Inc region or Read From File region. FlashPoint will automatically generate the serial number sequence for the Auto Inc region with the Start Value, Max Value, and Step Value provided. If you have a unique serial number generation scheme that you prefer, the Read From File region allows you to import the file with your serial number scheme programmed into the region. See the FlashPro User's Guide for custom serialization file format information. The following steps describe how to perform device serialization or inventory control using FlashROM: 1. Generate FlashROM using SmartGen. From the Properties section in the FlashROM Settings dialog box, select Auto Inc or Read From File region. For Auto Inc region, specify the desired step value. You will not be able to modify this value in the FlashPoint software. 2. Go through the regular design flow and finish place-and-route. 3. Select Programming File in Designer and open Generate Programming File (Figure 5-12 on page 5-12). 4. Click Program FlashROM, browse to the UFC file, and click Next. The FlashROM Settings window appears, as shown in Figure 5-13 on page 5-12. 5. Select the FlashROM page you want to program and the data value for the configured regions. The STAPL file generated will contain only the data that targets the selected FlashROM page. 6. Modify properties for the serialization. - For Auto Inc region, specify the Start and Max values. - For Read From File region, select the file name of the custom serialization file. 7. Select the FlashROM programming file type you want to generate from the two options below: - Single programming file for all devices: generates one programming file with all FlashROM values. - One programming file per device: generates a separate programming file for each FlashROM value. 8. Enter the number of devices you want to program and generate the required programming file. v1.1 5 - 13 FlashROM in Actel's Low-Power Flash Devices 9. Open the programming software and load the programming file. The programming software, FlashPro3 and Silicon Sculptor II, supports the device serialization feature. If, for some reason, the device fails to program a part during serialization, the software allows you to reuse the serial data or skip the serial data. Refer to the FlashPro User's Guide for details. Conclusion The IGLOO, Fusion, and ProASIC3 families are the only FPGAs that offer on-chip FlashROM support. This document presents information on the FlashROM architecture, possible applications, programming, access through the JTAG and UJTAG interface, and integration into your design. In addition, the Libero IDE tool set enables easy creation and modification of the FlashROM content. The nonvolatile FlashROM block in the FPGA can be customized, enabling multiple applications. Additionally, the security offered by the low-power flash devices keeps both the contents of FlashROM and the FPGA design safe from system over-builders, system cloners, and IP thieves. Related Documents Handbook Documents Security in Low-Power Flash Devices www.actel.com/documents/LPD_Security_HBs.pdf UJTAG Applications in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_UJTAG_HBs.pdf User's Guides FlashPro User's Guide http://www.actel.com/documents/FlashPro_UG.pdf FlashPoint User's Guide http://www.actel.com/documents/FlashPoint_UG.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-007-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) 5 -1 4 Changes in Current Version (v1.1) Page The chapter was updated to include the IGLOO PLUS family and information regarding 15 k gate devices. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. N/A v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices 6 - SRAM and FIFO Memories in Actel's LowPower Flash Devices Introduction As design complexity grows, greater demands are placed upon an FPGA's embedded memory. Actel IGLOO,(R) Fusion, and ProASIC(R)3 devices provide the flexibility of true dual-port and two-port SRAM blocks. The embedded memory, along with built-in, dedicated FIFO control logic, can be used to create cascading RAM blocks and FIFOs without using additional logic gates. IGLOO, IGLOO PLUS, and ProASIC3L FPGAs contain an additional feature that allows the device to be put in a low-power mode called Flash*Freeze.TM In this mode, the core draws minimal power (on the order of 4 to 127 W) and still retains values on the embedded SRAM/FIFO and registers. Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying power management and the use of SRAM/FIFOs. Device Architecture The low-power flash devices feature up to 504 kbits of RAM in 4,608-bit blocks (Figure 6-1 on page 6-2 and Figure 6-2 on page 6-3). The total embedded SRAM for each device can be found in the datasheets. These memory blocks are arranged along the top and bottom of the device to allow better access from the core and I/O (in some devices, they are only available on the north side of the device). Every RAM block has a flexible, hardwired, embedded FIFO controller, enabling the user to implement efficient FIFOs without sacrificing user gates. In the IGLOO and ProASIC3 families of devices, the following memories are supported: * 15 k and 30 k gate devices do not support SRAM and FIFO. * 60 k and 125 k gate devices support memories on the north side of the device only. * 250 k devices and larger support memories on the north and south sides of the device. In Fusion devices, the following memories are supported: * AFS090 and AFS250 support memories on the north side of the device only. * AFS600 and AFS1500 support memories on the north and south sides of the device. v1.1 6-1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption 1 User Nonvolatile FlashRom Flash*Freeze Technology 2 Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 2 Notes: 1. AES decryption not supported in 15 k and 30 k gate devices 2. Flash*Freeze is supported only in IGLOO, IGLOO PLUS, and IGLOOe and ProASIC3L devices. Figure 6-1 * IGLOO and ProASIC3 Device Architecture Overview 6 -2 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Bank 1 Bank 0 CCC/PLL RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block OSC I/Os CCC VersaTile Bank 4 Bank 2 ISP AES Decryption User Nonvolatile FlashROM (FROM) Flash Array Analog Quad Analog Quad Analog Quad Charge Pumps ADC Analog Quad Analog Quad Analog Quad RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Flash Array Analog Quad Analog Quad Analog Quad Analog Quad Bank 3 Figure 6-2 * Fusion Device Architecture Overview (AFS600) v1.1 6-3 SRAM and FIFO Memories in Actel's Low-Power Flash Devices SRAM/FIFO Support in Low-Power Devices The low-power flash families listed in Table 6-1 support SRAM and FIFO blocks and the functions described in this document. Table 6-1 * Low-Power Flash Families Family1 Description Timing Numbers2 IGLOO Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*FreezeTM IGLOO DC and Switching technology Characteristics IGLOO PLUS Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO PLUS DC and technology and enhanced I/O capabilities Switching Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional PLLs, IGLOOe DC and Switching and additional I/O standards Characteristics ProASIC3L Low-power, high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and technology Switching Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, and ProASIC3E DC and additional I/O standards Switching Characteristics ProASIC3 Automotive Low-power, high-performance FPGAs qualified for automotive Automotive ProASIC3 DC applications and Switching Characteristics Fusion Low-power mixed-signal Programmable System Chip (PSC) ProASIC3 DC and Switching Characteristics Fusion DC and Power Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 6-1) provide a selection of low-power, secure, live-atpower-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. The Actel Fusion(R) family, based on the highly successful ProASIC3 flash FPGA architecture, has been designed as a high-performance, mixed-signal Programmable System Chip. Fusion supports many peripherals, including embedded flash memory, analog-to-digital converter (ADC), high-drive outputs, RC and crystal oscillators, and real-time counter (RTC). The total available on-chip memory, including the flash array blocks, is greater than that found in SRAM FPGAs. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 6-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 6-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 6 -4 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices SRAM and FIFO Architecture To meet the needs of high-performance designs, the memory blocks operate strictly in synchronous mode for both read and write operations. The read and write clocks are completely independent, and each can operate at any desired frequency up to 250 MHz. * 4kx1, 2kx2, 1kx4, 512x9 (dual-port RAM--2 read / 2 write or 1 read / 1 write) * 512x9, 256x18 (2-port RAM--1 read / 1 write) * Sync write, sync pipelined / nonpipelined read Automotive ProASIC3 devices support single-port SRAM capabilities or dual-port SRAM only under specific conditions. Dual-port mode is supported if the clocks to the two SRAM ports are the same and 180 out of phase (i.e., the port A clock is the inverse of the port B clock). The Actel Libero(R) Integrated Design Environment (IDE) software macro libraries support a dual-port macro only. For use of this macro as a single-port SRAM, the inputs and clock of one port should be tied off (grounded) to prevent errors during design compile. For use in dual-port mode, the same clock with an inversion between the two clock pins of the macro should be used in the design to prevent errors during compile. The IGLOOe and ProASIC3E memory block includes dedicated FIFO control logic to generate internal addresses and external flag logic (FULL, EMPTY, AFULL, AEMPTY). Simultaneous dual-port read/write and write/write operations at the same address are allowed when certain timing requirements are met. During RAM operation, addresses are sourced by the user logic, and the FIFO controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM array by internal MUXes. The low-power flash device architecture enables the read and write sizes of RAMs to be organized independently, allowing for bus conversion. For example, the write size can be set to 256x18 and the read size to 512x9. Both the write width and read width for the RAM blocks can be specified independently with the WW (write width) and RW (read width) pins. The different DxW configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1. When widths of one, two, or four are selected, the ninth bit is unused. For example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing four-bit values and reading nine-bit values, the ninth bit of a read operation will be undefined. The RAM blocks employ little-endian byte order for read and write operations. Memory Blocks and Macros Memory blocks can be configured with many different aspect ratios, but are generically supported in the macro libraries as one of two memory elements: RAM4K9 or RAM512X18. The RAM4K9 is configured as a true dual-port memory block, and the RAM512X18 is configured as a two-port memory block. Dual-port memory allows the RAM to both read from and write to either port independently. Two-port memory allows the RAM to read from one port and write to the other using a common clock or independent read and write clocks. If needed, the RAM4K9 blocks can be configured as two-port memory blocks. The memory block can be configured as a FIFO by combining the basic memory block with dedicated FIFO controller logic. The FIFO macro is named FIFO4KX18 (Figure 6-3 on page 6-6). Clocks for the RAM blocks can be driven by the VersaNet (global resources) or by regular nets. When using local clock segments, the clock segment region that encompasses the RAM blocks can drive the RAMs. In the dual-port configuration (RAM4K9), each memory block port can be driven by either rising-edge or falling-edge clocks. Each port can be driven by clocks with different edges. Though only a rising-edge clock can drive the physical block itself, the Actel Designer software will automatically bubble-push the inversion to properly implement the falling-edge trigger for the RAM block. v1.1 6-5 SRAM and FIFO Memories in Actel's Low-Power Flash Devices RAM512x18 RAM4K9 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB0 DOUTB0 DINB8 DINB7 RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL0 AFVAL11 AFVAL10 REN RCLK DOUTB8 DOUTB7 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 PIPE ADDRB11 ADDRB10 FIFO4K18 AFVAL0 WADDR8 WADDR7 REN RBLK RCLK WADDR0 WD17 WD16 WD17 WD16 WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RESET WD0 WW1 WW0 WEN WBLK WCLK RPIPE WEN WCLK RESET RESET Note: Automotive ProASIC3 devices restrict RAM4K9 to a single port or to dual ports with the same clock 180 out of phase (inverted) between clock pins. In single-port mode, inputs to port B should be tied to ground to prevent errors during compile. For FIFO4K18, the same clock 180 out of phase (inverted) between clock pins should be used. Figure 6-3 * Supported Basic RAM Macros 6 -6 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices SRAM Features RAM4K9 Macro RAM4K9 is the dual-port configuration of the RAM block (Figure 6-4). The RAM4K9 nomenclature refers to both the deepest possible configuration and the widest possible configuration the dualport RAM block can assume, and does not denote a possible memory aspect ratio. The RAM block can be configured to the following aspect ratios: 4,096x1, 2,048x2, 1,024x4, and 512x9. RAM4K9 is fully synchronous and has the following features: * Two ports that allow fully independent reads and writes at different frequencies * Selectable pipelined or nonpipelined read * Active-low block enables for each port * Toggle control between read and write mode for each port * Active-low asynchronous reset * Pass-through write data or hold existing data on output. In pass-through mode, the data written to the write port will immediately appear on the read port. * Designer software will automatically facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. DINA DOUTA ADDRA BLKA WENA CLKA Write Data Write Data Read Data Read Data Address Address RAM4K9 BLK BLK WEN WEN CLK CLK DINB DOUTB ADDRB BLKB WENB CLKB Reset Note: For timing diagrams of the RAM signals, refer to the appropriate family datasheet. Figure 6-4 * RAM4K9 Simplified Configuration Signal Descriptions for RAM4K9 Note: Automotive ProASIC3 devices support single-port SRAM capabilities, or dual-port SRAM only under specific conditions. Dual-port mode is supported if the clocks to the two SRAM ports are the same and 180 out of phase (i.e., the port A clock is the inverse of the port B clock). Since Actel Libero IDE macro libraries support a dual-port macro only, certain modifications must be made. These are detailed below. The following signals are used to configure the RAM4K9 memory element: WIDTHA and WIDTHB These signals enable the RAM to be configured in one of four allowable aspect ratios (Table 6-2 on page 6-8). Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, WIDTHB should be tied to ground. v1.1 6-7 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Table 6-2 * Allowable Aspect Ratio Settings for WIDTHA[1:0] WIDTHA[1:0] WIDTHB[1:0] DxW 00 00 4kx1 01 01 2kx2 10 10 1kx4 11 11 512x9 Note: The aspect ratio settings are constant and cannot be changed on the fly. BLKA and BLKB These signals are active-low and will enable the respective ports when asserted. When a BLKx signal is deasserted, that port's outputs hold the previous value. Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, BLKB should be tied to ground. WENA and WENB These signals switch the RAM between read and write modes for the respective ports. A LOW on these signals indicates a write operation, and a HIGH indicates a read. Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, WENB should be tied to ground. CLKA and CLKB These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver. Note: For Automotive ProASIC3 devices, dual-port mode is supported if the clocks to the two SRAM ports are the same and 180 out of phase (i.e., the port A clock is the inverse of the port B clock). For use of this macro as a single-port SRAM, the inputs and clock of one port should be tied off (grounded) to prevent errors during design compile. PIPEA and PIPEB These signals are used to specify pipelined read on the output. A LOW on PIPEA or PIPEB indicates a nonpipelined read, and the data appears on the corresponding output in the same clock cycle. A HIGH indicates a pipelined read, and data appears on the corresponding output in the next clock cycle. Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, PIPEB should be tied to ground. For use in dual-port mode, the same clock with an inversion between the two clock pins of the macro should be used in the design to prevent errors during compile. WMODEA and WMODEB These signals are used to configure the behavior of the output when the RAM is in write mode. A LOW on these signals makes the output retain data from the previous read. A HIGH indicates passthrough behavior, wherein the data being written will appear immediately on the output. This signal is overridden when the RAM is being read. Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, WMODEB should be tied to ground. RESET This active-low signal resets the control logic, forces the output hold state registers to zero, disables reads and writes from the SRAM block, and clears the data hold registers when asserted. It does not reset the contents of the memory array. While the RESET signal is active, read and write operations are disabled. As with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. ADDRA and ADDRB These are used as read or write addresses, and they are 12 bits wide. When a depth of less than 4 k is specified, the unused high-order bits must be grounded (Table 6-3 on page 6-9). 6 -8 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, ADDRB should be tied to ground. Table 6-3 * Address Pins Unused/Used for Various Supported Bus Widths ADDRx DxW Unused Used 4kx1 None [11:0] 2kx2 [11] [10:0] 1kx4 [11:10] [9:0] 512x9 [11:9] [8:0] Note: The "x" in ADDRx implies A or B. DINA and DINB These are the input data signals, and they are nine bits wide. Not all nine bits are valid in all configurations. When a data width less than nine is specified, unused high-order signals must be grounded (Table 6-4). Note: When using the SRAM in single-port mode for Automotive ProASIC3 devices, DINB should be tied to ground. DOUTA and DOUTB These are the nine-bit output data signals. Not all nine bits are valid in all configurations. As with DINA and DINB, high-order bits may not be used (Table 6-4). The output data on unused pins is undefined. Table 6-4 * Unused/Used Input and Output Data Pins for Various Supported Bus Widths DINx/DOUTx DxW Unused Used 4kx1 [8:1] [0] 2kx2 [8:2] [1:0] 1kx4 [8:4] [3:0] 512x9 None [8:0] Note: The "x" in DINx or DOUTx implies A or B. RAM512X18 Macro RAM512X18 is the two-port configuration of the same RAM block (Figure 6-5 on page 6-10). Like the RAM4K9 nomenclature, the RAM512X18 nomenclature refers to both the deepest possible configuration and the widest possible configuration the two-port RAM block can assume. In twoport mode, the RAM block can be configured to either the 512x9 aspect ratio or the 256x18 aspect ratio. RAM512X18 is also fully synchronous and has the following features: * Dedicated read and write ports * Active-low read and write enables * Selectable pipelined or nonpipelined read * Active-low asynchronous reset * Designer software will automatically facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. v1.1 6-9 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Write Data WD WADDR Read Data RD Write Address Read Address RADDR RAM512X18 WEN WCLK Write Enable Read Enable Write CLK Read CLK REN RCLK Reset Note: For timing diagrams of the RAM signals, refer to the appropriate family datasheet. Figure 6-5 * 512X18 Two-Port RAM Block Diagram Signal Descriptions for RAM512X18 RAM512X18 has slightly different behavior from RAM4K9, as it has dedicated read and write ports. WW and RW These signals enable the RAM to be configured in one of the two allowable aspect ratios (Table 6-5). Table 6-5 * Aspect Ratio Settings for WW[1:0] WW[1:0] RW[1:0] DxW 01 01 512x9 10 10 256x18 00, 11 Reserved 00, 11 WD and RD These are the input and output data signals, and they are 18 bits wide. When a 512x9 aspect ratio is used for write, WD[17:9] are unused and must be grounded. If this aspect ratio is used for read, RD[17:9] are undefined. WADDR and RADDR These are read and write addresses, and they are nine bits wide. When the 256x18 aspect ratio is used for write or read, WADDR[8] and RADDR[8] are unused and must be grounded. WCLK and RCLK These signals are the write and read clocks, respectively. They can be clocked on the rising or falling edge of WCLK and RCLK. WEN and REN These signals are the write and read enables, respectively. They are both active-low by default. These signals can be configured as active-high. RESET This active-low signal resets the control logic, forces the output hold state registers to zero, disables reads and writes from the SRAM block, and clears the data hold registers when asserted. It does not reset the contents of the memory array. While the RESET signal is active, read and write operations are disabled. As with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. 6 -1 0 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices PIPE This signal is used to specify pipelined read on the output. A LOW on PIPE indicates a nonpipelined read, and the data appears on the output in the same clock cycle. A HIGH indicates a pipelined read, and data appears on the output in the next clock cycle. SRAM Usage The following descriptions refer to the usage of both RAM4K9 and RAM512X18. Clocking The dual-port SRAM blocks are only clocked on the rising edge. SmartGen allows falling-edgetriggered clocks by adding inverters to the netlist, hence achieving dual-port SRAM blocks that are clocked on either edge (rising or falling). For dual-port SRAM, each port can be clocked on either edge and by separate clocks by port. Note that for Automotive ProASIC3, the same clock, with an inversion between the two clock pins of the macro, should be used in design to prevent errors during compile. IGLOO and ProASIC3 devices support inversion (bubble-pushing) throughout the FPGA architecture, including the clock input to the SRAM modules. Inversions added to the SRAM clock pin on the design schematic or in the HDL code will be automatically accounted for during design compile without incurring additional delay in the clock path. The two-port SRAM can be clocked on the rising or falling edge of WCLK and RCLK. If negative-edge RAM and FIFO clocking is selected for memory macros, clock edge inversion management (bubble-pushing) is automatically used within the IGLOO and ProASIC3 development tools, without performance penalty. Modes of Operation There are two read modes and one write mode: * Read Nonpipelined (synchronous--1 clock edge): In the standard read mode, new data is driven onto the RD bus in the same clock cycle following RA and REN valid. The read address is registered on the read port clock active edge, and data appears at RD after the RAM access time. Setting PIPE to OFF enables this mode. * Read Pipelined (synchronous--2 clock edges): The pipelined mode incurs an additional clock delay from address to data but enables operation at a much higher frequency. The read address is registered on the read port active clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting PIPE to ON enables this mode. * Write (synchronous--1 clock edge): On the write clock active edge, the write data is written into the SRAM at the write address when WEN is HIGH. The setup times of the write address, write enables, and write data are minimal with respect to the write clock. RAM Initialization Each SRAM block can be individually initialized on power-up by means of the JTAG port using the UJTAG mechanism. The shift register for a target block can be selected and loaded with the proper bit configuration to enable serial loading. The 4,608 bits of data can be loaded in a single operation. FIFO Features The FIFO4KX18 macro is created by merging the RAM block with dedicated FIFO logic (Figure 6-6 on page 6-12). Since the FIFO logic can only be used in conjunction with the memory block, there is no separate FIFO controller macro. As with the RAM blocks, the FIFO4KX18 nomenclature does not refer to a possible aspect ratio, but rather to the deepest possible data depth and the widest possible data width. FIFO4KX18 can be configured into the following aspect ratios: 4,096x1, 2,048x2, 1,024x4, 512x9, and 256x18. In addition to being fully synchronous, the FIFO4KX18 also has the following features: * Four FIFO flags: Empty, Full, Almost-Empty, and Almost-Full * EMPTY flag is synchronized to the read clock * FULL flag is synchronized to the write clock * Both Almost-Empty and Almost-Full flags have programmable thresholds v1.1 6 - 11 SRAM and FIFO Memories in Actel's Low-Power Flash Devices * Active-low asynchronous reset * Active-low block enable * Active-low write enable * Active-high read enable * Ability to configure the FIFO to either stop counting after the empty or full states are reached or to allow the FIFO counters to continue * Designer software will automatically facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. WD Write Data Full Flag FULL AFULL WEN WCLK Read Data RD Empty Flag Almost-Full Flag EMPTY Almost-Empty Flag FIFO4KX18 Write Enable Read Enable Write Clock AEMPTY REN Read Clock RCLK Reset Figure 6-6 * FIFO4KX18 Block Diagram RBLK REN RPIPE FREN FWEN RD RW[2:0] WW[2:0] RD[17:0] WD[17:0] RCLK WCLK RAM RADD[J:0] WADD[J:0] REN WEN WD RCLK WCLK CNT 12 E = ESTOP AFVAL FULL AFULL AEMPTY WBLK WEN CNT 12 SUB 12 AEVAL E = FSTOP EMPTY Reset Note: For FIFO4K18, the same clock 180 out of phase (inverted) between clock pins should be used. Figure 6-7 * RAM Block with Embedded FIFO Controller The FIFOs maintain a separate read and write address. Whenever the difference between the write address and the read address is greater than or equal to the almost-full value (AFVAL), the Almost- 6 -1 2 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Full flag is asserted. Similarly, the Almost-Empty flag is asserted whenever the difference between the write address and read address is less than or equal to the almost-empty value (AEVAL). Due to synchronization between the read and write clocks, the Empty flag will deassert after the second read clock edge from the point that the write enable asserts. However, since the Empty flag is synchronized to the read clock, it will assert after the read clock reads the last data in the FIFO. Also, since the Full flag is dependent on the actual hardware configuration, it will assert when the actual physical implementation of the FIFO is full. For example, when a user configures a 128x18 FIFO, the actual physical implementation will be a 256x18 FIFO element. Since the actual implementation is 256x18, the Full flag will not trigger until the 256x18 FIFO is full, even though a 128x18 FIFO was requested. For this example, the AlmostFull flag can be used instead of the Full flag to signal when the 128th data word is reached. To accommodate different aspect ratios, the almost-full and almost-empty values are expressed in terms of data bits instead of data words. SmartGen translates the user's input, expressed in data words, into data bits internally. SmartGen allows the user to select the thresholds for the AlmostEmpty and Almost-Full flags in terms of either the read data words or the write data words, and makes the appropriate conversions for each flag. After the empty or full states are reached, the FIFO can be configured so the FIFO counters either stop or continue counting. For timing numbers, refer to the appropriate family datasheet. Signal Descriptions for FIFO4K18 The following signals are used to configure the FIFO4K18 memory element: WW and RW These signals enable the FIFO to be configured in one of the five allowable aspect ratios (Table 6-6). Table 6-6 * Aspect Ratio Settings for WW[2:0] WW[2:0] RW[2:0] DxW 000 000 4kx1 001 001 2kx2 010 010 1kx4 011 011 512x9 100 100 256x18 101, 110, 111 Reserved 101, 110, 111 WBLK and RBLK These signals are active-low and will enable the respective ports when LOW. When the RBLK signal is HIGH, that port's outputs hold the previous value. WEN and REN Read and write enables. WEN is active-low and REN is active-high by default. These signals can be configured as active-high or -low. WCLK and RCLK These are the clock signals for the synchronous read and write operations. For FIFO4K18, the same clock 180 out of phase (inverted) between clock pins should be used. Note: (For Automotive ProASIC3) These can be driven independently or with the same driver. RPIPE This signal is used to specify pipelined read on the output. A LOW on RPIPE indicates a nonpipelined read, and the data appears on the output in the same clock cycle. A HIGH indicates a pipelined read, and data appears on the output in the next clock cycle. RESET This active-low signal resets the control logic and forces the output hold state registers to zero when asserted. It does not reset the contents of the memory array (Table 6-7 on page 6-14). v1.1 6 - 13 SRAM and FIFO Memories in Actel's Low-Power Flash Devices While the RESET signal is active, read and write operations are disabled. As with any asynchronous RESET signal, care must be taken not to assert it too close to the edges of active read and write clocks. WD This is the input data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. When a data width less than 18 is specified, unused higher-order signals must be grounded (Table 6-7). RD This is the output data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. Like the WD bus, high-order bits become unusable if the data width is less than 18. The output data on unused pins is undefined (Table 6-7). Table 6-7 * Input Data Signal Usage for Different Aspect Ratios DxW WD/RD Unused 4kx1 WD[17:1], RD[17:1] 2kx2 WD[17:2], RD[17:2] 1kx4 WD[17:4], RD[17:4] 512x9 WD[17:9], RD[17:9] 256x18 - ESTOP, FSTOP ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e., the EMPTY flag goes HIGH). A HIGH on this signal inhibits the counting. FSTOP is used to stop the FIFO write counter from further counting once the FIFO is full (i.e., the FULL flag goes HIGH). A HIGH on this signal inhibits the counting. For more information on these signals, refer to the "ESTOP and FSTOP Usage" section on page 6-15. FULL, EMPTY When the FIFO is full and no more data can be written, the FULL flag asserts HIGH. The FULL flag is synchronous to WCLK to inhibit writing immediately upon detection of a full condition and to prevent overflows. Since the write address is compared to a resynchronized (and thus timedelayed) version of the read address, the FULL flag will remain asserted until two WCLK active edges after a read operation eliminates the full condition. When the FIFO is empty and no more data can be read, the EMPTY flag asserts HIGH. The EMPTY flag is synchronous to RCLK to inhibit reading immediately upon detection of an empty condition and to prevent underflows. Since the read address is compared to a resynchronized (and thus timedelayed) version of the write address, the EMPTY flag will remain asserted until two RCLK active edges after a write operation removes the empty condition. For more information on these signals, refer to the "FIFO Flag Usage Considerations" section on page 6-15. AFULL, AEMPTY These are programmable flags and will be asserted on the threshold specified by AFVAL and AEVAL, respectively. When the number of words stored in the FIFO reaches the amount specified by AEVAL while reading, the AEMPTY output will go HIGH. Likewise, when the number of words stored in the FIFO reaches the amount specified by AFVAL while writing, the AFULL output will go HIGH. AFVAL, AEVAL The AEVAL and AFVAL pins are used to specify the almost-empty and almost-full threshold values. They are 12-bit signals. For more information on these signals, refer to the "FIFO Flag Usage Considerations" section on page 6-15. 6 -1 4 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices FIFO Usage ESTOP and FSTOP Usage The ESTOP pin is used to stop the read counter from counting any further once the FIFO is empty (i.e., the EMPTY flag goes HIGH). Likewise, the FSTOP pin is used to stop the write counter from counting any further once the FIFO is full (i.e., the FULL flag goes HIGH). The FIFO counters in the IGLOOe and ProASIC3E device start the count at zero, reach the maximum depth for the configuration (e.g., 511 for a 512x9 configuration), and then restart at zero. An example application for ESTOP, where the read counter keeps counting, would be writing to the FIFO once and reading the same content over and over without doing another write. FIFO Flag Usage Considerations The AEVAL and AFVAL pins are used to specify the 12-bit AEMPTY and AFULL threshold values. The FIFO contains separate 12-bit write address (WADDR) and read address (RADDR) counters. WADDR is incremented every time a write operation is performed, and RADDR is incremented every time a read operation is performed. Whenever the difference between WADDR and RADDR is greater than or equal to AFVAL, the AFULL output is asserted. Likewise, whenever the difference between WADDR and RADDR is less than or equal to AEVAL, the AEMPTY output is asserted. To handle different read and write aspect ratios, AFVAL and AEVAL are expressed in terms of total data bits instead of total data words. When users specify AFVAL and AEVAL in terms of read or write words, the SmartGen tool translates them into bit addresses and configures these signals automatically. SmartGen configures the AFULL flag to assert when the write address exceeds the read address by at least a predefined value. In a 2kx8 FIFO, for example, a value of 1,500 for AFVAL means that the AFULL flag will be asserted after a write when the difference between the write address and the read address reaches 1,500 (there have been at least 1,500 more writes than reads). It will stay asserted until the difference between the write and read addresses drops below 1,500. The AEMPTY flag is asserted when the difference between the write address and the read address is less than a predefined value. In the example above, a value of 200 for AEVAL means that the AEMPTY flag will be asserted when a read causes the difference between the write address and the read address to drop to 200. It will stay asserted until that difference rises above 200. Note that the FIFO can be configured with different read and write widths; in this case, the AFVAL setting is based on the number of write data entries, and the AEVAL setting is based on the number of read data entries. For aspect ratios of 512x9 and 256x18, only 4,096 bits can be addressed by the 12 bits of AFVAL and AEVAL. The number of words must be multiplied by 8 and 16 instead of 9 and 18. The SmartGen tool automatically uses the proper values. To avoid halfwords being written or read, which could happen if different read and write aspect ratios were specified, the FIFO will assert FULL or EMPTY as soon as at least one word cannot be written or read. For example, if a two-bit word is written and a four-bit word is being read, the FIFO will remain in the empty state when the first word is written. This occurs even if the FIFO is not completely empty, because in this case, a complete word cannot be read. The same is applicable in the full state. If a four-bit word is written and a two-bit word is read, the FIFO is full and one word is read. The FULL flag will remain asserted because a complete word cannot be written at this point. Variable Aspect Ratio and Cascading Variable aspect ratio and cascading allow users to configure the memory in the width and depth required. The memory block can be configured as a FIFO by combining the basic memory block with dedicated FIFO controller logic. The FIFO macro is named FIFO4KX18. Low-power flash device RAM can be configured as 1, 2, 4, 9, or 18 bits wide. By cascading the memory blocks, any multiple of those widths can be created. The RAM blocks can be from 256 to 4,096 bits deep, depending on the aspect ratio, and the blocks can also be cascaded to create deeper areas. Refer to the aspect ratios available for each macro cell in the "SRAM Features" section on page 6-7. The largest continuous configurable memory area is equal to half the total memory available on the device, because the RAM is separated into two groups, one on each side of the device. The Actel SmartGen core generator will automatically configure and cascade both RAM and FIFO blocks. Cascading is accomplished using dedicated memory logic and does not consume user gates for depths up to 4,096 bits deep and widths up to 18, depending on the configuration. Deeper memory will utilize some user gates to multiplex the outputs. v1.1 6 - 15 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Generated RAM and FIFO macros can be created as either structural VHDL or Verilog for easy instantiation into the design. Users of Actel Libero IDE can create a symbol for the macro and incorporate it into a design schematic. Table 6-10 on page 6-17 shows the number of memory blocks required for each of the supported depth and width memory configurations, and for each depth and width combination. For example, a 256-bit deep by 32-bit wide two-port RAM would consist of two 256x18 RAM blocks. The first 18 bits would be stored in the first RAM block, and the remaining 14 bits would be implemented in the other 256x18 RAM block. This second RAM block would have four bits of unused storage. Similarly, a dual-port memory block that is 8,192 bits deep and 8 bits wide would be implemented using 16 memory blocks. The dual-port memory would be configured in a 4,096x1 aspect ratio. These blocks would then be cascaded two deep to achieve 8,192 bits of depth, and eight wide to achieve the eight bits of width. Table 6-8 and Table 6-9 show the maximum potential width and depth configuration for each device. Note that 15 k and 30 k gate devices do not support RAM or FIFO. Table 6-8 * Memory Availability per IGLOO and ProASIC3 Devices Maximum Potential Width1 Maximum Potential Depth2 Device IGLOO/ IGLOO PLUS ProASIC3/ ProASIC3L RAM Blocks Depth Width Depth Width AGL060 / AGLP060 A3P060 4 256 72 (4x18) 16,384 (4,096x4) 1 AGL125 AGLP125 A3P125 8 256 144 (8x18) 32,768 (4,094x8) 1 AGL250 A3P250/L 8 256 144 (8x18) 32,768 (4,096x8) 1 A3P400 12 256 216 (12x18) 49,152 (4,096x12) 1 AGL600 A3P600/L 24 256 432 (24x18) 98,304 (4,096x24) 1 AGL1000 A3P1000/L 32 256 576 (32x18) 131,072 (4,096x32) 1 AGLE600 A3PE600 24 256 432 (24x18) 98,304 (4,096x24) 1 A3PE1500 60 256 1,080 (60x18) 245,760 (4,096x60) 1 A3PE3000/L 112 256 2,016 (112x18) 458,752 (4,096x112) 1 AGLE3000 Notes: 1. Maximum potential width uses the two-port configuration. 2. Maximum potential depth uses the dual-port configuration. Table 6-9 * Memory Availability per Fusion Device Maximum Potential Width1 RAM Blocks Depth Width AFS090 6 256 AFS250 8 256 AFS600 24 AFS1500 60 Device Depth Width 108 (6x18) 24,576 (4,094x6) 1 144 (8x18) 32,768 (4,094x8) 1 256 432 (24x18) 98,304 (4,096x24) 1 256 1,080 (60x18) 245,760 (4,096x60) 1 Notes: 1. Maximum potential width uses the two-port configuration. 2. Maximum potential depth uses the dual-port configuration. 6 -1 6 Maximum Potential Depth2 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Table 6-10 * RAM and FIFO Memory Block Consumption Depth 256 Two-Port 1 Number Block Configuration 2 Number Block Configuration 4 Number Block Configuration 8 Number Block Configuration 9 Number Block Configuration Width 16 Number Block Configuration 18 Number Block Configuration 32 Number Block Configuration 36 Number Block Configuration 64 Number Block Configuration 72 Number Block Configuration Note: Dual-Port 512 1,024 2,048 4,096 8,192 16,384 32,768 65,536 Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port 1 1 1 1 1 1 2 4 8 16 x 1 Any Any Any 1,024 x 4 2,048 x 2 4,096 x 1 2 x (4,096 x 1) Cascade Deep 4 x (4,096 x 1) Cascade Deep 8 x (4,096 x 1) Cascade Deep 16 x (4,096 x 1) Cascade Deep 16 32 1 1 1 1 1 2 4 8 Any Any Any 1,024x4 2,048 x 2 2 x (4,096 x 1) Cascaded Wide 4 x (4,096 x 1) Cascaded 2 Deep and 2 Wide 8 x (4,096 x 1) Cascaded 4 Deep and 2 Wide 1 1 1 1 2 4 8 16 Any Any Any 1,024 x 4 2 x (2,048 x 2) Cascaded Wide 4 x (4,096 x 1) Cascaded Wide 4 x (4,096 x 1) Cascaded 2 Deep and 4 Wide 16 x (4,096 x 1) Cascaded 4 Deep and 4 Wide 16 x (4,096 x 1) 32 x (4,096 x 1) Cascaded 8 Deep Cascaded 16 Deep and 2 Wide and 2 Wide 32 1 1 1 2 4 8 16 32 64 Any Any Any 2 x (1,024 x 4) Cascaded Wide 4 x (2,048 x 2) Cascaded Wide 8 x (4,096 x 1) Cascaded Wide 16 x (4,096 x 1) Cascaded 2 Deep and 8 Wide 32 x (4,096 x 1) Cascaded 4 Deep and 8 Wide 64 x (4,096 x 1) Cascaded 8 Deep and 8 Wide 1 1 1 2 4 8 16 32 Any Any Any 2 x (512 x 9) Cascaded Deep 4 x (512 x 9) Cascaded Deep 8 x (512 x 9) Cascaded Deep 16 x (512 x 9) Cascaded Deep 32 x (512 x 9) Cascaded Deep 1 1 1 4 8 16 32 64 256 x 18 256 x 18 256 x 18 4 x (1,024 x 4) Cascaded Wide 8 x (2,048 x 2) Cascaded Wide 16 x (4,096 x 1) Cascaded Wide 32 x (4,096 x 1) Cascaded 2 Deep and 16 Wide 32 x (4,096 x 1) Cascaded 4 Deep and 16 Wide 18 32 1 2 2 4 8 256 x 8 2 x (512 x 9) Cascaded Wide 2 x (512 x 9) Cascaded Wide 4 x (512 x 9) Cascaded 2 Deep and 2 Wide 8 x (512 x 9) Cascaded 4 Deep and 2 Wide 16 x (512 x 9) 16 x (512 x 9) Cascaded 8 Deep Cascaded 16 Deep and 2 Wide and 2 Wide 2 4 4 8 16 32 64 2 x (256 x 18) Cascaded Wide 4 x (512 x 9) Cascaded Wide 4 x (512 x 9) Cascaded Wide 8 x (1,024 x 4) Cascaded Wide 16 x (2,048 x 2) Cascaded Wide 32 x (4,096 x 1) Cascaded Wide 64 x (4,096 x 1) Cascaded 2 Deep and 32 Wide 2 4 4 8 16 32 2 x (256 x 18) Cascaded Wide 4 x (512 x 9) Cascaded Wide 4 x (512 x 9) Cascaded Wide 4 x (512 x 9) Cascaded 2 Deep and 4 Wide 16 x (512 x 9) Cascaded 4 Deep and 4 Wide 16 x (512 x 9) Cascaded 8 Deep and 4 Wide 4 8 8 16 32 64 4 x (256 x 18) Cascaded Wide 8 x (512 x 9) Cascaded Wide 8 x (512 x 9) Cascaded Wide 16 x (1,024 x 4) Cascaded Wide 32 x (2,048 x 2) Cascaded Wide 64 x (4,096 x 1) Cascaded Wide 4 8 8 16 32 4 x (256 x 18) Cascaded Wide 8 x (512 x 9) Cascaded Wide 8 x (512 x 9) Cascaded Wide 16 x (512 x 9) Cascaded Wide 16 x (512 x 9) Cascaded 4 Deep and 8 Wide 64 32 x (4,096 x 1) 64 x (4,096 x 1) Cascaded 8 Deep Cascaded 16 Deep and 4 Wide and 4 Wide Memory configurations represented by grayed cells are not supported. v1.1 6 - 17 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Initializing the RAM/FIFO The SRAM blocks can be initialized with data to use as a lookup table (LUT). Data initialization can be accomplished either by loading the data through the design logic or through the UJTAG interface. The UJTAG macro is used to allow access from the JTAG port to the internal logic in the device. By sending the appropriate initialization string to the JTAG Test Access Port (TAP) Controller, the designer can put the JTAG circuitry into a mode that allows the user to shift data into the array logic through the JTAG port using the UJTAG macro. For a more detailed explanation of the UJTAG macro, refer to UJTAG Applications in Actel's Low-Power Flash Devices. A user interface is required to receive the user command, initialization data, and clock from the UJTAG macro. The interface must synchronize and load the data into the correct RAM block of the design. The main outputs of the user interface block are the following: * Memory block chip select: Selects a memory block for initialization. The chip selects signals for each memory block that can be generated from different user-defined pockets or simple logic, such as a ring counter (see below). * Memory block write address: Identifies the address of the memory cell that needs to be initialized. * Memory block write data: The interface block receives the data serially from the UTDI port of the UJTAG macro and loads it in parallel into the write data ports of the memory blocks. * Memory block write clock: Drives the WCLK of the memory block and synchronizes the write data, write address, and chip select signals. Figure 6-8 shows the user interface between UJTAG and the memory blocks. RAM1 WD WADDR WCLK UJTAG TRST TDO TDI TRST TDO TDI TMS TMS TCK TCK UIREG[7:0] URSTB User Interface IR[7:0] Reset UDRUPD DR_UPDATE UDRSH UDRCAP UDRCK UTDI UTDO DR_SHIFT DR_CAPTURE DR_CLK DIN DOUT WDATA WADDR WCLK WEN1 WEN RAM2 WD WADDR WCLK WEN2 WEN WEN3 RAM3 WD WADDR WCLK WEN Figure 6-8 * Interfacing TAP Ports and SRAM Blocks An important component of the interface between the UJTAG macro and the RAM blocks is a serial-in/parallel-out shift register. The width of the shift register should equal the data width of the RAM blocks. The RAM data arrives serially from the UTDI output of the UJTAG macro. The data must be shifted into a shift register clocked by the JTAG clock (provided at the UDRCK output of the UJTAG macro). Then, after the shift register is fully loaded, the data must be transferred to the write data port of the RAM block. To synchronize the loading of the write data with the write address and write clock, the output of the shift register can be pipelined before driving the RAM block. The write address can be generated in different ways. It can be imported through the TAP using a different instruction opcode and another shift register, or generated internally using a simple 6 -1 8 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices counter. Using a counter to generate the address bits and sweep through the address range of the RAM blocks is recommended, since it reduces the complexity of the user interface block and the board-level JTAG driver. Moreover, using an internal counter for address generation speeds up the initialization procedure, since the user only needs to import the data through the JTAG port. The designer may use different methods to select among the multiple RAM blocks. Using counters along with demultiplexers is one approach to set the write enable signals. Basically, the number of RAM blocks needing initialization determines the most efficient approach. For example, if all the blocks are initialized with the same data, one enable signal is enough to activate the write procedure for all of them at the same time. Another alternative is to use different opcodes to initialize each memory block. For a small number of RAM blocks, using counters is an optimal choice. For example, a ring counter can be used to select from multiple RAM blocks. The clock driver of this counter needs to be controlled by the address generation process. Once the addressing of one block is finished, a clock pulse is sent to the (ring) counter to select the next memory block. Figure 6-9 illustrates a simple block diagram of an interface block between UJTAG and RAM blocks. Serial-to-Port Shift Register UTDI SIN POUT UDRSH Enable SOUT UDRCK CLK UTDO Data Reg. Q D n n CLK UDRUPDI UIREG WDATA WCLK In Compare Result with Defined Opcode En Reset CLK URSTB Chip Select WEN1 Ring Counter WEN2 WENi m En Reset CLK Addr Counter Q m WADDR Binary Counter Figure 6-9 * Block Diagram of a Sample User Interface In the circuit shown in Figure 6-9, the shift register is enabled by the UDRSH output of the UJTAG macro. The counters and chip select outputs are controlled by the value of the TAP Instruction Register. The comparison block compares the UIREG value with the "start initialization" opcode value (defined by the user). If the result is true, the counters start to generate addresses and activate the WEN inputs of appropriate RAM blocks. The UDRUPD output of the UJTAG macro, also shown in Figure 6-9, is used for generating the write clock (WCLK) and synchronizing the data register and address counter with WCLK. UDRUPD is HIGH when the TAP Controller is in the Data Register Update state, which is an indication of completing the loading of one data word. Once the TAP Controller goes into the Data Register Update state, the UDRUPD output of the UJTAG macro goes HIGH. Therefore, the pipeline register and the address counter place the proper data and address on the outputs of the interface block. Meanwhile, WCLK is defined as the inverted UDRUPD. This will provide enough time (equal to the UDRUPD HIGH time) for the data and address to be placed at the proper ports of the RAM block before the rising edge of WCLK. The inverter is not required if the RAM blocks are clocked at the falling edge of the write clock. An example of this is described in the "Example of RAM Initialization" section on page 6-20. v1.1 6 - 19 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Example of RAM Initialization This section of the document presents a sample design in which a 4x4 RAM block is being initialized through the JTAG port. A test feature has been implemented in the design to read back the contents of the RAM after initialization to verify the procedure. The interface block of this example performs two major functions: initialization of the RAM block and running a test procedure to read back the contents. The clock output of the interface is either the write clock (for initialization) or the read clock (for reading back the contents). The Verilog code for the interface block is included in the "Sample Verilog Code" section on page 6-21. For simulation purposes, users can declare the input ports of the UJTAG macro for easier assignment in the testbench. However, the UJTAG input ports should not be declared on the top level during synthesis. If the input ports of the UJTAG are declared during synthesis, the synthesis tool will instantiate input buffers on these ports. The input buffers on the ports will cause Compile to fail in Designer. Figure 6-10 shows the simulation results for the initialization step of the example design. The CLK_OUT signal, which is the clock output of the interface block, is the inverted DR_UPDATE output of the UJTAG macro. It is clear that it gives sufficient time (while the TAP Controller is in the Data Register Update state) for the write address and data to become stable before loading them into the RAM block. Figure 6-11 presents the test procedure of the example. The data read back from the memory block matches the written data, thus verifying the design functionality. Figure 6-10 * Simulation of Initialization Step Figure 6-11 * Simulation of the Test Procedure of the Example 6 -2 0 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices The ROM emulation application is based on RAM block initialization. If the user's main design has access only to the read ports of the RAM block (RADDR, RD, RCLK, and REN), and the contents of the RAM are already initialized through the TAP, then the memory blocks will emulate ROM functionality for the core design. In this case, the write ports of the RAM blocks are accessed only by the user interface block, and the interface is activated only by the TAP Instruction Register contents. Users should note that the contents of the RAM blocks are lost in the absence of applied power. However, the 1 kbit of flash memory, FlashROM, in low-power flash devices can be used to retain data after power is removed from the device. Refer to FlashROM in Actel's Low-Power Flash Devices for more information. Sample Verilog Code Interface Block define Initialize_start 8'h22 //INITIALIZATION START COMMAND VALUE define Initialize_stop 8'h23 //INITIALIZATION START COMMAND VALUE module interface(IR, rst_n, data_shift, clk_in, data_update, din_ser, dout_ser, test, test_out,test_clk,clk_out,wr_en,rd_en,write_word,read_word,rd_addr, wr_addr); input [7:0] IR; input [3:0] read_word; //RAM DATA READ BACK input rst_n, data_shift, clk_in, data_update, din_ser; //INITIALIZATION SIGNALS input test, test_clk; //TEST PROCEDURE CLOCK AND COMMAND INPUT output [3:0] test_out; //READ DATA output [3:0] write_word; //WRITE DATA output [1:0] rd_addr; //READ ADDRESS output [1:0] wr_addr; //WRITE ADDRESS output dout_ser; //TDO DRIVER output clk_out, wr_en, rd_en; wire wire wire wire wire [3:0] write_word; [1:0] rd_addr; [1:0] wr_addr; [3:0] Q_out; enable, test_active; reg clk_out; //SELECT CLOCK FOR INITIALIZATION OR READBACK TEST always @(enable or test_clk or data_update) begin case ({test_active}) 1 : clk_out = test_clk ; 0 : clk_out = !data_update; default : clk_out = 1'b1; endcase end assign assign assign assign assign assign test_active = test && (IR == 8'h23); enable = (IR == 8'h22); wr_en = !enable; rd_en = !test_active; test_out = read_word; dout_ser = Q_out[3]; //4-bit SIN/POUT SHIFT REGISTER shift_reg data_shift_reg (.Shiften(data_shift), .Shiftin(din_ser), .Clock(clk_in), .Q(Q_out)); //4-bit PIPELINE REGISTER D_pipeline pipeline_reg (.Data(Q_out), .Clock(data_update), .Q(write_word)); v1.1 6 - 21 SRAM and FIFO Memories in Actel's Low-Power Flash Devices // addr_counter counter_1 (.Clock(data_update), .Q(wr_addr), .Aset(rst_n), .Enable(enable)); addr_counter counter_2 (.Clock(test_clk), .Q(rd_addr), .Aset(rst_n), .Enable( test_active)); endmodule Interface Block / UJTAG Wrapper This example is a sample wrapper, which connects the interface block to the UJTAG and the memory blocks. // WRAPPER module top_init (TDI, TRSTB, TMS, TCK, TDO, test, test_clk, test_ out); input TDI, TRSTB, TMS, TCK; output TDO; input test, test_clk; output [3:0] test_out; wire wire wire wire wire [7:0] IR; reset, DR_shift, DR_cap, init_clk, DR_update, data_in, data_out; clk_out, wen, ren; [3:0] word_in, word_out; [1:0] write_addr, read_addr; UJTAG UJTAG_U1 (.UIREG0(IR[0]), .UIREG1(IR[1]), .UIREG2(IR[2]), .UIREG3(IR[3]), .UIREG4(IR[4]), .UIREG5(IR[5]), .UIREG6(IR[6]), .UIREG7(IR[7]), .URSTB(reset), .UDRSH(DR_shift), .UDRCAP(DR_cap), .UDRCK(init_clk), .UDRUPD(DR_update), .UT-DI(data_in), .TDI(TDI), .TMS(TMS), .TCK(TCK), .TRSTB(TRSTB), .TDO(TDO), .UT-DO(data_out)); mem_block RAM_block (.DO(word_out), .RCLOCK(clk_out), .WCLOCK(clk_out), .DI(word_in), .WRB(wen), .RDB(ren), .WAD-DR(write_addr), .RADDR(read_addr)); interface init_block (.IR(IR), .rst_n(reset), .data_shift(DR_shift), .clk_in(init_clk), .data_update(DR_update), .din_ser(data_in), .dout_ser(data_out), .test(test), .test_out(test_out), .test_clk(test_clk), .clk_out(clk_out), .wr_en(wen), .rd_en(ren), .write_word(word_in), .read_word(word_out), .rd_addr(read_addr), .wr_addr(write_addr)); endmodule Address Counter module addr_counter (Clock, Q, Aset, Enable); input Clock; output [1:0] Q; input Aset; input Enable; reg [1:0] Qaux; always @(posedge Clock or negedge Aset) begin if (!Aset) Qaux <= 2'b11; else if (Enable) Qaux <= Qaux + 1; end assign Q = Qaux; endmodule 6 -2 2 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Pipeline Register module D_pipeline (Data, Clock, Q); input [3:0] Data; input Clock; output [3:0] Q; reg [3:0] Q; always @ (posedge Clock) Q <= Data; endmodule 4x4 RAM Block (created by SmartGen Core Generator) module mem_block(DI,DO,WADDR,RADDR,WRB,RDB,WCLOCK,RCLOCK); input [3:0] DI; output [3:0] DO; input [1:0] WADDR, RADDR; input WRB, RDB, WCLOCK, RCLOCK; wire WEBP, WEAP, VCC, GND; VCC VCC_1_net(.Y(VCC)); GND GND_1_net(.Y(GND)); INV WEBUBBLEB(.A(WRB), .Y(WEBP)); RAM4K9 RAMBLOCK0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(GND), .ADDRA8(GND), .ADDRA7(GND), .ADDRA6(GND), .ADDRA5(GND), .ADDRA4(GND), .ADDRA3(GND), .ADDRA2(GND), .ADDRA1(RADDR[1]), .ADDRA0(RADDR[0]), .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(GND), .ADDRB8(GND), .ADDRB7(GND), .ADDRB6(GND), .ADDRB5(GND), .ADDRB4(GND), .ADDRB3(GND), .ADDRB2(GND), .ADDRB1(WADDR[1]), .ADDRB0(WADDR[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND), .DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(GND), .DINA0(GND), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND), .DINB4(GND), .DINB3(DI[3]), .DINB2(DI[2]), .DINB1(DI[1]), .DINB0(DI[0]), .WIDTHA0(GND), .WIDTHA1(VCC), .WIDTHB0(GND), .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND), .BLKA(WEAP), .BLKB(WEBP), .WENA(VCC), .WENB(GND), .CLKA(RCLOCK), .CLKB(WCLOCK), .RESET(VCC), .DOUTA8(), .DOUTA7(), .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(DO[3]), .DOUTA2(DO[2]), .DOUTA1(DO[1]), .DOUTA0(DO[0]), .DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), .DOUTB4(), .DOUTB3(), .DOUTB2(), .DOUTB1(), .DOUTB0()); INV WEBUBBLEA(.A(RDB), .Y(WEAP)); endmodule v1.1 6 - 23 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Software Support The SmartGen core generator is the easiest way to select and configure the memory blocks (Figure 6-12). SmartGen automatically selects the proper memory block type and aspect ratio, and cascades the memory blocks based on the user's selection. SmartGen also configures any additional signals that may require tie-off. SmartGen will attempt to use the minimum number of blocks required to implement the desired memory. When cascading, SmartGen will configure the memory for width before configuring for depth. For example, if the user requests a 256x8 FIFO, SmartGen will use a 512x9 FIFO configuration, not 256x18. Figure 6-12 * SmartGen Core Generator Interface 6 -2 4 v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices SmartGen enables the user to configure the desired RAM element to use either a single clock for read and write, or two independent clocks for read and write. The user can select the type of RAM as well as the width/depth and several other parameters (Figure 6-13). Figure 6-13 * SmartGen Memory Configuration Interface SmartGen also has a Port Mapping option that allows the user to specify the names of the ports generated in the memory block (Figure 6-14). Figure 6-14 * Port Mapping Interface for SmartGen-Generated Memory v1.1 6 - 25 SRAM and FIFO Memories in Actel's Low-Power Flash Devices SmartGen also configures the FIFO according to user specifications. Users can select no flags, static flags, or dynamic flags. Static flag settings are configured using configuration flash and cannot be altered without reprogramming the device. Dynamic flag settings are determined by register values and can be altered without reprogramming the device by reloading the register values either from the design or through the UJTAG interface described in the "Initializing the RAM/FIFO" section on page 6-18. SmartGen can also configure the FIFO to continue counting after the FIFO is full. In this configuration, the FIFO write counter will wrap after the counter is full and continue to write data. With the FIFO configured to continue to read after the FIFO is empty, the read counter will also wrap and re-read data that was previously read. This mode can be used to continually read back repeating data patterns stored in the FIFO (Figure 6-15). Figure 6-15 * SmartGen FIFO Configuration Interface FIFOs configured using SmartGen can also make use of the port mapping feature to configure the names of the ports. Limitations Users should be aware of the following limitations when configuring SRAM blocks for low-power flash devices: 6 -2 6 * SmartGen does not track the target device in a family, so it cannot determine if a configured memory block will fit in the target device. * Dual-port RAMs with different read and write aspect ratios are not supported. * Cascaded memory blocks can only use a maximum of 64 blocks of RAM. * The Full flag of the FIFO is sensitive to the maximum depth of the actual physical FIFO block, not the depth requested in the SmartGen interface. v1.1 SRAM and FIFO Memories in Actel's Low-Power Flash Devices Conclusion IGLOO, Fusion, and ProASIC3 devices provide users with extremely flexible SRAM blocks for most design needs, with the ability to choose between an easy-to-use dual-port memory or a wide-word two-port memory. Used with the built-in FIFO controllers, these memory blocks also serve as highly efficient FIFOs that do not consume user gates when implemented. The Actel SmartGen core generator provides a fast and easy way to configure these memory elements for use in designs. Related Documents Handbook Documents UJTAG Applications in Actel's Low-Power Flash Devices www.actel.com/documents/LPD_UJTAG_HBs.pdf FlashROM in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_FlashROM_HBs.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-008-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) Changes in the Current Version (v1.1) Page The "Introduction" section was updated to include the IGLOO PLUS family. 6-1 The "Device Architecture" section was updated to state that 15 k gate devices do not support SRAM and FIFO. 6-1 The first note in Figure 6-1 * IGLOO and ProASIC3 Device Architecture Overview was updated to include mention of 15 k gate devices, and IGLOO PLUS was added to the second note. 6-3 The Table 6-1 * Low-Power Flash Families table and associated text were updated to include the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 6-4 The text introducing Table 6-8 * Memory Availability per IGLOO and ProASIC3 Devices was updated to replace "A3P030 and AGL030" with "15 k and 30 k gate devices. Table 6-8 * Memory Availability per IGLOO and ProASIC3 Devices was updated to remove AGL400 and AGLE1500 and include IGLOO PLUS and ProASIC3L devices. 6-16 v1.1 6 - 27 I/O Descriptions and Usage 7 - I/O Structures in IGLOO and ProASIC3 Devices Introduction Low-power flash devices feature a flexible I/O structure, supporting a range of mixed voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V) through bank-selectable voltages. IGLOO,(R) ProASIC3(R)L, and ProASIC3 families support Standard, Standard Plus, and Advanced I/Os. Users designing I/O solutions are faced with a number of implementation decisions and configuration choices that can directly impact the efficiency and effectiveness of their final design. The flexible I/O structure, supporting a wide variety of voltages and I/O standards, enables users to meet the growing challenges of their many diverse applications. The Actel Libero(R) Integrated Design Environment (IDE) provides an easy way to implement I/Os that will result in robust I/O design. This document first describes the two different I/O types in terms of the standards and features they support. It then explains the individual features and how to implement them in Actel's Libero IDE. I/O / Q0 1 Input Register 2 Input Register To FPGA Core Y Pull-Up/-Down Resistor Control CLR/PRE I/O / Q1 3 Input ICE Register PAD CLR/PRE I/O / ICLK Signal Drive Strength and Slew Rate Control A I/O / D0 E = Enable Pin 4 Output OCE Register From FPGA Core CLR/PRE I/O / D1 / ICE ICE I/O / OCLK 5 Output Register CLR/PRE I/O / OE OCE I/O / CLR or I/O / PRE / OCE 6 Output Enable Register CLR/PRE Figure 7-1 * I/O Block Logical Representation v1.1 7-1 I/O Structures in IGLOO and ProASIC3 Devices Low-Power Flash Device I/O Support The low-power flash families listed in Table 7-1 support I/Os and the functions described in this document. Table 7-1 * Low-Power Flash Families Family1 IGLOO Timing Numbers2 Description Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO DC and Switching technology Characteristics IGLOO PLUS Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO PLUS DC and Switching technology and enhanced I/O capabilities Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional IGLOOe DC and Switching PLLs, and additional I/O standards Characteristics ProASIC3L Low-power, high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and Switching technology Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, and ProASIC3E DC and Switching additional I/O standards Characteristics ProASIC3 DC and Switching Characteristics ProASIC3 Low-power, high-performance FPGAs qualified for automotive Automotive ProASIC3 DC and Automotive applications Switching Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 7-1) provide a selection of low-power, secure, liveat-power-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 7-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 7-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 7 -2 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices Advanced I/Os--IGLOO, ProASIC3L, and ProASIC3 Table 7-2 and Table 7-3 show the voltages and compatible I/O standards for IGLOO, ProASIC3L, and ProASIC3 families. I/Os provide programmable slew rates (except 30 k gate devices), drive strengths, and weak pull-up and pull-down circuits. 3.3 V PCI and 3.3 V PCI-X are 5 V-tolerant. See the "5 V Input Tolerance" section on page 7-20 for possible implementations of 5 V tolerance. All I/Os are in a known state during power-up, and any power-up sequence is allowed without current impact. Refer to the "I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)" section in the datasheet for more information. During power-up, before reaching activation levels, the I/O input and output buffers are disabled while the weak pull-up is enabled. Activation levels are described in the datasheet. Table 7-2 * Supported I/O Standards IGLOO AGL030 AGL060 AGL125 AGL250 AGL600 AGL1000 ProASIC3 A3P250/ A3P600/ A3P1000/ A3P030 A3P060 A3P125 A3P250L A3P400 A3P600L A3P1000L Single-Ended LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5 V, LVCMOS 2.5/5.0 V 3.3 V PCI/PCI-X - - - - Differential LVPECL, LVDS, BLVDS, M-LVDS I/O Banks and I/O Standards Compatibility I/Os are grouped into I/O voltage banks. Each I/O voltage bank has dedicated I/O supply and ground voltages (VMV/GNDQ for input buffers and VCCI /GND for output buffers). This isolation is necessary to minimize simultaneous switching noise from the input and output (SSI and SSO). The switching noise (ground bounce and power bounce) is generated by the output buffers and transferred into input buffer circuits, and vice versa. Because of these dedicated supplies, only I/Os with compatible standards can be assigned to the same I/O voltage bank. Table 7-3 shows the required voltage compatibility values for each of these voltages. There are four I/O banks on the 250 k gate through 1 M gate devices. There are two I/O banks on the 30 k, 60 k, and 125 k gate devices. I/O standards are compatible if their VCCI and VMV values are identical. VMV and GNDQ are "quiet" input power supply pins and are not used on 30 k gate devices (Table 7-3). Table 7-3 * VCCI Voltages and Compatible IGLOO and ProASIC3 Standards VCCI and VMV (typical) Compatible Standards 3.3 V LVTTL/LVCMOS 3.3, PCI 3.3, PCI-X 3.3 LVPECL 2.5 V LVCMOS 2.5, LVCMOS 2.5/5.0, LVDS, BLVDS, M-LVDS 1.8 V LVCMOS 1.8 1.5 V LVCMOS 1.5 v1.1 7-3 I/O Structures in IGLOO and ProASIC3 Devices I/O Banks Advanced I/Os are divided into multiple technology banks. Each device has two to four banks, and the number of banks is device-dependent as described above. The bank types have different characteristics, such as drive strength, the I/O standards supported, and timing and power differences. There are three types of banks: Advanced I/O banks, Standard Plus I/O banks, and Standard I/O banks. Advanced I/O banks offer single-ended and differential capabilities. These banks are available on the east and west sides of 250 k, 400 k, 600 k and 1 M gate devices. Standard Plus I/O banks offer LVTTL/LVCMOS and PCI single-ended I/O standards. These banks are available on the north and south sides of 250 k, 400 k, 600 k, and 1 M gate devices as well as all sides of 125 k and 60 k devices. Standard I/O banks offer LVTTL/LVCMOS single-ended I/O standards. These banks are available on all sides of 30 k gate devices. Table 7-5 shows the I/O bank types, devices and bank locations supported, drive strength, slew rate control, and supported standards. Orphan--All inputs and disabled outputs are voltage-tolerant up to 3.3 V. For more information about I/O and global assignments to I/O banks in a device, refer to the specific pin table for the device in the packaging section of the datasheet and the "User I/O Naming Convention" section on page 7-32. Table 7-4 * IGLOO and ProASIC3 Bank Type Definitions and Differences I/O Standards Supported I/O Bank Type Device and Bank Location Drive Strength LVTTL/ LVCMOS PCI/PCI-X LVPECL, LVDS, BLVDS, M-LVDS Refer to Table 7-14 on page 7-29 Not Supported Not Supported Standard Plus 60 k and 125 k gate devices Refer to Table 7-15 (all banks) on page 7-29 Not Supported North and south banks of Refer to Table 7-15 250 k and 1 M gate devices on page 7-29 Not Supported East and west banks of 250 k Refer to Table 7-16 and 1 M gate devices on page 7-30 Standard Advanced 7 -4 30 k gate devices (all banks) v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices Features Supported on Every I/O Table 7-5 lists all features supported by transmitter/receiver for single-ended and differential I/Os. Table 7-6 on page 7-6 lists the performance of each IO technology. Table 7-5 * I/O Features Feature All I/O Single-Ended Transmitter Features Description * High performance (Table 7-6 on page 7-6) * Electrostatic discharge (ESD) protection * I/O register combining option * Hot-swap: - 30 k gate devices: hot-swap in every mode - All other IGLOO and ProASIC3 devices: no hot-swap * Output slew rate: 2 slew rates (except 30 k gate devices) * Weak pull-up and pull-down resistors * Output drive: 3 drive strengths * Programmable output loading * Skew between output buffer enable/disable time: 2 ns delay on rising edge and 0 ns delay on falling edge (see the "Selectable Skew between Output Buffer Enable and Disable Times" section on page 7-25 for more information) * LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs * 5 V-input-tolerant page 7-19) * Separate ground plane for GNDQ pin and power plane for VMV pin are used for input buffer to reduce output-induced noise. Differential Receiver Features--250 k * through 1 M Gate Devices Separate ground plane for GNDQ pin and power plane for VMV pin are used for input buffer to reduce output-induced noise. CMOS-Style LVDS, BLVDS, M-LVDS, or * LVPECL Transmitter Two I/Os and external resistors are used to provide a CMOS-style LVDS, DDR LVDS, BLVDS, and M-LVDS/LVPECL transmitter solution. Single-Ended Receiver Features receiver (Table 7-12 * High slew rate * Weak pull-up and pull-down resistors * Programmable output loading v1.1 on 7-5 I/O Structures in IGLOO and ProASIC3 Devices Table 7-6 * Maximum I/O Frequency for Single-Ended and Differential I/Os in All Banks in IGLOO and ProASIC Devices (maximum drive strength and high slew selected) Maximum Performance 7 -6 Specification ProASIC3 IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage LVTTL/LVCMOS 3.3 V 200 MHz 180 MHz TBD LVCMOS 2.5 V 250 MHz 230 MHz TBD LVCMOS 1.8 V 200 MHz 180 MHz TBD LVCMOS 1.5 V 130 MHz 120 MHz TBD PCI 200 MHz 180 MHz TBD PCI-X 200 MHz 180 MHz TBD LVDS 350 MHz 300 MHz TBD LVPECL 350 MHz 300 MHz TBD v1.1 IGLOO V2, 1.2 V DC Core Supply Voltage I/O Structures in IGLOO and Pro ASIC3 Devices I/O Architecture I/O Tile The I/O tile provides a flexible, programmable structure for implementing a large number of I/O standards. In addition, the registers available in the I/O tile can be used to support highperformance register inputs and outputs, with register enable if desired (Figure 7-2). The registers can also be used to support the JESD-79C Double Data Rate (DDR) standard within the I/O structure (see DDR for Actel's Low-Power Flash Devices for more information). In addition, the registers available in the I/O tile can be used to support high-performance register inputs and outputs, with register enable if desired (Figure 7-2). As depicted in Figure 7-2, all I/O registers share one CLR port. The output register and output enable register share one CLK port. I/O / Q0 1 Input Register 2 Input Register To FPGA Core Y Pull-Up/-Down Resistor Control CLR/PRE I/O / Q1 3 Input ICE Register PAD CLR/PRE I/O / ICLK Signal Drive Strength and Slew Rate Control A I/O / D0 E = Enable Pin 4 Output OCE Register From FPGA Core CLR/PRE I/O / D1 / ICE ICE I/O / OCLK 5 Output Register CLR/PRE I/O / OE OCE I/O / CLR or I/O / PRE / OCE 6 Output Enable Register CLR/PRE Figure 7-2 * I/O Block Logical Representation v1.1 7-7 I/O Structures in IGLOO and ProASIC3 Devices I/O Bank Structure Low-power flash device I/Os are divided into multiple technology banks. The number of banks is device-dependent. The IGLOOe, ProASIC3EL, and ProASIC3E devices have eight banks (two per side); and IGLOO, ProASIC3L, and ProASIC3 devices have two to four banks. Each bank has its own VCCI power supply pin. Multiple I/O standards can co-exist within a single I/O bank. In IGLOOe, ProASIC3EL, and ProASIC3E devices, each I/O bank is subdivided into VREF minibanks. These are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All I/Os in a given minibank share a common VREF line (only one VREF pin is needed per VREF minibank). Therefore, if an I/O in a VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use the voltage assigned to that pin. If the location of the VREF pin is selected manually in the software, the user must satisfy VREF rules (refer to the I/O Software Control in Low-Power Flash Devices). If the user does not pick the VREF pin manually, the software automatically assigns the VREF pin. Figure 7-3 is a snapshot of a section of the I/O ring, showing the basic elements of an I/O tile, as viewed from the Designer place-and-route tool's MultiView Navigator (MVN). I/O Pad/Buffer I/O Logic (assigned) { Other Minibanks N Side P Side (assigned) (unassigned) Diffio Tile Minibank Figure 7-3 * Snapshot of an I/O Tile Low-power flash device I/Os are implemented using two tile types: I/O and differential I/O (diffio). The diffio tile is built up using two I/O tiles, which form an I/O pair (P side and N side). These I/O pairs are used according to differential I/O standards. Both the P and N sides of the diffio tile include an I/O buffer and two I/O logic blocks (auxiliary and main logic). Every minibank (E devices only) is built up from multiple diffio tiles. The number of the minibank depends on the different-size dies. Refer to the "I/O Architecture" section on page 7-7 for an illustration of the minibank structure. Figure 7-4 on page 7-9 shows a simplified diagram of the I/O buffer circuitry. The Output Enable signal (OE) enables the output buffer to pass the signal from the core logic to the pin. The output buffer contains ESD protection circuitry, an n-channel transistor that shunts all ESD surges (up to the limit of the device ESD specification) to GND. This transistor also serves as an output pull-down resistor. Each output buffer also contains programmable slew rate, drive strength, programmable power-up state (pull-up/-down resistor), hot-swap, 5 V tolerance, and clamp diode control circuitry. Multiple flash switches (not shown in Figure 7-4 on page 7-9) are programmed by user selections in the software to activate different I/O features. 7 -8 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices Output Buffer Hot-Swap, 5 V Tolerance, and Clamp Diode Control VCCI VCCI VCCI Weak Pull-Up Control (from core) OE (from core logic) Output Buffer Logic and Enable Skew Circuit ESD Protection1 Clamp Diode I/O PAD Drive Strength and Output Slew Rate Control Clamp Diode Output Signal (from core logic) Weak PullDown Control (from core) ESD Protection1 Input Buffer Input Buffer Standard2 and Schmitt Trigger Control Input Signal to Core Logic Programmable Input Delay Control Notes: 1. All NMOS transistors connected to the I/O pad serve as ESD protection. 2. See Table 7-2 on page 7-3 for available I/O standards. Figure 7-4 * Simplified I/O Buffer Circuitry I/O Registers Each I/O module contains several input, output, and enable registers. Refer to Figure 7-4 for a simplified representation of the I/O block. The number of input registers is selected by a set of switches (not shown in Figure 7-2 on page 7-7) between registers to implement single-ended or differential data transmission to and from the FPGA core. The Designer software sets these switches for the user. A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input Register 2 does not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O register combining must satisfy certain rules. v1.1 7-9 I/O Structures in IGLOO and ProASIC3 Devices I/O Standards Single-Ended Standards These I/O standards use a push-pull CMOS output stage with a voltage referenced to system ground to designate logical states. The input buffer configuration, output drive, and I/O supply voltage (VCCI) vary among the I/O standards (Figure 7-5). VCCI OUT IN VCCI Device 1 Device 2 GND GND Figure 7-5 * Single-Ended I/O Standard Topology The advantage of these standards is that a common ground can be used for multiple I/Os. This simplifies board layout and reduces system cost. Their low-edge-rate (dv/dt) data transmission causes less electromagnetic interference (EMI) on the board. However, they are not suitable for high-frequency (>200 MHz) switching due to noise impact and higher power consumption. LVTTL (Low-Voltage TTL) This is a general-purpose standard (EIA/JESD8-B) for 3.3 V applications. It uses an LVTTL input buffer and a push-pull output buffer. The LVTTL output buffer can have up to six different programmable drive strengths. The default drive strength is 12 mA. VCCI is 3.3 V. Refer to "I/O Programmable Features" on page 7-14 for details. LVCMOS (Low-Voltage CMOS) The low-power flash devices provide four different kinds of LVCMOS: LVCMOS 3.3 V, LVCMOS 2.5 V, LVCMOS 1.8 V, and LVCMOS 1.5 V. LVCMOS 3.3 V is an extension of the LVCMOS standard (JESD8-B- compliant) used for general-purpose 3.3 V applications. LVCMOS 2.5 V is an extension of the LVCMOS standard (JESD8-5-compliant) used for general-purpose 2.5 V applications. LVCMOS 2.5 V for the 30 k gate devices has a clamp diode to VCCI, but for all other devices there is no clamp diode. There is yet another standard supported by IGLOO and ProASIC3 devices (except A3P030): LVCMOS 2.5/5.0 V. This standard is similar to LVCMOS 2.5 V, with the exception that it can support up to 3.3 V on the input side (2.5 V output drive). LVCMOS 1.8 V is an extension of the LVCMOS standard (JESD8-7-compliant) used for general-purpose 1.8 V applications. LVCMOS 1.5 V is an extension of the LVCMOS standard (JESD8-11-compliant) used for general-purpose 1.5 V applications. The VCCI values for these standards are 3.3 V, 2.5 V, 1.8 V, and 1.5 V, respectively. All these versions use a 3.3 V-tolerant CMOS input buffer and a push-pull output buffer. Like LVTTL, the output buffer has up to seven different programmable drive strengths (2, 4, 6, 8, 12, 16, and 24 mA). Refer to "I/O Programmable Features" on page 7-14 for details. 3.3 V PCI (Peripheral Component Interface) This standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses an LVTTL input buffer and a push-pull output buffer. With the aid of an external resistor, this I/O standard can be 5 V-compliant for low-power flash devices. It does not have programmable drive strength. 7 -1 0 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices 3.3 V PCI-X (Peripheral Component Interface Extended) An enhanced version of the PCI specification, 3.3 V PCI-X can support higher average bandwidths; it increases the speed that data can move within a computer from 66 MHz to 133 MHz. It is backward-compatible, which means devices can operate at conventional PCI frequencies (33 MHz and 66 MHz). PCI-X is more fault-tolerant than PCI. It also does not have programmable drive strength. Voltage-Referenced Standards I/Os using these standards are referenced to an external reference voltage (VREF) and are supported on E devices only. HSTL Class I and II (High-Speed Transceiver Logic) These are general-purpose, high-speed 1.5 V bus standards (EIA/JESD 8-6) for signaling between integrated circuits. The signaling range is 0 V to 1.5 V, and signals can be either single-ended or differential. HSTL requires a differential amplifier input buffer and a push-pull output buffer. The reference voltage (VREF) is 0.75 V. These standards are used in the memory bus interface with data switching capability of up to 400 MHz. The other advantages of these standards are low power and fewer EMI concerns. HSTL has four classes, of which low-power flash devices support Class I and II. These classes are defined by standard EIA/JESD 8-6 from the Electronic Industries Alliance (EIA): * Class I - Unterminated or symmetrically parallel-terminated * Class II - Series-terminated * Class III - Asymmetrically parallel-terminated * Class IV - Asymmetrically double-parallel-terminated SSTL2 Class I and II (Stub Series Terminated Logic 2.5 V) These are general-purpose 2.5 V memory bus standards (JESD 8-9) for driving transmission lines, designed specifically for driving the DDR SDRAM modules used in computer memory. SSTL2 requires a differential amplifier input buffer and a push-pull output buffer. The reference voltage (VREF) is 1.25 V. SSTL3 Class I and II (Stub Series Terminated Logic 3.3 V) These are general-purpose 3.3 V memory bus standards (JESD 8-8) for driving transmission lines. SSTL3 requires a differential amplifier input buffer and a push-pull output buffer. The reference voltage (VREF) is 1.5 V. VCCI OUT IN Device 2 Device 1 GND VCCI VREF GND VREF Figure 7-6 * SSTL and HSTL Topology v1.1 7 - 11 I/O Structures in IGLOO and ProASIC3 Devices GTL 2.5 V (Gunning Transceiver Logic 2.5 V) This is a low-power standard (JESD 8.3) for electrical signals used in CMOS circuits that allows for low electromagnetic interference at high transfer speeds. It has a voltage swing between 0.4 V and 1.2 V and typically operates at speeds of between 20 and 40 MHz. VCCI must be connected to 2.5 V. The reference voltage (VREF) is 0.8 V. GTL 3.3 V (Gunning Transceiver Logic 3.3 V) This is the same as GTL 2.5 V above, except VCCI must be connected to 3.3 V. GTL+ (Gunning Transceiver Logic Plus) This is an enhanced version of GTL that has defined slew rates and higher voltage levels. It requires a differential amplifier input buffer and an open-drain output buffer. Even though the output is open-drain, VCCI must be connected to either 2.5 V or 3.3 V. The reference voltage (VREF) is 1 V. Differential Standards These standards require two I/Os per signal (called a "signal pair"). Logic values are determined by the potential difference between the lines, not with respect to ground. This is why differential drivers and receivers have much better noise immunity than single-ended standards. The differential interface standards offer higher performance and lower power consumption than their single-ended counterparts. Two I/O pins are used for each data transfer channel. Both differential standards require resistor termination. VCCI OUTp INp DEVICE 1 OUTn INn GND VREF VCCI DEVICE 2 GND VREF Figure 7-7 * Differential Topology LVPECL (Low-Voltage Positive Emitter Coupled Logic) LVPECL requires that one data bit be carried through two signal lines; therefore, two pins are needed per input or output. It also requires external resistor termination. The voltage swing between the two signal lines is approximately 850 mV. When the power supply is +3.3 V, it is commonly referred to as Low-Voltage PECL (LVPECL). Refer to the device datasheet for the full implementation of the LVPECL transmitter and receiver. LVDS (Low-Voltage Differential Signal) LVDS is a moderate-speed differential signaling system, in which the transmitter generates two different voltages that are compared at the receiver. LVDS uses a differential driver connected to a terminated receiver through a constant-impedance transmission line. It requires that one data bit be carried through two signal lines; therefore, the user will need two pins per input or output. It also requires external resistor termination. The voltage swing between the two signal lines is approximately 350 mV. VCCI is 2.5 V. Low-power flash devices contain dedicated circuitry supporting a high-speed LVDS standard that has its own user specification. Refer to the device datasheet for the full implementation of the LVDS transmitter and receiver. 7 -1 2 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices BLVDS/M-LVDS Bus LVDS (BLVDS) refers to bus interface circuits based on LVDS technology. Multipoint LVDS (M-LVDS) specifications extend the LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive current required by BLVDS and M-LVDS to accommodate the loading. The driver requires series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus, since the driver can be located anywhere on the bus. These configurations can be implemented using TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 7-8 on page 7-13. The input and output buffer delays are available in the LVDS sections in the datasheet. Example: For a bus consisting of 20 equidistant loads, the terminations given in EQ 7-1 provide the required differential voltage, in worst-case industrial operating conditions, at the farthest receiver: RS = 60 , RT = 70 , given ZO = 50 (2") and a Zstub = 50 (~1.5"). EQ 7-1 Receiver Transceiver EN + R RS Driver D EN - + RS T RS - + RS Receiver EN EN RS Transceiver + RS R RS Zstub Zstub Zstub Zstub Zstub Zstub Zstub Z0 Z0 Z0 Z0 EN - + RS Zstub T RS ... Zstub Z0 RT BIBUF_LVDS RS Zstub Z0 Z0 Z0 Z0 Z0 Z0 RT Z0 Figure 7-8 * A BLVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers v1.1 7 - 13 I/O Structures in IGLOO and ProASIC3 Devices I/O Features Low-power flash devices support multiple I/O features that make board design easier. For example, an I/O feature like Schmitt Trigger in the ProASIC3E input buffer saves the board space that would be used by an external Schmitt trigger for a slow or noisy input signal. These features are also programmable for each I/O, which in turn gives flexibility in interfacing with other components. The following is a detailed description of all available features in low-power flash devices. I/O Programmable Features Low-power flash devices offer many flexible I/O features to support a wide variety of board designs. Some of the features are programmable, with a range for selection. Table 7-7 lists programmable I/O features and their ranges. Table 7-7 * Programmable I/O Features (user control via I/O Attribute Editor) Feature Description Range Slew Control Output slew rate HIGH, LOW Output Drive (mA) Output drive strength 2, 4, 6, 8, 12, 16, 24 Skew Control Output tristate enable Delay option ON, OFF Resistor Pull Resistor pull circuit Input Delay Input delay OFF, 0-7 Schmitt Trigger Schmitt trigger for input only ON, OFF Up, Down, None Note: Limitations of these features with respect to different devices are discussed in later sections. Hot-Swap Support A pull-up clamp diode must not be present in the I/O circuitry if the hot-swap feature is used. The 3.3 V PCI standard requires a pull-up clamp diode on the I/O, so it cannot be selected if hot-swap capability is required. The A3P030 device does not support 3.3 V PCI, so it is the only device in the ProASIC3 family that supports the hot-swap feature. All devices in the ProASIC3E family are hotswappable. All standards except LVCMOS 2.5/5.0 V and 3.3 V PCI/PCI-X support the hot-swap feature. The hot-swap feature appears as a read-only check box in the I/O Attribute Editor that shows whether an I/O is hot-swappable or not. Refer to Power-Up/-Down Behavior of ProASIC3/E Devices for details on hot-swapping. Hot-swapping (also called hot-plugging) is the operation of hot insertion or hot removal of a card in a powered-up system. The levels of hot-swap support and examples of related applications are described in Table 7-8 on page 7-15 to Table 7-11 on page 7-16. The I/Os also need to be configured in hot-insertion mode if hot-plugging compliance is required. The AGL030 and A3P030 devices have an I/O structure that allows the support of Level 3 and Level 4 hot-swap with only two levels of staging. 7 -1 4 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices Table 7-8 * Hot-Swap Level 1 Description Cold-swap Power Applied to Device No Bus State - Card Ground Connection - Device Circuitry Connected to Bus Pins - Example Application System and card with Actel FPGA chip are powered down, and the card is plugged into the system. Then the power supplies are turned on for the system but not for the FPGA on the card. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices: Compliant Other IGLOO/ProASIC3 devices: Compliant if bus switch used to isolate FPGA I/Os from rest of system IGLOOe/ProASIC3E devices: Compliant I/Os can but do not have to be set to hot-insertion mode. Table 7-9 * Hot-Swap Level 2 Description Hot-swap while reset Power Applied to Device Yes Bus State Held in reset state Card Ground Connection Reset must be maintained for 1 ms before, during, and after insertion/removal. Device Circuitry Connected to Bus Pins - Example Application In the PCI hot-plug specification, reset control circuitry isolates the card busses until the card supplies are at their nominal operating levels and stable. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices, all IGLOOe/ProASIC3E devices: Compliant I/Os can but do not have to be set to hot-insertion mode. Other IGLOO/ProASIC3 devices: Compliant v1.1 7 - 15 I/O Structures in IGLOO and ProASIC3 Devices Table 7-10 * Hot-Swap Level 3 Description Hot-swap while bus idle Power Applied to Device Yes Bus State Held idle (no ongoing I/O processes during insertion/removal) Card Ground Connection Reset must be maintained for 1 ms before, during, and after insertion/removal. Device Circuitry Connected to Bus Pins Must remain glitch-free during power-up or power-down Example Application Board bus shared with card bus is "frozen," and there is no toggling activity on the bus. It is critical that the logic states set on the bus signal not be disturbed during card insertion/removal. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices, all IGLOOe/ProASIC3E devices: Compliant with two levels of staging (first: GND; second: all other pins) Other IGLOO/ProASIC3 devices: Compliant: Option A - Two levels of staging (first: GND; second: all other pins) together with bus switch on the I/Os Option B - Three levels of staging (first: GND; second: supplies; third: all other pins) Table 7-11 * Hot-Swap Level 4 Description Hot-swap on an active bus Power Applied to Device Yes Bus State Bus may have active I/O processes ongoing, but device being inserted or removed must be idle. Card Ground Connection Reset must be maintained for 1 ms before, during, and after insertion/removal. Device Circuitry Connected to Bus Pins Must remain glitch-free during power-up or power-down Example Application There is activity on the system bus, and it is critical that the logic states set on the bus signal not be disturbed during card insertion/removal. Compliance of IGLOO and ProASIC3 Devices 30 k gate devices, all IGLOOe/ProASIC3E devices: Compliant with two levels of staging (first: GND; second: all other pins) Other IGLOO/ProASIC3 devices: Compliant: Option A - Two levels of staging (first: GND; second: all other pins) together with bus switch on the I/Os Option B - Three levels of staging (first: GND; second: supplies; third: all other pins) 7 -1 6 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices IGLOO and ProASIC3 For boards and cards with three levels of staging, card power supplies must have time to reach their final values before the I/Os are connected. Pay attention to the sizing of power supply decoupling capacitors on the card to ensure that the power supplies are not overloaded with capacitance. Cards with three levels of staging should have the following sequence: * Grounds * Powers * I/Os and other pins For Level 3 and Level 4 compliance with the 30 k gate device, cards with two levels of staging should have the following sequence: * Grounds * Powers, I/Os, and other pins Cold-Sparing Support Cold-sparing refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. The resistor value is calculated based on the decoupling capacitance on a given power supply. The RC constant should be greater than 3 s. To remove resistor current during operation, it is suggested that the resistor be disconnected (e.g., with an NMOS switch) from the power supply after the supply has reached its final value. Refer to the Power-Up/-Down Behavior of ProASIC3/E Devices chapter of the ProASIC3 and ProASIC3E handbooks for details on cold-sparing. Cold-sparing means that a subsystem with no power applied (usually a circuit board) is electrically connected to the system that is in operation. This means that all input buffers of the subsystem must present very high input impedance with no power applied so as not to disturb the operating portion of the system. The 30 k gate devices fully support cold-sparing, since the I/O clamp diode is always off (see Table 7-12 on page 7-19). If the 30 k gate device is used in applications requiring cold-sparing, a discharge path from the power supply to ground should be provided. This can be done with a discharge resistor or a switched resistor. This is necessary because the 30 k gate devices do not have built-in I/O clamp diodes. For other IGLOO and ProASIC3 devices, since the I/O clamp diode is always active, cold-sparing can be accomplished either by employing a bus switch to isolate the device I/Os from the rest of the system or by driving each I/O pin to 0 V. If the resistor is chosen, the resistor value must be calculated based on decoupling capacitance on a given power supply on the board (this decoupling capacitance is in parallel with the resistor). The RC time constant should ensure full discharge of supplies before cold-sparing functionality is required. The resistor is necessary to ensure that the power pins are discharged to ground every time there is an interruption of power to the device. IGLOOe and ProASIC3E devices support cold-sparing for all I/O configurations. Standards, such as PCI, that require I/O clamp diodes can also achieve cold-sparing compliance, since clamp diodes get disconnected internally when the supplies are at 0 V. When targeting low-power applications, I/O cold-sparing may add additional current if a pin is configured with either a pull-up or pull-down resistor and driven in the opposite direction. A small static current is induced on each I/O pin when the pin is driven to a voltage opposite to the weak pull resistor. The current is equal to the voltage drop across the input pin divided by the pull resistor. Refer to the "Detailed I/O DC Characteristics" section of the appropriate family datasheet for the specific pull resistor value for the corresponding I/O standard. For example, assuming an LVTTL 3.3 V input pin is configured with a weak pull-up resistor, a current will flow through the pull-up resistor if the input pin is driven LOW. For LVTTL 3.3 V, the pull-up resistor is ~45 k, and the resulting current is equal to 3.3 V / 45 k = 73 A for the I/O pin. This is true also when a weak pull-down is chosen and the input pin is driven HIGH. This current can v1.1 7 - 17 I/O Structures in IGLOO and ProASIC3 Devices be avoided by driving the input LOW when a weak pull-down resistor is used and driving it HIGH when a weak pull-up resistor is used. This current draw can occur in the following cases: * * In Active and Static modes: - Input buffers with pull-up, driven LOW - Input buffers with pull-down, driven HIGH - Bidirectional buffers with pull-up, driven LOW - Bidirectional buffers with pull-down, driven HIGH - Output buffers with pull-up, driven LOW - Output buffers with pull-down, driven HIGH - Tristate buffers with pull-up, driven LOW - Tristate buffers with pull-down, driven HIGH In Flash*Freeze mode: - Input buffers with pull-up, driven LOW - Input buffers with pull-down, driven HIGH - Bidirectional buffers with pull-up, driven LOW - Bidirectional buffers with pull-down, driven HIGH Electrostatic Discharge Protection Low-power flash devices are tested per JEDEC Standard JESD22-A114-B. These devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all device pads against damage from ESD as well as from excessive voltage transients. All IGLOO and ProASIC3 devices are tested to the following models: the Human Body Model (HBM) with a tolerance of 2,000 V, the Machine Model (MM) with a tolerance of 250 V, and the Charged Device Model (CDM) with a tolerance of 200 V. Each I/O has two clamp diodes. One diode has its positive (P) side connected to the pad and its negative (N) side connected to VCCI. The second diode has its P side connected to GND and its N side connected to the pad. During operation, these diodes are normally biased in the off state, except when transient voltage is significantly above VCCI or below GND levels. In 30 k gate devices, the first diode is always off. In other devices, the clamp diode is always on and cannot be switched off. By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to Table 7-12 on page 7-19 for more information about the I/O standards and the clamp diode. The second diode is always connected to the pad, regardless of the I/O configuration selected. 7 -1 8 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices Table 7-12 * I/O Hot-Swap and 5 V Input Tolerance Capabilities in IGLOO and ProASIC3 Devices Clamp Diode1 Other AGL030 IGLOO and and ProASIC3 A3P030 Devices I/O Assignment 3.3 V LVTTL/LVCMOS No 3.3 V PCI, 3.3 V PCI-X LVCMOS 2.5 V N/A 5 No 6 Yes Yes Yes Hot Insertion 5 V Input Tolerance2 AGL030 and A3P030 Other IGLOO and ProASIC3 Devices AGL030 and A3P030 Yes Yes Yes2 Yes2 Enabled/Disabled Yes N/A 2 Enabled/Disabled Yes 2 4 Enabled/Disabled 4 Enabled/Disabled N/A Yes Yes Other IGLOO and ProASIC3 Input and Output Buffer Devices Yes Yes N/A Yes N/A Yes N/A Yes LVCMOS 1.8 V No Yes Yes Yes No No Enabled/Disabled LVCMOS 1.5 V No Yes Yes Yes No No Enabled/Disabled Differential, LVDS/ BLVDS/M-LVDS/ LVPECL N/A Yes N/A Yes N/A No Enabled/Disabled LVCMOS 2.5 V / 5.0 V Notes: 1. The clamp diode is always off for the AGL030 and A3P030 device and always active for other IGLOO and ProASIC3 devices. 2. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor. 3. Refer to Table 7-8 on page 7-15 to Table 7-11 on page 7-16 for device-compliant information. 4. Can be implemented with an external resistor and an internal clamp diode. 5. The LVCMOS 2.5 V I/O standard is supported by the 30 k gate devices only; select the LVCMOS25 macro. 6. The LVCMOS 2.5 V / 5.0 V I/O standard is supported by all IGLOO and ProASIC3 devices except 30 k gate devices; select the LVCMOS5 macro. v1.1 7 - 19 I/O Structures in IGLOO and ProASIC3 Devices 5 V Input and Output Tolerance IGLOO and ProASIC3 devices are both 5 V-input- and 5 V-output-tolerant if certain I/O standards are selected. Table 7-5 on page 7-5 shows the I/O standards that support 5 V input tolerance. Only 3.3 V LVTTL/LVCMOS standards support 5 V output tolerance. Refer to the appropriate family datasheet for the detailed description and configuration information. This feature is not shown in the I/O Attribute Editor. 5 V Input Tolerance I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2.5 V, and LVCMOS 2.5 V / 5.0 V configurations are used (see Table 7-12 on page 7-19). There are four recommended solutions for achieving 5 V receiver tolerance (see Figure 7-9 on page 7-21 to Figure 7-12 on page 7-23 for details of board and macro setups). All the solutions meet a common requirement of limiting the voltage at the input to 3.6 V or less. In fact, the I/O absolute maximum voltage rating is 3.6 V, and any voltage above 3.6 V may cause long-term gate oxide failures. Solution 1 The board-level design must ensure that the reflected waveform at the pad does not exceed the limits provided in the recommended operating conditions in the datasheet. This is a requirement to ensure long-term reliability. This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the two external resistors as explained below. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. This solution requires two board resistors, as demonstrated in Figure 7-9 on page 7-21. Here are some examples of possible resistor values (based on a simplified simulation model with no line effects and 10 transmitter output resistance, where Rtx_out_high = (VCCI - VOH) / IOH and Rtx_out_low = VOL / IOL). Example 1 (high speed, high current): Rtx_out_high = Rtx_out_low = 10 R1 = 36 (5%), P(r1)min = 0.069 R2 = 82 (5%), P(r2)min = 0.158 Imax_tx = 5.5 V / (82 x 0.95 + 36 x 0.95 + 10) = 45.04 mA tRISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Example 2 (low-medium speed, medium current): Rtx_out_high = Rtx_out_low = 10 R1 = 220 (5%), P(r1)min = 0.018 R2 = 390 (5%), P(r2)min = 0.032 Imax_tx = 5.5 V / (220 x 0.95 + 390 x 0.95 + 10) = 9.17 mA tRISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Other values of resistors are also allowed as long as the resistors are sized appropriately to limit the voltage at the receiving end to 2.5 V < Vin (rx) < 3.6 V when the transmitter sends a logic 1. This range of Vin_dc(rx) must be assured for any combination of transmitter supply (5 V 0.5 V), transmitter output resistance, and board resistor tolerances. 7 -2 0 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices Temporary overshoots are allowed according to the overshoot and undershoot table in the datasheet. Solution 1 I/O Input 3.3 V 5.5 V Rext1 Rext2 Requires two board resistors, LVCMOS 3.3 V I/Os Figure 7-9 * Solution 1 Solution 2 The board-level design must ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the datasheet. This is a requirement to ensure long-term reliability. This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the external resistors and Zener, as shown in Figure 7-10. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. Solution 2 I/O Input 3.3 V 5.5 V Rext1 Zener 3.3 V Requires one board resistor, one Zener 3.3 V diode, LVCMOS 3.3 V I/Os Figure 7-10 * Solution 2 v1.1 7 - 21 I/O Structures in IGLOO and ProASIC3 Devices Solution 3 The board-level design must ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the datasheet. This is a requirement to ensure long-term reliability. This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the bus switch, as shown in Figure 7-11. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. Solution 3 I/O Input Bus Switch IDTQS32X23 3.3 V 5.5 V 5.5 V Requires a bus switch on the board, LVTTL/LVCMOS 3.3 V I/Os. Figure 7-11 * Solution 3 7 -2 2 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices Solution 4 The board-level design must ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the DS. This is a requirement to ensure long-term reliability. Solution 4 I/O Input 2.5 V 5.5 V On-Chip Clamp Diode 2.5 V Rext Requires one board resistor. Available for LVCMOS 2.5 V / 5.0 V. Figure 7-12 * Solution 4 v1.1 7 - 23 I/O Structures in IGLOO and ProASIC3 Devices Table 7-13 * Comparison Table for 5 V-Compliant Receiver Solutions Solution Board Components 1 Two resistors 2 Resistor and Zener 3.3 V 3 Bus switch 4 Speed Low to High Medium High 2,3,4,5 Minimum resistor value R = 47 at TJ = 70C Medium Current Limitations 1 Limited by transmitter's drive strength Limited by transmitter's drive strength N/A Maximum diode current at 100% duty cycle, signal constantly at 1 R = 150 at TJ = 85C 52.7 mA at TJ = 70C / 10-year lifetime R = 420 at TJ = 100C 16.5 mA at TJ = 85C / 10-year lifetime 5.9 mA at TJ = 100C / 10-year lifetime For duty cycles other than 100%, the currents can be increased by a factor of 1 / (duty cycle). Example: 20% duty cycle at 70C Maximum current = (1 / 0.2) x 52.7 mA = 5 x 52.7 mA = 263.5 mA Notes: 1. Speed and current consumption increase as the board resistance values decrease. 2. Resistor values ensure I/O diode long-term reliability. 3. At 70C, customers could still use 420 on every I/O. 4. At 85C, a 5 V solution on every other I/O is permitted, since the resistance is lower (150 ) and the current is higher. Also, the designer can still use 420 and use the solution on every I/O. 5. At 100C, the 5 V solution on every I/O is permitted, since 420 are used to limit the current to 5.9 mA. 5 V Output Tolerance IGLOO and ProASIC3 I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It is also critical that there be NO external I/O pull-up resistor to 5 V, since this resistor would pull the I/O pad voltage beyond the 3.6 V absolute maximum value and consequently cause damage to the I/O. When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, the I/Os can directly drive signals into 5 V TTL receivers. In fact, VOL = 0.4 V and VOH = 2.4 V in both 3.3 V LVTTL and 3.3 V LVCMOS modes exceeds the VIL = 0.8 V and VIH = 2 V level requirements of 5 V TTL receivers. Therefore, level 1 and level 0 will be recognized correctly by 5 V TTL receivers. Schmitt Trigger A Schmitt trigger is a buffer used to convert a slow or noisy input signal into a clean one before passing it to the FPGA. Using Schmitt trigger buffers guarantees a fast, noise-free input signal to the FPGA. The Schmitt trigger is available for the LVTTL, LVCMOS, and 3.3 V PCI I/O standards. This feature can be implemented by using a Physical Design Constraints (PDC) command (Table 7-5 on page 7-5) or by selecting a check box in the I/O Attribute Editor in Designer. The check box is cleared by default. 7 -2 4 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices Selectable Skew between Output Buffer Enable and Disable Times Low-power flash devices have a configurable skew block in the output buffer circuitry that can be enabled to delay output buffer assertion without affecting deassertion time. Since this skew block is only available for the OE signal, the feature can be used in tristate and bidirectional buffers. A typical 1.2 ns delay is added to the OE signal to prevent potential bus contention. Refer to the appropriate family datasheet for detailed timing diagrams and descriptions. The skew feature is available for all I/O standards. This feature can be implemented by using a PDC command (Table 7-5 on page 7-5) or by selecting a check box in the I/O Attribute Editor in Designer. The check box is cleared by default. The configurable skew block is used to delay output buffer assertion (enable) without affecting deassertion (disable) time. Output Enable ENABLE (IN) (from FPGA core) MUX ENABLE (OUT) Skew Circuit I/O Output Buffers Skew Select Figure 7-13 * Block Diagram of Output Enable Path ENABLE (IN) ENABLE (OUT) Less than 0.1 ns Less than 0.1 ns Figure 7-14 * Timing Diagram (option 1: bypasses skew circuit) v1.1 7 - 25 I/O Structures in IGLOO and ProASIC3 Devices ENABLE (IN) ENABLE (OUT) 1.2 ns (typical) Less than 0.1 ns Figure 7-15 * Timing Diagram (option 2: enables skew circuit) At the system level, the skew circuit can be used in applications where transmission activities on bidirectional data lines need to be coordinated. This circuit, when selected, provides a timing margin that can prevent bus contention and subsequent data loss and/or transmitter over-stress due to transmitter-to-transmitter current shorts. Figure 7-16 presents an example of the skew circuit implementation in a bidirectional communication system. Figure 7-17 on page 7-27 shows how bus contention is created, and Figure 7-18 on page 7-27 shows how it can be avoided with the skew circuit. Transmitter ENABLE/ DISABLE Transmitter 1: ProASIC3 I/O Skew or Bypass Skew EN (r1) Routing Delay (t1) Transmitter 2: Generic I/O EN (b2) EN (b1) Routing Delay (t2) ENABLE(t2) ENABLE (t1) Bidirectional Data Bus Figure 7-16 * Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using IGLOO or ProASIC3 Devices 7 -2 6 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices EN (b1) EN (b2) ENABLE (r1) ENABLE (t1) Transmitter 1: OFF Transmitter 1: ON Transmitter 1: OFF ENABLE (t2) Transmitter 2: ON Transmitter 2: OFF Bus Contention Figure 7-17 * Timing Diagram (bypasses skew circuit) EN (b1) EN (b2) ENABLE (t1) Transmitter 1: OFF Transmitter 1: ON Transmitter 1: OFF ENABLE (t2) Transmitter 2: ON Transmitter 2: OFF Result: No Bus Contention Figure 7-18 * Timing Diagram (with skew circuit selected) v1.1 7 - 27 I/O Structures in IGLOO and ProASIC3 Devices I/O Register Combining Every I/O has several embedded registers in the I/O tile that are close to the I/O pads. Rather than using the internal register from the core, the user has the option of using these registers for faster clock-to-out timing, and external hold and setup. When combining these registers at the I/O buffer, some architectural rules must be met. Provided these rules are met, the user can enable register combining globally during Compile (as shown in the "Compiling the Design" section in the I/O Software Control in Low-Power Flash Devices section of the handbook). This feature is supported by all I/O standards. Rules for Registered I/O Function: 1. The fanout between an I/O pin (D, Y, or E) and a register must be equal to one for combining to be considered on that pin. 2. All registers (Input, Output, and Output Enable) connected to an I/O must share the same clear or preset function: - If one of the registers has a CLR pin, all the other registers that are candidates for combining in the I/O must have a CLR pin. - If one of the registers has a PRE pin, all the other registers that are candidates for combining in the I/O must have a PRE pin. - If one of the registers has neither a CLR nor a PRE pin, all the other registers that are candidates for combining must have neither a CLR nor a PRE pin. - If the clear or preset pins are present, they must have the same polarity. - If the clear or preset pins are present, they must be driven by the same signal (net). 3. Registers connected to an I/O on the Output and Output Enable pins must have the same clock and enable function: - Both the Output and Output Enable registers must have an E pin (clock enable), or none at all. - If the E pins are present, they must have the same polarity. The CLK pins must also have the same polarity. In some cases, the user may want registers to be combined with the input of a bibuf while maintaining the output as-is. This can be achieved by using PDC commands as follows: set_io <signal name> -REGISTER yes ------register will combine set_preserve <signal name> ----register will not combine Weak Pull-Up and Weak Pull-Down Resistors IGLOO and ProASIC3 devices support optional weak pull-up and pull-down resistors on each I/O pin. When the I/O is pulled up, it is connected to the VCCI of its corresponding I/O bank. When it is pulled down, it is connected to GND. Refer to the datasheet for more information. For low-power applications, configuration of the pull-up or pull-down of the I/O can be used to set the I/O to a known state while the device is in Flash*Freeze mode. Refer to Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices for more information. The Flash*Freeze (FF) pin cannot be configured with a weak pull-down or pull-up I/O attribute, as the signal needs to be driven at all times. Output Slew Rate Control The slew rate is the amount of time an input signal takes to get from logic LOW to logic HIGH or vice versa. It is commonly defined as the propagation delay between 10% and 90% of the signal's voltage swing. Slew rate control is available for the output buffers of low-power flash devices. The output buffer has a programmable slew rate for both HIGH-to-LOW and LOW-to-HIGH transitions. Slew rate control is available for LVTTL, LVCMOS, and PCI-X I/O standards. The other I/O standards have a preset slew value. 7 -2 8 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices The slew rate can be implemented by using a PDC command (Table 7-5 on page 7-5), setting "High" or "Low" in the I/O Attribute Editor in Designer, or instantiating a special I/O macro. The default slew rate value is "High." IGLOO and ProASIC3 devices support output slew rate control: high and low. Actel recommends the high slew rate option to minimize the propagation delay. This high-speed option may introduce noise into the system if appropriate signal integrity measures are not adopted. Selecting a low slew rate reduces this kind of noise but adds some delays in the system. Low slew rate is recommended when bus transients are expected. Output Drive The output buffers of IGLOO and ProASIC3 devices can provide multiple drive strengths to meet signal integrity requirements. The LVTTL and LVCMOS (except 1.2 V LVCMOS) standards have selectable drive strengths. Other standards have a preset value. Drive strength should also be selected according to the design requirements and noise immunity of the system. The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and LVCMOS 1.5 V. All other I/O standards have a high output slew rate by default. For 30 k gate devices, refer to Table 7-14. For other ProASIC3 and IGLOO devices, refer to Table 7-15 through Table 7-16 on page 7-30 for more information about the slew rate and drive strength specification. Refer to Table 7-4 on page 7-4 for I/O bank type definitions. There will be a difference in timing between the Standard Plus I/O banks and the Advanced I/O banks. Refer to the I/O timing tables in the datasheet for the standards supported by each device. Table 7-14 * IGLOO and ProASIC3 Output Drive and Slew for Standard I/O Bank Type (for 30 k gate devices) I/O Standards 2 mA 4 mA 6 mA 8 mA Slew LVTTL/LVCMOS 3.3 V High Low LVCMOS 2.5 V High Low LVCMOS 1.8 V - - High Low LVCMOS 1.5 V - - - High Low Table 7-15 * IGLOO and ProASIC3 Output Drive and Slew for Standard Plus I/O Bank Type I/O Standards 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Slew LVTTL High Low LVCMOS 3.3 V High Low LVCMOS 2.5 V * * - High Low LVCMOS 1.8 V - - High Low LVCMOS 1.5 V - - - - High Low Note: *Not available in Automotive devices. v1.1 7 - 29 I/O Structures in IGLOO and ProASIC3 Devices Table 7-16 * IGLOO and ProASIC3 Output Drive and Slew for Advanced I/O Bank Type I/O Standards 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Slew LVTTL High Low LVCMOS 3.3 V High Low LVCMOS 2.5 V * * High Low LVCMOS 2.5/5.0 V * * High Low LVCMOS 1.8 V - High Low LVCMOS 1.5 V - - High Low Note: Not available in Automotive devices. Simultaneously Switching Outputs (SSOs) and Printed Circuit Board Layout Each I/O voltage bank has a separate ground and power plane for input and output circuits (VMV/GNDQ for input buffers and VCCI/GND for output buffers). This isolation is necessary to minimize simultaneous switching noise from the input and output (SSI and SSO). The switching noise (ground bounce and power bounce) is generated by the output buffers and transferred into input buffer circuits, and vice versa. Since voltage bounce originates on the package inductance, the VMV and VCCI supplies have separate package pin assignments. For the same reason, GND and GNDQ also have separate pin assignments. The VMV and VCCI pins must be shorted to each other on the board. Also, the GND and GNDQ pins must be shorted to each other on the board. This will prevent unwanted current draw from the power supply. SSOs can cause signal integrity problems on adjacent signals that are not part of the SSO bus. Both inductive and capacitive coupling parasitics of bond wires inside packages and of traces on PCBs will transfer noise from SSO busses onto signals adjacent to those busses. Additionally, SSOs can produce ground bounce noise and VCCI dip noise. These two noise types are caused by rapidly changing currents through GND and VCCI package pin inductances during switching activities (EQ 7-2 and EQ 7-3). Ground bounce noise voltage = L(GND) x di/dt EQ 7-2 VCCI dip noise voltage = L(VCCI) x di/dt EQ 7-3 Any group of four or more input pins switching on the same clock edge is considered an SSO bus. The shielding should be done both on the board and inside the package unless otherwise described. In-package shielding can be achieved in several ways; the required shielding will vary depending on whether pins next to the SSO bus are LVTTL/LVCMOS inputs, LVTTL/LVCMOS outputs, or GTL/SSTL/HSTL/LVDS/LVPECL inputs and outputs. Board traces in the vicinity of the SSO bus have to be adequately shielded from mutual coupling and inductive noise that can be generated by the SSO bus. Also, noise generated by the SSO bus needs to be reduced inside the package. PCBs perform an important function in feeding stable supply voltages to the IC and, at the same time, maintaining signal integrity between devices. Key issues that need to be considered are as follows: * Power and ground plane design and decoupling network design * Transmission line reflections and terminations For extensive data per package on the SSO and PCB issues, refer to ProASIC3/E SSO and Pin Placement and Guidelines chapter of the handbook. 7 -3 0 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices I/O Software Support In Actel's Libero IDE software, default settings have been defined for the various I/O standards supported. Changes can be made to the default settings via the use of attributes; however, not all I/O attributes are applicable for all I/O standards. Table 7-17 list the valid I/O attributes that can be manipulated by the user for each I/O standard. Single-ended I/O standards in low-power flash devices support up to five different drive strengths. Table 7-17 * IGLOO and ProASIC3 I/O Attributes vs. I/O Standard Applications I/O Standard SLEW (output OUT_DRIVE only) (output only) SKEW (all macros with OE) OUT_LOAD RES_PULL (output only) COMBINE_REGISTER LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 2.5/5.0 V LVCMOS 1.8 V LVCMOS 1.5 V PCI (3.3 V) PCI-X (3.3 V) LVDS, BLVDS, M-LVDS LVPECL Note: Applies to all 30 k gate devices. Table 7-18 lists the default values for the above selectable I/O attributes as well as those that are preset for that I/O standard. See Table 7-14 on page 7-29 to Table 7-16 on page 7-30 for SLEW and OUT_DRIVE settings. Table 7-18 * IGLOO and ProASIC3 I/O Default Attributes I/O Standards LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 2.5/5.0 V SLEW (output only) OUT_DRIVE (output only) SKEW (tribuf OUT_LOAD and bibuf (output only) RES_PULL only) COMBINE_REGISTER See Table 7-14 See Table 7-14 on page 7-29 on page 7-29 to Table 7-16 to Table 7-16 on page 7-30. on page 7-30. Off LVCMOS 1.8 V None 35 pF - Off None 35 pF - Off None 35 pF - Off None 35 pF - LVCMOS 1.5 V Off None 35 pF - PCI (3.3 V) Off None 10 pF - PCI-X (3.3 V) Off None 10 pF - LVDS, BLVDS, M-LVDS Off None 0 pF - LVPECL Off None 0 pF - v1.1 7 - 31 I/O Structures in IGLOO and ProASIC3 Devices User I/O Naming Convention IGLOO and ProASIC3 Due to the comprehensive and flexible nature of IGLOO and ProASIC3 device user I/Os, a naming scheme is used to show the details of each I/O (Figure 7-19 on page 7-33 and Figure 7-20 on page 7-33). The name identifies to which I/O bank it belongs, as well as pairing and pin polarity for differential I/Os. I/O Nomenclature = FF/Gmn/IOuxwBy Gmn is only used for I/Os that also have CCC access--i.e., global pins. 7 -3 2 FF = Indicates the I/O dedicated for the Flash*Freeze mode activation pin in IGLOO and ProASIC3L devices only G = Global m = Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east middle), D (southeast corner), E (southwest corner), and F (west middle) n = Global input MUX and pin number of the associated Global location m--either A0, A1, A2, B0, B1, B2, C0, C1, or C2. Refer to Global Resources in Actel Low-Power Flash Devices for information about the three input pins per clock source MUX at CCC location m. u = I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise direction x = P or U (Positive), N or V (Negative) for differential pairs, or R (Regular--single-ended) for the I/Os that support single-ended and voltage-referenced I/O standards only. U (Positive) or V (Negative)--for LVDS, DDR LVDS, BLVDS, and M-LVDS only--restricts the I/O differential pair from being selected as an LVPECL pair. w = D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out. For Differential Pairs (D), adjacency for ball grid packages means only vertical or horizontal. Diagonal adjacency does not meet the requirements for a true differential pair. B = Bank y = Bank number (0-3). The Bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise direction. v1.1 GND VCC GND VCCIB1 VCOMPLF VCCPLF CCC "A" GNDQ GND Vcc VCCIB0 GND Vcc VCCIB0 GND CCC "B" Bank 0 GND GNDQ VMV0 VCC Bank 0 GND VCCIB0 Bank 1 AGL030/A3P030 AGL060/A3P060 AGL125/A3P125 CCC/PLL "F" GND VCC VCCIB1 GND VMV1 VCCIB0 GND VMV0 GNDQ I/O Structures in IGLOO and Pro ASIC3 Devices CCC "C" GND VCC Bank 0 VCCIB0 GND Bank 1 CCC "E" CCC "D" Bank 1 VJTAG TRST TDO VPUMP GND TCK TDI TMS VMV1 GNDQ GND VCCIB1 VCC GND VCCIB1 VCC GND VCCIB1 GND Vcc GND VCCIB3 VCOMPLF VCCPLF GND VCC VCCIB3 GND VMV3 CCC "A" VCC VCCIB0 GND VCC VCCIB0 GND VCCIB0 GND VMV0 GNDQ Note: The 30 k gate devices do not support a PLL (VCOMPLF and VCCPLF pins). Figure 7-19 * Naming Conventions of IGLOO and ProASIC3 Devices with Two I/O Banks - Top View CCC "B" Bank 0 Bank 3 Bank 1 A3P250 A3P400 A3P600 A3P1000 CCC/PLL "F" VCC GND VCCIB1 CCC "C" Bank 3 Bank 1 GNDQ GND CCC "E" GND GNDQ VMV1 CCC "D" Bank 2 GND VCC VCCIB1 GND VJTAG TRST TDO VPUMP GND TCK TDI TMS VMV2 GNDQ GND VCCIB2 VCC GND VCCIB2 VCC GND VCCIB2 Figure 7-20 * Naming Conventions of IGLOO and ProASIC3 Devices with Four I/O Banks - Top View v1.1 7 - 33 I/O Structures in IGLOO and ProASIC3 Devices Board-Level Considerations Low-power flash devices have robust I/O features that can help in reducing board-level components. The devices offer single-chip solutions, which makes the board layout simpler and more immune to signal integrity issues. Although, in many cases, these devices resolve board-level issues, special attention should always be given to overall signal integrity. This section covers important board-level considerations to facilitate optimum device performance. Termination Proper termination of all signals is essential for good signal quality. Nonterminated signals, especially clock signals, can cause malfunctioning of the device. For general termination guidelines, refer to the Board-Level Considerations application note for Actel FPGAs. Also refer to Pin Descriptions for termination requirements for specific pins. Low-power flash I/Os are equipped with on-chip pull-up/-down resistors. The user can enable these resistors by instantiating them either in the top level of the design (refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide for the available I/O macros with pull-up/-down) or in the I/O Attribute Editor in Designer if generic input or output buffers are instantiated in the top level. Unused I/O pins are configured as inputs with pull-up resistors. As mentioned earlier, low-power flash devices have multiple programmable drive strengths, and the user can eliminate unwanted overshoot and undershoot by adjusting the drive strengths. Power-Up Behavior Low-power flash devices are power-up/-down friendly; i.e., no particular sequencing is required for power-up and power-down. This eliminates extra board components for power-up sequencing, such as a power-up sequencer. During power-up, all I/Os are tristated, irrespective of I/O macro type (input buffers, output buffers, I/O buffers with weak pull-ups or weak pull-downs, etc.). Once I/Os become activated, they are set to the user-selected I/O macros. Refer to the Power-Up/-Down Behavior of ProASIC3/E Devices chapter of the ProASIC3 and ProASIC3E handbooks for details. Drive Strength Low-power flash devices have up to seven programmable output drive strengths. The user can select the drive strength of a particular output in the I/O Attribute Editor or can instantiate a specialized I/O macro, such as OUTBUF_S_12 (slew = low, out_drive = 12 mA). The maximum available drive strength is 24 mA per I/O. Though no I/O should be forced to source or sink more than 24 mA indefinitely, I/Os may handle a higher amount of current (refer to the device IBIS model for maximum source/sink current) during signal transition (AC current). Every device package has its own power dissipation limit; hence, power calculation must be performed accurately to determine how much current can be tolerated per I/O within that limit. I/O Interfacing Low-power flash devices are 5 V-input- and 5 V-output-tolerant without adding any extra circuitry. Along with other low-voltage I/O macros, this 5 V tolerance makes these devices suitable for many types of board component interfacing. 7 -3 4 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices Table 7-19 shows some high-level interfacing examples using low-power flash devices. Table 7-19 * High-Level Interface Examples Clock Interface I/O Type Frequency Type Signals In Signals Out Data I/O GM Src Sync 125 MHz LVTTL 8 8 125 Mbps TBI Src Sync 125 MHz LVTTL 10 10 125 Mbps XSBI Src Sync 644 MHz LVDS 16 16 644 Mbps XGMI Src Sync DDR 156 MHz HSTL1 32 32 312 Mbps FlexBus 3 Sys Sync 104 MHz LVTTL 32 32 104 Pos-PHY3/SPI-3 Sys Sync 104 LVTTL 8,16,32 8,16,32 104 Mbps FlexBus 4/SPI-4.1 Src Sync 200 MHz HSTL1 16,64 16,64 200 Mbps Pos-PHY4/SPI-4.2 Src Sync DDR 311 MHz LVDS 16 16 622 Mbps SFI-4.1 Src Sync 622 MHz LVDS 16 16 622 Mbps CSIX L1 Sys Sync 250 MHz HSTL1 32,64,96,128 32,64,96,128 250 Mbps Hyper Transport Sys Sync DDR 800 MHz LVDS 2,4,8,16 2,4,8,16 1.6 Gbps Rapid I/O Parallel Sys Sync DDR 250 MHz - 1 GHz LVDS 8,16 8,16 2 Gbps LVDS 4 4 622 Mbps Star Fabric CDR Note: Sys Sync = System Synchronous Clocking, Src Sync = Source Synchronous Clocking, and CDR = Clock and Data Recovery. Conclusion IGLOO and ProASIC3 support for multiple I/O standards minimizes board-level components and makes possible a wide variety of applications. The Actel Designer software, integrated with Actel Libero IDE, presents a clear visual display of I/O assignments, allowing users to verify I/O and boardlevel design requirements before programming the device. The IGLOO and ProASIC3 device I/O features and functionalities ensure board designers can produce low-cost and low-power FPGA applications fulfilling the complexities of contemporary design needs. v1.1 7 - 35 I/O Structures in IGLOO and ProASIC3 Devices Related Documents Handbook Documents Board-Level Considerations http://www.actel.com/documents/BoardLevelCons_AN.pdf DDR for Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_DDR_HBs.pdf Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices http://www.actel.com/documents/LPD_FlashFreeze_HBs.pdf Global Resources in Actel Low-Power Flash Devices http://www.actel.com/documents/LPD_Global_HBs.pdf Pin Descriptions http://www.actel.com/documents/LPD_PinDescriptions.HBs.pdf Power-Up/-Down Behavior of ProASIC3/E Devices http://www.actel.com/documents/ProASIC3_E_PowerUp_HBs.pdf ProASIC3/E SSO and Pin Placement and Guidelines http://www.actel.com/documents/PA3_E_SSO_HBs.pdf User's Guides Actel Libero IDE User's Guide http://www.actel.com/documents/libero_ug.pdf IGLOO, Fusion, and ProASIC3 Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf SmartGen Core Reference Guide http://www.actel.com/documents/genguide_ug.pdf 7 -3 6 v1.1 I/O Structures in IGLOO and Pro ASIC3 Devices Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-009-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version v1.0 (January 2008) Changes in Current Version (v1.1) Page Originally, this document contained information on all IGLOO and ProASIC3 families. With the addition of new families and to highlight the differences between the features, the document has been separated into 3 documents: N/A This document contains information specific to IGLOO, ProASIC3, and ProASIC3L. I/O Structures in IGLOOe and ProASIC3E Devices contains information specific to IGLOOe, ProASIC3E, and ProASIC3EL I/O features. I/O Structures in IGLOO PLUS Devices contains information specific to IGLOO PLUS I/O features. v1.1 7 - 37 I/O Software Control in Low-Power Flash Devices 8 - I/O Software Control in Low-Power Flash Devices Actel Fusion,(R) IGLOO,(R) and ProASIC(R)3 I/Os provide more design flexibility, allowing the user to control specific features by enabling certain I/O standards. Some features are selectable only for certain I/O standards, whereas others are available for all I/O standards. For example, slew control is not supported by differential I/O standards. Conversely, I/O register combining is supported by all I/O standards. For detailed information about which I/O standards and features are available on each device and each I/O type, refer to the I/O Structures section of the handbook for the device you are using. Figure 8-1 shows the various points in the software design flow where a user can provide input or control of the I/O selection and parameters. A detailed description is provided throughout this document. Design Entry 1. I/O Macro Using SmartGen 2. I/O Buffer Cell Schematic Entry 3. Instantiating I/O Library Macro in HDL Code 4. Generic Buffer Using 1, 2, 3 Method 5. Synthesis 6. Compile 6.1 I/O Assignments by PDC Import 7. I/O Assignments by Multi-View Navigator (MVN) I/O Standard Selection for Generic I/O Macro I/O Standards and VREF Assignment by I/O Bank Assigner I/O Attribute Selection for I/O Standards 8. Layout and Other Steps Figure 8-1 * User I/O Assignment Flow Chart v1.1 8-1 I/O Software Control in Low-Power Flash Devices IGLOO and ProASIC3 I/O Support The low-power flash families listed in Table 8-1 support I/Os and the functions described in this document. Table 8-1 * Low-Power Flash Families Family1 IGLOO Timing Numbers2 Description Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*FreezeTM IGLOO DC and Switching technology Characteristics IGLOO PLUS Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO PLUS DC and Switching technology and enhanced I/O capabilities Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional IGLOOe DC and Switching PLLs, and additional I/O standards Characteristics ProASIC3L Low-power, high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and Switching technology Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, and ProASIC3E DC and Switching additional I/O standards Characteristics ProASIC3 DC and Switching Characteristics ProASIC3 Low-power, high-performance FPGAs qualified for Automotive Automotive ProASIC3 DC and Automotive applications Switching Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 8-1) provide a selection of low-power, secure, live-atpower-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze Mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. The Actel Fusion family, based on the highly successful ProASIC3 flash FPGA architecture, has been designed as a high-performance, mixed-signal Programmable System Chip. Fusion supports many peripherals, including embedded flash memory, analog-to-digital converter (ADC), high-drive outputs, RC and crystal oscillators, and real-time counter (RTC). The total available on-chip memory, including the flash array blocks, is greater than that found in SRAM FPGAs. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 8-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 8-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 8 -2 v1.1 I/O Software Control in Low-Power Flash Devices Software-Controlled I/O Attributes Users may modify these programmable I/O attributes using the I/O Attribute Editor. Modifying an I/O attribute may result in a change of state in Designer. Table 8-2 details which steps have to be rerun as a function of modified I/O attribute. Table 8-2 * Designer State (resulting from I/O attribute modification) Designer States I/O Attribute Compile Layout Fuse Timing Power Slew Control No No Yes Yes Yes Output Drive (mA) No No Yes Yes Yes Skew Control No No Yes Yes Yes Resistor Pull No No Yes Yes Yes Input Delay No No Yes Yes Yes Schmitt Trigger No No Yes Yes Yes OUT_LOAD No No No Yes Yes COMBINE_REGISTER Yes Yes N/A N/A N/A Notes: 1. No = Remains the same, Yes = Re-run the step, N/A = Not applicable 2. Skew control and input delay do not apply to IGLOO PLUS. v1.1 8-3 I/O Software Control in Low-Power Flash Devices Implementing I/Os in Actel Software Actel Libero(R) Integrated Design Environment (IDE) is integrated with design entry tools such as the SmartGen macro builder, the ViewDraw schematic entry tool, and an HDL editor. It is also integrated with the synthesis and Designer tools. In this section, all necessary steps to implement the I/Os are discussed. Design Entry There are three ways to implement I/Os in a design: 1. Use the SmartGen macro builder to configure I/Os by generating specific I/O library macros and then instantiating them in top-level code. This is especially useful when creating I/O bus structures. 2. Use an I/O buffer cell in a schematic design. 3. Manually instantiate specific I/O macros in the top-level code. If technology-specific macros, such as INBUF_LVCMOS33 and OUTBUF_PCI, are used in the HDL code or schematic, the user will not be able to change the I/O standard later on in Designer. If generic I/O macros are used, such as INBUF, OUTBUF, TRIBUF, CLKBUF, and BIBUF, the user can change the I/O standard using the Designer I/O Attribute Editor tool. Using SmartGen for I/O Configuration The SmartGen tool in Libero IDE provides a GUI-based method of configuring the I/O attributes. The user can select certain I/O attributes while configuring the I/O macro in SmartGen. The steps to configure an I/O macro with specific I/O attributes are as follows: 1. Open Libero IDE. 2. On the left hand side of the Catalog View, select I/O, as shown in Figure 8-2. Figure 8-2 * SmartGen Catalog 8 -4 v1.1 I/O Software Control in Low-Power Flash Devices 3. Expand the I/O section and double-click one of the options (Figure 8-3). Figure 8-3 * Expanded I/O Section 4. Double-click any of the varieties. The I/O Create Core window opens (Figure 8-4). Figure 8-4 * I/O Create Core Window As seen in Figure 8-4, there are five tabs to configure the I/O macro: Input Buffers, Output Buffers, Bidirectional Buffers, Tristate Buffers, and DDR. Input Buffers There are two variations: Regular and Special. If the Regular variation is selected, only the Width (1 to 128) needs to be entered. The default value for Width is 1. The Special variation has Width, Technology, Voltage Level, and Resistor Pull-Up/-Down options (see Figure 8-4). All the I/O standards and supply voltages (VCCI) supported for the device family are available for selection. v1.1 8-5 I/O Software Control in Low-Power Flash Devices Output Buffers There are two variations: Regular and Special. If the Regular variation is selected, only the Width (1 to 128) needs to be entered. The default value for Width is 1. The Special variation has Width, Technology, Output Drive, and Slew Rate options. Bidirectional Buffers There are two variations: Regular and Special. The Regular variation has Enable Polarity (Active High, Active Low) in addition to the Width option. The Special variation has Width, Technology, Output Drive, Slew Rate, and Resistor Pull-Up/-Down options. Tristate Buffers Same as Bidirectional Buffers. DDR There are eight variations: DDR with Regular Input Buffers, Special Input Buffers, Regular Output Buffers, Special Output Buffers, Regular Tristate Buffers, Special Tristate Buffers, Regular Bidirectional Buffers, and Special Bidirectional Buffers. These variations resemble the options of the previous I/O macro. For example, the Special Input Buffers variation has Width, Technology, Voltage Level, and Resistor Pull-Up/-Down options. DDR is not available on IGLOO PLUS devices. 5. Once the desired configuration is selected, click the Generate button. The Generate Core window opens (Figure 8-5). 6. Enter a name for the macro. Click OK. The core will be generated and saved to the appropriate location within the project files (Figure 8-6 on page 8-7). Figure 8-5 * Generate Core Window 7. Instantiate the I/O macro in the top-level code. The user must instantiate the DDR_REG or DDR_OUT macro in the design. Use SmartGen to generate both these macros and then instantiate them in your top level. To combine the DDR macros with the I/O, the following rules must be met: 8 -6 v1.1 I/O Software Control in Low-Power Flash Devices Rules for the DDR I/O Function * The fanout between an I/O pin (D or Y) and a DDR (DDR_REG or DDR_OUT) macro must be equal to one for the combining to happen on that pin. * If a DDR_REG macro and a DDR_OUT macro are combined on the same bidirectional I/O, they must share the same clear signal. * Registers will not be combined in an I/O in the presence of DDR combining on the same I/O. Using the I/O Buffer Schematic Cell Libero IDE includes the ViewDraw schematic entry tool. Using ViewDraw, the user can insert any supported I/O buffer cell in the top-level schematic. Figure 8-6 shows a top-level schematic with different I/O buffer cells. When synthesized, the netlist will contain the same I/O macro. Figure 8-6 * I/O Buffer Schematic Cell Usage v1.1 8-7 I/O Software Control in Low-Power Flash Devices Instantiating in HDL code All the supported I/O macros can be instantiated in the top-level HDL code (refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide for a detailed list of all I/O macros). The following is an example: library ieee; use ieee.std_logic_1164.all; library proasic3e; entity TOP is port(IN2, IN1 : in std_logic; OUT1 : out std_logic); end TOP; architecture DEF_ARCH of TOP is component INBUF_LVCMOS5U port(PAD : in std_logic := 'U'; Y : out std_logic); end component; component INBUF_LVCMOS5 port(PAD : in std_logic := 'U'; Y : out std_logic); end component; component OUTBUF_SSTL3_II port(D : in std_logic := 'U'; PAD : out std_logic); end component; Other component ..... signal x, y, z.......other signals : std_logic; begin I1 : INBUF_LVCMOS5U port map(PAD => IN1, Y =>x); I2 : INBUF_LVCMOS5 port map(PAD => IN2, Y => y); I3 : OUTBUF_SSTL3_II port map(D => z, PAD => OUT1); other port mapping... end DEF_ARCH; Synthesizing the Design Libero IDE integrates with the Synplify(R) synthesis tool. Other synthesis tools can also be used with Libero IDE. Refer to the Actel Libero IDE User's Guide or Libero IDE online help for details on how to set up the Libero IDE tool profile with synthesis tools from other vendors. During synthesis, the following rules apply: * * Generic macros: - Users can instantiate generic INBUF, OUTBUF, TRIBUF, and BIBUF macros. - Synthesis will automatically infer generic I/O macros. - The default I/O technology for these macros is LVTTL. - Users will need to use the I/O Attribute Editor in Designer to change the default I/O standard if needed (see Figure 8-7 on page 8-9). Technology-specific I/O macros: - 8 -8 Technology-specific I/O macros, such as INBUF_LVCMO25 and OUTBUF_GTL25, can be instantiated in the design. Synthesis will infer these I/O macros in the netlist. v1.1 I/O Software Control in Low-Power Flash Devices - The I/O standard of technology-specific I/O macros cannot be changed in the I/O Attribute Editor (see Figure 8-7). - The user MUST instantiate differential I/O macros (LVDS/LVPECL) in the design. This is the only way to use these standards in the design. - To implement the DDR I/O function, the user must instantiate a DDR_REG or DDR_OUT macro. This is the only way to use a DDR macro in the design. Figure 8-7 * Assigning a Different I/O Standard to the Generic I/O Macro Performing Place-and-Route on the Design The netlist created by the synthesis tool should now be imported into Designer and compiled. During Compile, the user can specify the I/O placement and attributes by importing the PDC file. The user can also specify the I/O placement and attributes using ChipPlanner and the I/O Attribute Editor, under MVN. Defining I/O Assignments in the PDC File A PDC file is a Tcl script file specifying physical constraints. This file can be imported to and exported from Designer. Table 8-3 shows I/O assignment constraints supported in the PDC file. Table 8-3 * Command PDC I/O Constraints Action Example Comment I/O Banks Setting Constraints set_iobank set_vref Sets the I/O supply voltage, VCCI, and the input reference voltage, VREF, for the specified I/O bank. set_iobank bankname [-vcci vcci_voltage] [-vref vref_voltage] Must use in case of mixed I/O voltage (VCCI) design set_iobank Bank7 -vcci 1.50 -vref 0.75 Assigns a VREF pin to a set_vref -bank [bankname] [pinnum] bank. Must use if voltagereferenced I/Os are used set_vref -bank Bank0 685 704 723 742 761 Note: Refer to the Actel Libero IDE User's Guide for detailed rules on PDC naming and syntax conventions. v1.1 8-9 I/O Software Control in Low-Power Flash Devices Table 8-3 * PDC I/O Constraints (continued) Command Action Example Comment set_vref_defaults Sets the default VREF set_vref_defaults bankname pins for the specified set_vref_defaults bank2 bank. This command is ignored if the bank does not need a VREF pin. I/O Attribute Constraint set_io Sets the attributes of an set_io portname [-pinname value] I/O [-fixed value] [-iostd value] [-out_drive value] [-slew value] [-res_pull value] [-schmitt_trigger value] [-in_delay value] [-skew value] [-out_load value] [-register value] set_io IN2 -pinname 28 -fixed yes -iostd LVCMOS15 -out_drive 12 -slew high -RES_PULL None -SCHMITT_TRIGGER Off -IN_DELAY Off -skew off -REGISTER No If the I/O macro is generic (e.g., INBUF) or technologyspecific (INBUF_LVCMOS25), then all I/O attributes can be assigned using this constraint. If netlist has an I/O macro that specifies one of its attributes, that attribute cannot be changed using this constraint, though other attributes can be changed. Example: OUTBUF_S_24 (low slew, output drive 24 mA) Slew and output cannot be changed. drive I/O Region Placement Constraints define_region If any number of I/Os must Defines either a define_region be assigned to a particular rectangular region or a -name [region_name] -type [region_type] x1 y1 x2 y2 I/O region, such a region can rectilinear region be created with this define_region -name test constraint. -type inclusive 0 15 2 29 assign_region Assigns a set of macros assign_region [region name] [macro_name...] to a specified region assign_region test U12 This constraint assigns I/O macros to the I/O regions. When assigning an I/O macro, PDC naming conventions must be followed if the macro name contains special characters; e.g., if the macro name is \\$1I19\\, the correct use of escape characters is \\\\\$1I19\\\\. Note: Refer to the Actel Libero IDE User's Guide for detailed rules on PDC naming and syntax conventions. 8 -1 0 v1.1 I/O Software Control in Low-Power Flash Devices Compiling the Design During Compile, a PDC I/O constraint file can be imported along with the netlist file. If only the netlist file is compiled, certain I/O assignments need to be completed before proceeding to Layout. All constraints that can be entered in PDC can also be entered using ChipPlanner, I/O Attribute Editor, and PinEditor. There are certain rules that must be followed in implementing I/O register combining and the I/O DDR macro (refer to the I/O Registers section of the handbook for the device that you are using and the "DDR" section on page 8-6 for details). Provided these rules are met, the user can enable or disable I/O register combining by using the PDC command set_io portname -register yes|no in the I/O Attribute Editor or selecting a check box in the Compile Options dialog box (see Figure 8-8). The Compile Options dialog box appears when the design is compiled for the first time. It can also be accessed by choosing Options > Compile during successive runs. I/O register combining is off by default. The PDC command overrides the setting in the Compile Options dialog box. Figure 8-8 * Setting Register Combining During Compile Understanding the Compile Report The I/O bank report is generated during Compile and displayed in the log window. This report lists the I/O assignments necessary before Layout can proceed. When Designer is started, the I/O Bank Assigner tool is run automatically if the Layout command is executed. The I/O Bank Assigner takes care of the necessary I/O assignments. However, these assignments can also be made manually with MVN or by importing the PDC file. Refer to the "Assigning Technologies and VREF to I/O Banks" section on page 8-14 for further description. The I/O bank report can also be extracted from Designer by choosing Tools > Report and setting the Report Type to IOBank. This report has the following tables: I/O Function, I/O Technology, I/O Bank Resource Usage, and I/O Voltage Usage. This report is useful if the user wants to do I/O assignments manually. v1.1 8 - 11 I/O Software Control in Low-Power Flash Devices I/O Function Figure 8-9 shows an example of the I/O Function table included in the I/O bank report: Figure 8-9 * I/O Function Table This table lists the number of input I/Os, output I/Os, bidirectional I/Os, and differential input and output I/O pairs that use I/O and DDR registers. Certain rules must be met to implement registered and DDR I/O functions (refer to the I/O Structures section of the handbook for the device you are using and the "DDR" section on page 8-6). I/O Technology The I/O Technology table (shown in Figure 8-10) gives the values of VCCI and VREF (reference voltage) for all the I/O standards used in the design. The user should assign these voltages appropriately. Figure 8-10 * I/O Technology Table 8 -1 2 v1.1 I/O Software Control in Low-Power Flash Devices I/O Bank Resource Usage This is an important portion of the report. The user must meet the requirements stated in this table. Figure 8-11 shows the I/O Bank Resource Usage table included in the I/O bank report: Figure 8-11 * I/O Bank Resource Usage Table The example in Figure 8-11 shows that none of the I/O macros is assigned to the bank because more than one VCCI is detected. I/O Voltage Usage The I/O Voltage Usage table provides the number of VREF (E devices only) and VCCI assignments required in the design. If the user decides to make I/O assignments manually (PDC or MVN), the issues listed in this table must be resolved before proceeding to Layout. As stated earlier, VREF assignments must be made if there are any voltage-referenced I/Os. Figure 8-12 shows the I/O Voltage Usage table included in the I/O bank report. Figure 8-12 * I/O Voltage Usage Table The table in Figure 8-12 indicates that there are two voltage-referenced I/Os used in the design. Even though both of the voltage-referenced I/O technologies have the same VCCI voltage, their VREF voltages are different. As a result, two I/O banks are needed to assign the VCCI and VREF voltages. v1.1 8 - 13 I/O Software Control in Low-Power Flash Devices In addition, there are six single-ended I/Os used that have the same VCCI voltage. Since two banks are already assigned with the same VCCI voltage and there are enough unused bonded I/Os in those banks, the user does not need to assign the same VCCI voltage to another bank. The user needs to assign the other three VCCI voltages to three more banks. Assigning Technologies and VREF to I/O Banks Low-power flash devices offer a wide variety of I/O standards, including voltage-referenced standards. Before proceeding to Layout, each bank must have the required VCCI voltage assigned for the corresponding I/O technologies used for that bank. The voltage-referenced standards require the use of a reference voltage (VREF). This assignment can be done manually or automatically. The following sections describe this in detail. Manually Assigning Technologies to I/O Banks The user can import the PDC at this point and resolve this requirement. The PDC command is set_iobank [bank name] -vcci [vcci value] Another method is to use the I/O Bank Settings dialog box (MVN > Edit > I/O Bank Settings) to set up the VCCI voltage for the bank (Figure 8-13). Figure 8-13 * Setting VCCI for a Bank 8 -1 4 v1.1 I/O Software Control in Low-Power Flash Devices The procedure is as follows: 1. Select the bank to which you want VCCI to be assigned from the Choose Bank list. 2. Select the I/O standards for that bank. If you select any standard, the tool will automatically show all compatible standards that have a common VCCI voltage requirement. 3. Click Apply. 4. Repeat steps 1-3 to assign VCCI voltages to other banks. Refer to Figure 8-12 on page 8-13 to find out how many I/O banks are needed for VCCI bank assignment. Manually Assigning VREF Pins Voltage-referenced inputs require an input reference voltage (VREF). The user must assign VREF pins before running Layout. Before assigning a VREF pin, the user must set a VREF technology for the bank to which the pin belongs. VREF Rules for the Implementation of Voltage-Referenced I/O Standards The VREF rules are as follows: 1. Any I/O (except JTAG I/Os) can be used as a VREF pin. 2. One VREF pin can support up to 15 I/Os. It is recommended, but not required, that eight of them be on one side and seven on the other side (in other words, all 15 can still be on one side of VREF). 3. SSTL3 (I) and (II): Up to 40 I/Os per north or south bank in any position 4. LVPECL / GTL+ 3.3 V / GTL 3.3 V: Up to 48 I/Os per north or south bank in any position 5. SSTL2 (I) and (II) / GTL+ 2.5 V / GTL 2.5 V: Up to 72 I/Os per north or south bank in any position. 6. VREF minibanks partition rule: Each I/O bank is physically partitioned into VREF minibanks. The VREF pins within a VREF minibank are interconnected internally, and consequently, only one VREF voltage can be used within each VREF minibank. If a bank does not require a VREF signal, the VREF pins of that bank are available as user I/Os. 7. The first VREF minibank includes all I/Os starting from one end of the bank to the first power triple and eight more I/Os after the power triple. Therefore, the first VREF minibank may contain (0 + 8), (2 + 8), (4 + 8), (6 + 8), or (8 + 8) I/Os. The second VREF minibank is adjacent to the first VREF minibank and contains eight I/Os, a power triple, and eight more I/Os after the triple. An analogous rule applies to all other VREF minibanks but the last. The last VREF minibank is adjacent to the previous one but contains eight I/Os, a power triple, and all I/Os left at the end of the bank. This bank may also contain (8 + 0), (8 + 2), (8 + 4), (8 + 6), or (8 + 8) available I/Os. Example: 4 I/Os Triple 8 I/Os, 8 I/Os Triple 8 I/Os, 8 I/Os Triple 2 I/Os i.e., minibank A = (4 + 8) I/Os, minibank B = (8 + 8) I/Os, minibank C = (8 + 2) I/Os Assigning the VREF Voltage to a Bank When importing the PDC file, the VREF voltage can be assigned to the I/O bank. The PDC command is as follows: set_iobank -vref [value] Another method for assigning VREF is by using MVN > Edit > I/O Bank Settings (Figure 8-14 on page 8-16). v1.1 8 - 15 I/O Software Control in Low-Power Flash Devices VREF for GTL+ 3.3 V Figure 8-14 * Selecting VREF Voltage for the I/O Bank Assigning VREF Pins for a Bank The user can use default pins for VREF. In this case, select the Use default pins for VREFs check box (Figure 8-14). This option guarantees full VREF coverage of the bank. The equivalent PDC command is as follows: set_vref_default [bank name] To be able to choose VREF pins, adequate VREF pins must be created to allow legal placement of the compatible voltage-referenced I/Os. To assign VREF pins manually, the PDC command is as follows: set_vref -bank [bank name] [package pin numbers] For ChipPlanner/PinEditor to show the range of a VREF pin, perform the following steps: 1. Assign VCCI to a bank using MVN > Edit > I/O Bank Settings. 2. Open ChipPlanner. Zoom in on an I/O package pin in that bank. 3. Highlight the pin and then right-click. Choose Use Pin for VREF. 8 -1 6 v1.1 I/O Software Control in Low-Power Flash Devices 4. Right-click and then choose Show VREF range. All the pins covered by that VREF pin will be highlighted (Figure 8-15). Figure 8-15 * VREF Range Using PinEditor or ChipPlanner, VREF pins can also be assigned (Figure 8-16). Figure 8-16 * Assigning VREF from PinEditor To unassign a VREF pin: 1. Select the pin to unassign. 2. Right-click and choose Use Pin for VREF. The check mark next to the command disappears. The VREF pin is now a regular pin. Resetting the pin may result in unassigning I/O cores, even if they are locked. In this case, a warning message appears so you can cancel the operation. After you assign the VREF pins, right-click a VREF pin and choose Highlight VREF Range to see how many I/Os are covered by this pin. To unhighlight the range, choose Unhighlight All from the Edit menu. v1.1 8 - 17 I/O Software Control in Low-Power Flash Devices Automatically Assigning Technologies to I/O Banks The I/O Bank Assigner (IOBA) tool runs automatically when you run Layout. You can also use this tool from within the MultiView Navigator (Figure 8-18). The IOBA tool automatically assigns technologies and VREF pins (if required) to every I/O bank that does not currently have any technologies assigned to it. This tool is available when at least one I/O bank is unassigned. To automatically assign technologies to I/O banks, choose I/O Bank Assigner from the Tools menu (or click the I/O Bank Assigner's toolbar button, shown in Figure 8-17). Figure 8-17 * I/O Bank Assigner's Toolbar Button Messages will appear in the Output window informing you when the automatic I/O bank assignment begins and ends. If the assignment is successful, the message "I/O Bank Assigner completed successfully" appears in the Output window, as shown in Figure 8-18. Figure 8-18 * I/O Bank Assigner Displays Messages in Output Window 8 -1 8 v1.1 I/O Software Control in Low-Power Flash Devices If the assignment is not successful, an error message appears in the Output window. To undo the I/O bank assignments, choose Undo from the Edit menu. Undo removes the I/O technologies assigned by the IOBA. It does not remove the I/O technologies previously assigned. To redo the changes undone by the Undo command, choose Redo from the Edit menu. To clear I/O bank assignments made before using the Undo command, manually unassign or reassign I/O technologies to banks. To do so, choose I/O Bank Settings from the Edit menu to display the I/O Bank Settings dialog box. Conclusion IGLOO and ProASIC3 support for multiple I/O standards minimizes board-level components and makes possible a wide variety of applications. The Actel Designer software, integrated with Actel Libero IDE, presents a clear visual display of I/O assignments, allowing users to verify I/O and boardlevel design requirements before programming the device. The device I/O features and functionalities ensure board designers can produce low-cost and low-power FPGA applications fulfilling the complexities of contemporary design needs. Related Documents Handbook Documents DDR for Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_DDR_HBs.pdf Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices http://www.actel.com/documents/LPD_FlashFreeze_HBs.pdf Global Resources in Actel Low-Power Flash Devices http://www.actel.com/documents/LPD_Global_HBs.pdf I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/IGLOO_PA3_IO_HBs.pdf I/O Structures in IGLOO PLUS Devices http://www.actel.com/documents/IGLOOPLUS_IO_HBs.pdf I/O Structures in IGLOOe and ProASIC3E Devices http://www.actel.com/documents/IGLOOe_PA3E_IO_HBs.pdf Pin Descriptions http://www.actel.com/documents/LPD_PinDescriptions_HBs.pdf Power-Up/-Down Behavior of ProASIC3/E Devices http://www.actel.com/documents/ProASIC3_E_PowerUp_HBs.pdf ProASIC3/E SSO and Pin Placement and Guidelines http://www.actel.com/documents/PA3_E_SSO_HBs.pdf User's Guides Actel Libero IDE User's Guide http://www.actel.com/documents/libero_ug.pdf IGLOO, Fusion, and ProASIC3 Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf SmartGen Core Reference Guide http://www.actel.com/documents/genguide_ug.pdf v1.1 8 - 19 I/O Software Control in Low-Power Flash Devices Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-026-0 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version v1.0 (January 2008) 8 -2 0 Changes in Current Version (v1.1) Page This document was previously part of the I/O Structures in IGLOO and ProASIC3 Devices document. The content was separated and made into a new document. N/A Table 8-2 * Designer State (resulting from I/O attribute modification) was updated to include note 2 for IGLOO PLUS. 8-3 v1.1 DDR for Actel's Low-Power Flash Devices 9 - DDR for Actel's Low-Power Flash Devices Introduction The I/Os in IGLOO,(R) Fusion, and ProASIC(R)3 devices support Double Data Rate (DDR) mode. In this mode, new data is present on every transition (or clock edge) of the clock signal. This mode doubles the data transfer rate compared with Single Data Rate (SDR) mode, where new data is present on one transition (or clock edge) of the clock signal. Low-power flash devices have DDR circuitry built into the I/O tiles. I/Os are configured to be DDR receivers or transmitters by instantiating the appropriate special macros (examples shown in Figure 9-4 on page 9-6 and Figure 9-5 on page 9-7) and buffers (DDR_OUT or DDR_REG) in the RTL design. This document discusses the options the user can choose to configure the I/Os in this mode and how to instantiate them in the design. Double Data Rate (DDR) Architecture Low-power flash devices support 350 MHz DDR inputs and outputs. In DDR mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidths and signal integrity requirements, making them very efficient for implementing very high-speed systems. High-speed DDR interfaces can be implemented using LVDS. In IGLOOe and ProASIC3E devices, DDR interfaces can also be implemented using the HSTL, SSTL, and LVPECL I/O standards. The DDR feature is primarily implemented in the FPGA core periphery and is not tied to a specific I/O technology or limited to any I/O standard. INBUF_SSTL2_I PAD PAD Y DDR_REG D DataR QR DDR_OUT DR DF Q OUTBUF_SSTL3_I Q PAD DataF CLK QF CLR CLR CLR Figure 9-1 * DDR Support in Low-Power Flash Devices v1.1 9-1 DDR for Actel's Low-Power Flash Devices DDR Support in Low-Power Devices The low-power flash families listed in Table 9-1 support the DDR feature and the functions described in this document. Table 9-1 * Family Low-Power Flash Families 1 Timing Numbers2 Description IGLOO Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*FreezeTM IGLOO DC and Switching technology Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional IGLOOe DC and Switching PLLs, and additional I/O standards Characteristics ProASIC3L Low-power, high-performance Flash*Freeze technology ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, ProASIC3E DC and Switching and additional I/O standards Characteristics ProASIC3 Automotive Low-power, high-performance Automotive applications Fusion Low-power mixed-signal Programmable System Chip (PSC) 1.2 V FPGAs FPGAs with ProASIC3L DC and Switching Characteristics ProASIC3 DC and Switching Characteristics qualified for Automotive ProASIC3 DC and Switching Characteristics Fusion DC and Power Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 9-1) provide a selection of secure, low-power, liveat-power-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO FPGAs are the only 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 30% less static power and over 50% less dynamic power than PLD alternatives. Flash*Freeze technology used in IGLOO and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. The Actel Fusion(R) family, based on the highly successful ProASIC3 flash FPGA architecture, has been designed as a high-performance, mixed-signal Programmable System Chip. Fusion supports many peripherals, including embedded flash memory, analog-to-digital Converter (ADC), high-drive outputs, RC and crystal oscillators, and real-time counter (RTC). The total available on-chip memory, including the flash array blocks, is greater than that found in SRAM FPGAs. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 9-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 9-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 9 -2 v1.1 DDR for Actel's Low-Power Flash Devices I/O Cell Architecture Low-power flash devices support DDR in the I/O cells in four different modes: Input, Output, Tristate, and Bidirectional pins. For each mode, different I/O standards are supported, with most I/O standards having special sub-options. Refer to Table 9-2 for a sample of the available I/O options. Additional I/O options can be found in the relevant family datasheet. Table 9-2 * DDR I/O Options DDR Register Type Receive Register Transmit Register I/O Type I/O Standard Sub-Options Input Normal None LVCMOS Voltage 1.5 V, 1.8 V, 2.5 V, 5 V (1.5 V default) Pull-Up None (default) Output Comments 3.3 V TTL (default) PCI/PCI-X None GTL/GTL+ Voltage HSTL Class I / II (I default) SSTL2/SSTL3 Class I / II (I default) LVPECL None LVDS None Normal None LVTTL Output Drive Slew Rate 2.5 V, 3.3 V (3.3 V default) 3.3 V TTL (default) 2, 4, 6, 8, 12, 16, 24, 36 mA (8 mA default) Low/high (high default) LVCMOS Voltage PCI/PCI-X None GTL/GTL+ Voltage HSTL Class I / II (I default) SSTL2/SSTL3 Class I / II (I default) LVPECL None LVDS None v1.1 1.5 V, 1.8 V, 2.5 V, 5 V (1.5 V default) 1.8 V, 2.5 V, 3.3 V (3.3 V default) 9-3 DDR for Actel's Low-Power Flash Devices Table 9-2 * DDR I/O Options (continued) DDR Register Type I/O Type I/O Standard Transmit Register (continued) Tristate Buffer Normal LVTTL Sub-Options Comments Enable Polarity Low/high (low default) Output Drive Slew Rate 2, 4, 6, 8, 12,16, 24, 36 mA (8 mA default) Low/high (high default) Enable Polarity Low/high (low default) Pull-Up/-Down None (default) LVCMOS Voltage Output Drive Slew Rate 1.5 V, 1.8 V, 2.5 V, 5 V (1.5 V default) 2, 4, 6, 8, 12, 16, 24, 36 mA (8 mA default) Low/high (high default) Enable Polarity Low/high (low default) Pull-Up/-Down None (default) PCI/PCI-X GTL/GTL+ Enable Polarity Low/high (low default) Voltage 1.8 V, 2.5 V, 3.3 V (3.3 V default) Enable Polarity Low/high (low default) HSTL Class I / II (I default) Enable Polarity Low/high (low default) SSTL2/SSTL3 Class I / II (I default) Enable Polarity Low/high (low default) Bidirectional Buffer Normal LVTTL Enable Polarity Low/high (low default) Output Drive Slew Rate 2, 4, 6, 8, 12, 16, 24, 36 mA (8 mA default) Low/high (high default) Enable Polarity Low/high (low default) Pull-Up/-Down None (default) LVCMOS Voltage 1.5 V, 1.8 V, 2.5 V, 5 V (1.5 V default) Enable Polarity Low/high (low default) Pull-Up PCI/PCI-X None (default) None Enable Polarity Low/high (low default) GTL/GTL+ Voltage 1.8 V, 2.5 V, 3.3 V (3.3 V default) Enable Polarity Low/high (low default) HSTL Class I / II (I default) Enable Polarity Low/high (low default) SSTL2/SSTL3 Class I / II (I default) Enable Polarity Low/high (low default) 9 -4 v1.1 DDR for Actel's Low-Power Flash Devices Input Support for DDR The basic structure to support a DDR input is shown in Figure 9-2. Three input registers are used to capture incoming data, which is presented to the core on each rising edge of the I/O register clock. Each I/O tile supports DDR inputs. INBUF_SSTL2_I DDR_REG Y PAD D QR PAD QR CLK QF QF CLR CLR Figure 9-2 * DDR Input Register Support in Low-Power Flash Devices Output Support for DDR The basic DDR output structure is shown in Figure 9-1 on page 9-1. New data is presented to the output every half clock cycle. Note: DDR macros and I/O registers do not require additional routing. The combiner automatically recognizes the DDR macro and pushes its registers to the I/O register area at the edge of the chip. The routing delay from the I/O registers to the I/O buffers is already taken into account in the DDR macro. DDR_OUT DataR DataF DR DF Q OUTBUF_SSTL3_I Q PAD CLK CLR CLR Figure 9-3 * DDR Output Register (SSTL3 Class I) v1.1 9-5 DDR for Actel's Low-Power Flash Devices Instantiating DDR Registers Using SmartGen is the simplest way to generate the appropriate RTL files for use in the design. Figure 9-4 shows an example of using SmartGen to generate a DDR SSTL2 Class I input register. SmartGen provides the capability to generate all of the DDR I/O cells as described. The user, through the graphical user interface, can select from among the many supported I/O standards. The output formats supported are Verilog, VHDL, and EDIF. Figure 9-5 on page 9-7 through Figure 9-8 on page 9-10 show the I/O cell configured for DDR using SSTL2 Class I technology. For each I/O standard, the I/O pad is buffered by a special primitive that indicates the I/O standard type. Figure 9-4 * Example of Using SmartGen to Generate a DDR SSTL2 Class I Input Register 9 -6 v1.1 DDR for Actel's Low-Power Flash Devices DDR Input Register INBUF_SSTL2_I DDR_REG Y PAD D QR PAD QR CLK QF QF CLR CLR Figure 9-5 * DDR Input Register (SSTL2 Class I) The corresponding structural representations, as generated by SmartGen, are shown below: Verilog module DDR_InBuf_SSTL2_I(PAD,CLR,CLK,QR,QF); input output PAD, CLR, CLK; QR, QF; wire Y; INBUF_SSTL2_I INBUF_SSTL2_I_0_inst(.PAD(PAD),.Y(Y)); DDR_REG DDR_REG_0_inst(.D(Y),.CLK(CLK),.CLR(CLR),.QR(QR),.QF(QF)); endmodule VHDL library ieee; use ieee.std_logic_1164.all; --The correct library will be inserted automatically by SmartGen library proasic3; use proasic3.all; --library fusion; use fusion.all; --library igloo; use igloo.all; entity DDR_InBuf_SSTL2_I is port(PAD, CLR, CLK : in std_logic; end DDR_InBuf_SSTL2_I; architecture DEF_ARCH of QR, QF : out std_logic) ; DDR_InBuf_SSTL2_I is component INBUF_SSTL2_I port(PAD : in std_logic := 'U'; Y : out std_logic) ; end component; component DDR_REG port(D, CLK, CLR : in std_logic := 'U'; QR, QF : out std_logic) ; end component; signal Y : std_logic ; begin INBUF_SSTL2_I_0_inst : INBUF_SSTL2_I port map(PAD => PAD, Y => Y); DDR_REG_0_inst : DDR_REG port map(D => Y, CLK => CLK, CLR => CLR, QR => QR, QF => QF); end DEF_ARCH; v1.1 9-7 DDR for Actel's Low-Power Flash Devices DDR Output Register DDR_OUT DataR DataF DR DF Q OUTBUF_SSTL3_I Q PAD CLK CLR CLR Figure 9-6 * DDR Output Register (SSTL3 Class I) Verilog module DDR_OutBuf_SSTL3_I(DataR,DataF,CLR,CLK,PAD); input output DataR, DataF, CLR, CLK; PAD; wire Q, VCC; VCC VCC_1_net(.Y(VCC)); DDR_OUT DDR_OUT_0_inst(.DR(DataR),.DF(DataF),.CLK(CLK),.CLR(CLR),.Q(Q)); OUTBUF_SSTL3_I OUTBUF_SSTL3_I_0_inst(.D(Q),.PAD(PAD)); endmodule VHDL library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity DDR_OutBuf_SSTL3_I is port(DataR, DataF, CLR, CLK : in std_logic; end DDR_OutBuf_SSTL3_I; architecture DEF_ARCH of PAD : out std_logic) ; DDR_OutBuf_SSTL3_I is component DDR_OUT port(DR, DF, CLK, CLR : in std_logic := 'U'; Q : out std_logic) ; end component; component OUTBUF_SSTL3_I port(D : in std_logic := 'U'; PAD : out std_logic) ; end component; component VCC port( Y : out std_logic); end component; signal Q, VCC_1_net : std_logic ; begin VCC_2_net : VCC port map(Y => VCC_1_net); DDR_OUT_0_inst : DDR_OUT port map(DR => DataR, DF => DataF, CLK => CLK, CLR => CLR, Q => Q); OUTBUF_SSTL3_I_0_inst : OUTBUF_SSTL3_I port map(D => Q, PAD => PAD); end DEF_ARCH; 9 -8 v1.1 DDR for Actel's Low-Power Flash Devices DDR Tristate Output Register Y TrienAux Trien INV A DDR_OUT DataR DataF DR DF Q Q PAD TRIBUFF_F_8U CLK CLR CLR Figure 9-7 * DDR Tristate Output Register, LOW Enable, 8 mA, Pull-Up (LVTTL) Verilog module DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp(DataR, DataF, CLR, CLK, Trien, PAD); input output DataR, DataF, CLR, CLK, Trien; PAD; wire TrienAux, Q; INV Inv_Tri(.A(Trien),.Y(TrienAux)); DDR_OUT DDR_OUT_0_inst(.DR(DataR),.DF(DataF),.CLK(CLK),.CLR(CLR),.Q(Q)); TRIBUFF_F_8U TRIBUFF_F_8U_0_inst(.D(Q),.E(TrienAux),.PAD(PAD)); endmodule VHDL library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp is port(DataR, DataF, CLR, CLK, Trien : in std_logic; PAD : out std_logic) ; end DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp; architecture DEF_ARCH of DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp is component INV port(A : in std_logic := 'U'; Y : out std_logic) ; end component; component DDR_OUT port(DR, DF, CLK, CLR : in std_logic := 'U'; Q : out std_logic) ; end component; component TRIBUFF_F_8U port(D, E : in std_logic := 'U'; PAD : out std_logic) ; end component; signal TrienAux, Q : std_logic ; begin Inv_Tri : INV v1.1 9-9 DDR for Actel's Low-Power Flash Devices port map(A => Trien, Y => TrienAux); DDR_OUT_0_inst : DDR_OUT port map(DR => DataR, DF => DataF, CLK => CLK, CLR => CLR, Q => Q); TRIBUFF_F_8U_0_inst : TRIBUFF_F_8U port map(D => Q, E => TrienAux, PAD => PAD); end DEF_ARCH; DDR Bidirectional Buffer Trien INV A Y E DDR_OUT DataR DataF DR DF Q CLK D PAD BIBUF_HSTL_I CLR CLR QR QF DDR_REG QR D Y QF CLR Figure 9-8 * DDR Bidirectional Buffer, LOW Output Enable (HSTL Class II) Verilog module DDR_BiDir_HSTL_I_LowEnb(DataR,DataF,CLR,CLK,Trien,QR,QF,PAD); input output inout DataR, DataF, CLR, CLK, Trien; QR, QF; PAD; wire TrienAux, D, Q; INV Inv_Tri(.A(Trien), .Y(TrienAux)); DDR_OUT DDR_OUT_0_inst(.DR(DataR),.DF(DataF),.CLK(CLK),.CLR(CLR),.Q(Q)); DDR_REG DDR_REG_0_inst(.D(D),.CLK(CLK),.CLR(CLR),.QR(QR),.QF(QF)); BIBUF_HSTL_I BIBUF_HSTL_I_0_inst(.PAD(PAD),.D(Q),.E(TrienAux),.Y(D)); endmodule 9 -1 0 v1.1 DDR for Actel's Low-Power Flash Devices VHDL library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity DDR_BiDir_HSTL_I_LowEnb is port(DataR, DataF, CLR, CLK, Trien : in std_logic; QR, QF : out std_logic; PAD : inout std_logic) ; end DDR_BiDir_HSTL_I_LowEnb; architecture DEF_ARCH of DDR_BiDir_HSTL_I_LowEnb is component INV port(A : in std_logic := 'U'; Y : out std_logic) ; end component; component DDR_OUT port(DR, DF, CLK, CLR : in std_logic := 'U'; Q : out std_logic) ; end component; component DDR_REG port(D, CLK, CLR : in std_logic := 'U'; QR, QF : out std_logic) ; end component; component BIBUF_HSTL_I port(PAD : inout std_logic := 'U'; D, E : in std_logic := 'U'; Y : out std_logic) ; end component; signal TrienAux, D, Q : std_logic ; begin Inv_Tri : INV port map(A => Trien, Y => TrienAux); DDR_OUT_0_inst : DDR_OUT port map(DR => DataR, DF => DataF, CLK => CLK, CLR => CLR, Q => Q); DDR_REG_0_inst : DDR_REG port map(D => D, CLK => CLK, CLR => CLR, QR => QR, QF => QF); BIBUF_HSTL_I_0_inst : BIBUF_HSTL_I port map(PAD => PAD, D => Q, E => TrienAux, Y => D); end DEF_ARCH; v1.1 9 - 11 DDR for Actel's Low-Power Flash Devices Design Example Figure 9-9 shows a simple example of a design using both DDR input and DDR output registers. The user can copy the HDL code in Actel Libero(R) Integrated Design Environment (IDE) and go thorough the design flow. Figure 9-10 and Figure 9-11 on page 9-13 show the netlist and ChipPlanner views of the ddr_test design. Diagrams may vary slightly for different families. INBUF_SSTL2_I PAD PAD Y DDR_REG D DataR QR DDR_OUT DR DF Q DataF CLK QF CLR CLR CLR Figure 9-9 * Design Example Figure 9-10 * DDR Test Design as Seen by NetlistViewer for IGLOO/e Devices 9 -1 2 v1.1 OUTBUF_SSTL3_I Q PAD DDR for Actel's Low-Power Flash Devices Figure 9-11 * DDR Input/Output Cells as Seen by ChipPlanner for IGLOO/e Devices Verilog module Inbuf_ddr(PAD,CLR,CLK,QR,QF); input PAD, CLR, CLK; output QR, QF; wire Y; DDR_REG DDR_REG_0_inst(.D(Y), .CLK(CLK), .CLR(CLR), .QR(QR), .QF(QF)); INBUF INBUF_0_inst(.PAD(PAD), .Y(Y)); endmodule module Outbuf_ddr(DataR,DataF,CLR,CLK,PAD); input DataR, DataF, CLR, CLK; output PAD; wire Q, VCC; VCC VCC_1_net(.Y(VCC)); DDR_OUT DDR_OUT_0_inst(.DR(DataR), .DF(DataF), .CLK(CLK), .CLR(CLR), .Q(Q)); OUTBUF OUTBUF_0_inst(.D(Q), .PAD(PAD)); endmodule v1.1 9 - 13 DDR for Actel's Low-Power Flash Devices module ddr_test(DIN, CLK, CLR, DOUT); input DIN, CLK, CLR; output DOUT; Inbuf_ddr Inbuf_ddr (.PAD(DIN), .CLR(clr), .CLK(clk), .QR(qr), .QF(qf)); Outbuf_ddr Outbuf_ddr (.DataR(qr),.DataF(qf), .CLR(clr), .CLK(clk),.PAD(DOUT)); INBUF INBUF_CLR (.PAD(CLR), .Y(clr)); INBUF INBUF_CLK (.PAD(CLK), .Y(clk)); endmodule Simulation Consideration Actel DDR simulation models use inertial delay modeling by default (versus transport delay modeling). As such, pulses that are shorter than the actual gate delays should be avoided, as they will not be seen by the simulator and may be an issue in post-routed simulations. The user must be aware of the default delay modeling and must set the correct delay model in the simulator as needed. Conclusion IGLOO, Fusion, and ProASIC3 devices support a wide range of DDR applications with different I/O standards and include built-in DDR macros. The powerful capabilities provided by SmartGen and its GUI can simplify the process of including DDR macros in designs and minimize design errors. Additional considerations should be taken into account by the designer in design floorplanning and placement of I/O flip-flops to minimize datapath skew and to help improve system timing margins. Other system-related issues to consider include PLL and clock partitioning. Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-010-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) 9 -1 4 Changes in the Current Version (v1.1) Page The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 9-2 v1.1 Packaging and Pin Descriptions Pin Descriptions 10 - Pin Descriptions Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always be connected to GND on the board. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.5 V for ProASIC(R)3/E devices, 1.5 V for IGLOO(R)/e V5 devices, and 1.2 V or 1.5 V for IGLOO/e V2 and ProASIC3L devices. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device. For IGLOO/e V2 and ProASIC3L devices, VCC can be switched dynamically from 1.2 V to 1.5 V or vice versa. This allows in-system programming (ISP) when VCC is at 1.5 V and the benefit of low-power operation when VCC is at 1.2 V. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to eight I/O banks on low-power flash devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.2 V (not supported on ProASIC3/E devices), 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the VMV plane is decoupled from the simultaneous switching noise originated from the output buffer VCCI domain. This minimizes the noise transfer within the package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.2 V (ProASIC3L and IGLOO/e devices only), 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLA/B/C/D/E/F PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V or 1.2 V, depending on the device family. * 1.5 V for IGLOO V5, IGLOOe V5, ProASIC3, and ProASIC3E devices * 1.2 V or 1.5 V for IGLOO V2, IGLOOe V2, ProASIC3L, and ProASIC3EL devices When the PLLs are not used, the Actel Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Actel recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from PLL. Refer to the PLL Power Supply Decoupling section of Clock Conditioning Circuits in IGLOO and ProASIC3 Devices for a complete board solution for the PLL analog power supply and ground. * There is one VCCPLF pin on IGLOO, IGLOO PLUS, ProASIC3L, and ProASIC3 devices. * There are six VCCPLX pins on IGLOOe, ProASIC3EL, and ProASIC3E devices. v1.1 1 0 -1 Pin Descriptions VCOMPLA/B/C/D/E/F PLL Ground Ground to analog PLL power supplies. When the PLLs are not used, the Actel Designer place-androute tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. * There is one VCOMPLF pin on IGLOO, ProASIC3L, and ProASIC3 devices. * There are six VCOMPL pins (PLL ground) on IGLOOe, ProASIC3EL, and ProASIC3E devices. VJTAG JTAG Supply Voltage Low-power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. Actel recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. VPUMP Programming Supply Voltage IGLOO, ProASIC3L, and ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in the datasheet. When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 F and 0.33 F capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. Actel recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. User-Defined Supply Pins VREF I/O Voltage Reference Reference voltage for I/O minibanks in IGLOOe, ProASIC3EL, and ProASIC3E devices. VREF pins are configured by the user from regular I/Os, and any I/O in a bank, except JTAG I/Os, can be designated the voltage reference I/O. Only certain I/O standards require a voltage reference--HSTL (I) and (II), SSTL2 (I) and (II), SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support the number of I/Os available in its minibank. 1 0 -2 v1.1 Pin Descriptions User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. Unused I/Os are configured as follows: GL * Output buffer is disabled (with tristate value of high impedance) * Input buffer is disabled (with tristate value of high impedance) * Weak pull-up is programmed Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in Clock Conditioning Circuits in IGLOO and ProASIC3 Devices. All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input. Refer to the I/O Structure section of the handbook for the device you are using for an explanation of the naming of global pins. FF Flash*Freeze Mode Activation Pin Flash*FreezeTM is available on IGLOO and ProASIC3L devices. It is not supported on ProASIC3/E devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active-low, has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O. For IGLOOe and ProASIC3EL only, the FF pin can be configured as a Schmitt trigger input. When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted. The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin should be treated as a sensitive asynchronous signal. When defining pin placement and board layout, simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be considered. Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both Flash*Freeze mode and normal operation mode. No user intervention is required. v1.1 1 0 -3 Pin Descriptions Table 10-1 shows the Flash*Freeze pin location on the available packages for IGLOO and ProASIC3L devices. The Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing migration to larger or smaller IGLOO devices while maintaining the same pin location on the board. Refer to Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices for more information on I/O states during Flash*Freeze mode. Table 10-1 * Flash*Freeze Pin Location in IGLOO and ProASIC3L Family Packages (deviceindependent) IGLOO and ProASIC3L Packages Flash*Freeze Pin CS81/UC81 H2 CS121 J5 CS196 P3 QN68 18 QN132 B12 CS281 W2 CS201 (package only available for IGLOO PLUS devices) R4 CS289 (package only available for IGLOO PLUS devices) TBD VQ100 27 FG144 L3 FG256 T3 FG484 W6 FG896 AH4 PQ208 (package only available for ProASIC3L devices) PQ208-A3P250 56 PQ208-A3P600L 55 PQ2097-A3P1000L 55 PQ208-A3PE3000L 58 JTAG Pins Low-power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/-down resistor. If JTAG is not used, Actel recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. 1 0 -4 v1.1 Pin Descriptions Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 10-2 for more information. Table 10-2 * Recommended Tie-Off Values for the TCK and TRST Pins VJTAG Tie-Off Resistance VJTAG at 3.3 V 200 to 1 k VJTAG at 2.5 V 200 to 1 k VJTAG at 1.8 V 500 to 1 k VJTAG at 1.5 V 500 to 1 k Notes: 1. Equivalent parallel resistance if more than one device is on the JTAG chain 2. The TCK pin can be pulled up/down. 3. The TRST pin is pulled down. TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP, and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 10-2 and must satisfy the parallel resistance value requirement. The values in Table 10-2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In such cases, Actel recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Special Function Pins NC No Connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do Not Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. v1.1 1 0 -5 Pin Descriptions Related Documents Handbook Documents Clock Conditioning Circuits in IGLOO and ProASIC3 Devices http://www.actel.com/documents/LPD_CCC_HBs.pdf I/O Structures in IGLOO PLUS Devices http://www.actel.com/documents/IGLOOPLUS_IO_HBs.pdf I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/IGLOO_PA3_IO_HBs.pdf I/O Structures in IGLOOe and ProASIC3E Devices http://www.actel.com/documents/IGLOOe_PA3E_IO_HBs.pdf Flash*Freeze Technology and Low-Power Modes in IGLOO and ProASIC3L Devices http://www.actel.com/documents/LPD_FlashFreeze_HBs.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet. To improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage information. No technical changes were made to the content unless explicitly listed. Part Number 51700094-011-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) 1 0 -6 Changes in Current Version (v1.1) Page The "VCCIBx I/O Supply Voltage" section was revised to note that 1.2 V is not supported for ProASIC3/E devices. The "VMVx I/O Supply Voltage (quiet)" section was updated to state that VMVx can also be 1.2 V nominal voltage on ProASIC3L and IGLOO/e devices. 10-1 The "Handbook Documents" section was revised to include the three different I/O Structures chapters for IGLOO and ProASIC3 device families. 10-6 The "VCCPLA/B/C/D/E/F PLL Supply Voltage" section and "VCOMPLA/B/C/D/E/F PLL Ground" section were revised. The "VCCPLF PLL Supply Voltage" section and "VCOMPLF PLL Ground" section were removed. 10-1 to 10-2 The following packages were added to Table 10-1 * Flash*Freeze Pin Location in IGLOO and ProASIC3L Family Packages (device-independent): UC81, QN68, CS201, and CS289. Flash*Freeze pin W2 was specified for the CS281 package. The PG208 package was changed to the correct designation of PQ208. 10-4 v1.1 Packaging 11 - Packaging Semiconductor technology is constantly shrinking in size while growing in capability and functional integration. To enable next-generation silicon technologies, semiconductor packages have also evolved to provide improved performance and flexibility. Actel consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability and performance. Actel IC packaging technology efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition, Actel offers a variety of packages designed to meet your most demanding application and economic requirements for today's embedded and mobile systems. The following documents provide packaging information and device selection for low-power flash devices. Package Selector Guide http://www.actel.com/documents/selguide.pdf Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. Package Mechanical Drawings http://www.actel.com/documents/PckgMechDrwngs.pdf This document contains the package mechanical drawings for all packages currently or previously supplied by Actel. Use the bookmarks to navigate to the package mechanical drawings. Related Documents Additional packaging materials are available at http://www.actel.com/products/solutions/package/docs.aspx. Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 5170009-012-0 Revised January 2008 v1.0 1 1 -1 Design Migration Application Note AC314 12 - Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Introduction The purpose of this document is to assist in migrating designs in ProASIC(R)3 A3P1000, A3P600, and A3P400 devices from higher-density to mid-density devices. There are three possible migration paths: * A3P1000 to A3P600 * A3P1000 to A3P400 * A3P600 to A3P400 Since one of the key factors is pin compatibility, this document addresses pin compatibility for all available packages common to the A3P1000, A3P600, and A3P400 devices. Design Migration ProASIC3 family devices are architecturally compatible with each other. However, designers must pay attention to a few key areas when migrating a design. The specific issues discussed throughout this application note are as follows: * "Design and Device Evaluation" * "Device and Package Compatibility" on page 12-2 * "Migration and Implementation Methodologies" on page 12-3 * "I/O Banks and Standards" on page 12-4 * "Power Supply and Board-Level Considerations" on page 12-4 * "Pin Migration and Compatibility" on page 12-5 Design and Device Evaluation When migrating a design, the primary task should be to compare the available resources between the two devices. The designer should evaluate effective gate count, RAM size, I/O banks, and number of I/Os (Table 12-1). In addition, necessary design timing analysis and simulations should be validated when porting designs to new ProASIC3 derivatives. Table 12-1 * Device Information A3P1000 A3P600 A3P400 1M 600 k 400 k 24,576 13,824 9,126 RAM (kbits) 144 108 54 RAM Blocks (4,608 bits) 32 24 12 I/O Banks (+ JTAG) 4 4 4 PQ208 154/35 154/35 151/34 FG144 97/25 97/25 97/25 FG256 177/44 177/43 178/38 FG484 300/74 235/60 194/38 System Gates Tiles (D-flip-flop) Maximum User I/Os per Package Note: Maximum user I/O is listed as single-ended/double-ended. v1.1 1 2 -1 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Device and Package Compatibility ProASIC3 devices and packaging were designed to allow considerable footprint compatibility for smoother migration. Common and Convertible I/Os between A3P400, A3P600, and A3P1000 Devices Table 12-2 shows the number of I/Os that are common between any two of these devices, as well as the number of I/Os that will require conversion per the suggested design migration rules given in the "Migration and Implementation Methodologies" section on page 12-3. Table 12-2 * Common and Convertible I/Os A3P1000 A3P600 A3P600 A3P400 Common I/Os Convertible I/Os Common I/Os Convertible I/Os Common I/Os Convertible I/Os PQ208 154 0 154 5 151 5 FG144 97 0 97 0 98 0 FG256 178 31 177 59 177 33 FG484 236 96 192 75 236 166 Package 1 2 -2 A3P1000 A3P400 v1.1 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Migration and Implementation Methodologies Table 12-3 lists some possible migration combinations and the recommended implementation rules for compatible design conversions from higher-density to lower-density devices. Refer to the "Related Documents" section on page 12-40 for other relevant Actel documentation. The "Pin Migration and Compatibility" section on page 12-5 contains tables that list the required rules for different pin combinations. If "Rule x" is mentioned for a pin combination, that combination requires the implementation methodology given in Table 12-3. Note that many combinations of high-density/low-density pins do not require these rules; the pins have complete type compatibility. These pins are marked in the pin tables with "None." Table 12-3 * Migration Rules from Higher-Density to Mid-Density Devices Migration Rule Issue Higher Density Lower Density NC Implementation Methodology 1 I/O or global I/O Leave this pin floating OR program I/Os as unused (software cannot program NC to usable I/O). 2 Single-ended I/O Global I/O 3 Global I/O 4 VCC or VCCIB(x)1,3 NC 5 VCCIB(x)1 VCCI B(y)2 Make sure the two bank voltage levels are the same. Tie the pin to the board's corresponding VCCIBx/VMVx plane. 6 VMV(x)1 VMV(y)2 Make sure the two bank voltage levels are the same. Tie pin to the board's corresponding VCCIBx/VMVx plane. 7 VMV(x)2 I/O or global I/O Leave the pin tied to the board VCCIBx/VMVx plane. Instantiate the I/Os as tristate buffers with OE = 0 and no weak pull-ups/-downs. 8 GNDQ Global I/O Leave both pins tied to board GNDQ plane. Instantiate the I/O as tristate buffer with OE = 0 and no weak pull-ups/-downs. 9 GNDQ NC GNDQ and NC need to be connected to GND. Instantiate the I/O buffer as a global single-ended I/O. Single-ended I/O Use the physical design constraint (PDC) to promote the single-ended I/O to a global pin. There is an additional delay that affects the setup time on the board. Or, do not use this pin as a global input on the higher-density device. Leave pin connected to board VCC or VCCIBx plane. Notes: 1. (x) = 1, 2, 3, or 4 2. (y) = 1, 2, 3, or 4 3. Refer to I/O Structures in IGLOO and ProASIC3 Devices for I/O naming conventions. v1.1 1 2 -3 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices I/O Banks and Standards ProASIC3 I/Os are partitioned into multiple I/O voltage banks. The number of banks is devicedependent. There are four I/O banks in A3P1000, A3P600, and A3P400 devices. Package VCCIBx pins are routed through the corresponding banks of the devices. The banks have dedicated supplies; therefore, only I/Os with compatible voltage standards can be assigned to the same I/O voltage bank. Power Supply and Board-Level Considerations I/O power supply requirements are one of the key aspects to consider for design migration. Since the migration is within the ProASIC3 family, there is no issue with respect to the core voltage, VCC. Pins that must be appropriately connected are VCCIBx (bank supply voltage to I/O output buffer and I/O logic), VMVx (quiet I/O supply voltage), GNDQ (quiet GND), and GND. An important function of GNDQ and VMVx is to decouple simultaneous switching noise for outputs (SSOs) to enhance signal integrity and improve noise immunity. The following are the key rules of migration for the above-mentioned pins: * VMVx and VCCIBx must be at the same voltage level for a given bank. * VCCIBx pins and VMVx pins in unused banks must be connected to GND. * Unused I/Os are automatically disabled by software. A specific power-supply sequence at power-up is not required. Any incorrect connection during the migration may affect overall dynamic or inrush power consumption and might even result in device malfunction. Additionally, the I/O naming convention in ProASIC3 devices has significant embedded information (i.e., pin location, bank number, signal type, polarity, and clock conditioning). For a detailed explanation, refer to the "User I/O Naming Convention" section in the I/O Structures in IGLOO and ProASIC3 Devices. This datasheet also contains additional information on power issues. 1 2 -4 v1.1 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Pin Migration and Compatibility PQ208 Package Table 12-4 * Pin Compatibility and Migration Table for the PQ208 Package A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 1 GND GND GND None None None 2 GAA2/IO225PDB3 GAA2/IO170PDB3 GAA2/IO155UDB3 None None None 3 IO225NDB3 IO170NDB3 IO155VDB3 None None None 4 GAB2/IO224PDB3 GAB2/IO169PDB3 GAB2/IO154UDB3 None None None 5 IO224NDB3 IO169NDB3 IO154VDB3 None None None 6 GAC2/IO223PDB3 GAC2/IO168PDB3 GAC2/IO153UDB3 None None None 7 IO223NDB3 IO168NDB3 IO153VDB3 None None None 8 IO222PDB3 IO167PDB3 IO152UDB3 None None None 9 IO222NDB3 IO167NDB3 IO152VDB3 None None None 10 IO220PDB3 IO166PDB3 IO151UDB3 None None None 11 IO220NDB3 IO166NDB3 IO151VDB3 None None None 12 IO218PDB3 IO165PDB3 IO150PDB3 None None None 13 IO218NDB3 IO165NDB3 IO150NDB3 None None None 14 IO216PDB3 IO164PDB3 IO149PDB3 None None None 15 IO216NDB3 IO164NDB3 IO149NDB3 None None None 16 VCC VCC VCC None None None 17 GND GND GND None None None 18 VCCIB3 VCCIB3 VCCIB3 None None None 19 IO212PDB3 IO163PDB3 IO148PDB3 None None None 20 IO212NDB3 IO163NDB3 IO148NDB3 None None None 21 GFC1/IO209PDB3 GFC1/IO161PDB3 GFC1/IO147PDB3 None None None 22 GFC0/IO209NDB3 GFC0/IO161NDB3 GFC0/IO147NDB3 None None None 23 GFB1/IO208PDB3 GFB1/IO160PDB3 GFB1/IO146PDB3 None None None 24 GFB0/IO208NDB3 GFB0/IO160NDB3 GFB0/IO146NDB3 None None None 25 VCOMPLF VCOMPLF VCOMPLF None None None 26 GFA0/IO207NPB3 GFA0/IO159NPB3 GFA0/IO145NPB3 None None None 27 VCCPLF VCCPLF VCCPLF None None None 28 GFA1/IO207PPB3 GFA1/IO159PPB3 GFA1/IO145PPB3 None None None 29 GND GND GND None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 -5 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-4 * Pin Compatibility and Migration Table for the PQ208 Package (continued) Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 30 GFA2/IO206PDB3 GFA2/IO158PDB3 GFA2/IO144PDB3 None None None 31 IO206NDB3 IO158NDB3 IO144NDB3 None None None 32 GFB2/IO205PDB3 GFB2/IO157PDB3 GFB2/IO143PDB3 None None None 33 IO205NDB3 IO157NDB3 IO143NDB3 None None None 34 GFC2/IO204PDB3 GFC2/IO156PDB3 GFC2/IO142PDB3 None None None 35 IO204NDB3 IO156NDB3 IO142NDB3 None None None 36 VCC VCC NC None Rule 4 Rule 4 37 IO199PDB3 IO147PDB3 IO141PSB3 None None None 38 IO199NDB3 IO147NDB3 IO140PDB3 None None None 39 IO197PSB3 IO146PSB3 IO140NDB3 None None None 40 VCCIB3 VCCIB3 VCCIB3 None None None 41 GND GND GND None None None 42 IO191PDB3 IO145PDB3 IO138PDB3 None None None 43 IO191NDB3 IO145NDB3 IO138NDB3 None None None 44 GEC1/IO190PDB3 GEC1/IO144PDB3 GEC1/IO137PDB3 None None None 45 GEC0/IO190NDB3 GEC0/IO144NDB3 GEC0/IO137NDB3 None None None 46 GEB1/IO189PDB3 GEB1/IO143PDB3 GEB1/IO136PDB3 None None None 47 GEB0/IO189NDB3 GEB0/IO143NDB3 GEB0/IO136NDB3 None None None 48 GEA1/IO188PDB3 GEA1/IO142PDB3 GEA1/IO135PDB3 None None None 49 GEA0/IO188NDB3 GEA0/IO142NDB3 GEA0/IO135NDB3 None None None 50 VMV3 VMV3 VMV3 None None None 51 GNDQ GNDQ GNDQ None None None 52 GND GND GND None None None 53 VMV2 VMV2 VMV2 None None None 54 GEA2/IO187RSB2 GEA2/IO141RSB2 NC None Rule 1 Rule 1 55 GEB2/IO186RSB2 GEB2/IO140RSB2 GEA2/IO134RSB2 None None None 56 GEC2/IO185RSB2 GEC2/IO139RSB2 GEB2/IO133RSB2 None None None 57 IO184RSB2 IO138RSB2 GEC2/IO132RSB2 None Rule 2 Rule 2 58 IO183RSB2 IO137RSB2 IO131RSB2 None None None 59 IO182RSB2 IO136RSB2 IO130RSB2 None None None 60 IO181RSB2 IO135RSB2 IO129RSB2 None None None 61 IO180RSB2 IO134RSB2 IO128RSB2 None None None 62 VCCIB2 VCCIB2 VCCIB2 None None None Pin Number 1 2 -6 v1.1 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-4 * Pin Compatibility and Migration Table for the PQ208 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 63 IO178RSB2 IO133RSB2 IO125RSB2 None None None 64 IO176RSB2 IO131RSB2 IO123RSB2 None None None 65 GND GND GND None None None 66 IO174RSB2 IO129RSB2 IO121RSB2 None None None 67 IO172RSB2 IO127RSB2 IO119RSB2 None None None 68 IO170RSB2 IO125RSB2 IO117RSB2 None None None 69 IO168RSB2 IO123RSB2 IO115RSB2 None None None 70 IO166RSB2 IO121RSB2 IO113RSB2 None None None 71 VCC VCC VCC None None None 72 VCCIB2 VCCIB2 VCCIB2 None None None 73 IO162RSB2 IO118RSB2 IO112RSB2 None None None 74 IO160RSB2 IO117RSB2 IO111RSB2 None None None 75 IO158RSB2 IO116RSB2 IO110RSB2 None None None 76 IO156RSB2 IO115RSB2 IO109RSB2 None None None 77 IO154RSB2 IO114RSB2 IO108RSB2 None None None 78 IO152RSB2 IO113RSB2 IO107RSB2 None None None 79 IO150RSB2 IO112RSB2 IO106RSB2 None None None 80 IO148RSB2 IO110RSB2 IO104RSB2 None None None 81 GND GND GND None None None 82 IO143RSB2 IO109RSB2 IO102RSB2 None None None 83 IO141RSB2 IO108RSB2 IO101RSB2 None None None 84 IO139RSB2 IO107RSB2 IO100RSB2 None None None 85 IO137RSB2 IO106RSB2 IO99RSB2 None None None 86 IO135RSB2 IO105RSB2 IO98RSB2 None None None 87 IO133RSB2 IO104RSB2 IO97RSB2 None None None 88 VCC VCC VCC None None None 89 VCCIB2 VCCIB2 VCCIB2 None None None 90 IO128RSB2 IO102RSB2 IO94RSB2 None None None 91 IO126RSB2 IO100RSB2 IO92RSB2 None None None 92 IO124RSB2 IO98RSB2 IO90RSB2 None None None 93 IO122RSB2 IO96RSB2 IO88RSB2 None None None 94 IO120RSB2 IO94RSB2 IO86RSB2 None None None 95 IO118RSB2 IO90RSB2 IO84RSB2 None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 -7 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-4 * Pin Compatibility and Migration Table for the PQ208 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 96 GDC2/IO116RSB2 GDC2/IO89RSB2 GDC2/IO82RSB2 None None None 97 GND GND GND None None None 98 GDB2/IO115RSB2 GDB2/IO88RSB2 GDB2/IO81RSB2 None None None 99 GDA2/IO114RSB2 GDA2/IO87RSB2 GDA2/IO80RSB2 None None None 100 GNDQ GNDQ GNDQ None None None 101 TCK TCK TCK None None None 102 TDI TDI TDI None None None 103 TMS TMS TMS None None None 104 VMV2 VMV2 VMV2 None None None 105 GND GND GND None None None 106 VPUMP VPUMP VPUMP None None None 107 GNDQ GNDQ NC None Rule 8 Rule 8 108 TDO TDO TDO None None None 109 TRST TRST TRST None None None 110 VJTAG VJTAG VJTAG None None None 111 GDA0/IO113NDB1 GDA0/IO86NDB1 GDA0/IO79VDB1 None None None 112 GDA1/IO113PDB1 GDA1/IO86PDB1 GDA1/IO79UDB1 None None None 113 GDB0/IO112NDB1 GDB0/IO85NDB1 GDB0/IO78VDB1 None None None 114 GDB1/IO112PDB1 GDB1/IO85PDB1 GDB1/IO78UDB1 None None None 115 GDC0/IO111NDB1 GDC0/IO84NDB1 GDC0/IO77VDB1 None None None 116 GDC1/IO111PDB1 GDC1/IO84PDB1 GDC1/IO77UDB1 None None None 117 IO109NDB1 IO82NDB1 IO76VDB1 None None None 118 IO109PDB1 IO82PDB1 IO76UDB1 None None None 119 IO106NDB1 IO80NDB1 IO75NDB1 None None None 120 IO106PDB1 IO80PDB1 IO75PDB1 None None None 121 IO104PSB1 IO79PSB1 IO74RSB1 None None None 122 GND GND GND None None None 123 VCCIB1 VCCIB1 VCCIB1 None None None 124 IO99NDB1 IO75NDB1 NC None Rule 1 Rule 1 125 IO99PDB1 IO75PDB1 NC None Rule 1 Rule 1 126 NC NC VCC None Rule 4 Rule 4 127 IO96NDB1 IO73NDB1 IO72NDB1 None None None 128 GCC2/IO96PDB1 GCC2/IO73PDB1 GCC2/IO72PDB1 None None None Pin Number 1 2 -8 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-4 * Pin Compatibility and Migration Table for the PQ208 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 129 GCB2/IO95PSB1 GCB2/IO72PSB1 GCB2/IO71PSB1 None None None 130 GND GND GND None None None 131 GCA2/IO94PSB1 GCA2/IO71PSB1 GCA2/IO70PSB1 None None None 132 GCA1/IO93PDB1 GCA1/IO70PDB1 GCA1/IO69PDB1 None None None 133 GCA0/IO93NDB1 GCA0/IO70NDB1 GCA0/IO69NDB1 None None None 134 GCB0/IO92NDB1 GCB0/IO69NDB1 GCB0/IO68NDB1 None None None 135 GCB1/IO92PDB1 GCB1/IO69PDB1 GCB1/IO68PDB1 None None None 136 GCC0/IO91NDB1 GCC0/IO68NDB1 GCC0/IO67NDB1 None None None 137 GCC1/IO91PDB1 GCC1/IO68PDB1 GCC1/IO67PDB1 None None None 138 IO88NDB1 IO66NDB1 IO66NDB1 None None None 139 IO88PDB1 IO66PDB1 IO66PDB1 None None None 140 VCCIB1 VCCIB1 VCCIB1 None None None 141 GND GND GND None None None 142 VCC VCC VCC None None None 143 IO86PSB1 IO65PSB1 IO65RSB1 None None None 144 IO84NDB1 IO64NDB1 IO64NDB1 None None None 145 IO84PDB1 IO64PDB1 IO64PDB1 None None None 146 IO82NDB1 IO63NDB1 IO63NDB1 None None None 147 IO82PDB1 IO63PDB1 IO63PDB1 None None None 148 IO80NDB1 IO62NDB1 IO62NDB1 None None None 149 GBC2/IO80PDB1 GBC2/IO62PDB1 GBC2/IO62PDB1 None None None 150 IO79NDB1 IO61NDB1 IO61NDB1 None None None 151 GBB2/IO79PDB1 GBB2/IO61PDB1 GBB2/IO61PDB1 None None None 152 IO78NDB1 IO60NDB1 IO60NDB1 None None None 153 GBA2/IO78PDB1 GBA2/IO60PDB1 GBA2/IO60PDB1 None None None 154 VMV1 VMV1 VMV1 None None None 155 GNDQ GNDQ GNDQ None None None 156 GND GND GND None None None 157 VMV0 VMV0 VMV0 None None None 158 GBA1/IO77RSB0 GBA1/IO59RSB0 GBA1/IO59RSB0 None None None 159 GBA0/IO76RSB0 GBA0/IO58RSB0 GBA0/IO58RSB0 None None None 160 GBB1/IO75RSB0 GBB1/IO57RSB0 GBB1/IO57RSB0 None None None 161 GBB0/IO74RSB0 GBB0/IO56RSB0 GBB0/IO56RSB0 None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 -9 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-4 * Pin Compatibility and Migration Table for the PQ208 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 162 GND GND GND None None None 163 GBC1/IO73RSB0 GBC1/IO55RSB0 GBC1/IO55RSB0 None None None 164 GBC0/IO72RSB0 GBC0/IO54RSB0 GBC0/IO54RSB0 None None None 165 IO70RSB0 IO52RSB0 IO52RSB0 None None None 166 IO67RSB0 IO50RSB0 IO49RSB0 None None None 167 IO63RSB0 IO48RSB0 IO46RSB0 None None None 168 IO60RSB0 IO46RSB0 IO43RSB0 None None None 169 IO57RSB0 IO44RSB0 IO40RSB0 None None None 170 VCCIB0 VCCIB0 VCCIB0 None None None 171 VCC VCC VCC None None None 172 IO54RSB0 IO36RSB0 IO36RSB0 None None None 173 IO51RSB0 IO35RSB0 IO35RSB0 None None None 174 IO48RSB0 IO34RSB0 IO34RSB0 None None None 175 IO45RSB0 IO33RSB0 IO33RSB0 None None None 176 IO42RSB0 IO32RSB0 IO32RSB0 None None None 177 IO40RSB0 IO31RSB0 IO31RSB0 None None None 178 GND GND GND None None None 179 IO38RSB0 IO29RSB0 IO29RSB0 None None None 180 IO35RSB0 IO28RSB0 IO28RSB0 None None None 181 IO33RSB0 IO27RSB0 IO27RSB0 None None None 182 IO31RSB0 IO26RSB0 IO26RSB0 None None None 183 IO29RSB0 IO25RSB0 IO25RSB0 None None None 184 IO27RSB0 IO24RSB0 IO24RSB0 None None None 185 IO25RSB0 IO23RSB0 IO23RSB0 None None None 186 VCCIB0 VCCIB0 VCCIB0 None None None 187 VCC VCC VCC None None None 188 IO22RSB0 IO20RSB0 IO21RSB0 None None None 189 IO20RSB0 IO19RSB0 IO20RSB0 None None None 190 IO18RSB0 IO18RSB0 IO19RSB0 None None None 191 IO16RSB0 IO17RSB0 IO18RSB0 None None None 192 IO15RSB0 IO16RSB0 IO17RSB0 None None None 193 IO14RSB0 IO14RSB0 IO16RSB0 None None None 194 IO13RSB0 IO12RSB0 IO15RSB0 None None None Pin Number 1 2 -1 0 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-4 * Pin Compatibility and Migration Table for the PQ208 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 195 GND GND GND None None None 196 IO12RSB0 IO10RSB0 IO13RSB0 None None None 197 IO11RSB0 IO09RSB0 IO11RSB0 None None None 198 IO10RSB0 IO08RSB0 IO09RSB0 None None None 199 IO09RSB0 IO07RSB0 IO07RSB0 None None None 200 VCCIB0 VCCIB0 VCCIB0 None None None 201 GAC1/IO05RSB0 GAC1/IO05RSB0 GAC1/IO05RSB0 None None None 202 GAC0/IO04RSB0 GAC0/IO04RSB0 GAC0/IO04RSB0 None None None 203 GAB1/IO03RSB0 GAB1/IO03RSB0 GAB1/IO03RSB0 None None None 204 GAB0/IO02RSB0 GAB0/IO02RSB0 GAB0/IO02RSB0 None None None 205 GAA1/IO01RSB0 GAA1/IO01RSB0 GAA1/IO01RSB0 None None None 206 GAA0/IO00RSB0 GAA0/IO00RSB0 GAA0/IO00RSB0 None None None 207 GNDQ GNDQ GNDQ None None None 208 VMV0 VMV0 VMV0 None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 - 11 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices FG144 Package Table 12-5 * Pin Compatibility and Migration Table for the FG144 Package A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 A1 GNDQ GNDQ GNDQ None None None A2 VMV0 VMV0 VMV0 None None None A3 GAB0/IO02RSB0 GAB0/IO02RSB0 GAB0/IO02RSB0 None None None A4 GAB1/IO03RSB0 GAB1/IO03RSB0 GAB1/IO03RSB0 None None None A5 IO10RSB0 IO10RSB0 IO16RSB0 None None None A6 GND GND GND None None None A7 IO44RSB0 IO44RSB0 IO30RSB0 None None None A8 VCC VCC VCC None None None A9 IO69RSB0 IO69RSB0 IO34RSB0 None None None A10 GBA0/IO76RSB0 GBA0/IO76RSB0 GBA0/IO58RSB0 None None None A11 GBA1/IO77RSB0 GBA1/IO77RSB0 GBA1/IO59RSB0 None None None A12 GNDQ GNDQ GNDQ None None None B1 GAB2/IO224PDB3 GAB2/IO224PDB3 GAB2/IO154UDB3 None None None B2 GND GND GND None None None B3 GAA0/IO00RSB0 GAA0/IO00RSB0 GAA0/IO00RSB0 None None None B4 GAA1/IO01RSB0 GAA1/IO01RSB0 GAA1/IO01RSB0 None None None B5 IO13RSB0 IO13RSB0 IO14RSB0 None None None B6 IO26RSB0 IO26RSB0 IO19RSB0 None None None B7 IO35RSB0 IO35RSB0 IO23RSB0 None None None B8 IO60RSB0 IO60RSB0 IO31RSB0 None None None B9 GBB0/IO74RSB0 GBB0/IO74RSB0 GBB0/IO56RSB0 None None None B10 GBB1/IO75RSB0 GBB1/IO75RSB0 GBB1/IO57RSB0 None None None B11 GND GND GND None None None B12 VMV1 VMV1 VMV1 None None None C1 IO224NDB3 IO224NDB3 IO154VDB3 None None None C2 GFA2/IO206PPB3 GFA2/IO206PPB3 GFA2/IO144PPB3 None None None C3 GAC2/IO223PDB3 GAC2/IO223PDB3 GAC2/IO153UDB3 None None None C4 VCC VCC VCC None None None C5 IO16RSB0 IO16RSB0 IO12RSB0 None None None C6 IO29RSB0 IO29RSB0 IO17RSB0 None None None C7 IO32RSB0 IO32RSB0 IO25RSB0 None None None Pin Number 1 2 -1 2 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-5 * Pin Compatibility and Migration Table for the FG144 Package (continued) Pin Number A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 C8 IO63RSB0 IO63RSB0 IO32RSB0 None None None C9 IO66RSB0 IO66RSB0 IO53RSB0 None None None C10 GBA2/IO78PDB1 GBA2/IO78PDB1 GBA2/IO60PDB1 None None None C11 IO78NDB1 IO78NDB1 IO60NDB1 None None None C12 GBC2/IO80PPB1 GBC2/IO80PPB1 GBC2/IO62PPB1 None None None D1 IO213PDB3 IO213PDB3 IO149NDB3 None None None D2 IO213NDB3 IO213NDB3 IO149PDB3 None None None D3 IO223NDB3 IO223NDB3 IO153VDB3 None None None D4 GAA2/IO225PPB3 GAA2/IO225PPB3 GAA2/IO155UPB3 None None None D5 GAC0/IO04RSB0 GAC0/IO04RSB0 GAC0/IO04RSB0 None None None D6 GAC1/IO05RSB0 GAC1/IO05RSB0 GAC1/IO05RSB0 None None None D7 GBC0/IO72RSB0 GBC0/IO72RSB0 GBC0/IO54RSB0 None None None D8 GBC1/IO73RSB0 GBC1/IO73RSB0 GBC1/IO55RSB0 None None None D9 GBB2/IO79PDB1 GBB2/IO79PDB1 GBB2/IO61PDB1 None None None D10 IO79NDB1 IO79NDB1 IO61NDB1 None None None D11 IO80NPB1 IO80NPB1 IO62NPB1 None None None D12 GCB1/IO92PPB1 GCB1/IO92PPB1 GCB1/IO68PPB1 None None None E1 VCC VCC VCC None None None E2 GFC0/IO209NDB3 GFC0/IO209NDB3 GFC0/IO147NDB3 None None None E3 GFC1/IO209PDB3 GFC1/IO209PDB3 GFC1/IO147PDB3 None None None E4 VCCIB3 VCCIB3 VCCIB3 None None None E5 IO225NPB3 IO225NPB3 IO155VPB3 None None None E6 VCCIB0 VCCIB0 VCCIB0 None None None E7 VCCIB0 VCCIB0 VCCIB0 None None None E8 GCC1/IO91PDB1 GCC1/IO91PDB1 GCC1/IO67PDB1 None None None E9 VCCIB1 VCCIB1 VCCIB1 None None None E10 VCC VCC VCC None None None E11 GCA0/IO93NDB1 GCA0/IO93NDB1 GCA0/IO69NDB1 None None None E12 IO94NDB1 IO94NDB1 IO70NDB1 None None None F1 GFB0/IO208NPB3 GFB0/IO208NPB3 GFB0/IO146NPB3 None None None F2 VCOMPLF VCOMPLF VCOMPLF None None None F3 GFB1/IO208PPB3 GFB1/IO208PPB3 GFB1/IO146PPB3 None None None F4 IO206NPB3 IO206NPB3 IO144NPB3 None None None v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 - 13 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-5 * Pin Compatibility and Migration Table for the FG144 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 F5 GND GND GND None None None F6 GND GND GND None None None F7 GND GND GND None None None F8 GCC0/IO91NDB1 GCC0/IO91NDB1 GCC0/IO67NDB1 None None None F9 GCB0/IO92NPB1 GCB0/IO92NPB1 GCB0/IO68NPB1 None None None F10 GND GND GND None None None F11 GCA1/IO93PDB1 GCA1/IO93PDB1 GCA1/IO69PDB1 None None None F12 GCA2/IO94PDB1 GCA2/IO94PDB1 GCA2/IO70PDB1 None None None G1 GFA1/IO207PPB3 GFA1/IO207PPB3 GFA1/IO145PPB3 None None None G2 GND GND GND None None None G3 VCCPLF VCCPLF VCCPLF None None None G4 GFA0/IO207NPB3 GFA0/IO207NPB3 GFA0/IO145NPB3 None None None G5 GND GND GND None None None G6 GND GND GND None None None G7 GND GND GND None None None G8 GDC1/IO111PPB1 GDC1/IO111PPB1 GDC1/IO77UPB1 None None None G9 IO96NDB1 IO96NDB1 IO72NDB1 None None None G10 GCC2/IO96PDB1 GCC2/IO96PDB1 GCC2/IO72PDB1 None None None G11 IO95NDB1 IO95NDB1 IO71NDB1 None None None G12 GCB2/IO95PDB1 GCB2/IO95PDB1 GCB2/IO71PDB1 None None None H1 VCC VCC VCC None None None H2 GFB2/IO205PDB3 GFB2/IO205PDB3 GFB2/IO143PDB3 None None None H3 GFC2/IO204PSB3 GFC2/IO204PSB3 GFC2/IO142PSB3 None None None H4 GEC1/IO190PDB3 GEC1/IO190PDB3 GEC1/IO137PDB3 None None None H5 VCC VCC VCC None None None H6 IO105PDB1 IO105PDB1 IO75PDB1 None None None H7 IO105NDB1 IO105NDB1 IO75NDB1 None None None H8 GDB2/IO115RSB2 GDB2/IO115RSB2 GDB2/IO81RSB2 None None None H9 GDC0/IO111NPB1 GDC0/IO111NPB1 GDC0/IO77VPB1 None None None H10 VCCIB1 VCCIB1 VCCIB1 None None None H11 IO101PSB1 IO101PSB1 IO73PSB1 None None None H12 VCC VCC VCC None None None GEB1/IO189PDB3 GEB1/IO189PDB3 GEB1/IO136PDB3 None None None Pin Number J1 1 2 -1 4 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-5 * Pin Compatibility and Migration Table for the FG144 Package (continued) Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 J2 IO205NDB3 IO205NDB3 IO143NDB3 None None None J3 VCCIB3 VCCIB3 VCCIB3 None None None J4 GEC0/IO190NDB3 GEC0/IO190NDB3 GEC0/IO137NDB3 None None None J5 IO160RSB2 IO160RSB2 IO125RSB2 None None None J6 IO157RSB2 IO157RSB2 IO116RSB2 None None None J7 VCC VCC VCC None None None J8 TCK TCK TCK None None None J9 GDA2/IO114RSB2 GDA2/IO114RSB2 GDA2/IO80RSB2 None None None J10 TDO TDO TDO None None None J11 GDA1/IO113PDB1 GDA1/IO113PDB1 GDA1/IO79UDB1 None None None J12 GDB1/IO112PDB1 GDB1/IO112PDB1 GDB1/IO78UDB1 None None None K1 GEB0/IO189NDB3 GEB0/IO189NDB3 GEB0/IO136NDB3 None None None K2 GEA1/IO188PDB3 GEA1/IO188PDB3 GEA1/IO135PDB3 None None None K3 GEA0/IO188NDB3 GEA0/IO188NDB3 GEA0/IO135NDB3 None None None K4 GEA2/IO187RSB2 GEA2/IO187RSB2 GEA2/IO134RSB2 None None None K5 IO169RSB2 IO169RSB2 IO127RSB2 None None None K6 IO152RSB2 IO152RSB2 IO121RSB2 None None None K7 GND GND GND None None None K8 IO117RSB2 IO117RSB2 IO104RSB2 None None None K9 GDC2/IO116RSB2 GDC2/IO116RSB2 GDC2/IO82RSB2 None None None K10 GND GND GND None None None K11 GDA0/IO113NDB1 GDA0/IO113NDB1 GDA0/IO79VDB1 None None None K12 GDB0/IO112NDB1 GDB0/IO112NDB1 GDB0/IO78VDB1 None None None L1 GND GND GND None None None L2 VMV3 VMV3 VMV3 None None None L3 GEB2/IO186RSB2 GEB2/IO186RSB2 GEB2/IO133RSB2 None None None L4 IO172RSB2 IO172RSB2 IO128RSB2 None None None L5 VCCIB2 VCCIB2 VCCIB2 None None None L6 IO153RSB2 IO153RSB2 IO119RSB2 None None None L7 IO144RSB2 IO144RSB2 IO114RSB2 None None None L8 IO140RSB2 IO140RSB2 IO110RSB2 None None None L9 TMS TMS TMS None None None L10 VJTAG VJTAG VJTAG None None None Pin Number v1.1 1 2 - 15 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-5 * Pin Compatibility and Migration Table for the FG144 Package (continued) Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 L11 VMV2 VMV2 VMV2 None None None L12 TRST TRST TRST None None None M1 GNDQ GNDQ GNDQ None None None M2 GEC2/IO185RSB2 GEC2/IO185RSB2 GEC2/IO132RSB2 None None None M3 IO173RSB2 IO173RSB2 IO129RSB2 None None None M4 IO168RSB2 IO168RSB2 IO126RSB2 None None None M5 IO161RSB2 IO161RSB2 IO124RSB2 None None None M6 IO156RSB2 IO156RSB2 IO122RSB2 None None None M7 IO145RSB2 IO145RSB2 IO117RSB2 None None None M8 IO141RSB2 IO141RSB2 IO115RSB2 None None None M9 TDI TDI TDI None None None M10 VCCIB2 VCCIB2 VCCIB2 None None None M11 VPUMP VPUMP VPUMP None None None M12 GNDQ GNDQ GNDQ None None None Pin Number 1 2 -1 6 v1.1 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices FG256 Package Table 12-6 * Pin Compatibility and Migration Table for the FG256 Package A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 A1 GND GND GND None None None A2 GAA0/IO00RSB0 GAA0/IO00RSB0 GAA0/IO00RSB0 None None None A3 GAA1/IO01RSB0 GAA1/IO01RSB0 GAA1/IO01RSB0 None None None A4 GAB0/IO02RSB0 GAB0/IO02RSB0 GAB0/IO02RSB0 None None None A5 IO16RSB0 IO11RSB0 IO16RSB0 None None None A6 IO22RSB0 IO16RSB0 IO17RSB0 None None None A7 IO28RSB0 IO18RSB0 IO22RSB0 None None None A8 IO35RSB0 IO28RSB0 IO28RSB0 None None None A9 IO45RSB0 IO34RSB0 IO34RSB0 None None None A10 IO50RSB0 IO37RSB0 IO37RSB0 None None None A11 IO55RSB0 IO41RSB0 IO41RSB0 None None None A12 IO61RSB0 IO43RSB0 IO43RSB0 None None None A13 GBB1/IO75RSB0 GBB1/IO57RSB0 GBB1/IO57RSB0 None None None A14 GBA0/IO76RSB0 GBA0/IO58RSB0 GBA0/IO58RSB0 None None None A15 GBA1/IO77RSB0 GBA1/IO59RSB0 GBA1/IO59RSB0 None None None A16 GND GND GND None None None B1 GAB2/IO224PDB3 GAB2/IO173PDB3 GAB2/IO154UDB3 None None None B2 GAA2/IO225PDB3 GAA2/IO174PDB3 GAA2/IO155UDB3 None None None B3 GNDQ GNDQ IO12RSB0 None Rule 8 Rule 8 B4 GAB1/IO03RSB0 GAB1/IO03RSB0 GAB1/IO03RSB0 None None None B5 IO17RSB0 IO13RSB0 IO13RSB0 None None None B6 IO21RSB0 IO14RSB0 IO14RSB0 None None None B7 IO27RSB0 IO21RSB0 IO21RSB0 None None None B8 IO34RSB0 IO27RSB0 IO27RSB0 None None None B9 IO44RSB0 IO32RSB0 IO32RSB0 None None None B10 IO51RSB0 IO38RSB0 IO38RSB0 None None None B11 IO57RSB0 IO42RSB0 IO42RSB0 None None None B12 GBC1/IO73RSB0 GBC1/IO55RSB0 GBC1/IO55RSB0 None None None B13 GBB0/IO74RSB0 GBB0/IO56RSB0 GBB0/IO56RSB0 None None None B14 IO71RSB0 IO52RSB0 IO44RSB0 None None None B15 GBA2/IO78PDB1 GBA2/IO60PDB1 GBA2/IO60PDB1 None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 - 17 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-6 * Pin Compatibility and Migration Table for the FG256 Package (continued) Pin Number A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 B16 IO81PDB1 IO60NDB1 IO60NDB1 None None None C1 IO224NDB3 IO173NDB3 IO154VDB3 None None None C2 IO225NDB3 IO174NDB3 IO155VDB3 None None None C3 VMV3 VMV3 IO11RSB0 None Rule 7 Rule 7 C4 IO11RSB0 IO07RSB0 IO07RSB0 None None None C5 GAC0/IO04RSB0 GAC0/IO04RSB0 GAC0/IO04RSB0 None None None C6 GAC1/IO05RSB0 GAC1/IO05RSB0 GAC1/IO05RSB0 None None None C7 IO25RSB0 IO20RSB0 IO20RSB0 None None None C8 IO36RSB0 IO24RSB0 IO24RSB0 None None None C9 IO42RSB0 IO33RSB0 IO33RSB0 None None None C10 IO49RSB0 IO39RSB0 IO39RSB0 None None None C11 IO56RSB0 IO44RSB0 IO45RSB0 None None None C12 GBC0/IO72RSB0 GBC0/IO54RSB0 GBC0/IO54RSB0 None None None C13 IO62RSB0 IO51RSB0 IO48RSB0 None None None C14 VMV0 VMV0 VMV0 None None None C15 IO78NDB1 IO61NPB1 IO61NPB1 None None None C16 IO81NDB1 IO63PDB1 IO63PDB1 None None None D1 IO222NDB3 IO171NDB3 IO151VDB3 None None None D2 IO222PDB3 IO171PDB3 IO151UDB3 None None None D3 GAC2/IO223PDB3 GAC2/IO172PDB3 GAC2/IO153UDB3 None None None D4 IO223NDB3 IO06RSB0 IO06RSB0 None None None D5 GNDQ GNDQ GNDQ None None None D6 IO23RSB0 IO10RSB0 IO10RSB0 None None None D7 IO29RSB0 IO19RSB0 IO19RSB0 None None None D8 IO33RSB0 IO26RSB0 IO26RSB0 None None None D9 IO46RSB0 IO30RSB0 IO30RSB0 None None None D10 IO52RSB0 IO40RSB0 IO40RSB0 None None None D11 IO60RSB0 IO45RSB0 IO46RSB0 None None None D12 GNDQ GNDQ GNDQ None None None D13 IO80NDB1 IO50RSB0 IO47RSB0 None None None D14 GBB2/IO79PDB1 GBB2/IO61PPB1 GBB2/IO61PPB1 None None None D15 IO79NDB1 IO53RSB0 IO53RSB0 None None None D16 IO82NSB1 IO63NDB1 IO63NDB1 None None None 1 2 -1 8 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-6 * Pin Compatibility and Migration Table for the FG256 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 E1 IO217PDB3 IO166PDB3 IO150PDB3 None None None E2 IO218PDB3 IO167NPB3 IO08RSB0 None None None E3 IO221NDB3 IO172NDB3 IO153VDB3 None None None E4 IO221PDB3 IO169NDB3 IO152VDB3 None None None E5 VMV0 VMV0 VMV0 None None None E6 VCCIB0 VCCIB0 VCCIB0 None None None E7 VCCIB0 VCCIB0 VCCIB0 None None None E8 IO38RSB0 IO25RSB0 IO25RSB0 None None None E9 IO47RSB0 IO31RSB0 IO31RSB0 None None None E10 VCCIB0 VCCIB0 VCCIB0 None None None E11 VCCIB0 VCCIB0 VCCIB0 None None None E12 VMV1 VMV1 VMV1 None None None E13 GBC2/IO80PDB1 GBC2/IO62PDB1 GBC2/IO62PDB1 None None None E14 IO83PPB1 IO67PPB1 IO65RSB1 None None None E15 IO86PPB1 IO64PPB1 IO52RSB0 None None None E16 IO87PDB1 IO66PDB1 IO66PDB1 None None None F1 IO217NDB3 IO166NDB3 IO150NDB3 None None None F2 IO218NDB3 IO168NPB3 IO149NPB3 None None None F3 IO216PDB3 IO167PPB3 IO09RSB0 None None None F4 IO216NDB3 IO169PDB3 IO152UDB3 None None None F5 VCCIB3 VCCIB3 VCCIB3 None None None F6 GND GND GND None None None F7 VCC VCC VCC None None None F8 VCC VCC VCC None None None F9 VCC VCC VCC None None None F10 VCC VCC VCC None None None F11 GND GND GND None None None F12 VCCIB1 VCCIB1 VCCIB1 None None None F13 IO83NPB1 IO62NDB1 IO62NDB1 None None None F14 IO86NPB1 IO64NPB1 IO49RSB0 None None None F15 IO90PPB1 IO65PPB1 IO64PPB1 None None None F16 IO87NDB1 IO66NDB1 IO66NDB1 None None None G1 IO210PSB3 IO165NDB3 IO148NDB3 None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 - 19 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-6 * Pin Compatibility and Migration Table for the FG256 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 G2 IO213NDB3 IO165PDB3 IO148PDB3 None None None G3 IO213PDB3 IO168PPB3 IO149PPB3 None None None G4 GFC1/IO209PPB3 GFC1/IO164PPB3 GFC1/IO147PPB3 None None None G5 VCCIB3 VCCIB3 VCCIB3 None None None G6 VCC VCC VCC None None None G7 GND GND GND None None None G8 GND GND GND None None None G9 GND GND GND None None None G10 GND GND GND None None None G11 VCC VCC VCC None None None G12 VCCIB1 VCCIB1 VCCIB1 None None None G13 GCC1/IO91PPB1 GCC1/IO69PPB1 GCC1/IO67PPB1 None None None G14 IO90NPB1 IO65NPB1 IO64NPB1 None None None G15 IO88PDB1 IO75PDB1 IO73PDB1 None None None G16 IO88NDB1 IO75NDB1 IO73NDB1 None None None H1 GFB0/IO208NPB3 GFB0/IO163NPB3 GFB0/IO146NPB3 None None None H2 GFA0/IO207NDB3 GFA0/IO162NDB3 GFA0/IO145NDB3 None None None H3 GFB1/IO208PPB3 GFB1/IO163PPB3 GFB1/IO146PPB3 None None None H4 VCOMPLF VCOMPLF VCOMPLF None None None H5 GFC0/IO209NPB3 GFC0/IO164NPB3 GFC0/IO147NPB3 None None None H6 VCC VCC VCC None None None H7 GND GND GND None None None H8 GND GND GND None None None H9 GND GND GND None None None H10 GND GND GND None None None H11 VCC VCC VCC None None None H12 GCC0/IO91NPB1 GCC0/IO69NPB1 GCC0/IO67NPB1 None None None H13 GCB1/IO92PPB1 GCB1/IO70PPB1 GCB1/IO68PPB1 None None None H14 GCA0/IO93NPB1 GCA0/IO71NPB1 GCA0/IO69NPB1 None None None H15 IO96NPB1 IO67NPB1 NC None Rule 1 Rule 1 H16 GCB0/IO92NPB1 GCB0/IO70NPB1 GCB0/IO68NPB1 None None None J1 GFA2/IO206PSB3 GFA2/IO161PPB3 GFA2/IO144PPB3 None None None J2 GFA1/IO207PDB3 GFA1/IO162PDB3 GFA1/IO145PDB3 None None None Pin Number 1 2 -2 0 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-6 * Pin Compatibility and Migration Table for the FG256 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 J3 VCCPLF VCCPLF VCCPLF None None None J4 IO205NDB3 IO160NDB3 IO143NDB3 None None None J5 GFB2/IO205PDB3 GFB2/IO160PDB3 GFB2/IO143PDB3 None None None J6 VCC VCC VCC None None None J7 GND GND GND None None None J8 GND GND GND None None None J9 GND GND GND None None None J10 GND GND GND None None None J11 VCC VCC VCC None None None J12 GCB2/IO95PPB1 GCB2/IO73PPB1 GCB2/IO71PPB1 None None None J13 GCA1/IO93PPB1 GCA1/IO71PPB1 GCA1/IO69PPB1 None None None J14 GCC2/IO96PPB1 GCC2/IO74PPB1 GCC2/IO72PPB1 None None None J15 IO100PPB1 IO80PPB1 NC None Rule 1 Rule 1 J16 GCA2/IO94PSB1 GCA2/IO72PDB1 GCA2/IO70PDB1 None None None K1 GFC2/IO204PDB3 GFC2/IO159PDB3 GFC2/IO142PDB3 None None None K2 IO204NDB3 IO161NPB3 IO144NPB3 None None None K3 IO203NDB3 IO156PPB3 IO141PPB3 None None None K4 IO203PDB3 IO129RSB2 IO120RSB2 None None None K5 VCCIB3 VCCIB3 VCCIB3 None None None K6 VCC VCC VCC None None None K7 GND GND GND None None None K8 GND GND GND None None None K9 GND GND GND None None None K10 GND GND GND None None None K11 VCC VCC VCC None None None K12 VCCIB1 VCCIB1 VCCIB1 None None None K13 IO95NPB1 IO73NPB1 IO71NPB1 None None None K14 IO100NPB1 IO80NPB1 IO74RSB1 None None None K15 IO102NDB1 IO74NPB1 IO72NPB1 None None None K16 IO102PDB1 IO72NDB1 IO70NDB1 None None None L1 IO202NDB3 IO159NDB3 IO142NDB3 None None None L2 IO202PDB3 IO156NPB3 IO141NPB3 None None None L3 IO196PPB3 IO151PPB3 IO125RSB2 None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 - 21 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-6 * Pin Compatibility and Migration Table for the FG256 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 L4 IO193PPB3 IO158PSB3 IO139RSB3 None None None L5 VCCIB3 VCCIB3 VCCIB3 None None None L6 GND GND GND None None None L7 VCC VCC VCC None None None L8 VCC VCC VCC None None None L9 VCC VCC VCC None None None L10 VCC VCC VCC None None None L11 GND GND GND None None None L12 VCCIB1 VCCIB1 VCCIB1 None None None L13 GDB0/IO112NPB1 GDB0/IO87NPB1 GDB0/IO78VPB1 None None None L14 IO106NDB1 IO85NDB1 IO76VDB1 None None None L15 IO106PDB1 IO85PDB1 IO76UDB1 None None None L16 IO107PDB1 IO84PDB1 IO75PDB1 None None None M1 IO197NSB3 IO150PDB3 IO140PDB3 None None None M2 IO196NPB3 IO151NPB3 IO130RSB2 None None None M3 IO193NPB3 IO147NPB3 IO138NPB3 None None None M4 GEC0/IO190NPB3 GEC0/IO146NPB3 GEC0/IO137NPB3 None None None M5 VMV3 VMV3 VMV3 None None None M6 VCCIB2 VCCIB2 VCCIB2 None None None M7 VCCIB2 VCCIB2 VCCIB2 None None None M8 IO147RSB2 IO117RSB2 IO108RSB2 None None None M9 IO136RSB2 IO110RSB2 IO101RSB2 None None None M10 VCCIB2 VCCIB2 VCCIB2 None None None M11 VCCIB2 VCCIB2 VCCIB2 None None None M12 VMV2 VMV2 VMV2 None None None M13 IO110NDB1 IO94RSB2 IO83RSB2 None None None M14 GDB1/IO112PPB1 GDB1/IO87PPB1 GDB1/IO78UPB1 None None None M15 GDC1/IO111PDB1 GDC1/IO86PDB1 GDC1/IO77UDB1 None None None M16 IO107NDB1 IO84NDB1 IO75NDB1 None None None N1 IO194PSB3 IO150NDB3 IO140NDB3 None None None N2 IO192PPB3 IO147PPB3 IO138PPB3 None None None N3 GEC1/IO190PPB3 GEC1/IO146PPB3 GEC1/IO137PPB3 None None None N4 IO192NPB3 IO140RSB2 IO131RSB2 None None None Pin Number 1 2 -2 2 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-6 * Pin Compatibility and Migration Table for the FG256 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 N5 GNDQ GNDQ GNDQ None None None N6 GEA2/IO187RSB2 GEA2/IO143RSB2 GEA2/IO134RSB2 None None None N7 IO161RSB2 IO126RSB2 IO117RSB2 None None None N8 IO155RSB2 IO120RSB2 IO111RSB2 None None None N9 IO141RSB2 IO108RSB2 IO99RSB2 None None None N10 IO129RSB2 IO103RSB2 IO94RSB2 None None None N11 IO124RSB2 IO99RSB2 IO87RSB2 None None None N12 GNDQ GNDQ GNDQ None None None N13 IO110PDB1 IO92RSB2 IO93RSB2 None None None N14 VJTAG VJTAG VJTAG None None None N15 GDC0/IO111NDB1 GDC0/IO86NDB1 GDC0/IO77VDB1 None None None N16 GDA1/IO113PDB1 GDA1/IO88PDB1 GDA1/IO79UDB1 None None None P1 GEB1/IO189PDB3 GEB1/IO145PDB3 GEB1/IO136PDB3 None None None P2 GEB0/IO189NDB3 GEB0/IO145NDB3 GEB0/IO136NDB3 None None None P3 VMV2 VMV2 VMV2 None None None P4 IO179RSB2 IO138RSB2 IO129RSB2 None None None P5 IO171RSB2 IO136RSB2 IO128RSB2 None None None P6 IO165RSB2 IO131RSB2 IO122RSB2 None None None P7 IO159RSB2 IO124RSB2 IO115RSB2 None None None P8 IO151RSB2 IO119RSB2 IO110RSB2 None None None P9 IO137RSB2 IO107RSB2 IO98RSB2 None None None P10 IO134RSB2 IO104RSB2 IO95RSB2 None None None P11 IO128RSB2 IO97RSB2 IO88RSB2 None None None P12 VMV1 VMV1 IO84RSB2 None Rule 7 Rule 7 P13 TCK TCK TCK None None None P14 VPUMP VPUMP VPUMP None None None P15 TRST TRST TRST None None None P16 GDA0/IO113NDB1 GDA0/IO88NDB1 GDA0/IO79VDB1 None None None R1 GEA1/IO188PDB3 GEA1/IO144PDB3 GEA1/IO135PDB3 None None None R2 GEA0/IO188NDB3 GEA0/IO144NDB3 GEA0/IO135NDB3 None None None R3 IO184RSB2 IO139RSB2 IO127RSB2 None None None R4 GEC2/IO185RSB2 GEC2/IO141RSB2 GEC2/IO132RSB2 None None None R5 IO168RSB2 IO132RSB2 IO123RSB2 None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 - 23 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-6 * Pin Compatibility and Migration Table for the FG256 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 R6 IO163RSB2 IO127RSB2 IO118RSB2 None None None R7 IO157RSB2 IO121RSB2 IO112RSB2 None None None R8 IO149RSB2 IO114RSB2 IO106RSB2 None None None R9 IO143RSB2 IO109RSB2 IO100RSB2 None None None R10 IO138RSB2 IO105RSB2 IO96RSB2 None None None R11 IO131RSB2 IO98RSB2 IO89RSB2 None None None R12 IO125RSB2 IO96RSB2 IO85RSB2 None None None R13 GDB2/IO115RSB2 GDB2/IO90RSB2 GDB2/IO81RSB2 None None None R14 TDI TDI TDI None None None R15 GNDQ GNDQ NC None Rule 8 Rule 8 R16 TDO TDO TDO None None None T1 GND GND GND None None None T2 IO183RSB2 IO137RSB2 IO126RSB2 None None None T3 GEB2/IO186RSB2 GEB2/IO142RSB2 GEB2/IO133RSB2 None None None T4 IO172RSB2 IO134RSB2 IO124RSB2 None None None T5 IO170RSB2 IO125RSB2 IO116RSB2 None None None T6 IO164RSB2 IO123RSB2 IO113RSB2 None None None T7 IO158RSB2 IO118RSB2 IO107RSB2 None None None T8 IO153RSB2 IO115RSB2 IO105RSB2 None None None T9 IO142RSB2 IO111RSB2 IO102RSB2 None None None T10 IO135RSB2 IO106RSB2 IO97RSB2 None None None T11 IO130RSB2 IO102RSB2 IO92RSB2 None None None T12 GDC2/IO116RSB2 GDC2/IO91RSB2 GDC2/IO82RSB2 None None None T13 IO120RSB2 IO93RSB2 IO86RSB2 None None None T14 GDA2/IO114RSB2 GDA2/IO89RSB2 GDA2/IO80RSB2 None None None T15 TMS TMS TMS None None None T16 GND GND GND None None None Pin Number 1 2 -2 4 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices FG484 Package Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 A1 GND GND GND None None None A2 GND GND GND None None None A3 VCCIB0 VCCIB0 VCCIB0 None None None A4 IO07RSB0 NC NC Rule 1 Rule 1 None A5 IO09RSB0 NC NC Rule 1 Rule 1 None A6 IO13RSB0 IO09RSB0 IO15RSB0 None None None A7 IO18RSB0 IO15RSB0 IO18RSB0 None None None A8 IO20RSB0 NC NC Rule 1 Rule 1 None A9 IO26RSB0 NC NC Rule 1 Rule 1 None A10 IO32RSB0 IO22RSB0 IO23RSB0 None None None A11 IO40RSB0 IO23RSB0 IO29RSB0 None None None A12 IO41RSB0 IO29RSB0 IO35RSB0 None None None A13 IO53RSB0 IO35RSB0 IO36RSB0 None None None A14 IO59RSB0 NC NC Rule 1 Rule 1 None A15 IO64RSB0 NC NC Rule 1 Rule 1 None A16 IO65RSB0 IO46RSB0 IO50RSB0 None None None A17 IO67RSB0 IO48RSB0 IO51RSB0 None None None A18 IO69RSB0 NC NC Rule 1 Rule 1 None A19 NC NC NC None None None A20 VCCIB0 VCCIB0 VCCIB0 None None None A21 GND GND GND None None None A22 GND GND GND None None None AA1 GND GND GND None None None AA2 VCCIB3 VCCIB3 VCCIB3 None None None AA3 NC NC NC None None None AA4 IO181RSB2 NC NC Rule 1 Rule 1 None AA5 IO178RSB2 NC NC Rule 1 Rule 1 None AA6 IO175RSB2 IO135RSB2 NC None Rule 1 Rule 1 AA7 IO169RSB2 IO133RSB2 NC None Rule 1 Rule 1 AA8 IO166RSB2 NC NC Rule 1 Rule 1 None AA9 IO160RSB2 NC NC Rule 1 Rule 1 None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 - 25 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 AA10 IO152RSB2 NC NC Rule 1 Rule 1 None AA11 IO146RSB2 NC NC Rule 1 Rule 1 None AA12 IO139RSB2 NC NC Rule 1 Rule 1 None AA13 IO133RSB2 NC NC Rule 1 Rule 1 None AA14 NC NC NC None None None AA15 NC NC NC None None None AA16 IO122RSB2 IO101RSB2 NC None Rule 1 Rule 1 AA17 IO119RSB2 NC NC Rule 1 Rule 1 None AA18 IO117RSB2 NC NC Rule 1 Rule 1 None AA19 NC NC NC None None None AA20 NC NC NC None None None AA21 VCCIB1 VCCIB1 VCCIB1 None None None AA22 GND GND GND None None None AB1 GND GND GND None None None AB2 GND GND GND None None None AB3 VCCIB2 VCCIB2 VCCIB2 None None None AB4 IO180RSB2 NC NC Rule 1 Rule 1 None AB5 IO176RSB2 NC NC Rule 1 Rule 1 None AB6 IO173RSB2 IO130RSB2 IO121RSB2 None None None AB7 IO167RSB2 IO128RSB2 IO119RSB2 None None None AB8 IO162RSB2 IO122RSB2 IO114RSB2 None None None AB9 IO156RSB2 IO116RSB2 IO109RSB2 None None None AB10 IO150RSB2 NC NC Rule 1 Rule 1 None AB11 IO145RSB2 NC NC Rule 1 Rule 1 None AB12 IO144RSB2 IO113RSB2 IO104RSB2 None None None AB13 IO132RSB2 IO112RSB2 IO103RSB2 None None None AB14 IO127RSB2 NC NC Rule 1 Rule 1 None AB15 IO126RSB2 NC NC Rule 1 Rule 1 None AB16 IO123RSB2 IO100RSB2 IO91RSB2 None None None AB17 IO121RSB2 IO95RSB2 IO90RSB2 None None None AB18 IO118RSB2 NC NC Rule 1 Rule 1 None AB19 NC NC NC None None None AB20 VCCIB2 VCCIB2 VCCIB2 None None None Pin Number 1 2 -2 6 v1.1 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 AB21 GND GND GND None None None AB22 GND GND GND None None None B1 GND GND GND None None None B2 VCCIB3 VCCIB3 VCCIB3 None None None B3 NC NC NC None None None B4 IO06RSB0 NC NC Rule 1 Rule 1 None B5 IO08RSB0 NC NC Rule 1 Rule 1 None B6 IO12RSB0 IO08RSB0 NC None Rule 1 Rule 1 B7 IO15RSB0 IO12RSB0 NC None Rule 1 Rule 1 B8 IO19RSB0 NC NC Rule 1 Rule 1 None B9 IO24RSB0 NC NC Rule 1 Rule 1 None B10 IO31RSB0 IO17RSB0 NC None Rule 1 Rule 1 B11 IO39RSB0 NC NC Rule 1 Rule 1 None B12 IO48RSB0 NC NC Rule 1 Rule 1 None B13 IO54RSB0 IO36RSB0 NC None Rule 1 Rule 1 B14 IO58RSB0 NC NC Rule 1 Rule 1 None B15 IO63RSB0 NC NC Rule 1 Rule 1 None B16 IO66RSB0 IO47RSB0 NC None Rule 1 Rule 1 B17 IO68RSB0 IO49RSB0 NC None Rule 1 Rule 1 B18 IO70RSB0 NC NC Rule 1 Rule 1 None B19 NC NC NC None None None B20 NC NC NC None None None B21 VCCIB1 VCCIB1 VCCIB1 None None None B22 GND GND GND None None None C1 VCCIB3 VCCIB3 VCCIB3 None None None C2 IO220PDB3 NC NC Rule 1 Rule 1 None C3 NC NC NC None None None C4 NC NC NC None None None C5 GND GND GND None None None C6 IO10RSB0 NC NC Rule 1 Rule 1 None C7 IO14RSB0 NC NC Rule 1 Rule 1 None C8 VCC VCC VCC None None None C9 VCC VCC VCC None None None Pin Number v1.1 1 2 - 27 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Pin Number A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 C10 IO30RSB0 NC NC Rule 1 Rule 1 None C11 IO37RSB0 NC NC Rule 1 Rule 1 None C12 IO43RSB0 NC NC Rule 1 Rule 1 None C13 NC NC NC None None None C14 VCC VCC VCC None None None C15 VCC VCC VCC None None None C16 NC NC NC None None None C17 NC NC NC None None None C18 GND GND GND None None None C19 NC NC NC None None None C20 NC NC NC None None None C21 NC NC NC None None None C22 VCCIB1 VCCIB1 VCCIB1 None None None D1 IO219PDB3 NC NC Rule 1 Rule 1 None D2 IO220NDB3 NC NC Rule 1 Rule 1 None D3 NC NC NC None None None D4 GND GND GND None None None D5 GAA0/IO00RSB0 GAA0/IO00RSB0 GAA0/IO00RSB0 None None None D6 GAA1/IO01RSB0 GAA1/IO01RSB0 GAA1/IO01RSB0 None None None D7 GAB0/IO02RSB0 GAB0/IO02RSB0 GAB0/IO02RSB0 None None None D8 IO16RSB0 IO11RSB0 IO16RSB0 None None None D9 IO22RSB0 IO16RSB0 IO17RSB0 None None None D10 IO28RSB0 IO18RSB0 IO22RSB0 None None None D11 IO35RSB0 IO28RSB0 IO28RSB0 None None None D12 IO45RSB0 IO34RSB0 IO34RSB0 None None None D13 IO50RSB0 IO37RSB0 IO37RSB0 None None None D14 IO55RSB0 IO41RSB0 IO41RSB0 None None None D15 IO61RSB0 IO43RSB0 IO43RSB0 None None None D16 GBB1/IO75RSB0 GBB1/IO57RSB0 GBB1/IO57RSB0 None None None D17 GBA0/IO76RSB0 GBA0/IO58RSB0 GBA0/IO58RSB0 None None None D18 GBA1/IO77RSB0 GBA1/IO59RSB0 GBA1/IO59RSB0 None None None D19 GND GND GND None None None D20 NC NC NC None None None 1 2 -2 8 v1.1 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 D21 NC NC NC None None None D22 NC NC NC None None None E1 IO219NDB3 NC NC Rule 1 Rule 1 None E2 NC NC NC None None None E3 GND GND GND None None None E4 GAB2/IO224PDB3 GAB2/IO173PDB3 GAB2/IO154UDB3 None None None E5 GAA2/IO225PDB3 GAA2/IO174PDB3 GAA2/IO155UDB3 None None None E6 GNDQ GNDQ IO12RSB0 None Rule 8 Rule 8 E7 GAB1/IO03RSB0 GAB1/IO03RSB0 GAB1/IO03RSB0 None None None E8 IO17RSB0 IO13RSB0 IO13RSB0 None None None E9 IO21RSB0 IO14RSB0 IO14RSB0 None None None E10 IO27RSB0 IO21RSB0 IO21RSB0 None None None E11 IO34RSB0 IO27RSB0 IO27RSB0 None None None E12 IO44RSB0 IO32RSB0 IO32RSB0 None None None E13 IO51RSB0 IO38RSB0 IO38RSB0 None None None E14 IO57RSB0 IO42RSB0 IO42RSB0 None None None E15 GBC1/IO73RSB0 GBC1/IO55RSB0 GBC1/IO55RSB0 None None None E16 GBB0/IO74RSB0 GBB0/IO56RSB0 GBB0/IO56RSB0 None None None E17 IO71RSB0 IO52RSB0 IO44RSB0 None None None E18 GBA2/IO78PDB1 GBA2/IO60PDB1 GBA2/IO60PDB1 None None None E19 IO81PDB1 IO60NDB1 IO60NDB1 None None None E20 GND GND GND None None None E21 NC NC NC None None None E22 IO84PDB1 NC NC Rule 1 Rule 1 None F1 NC NC NC None None None F2 IO215PDB3 NC NC Rule 1 Rule 1 None F3 IO215NDB3 NC NC Rule 1 Rule 1 None F4 IO224NDB3 IO173NDB3 IO154VDB3 None None None F5 IO225NDB3 IO174NDB3 IO155VDB3 None None None F6 VMV3 VMV3 IO11RSB0 None Rule 7 Rule 7 F7 IO11RSB0 IO07RSB0 IO07RSB0 None None None F8 GAC0/IO04RSB0 GAC0/IO04RSB0 GAC0/IO04RSB0 None None None F9 GAC1/IO05RSB0 GAC1/IO05RSB0 GAC1/IO05RSB0 None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 - 29 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) Pin Number A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 F10 IO25RSB0 IO20RSB0 IO20RSB0 None None None F11 IO36RSB0 IO24RSB0 IO24RSB0 None None None F12 IO42RSB0 IO33RSB0 IO33RSB0 None None None F13 IO49RSB0 IO39RSB0 IO39RSB0 None None None F14 IO56RSB0 IO44RSB0 IO45RSB0 None None None F15 GBC0/IO72RSB0 GBC0/IO54RSB0 GBC0/IO54RSB0 None None None F16 IO62RSB0 IO51RSB0 IO48RSB0 None None None F17 VMV0 VMV0 VMV0 None None None F18 IO78NDB1 IO61NPB1 IO61NPB1 None None None F19 IO81NDB1 IO63PDB1 IO63PDB1 None None None F20 IO82PPB1 NC NC Rule 1 Rule 1 None F21 NC NC NC None None None F22 IO84NDB1 NC NC Rule 1 Rule 1 None G1 IO214NDB3 IO170NDB3 NC None Rule 1 Rule 1 G2 IO214PDB3 IO170PDB3 NC None Rule 1 Rule 1 G3 NC NC NC None None None G4 IO222NDB3 IO171NDB3 IO151VDB3 None None None G5 IO222PDB3 IO171PDB3 IO151UDB3 None None None G6 GAC2/IO223PDB3 GAC2/IO172PDB3 GAC2/IO153UDB3 None None None G7 IO223NDB3 IO06RSB0 IO06RSB0 None None None G8 GNDQ GNDQ GNDQ None None None G9 IO23RSB0 IO10RSB0 IO10RSB0 None None None G10 IO29RSB0 IO19RSB0 IO19RSB0 None None None G11 IO33RSB0 IO26RSB0 IO26RSB0 None None None G12 IO46RSB0 IO30RSB0 IO30RSB0 None None None G13 IO52RSB0 IO40RSB0 IO40RSB0 None None None G14 IO60RSB0 IO45RSB0 IO46RSB0 None None None G15 GNDQ GNDQ GNDQ None None None G16 IO80NDB1 IO50RSB0 IO47RSB0 None None None G17 GBB2/IO79PDB1 GBB2/IO61PPB1 GBB2/IO61PPB1 None None None G18 IO79NDB1 IO53RSB0 IO53RSB0 None None None G19 IO82NPB1 IO63NDB1 IO63NDB1 None None None G20 IO85PDB1 NC NC Rule 1 Rule 1 None 1 2 -3 0 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 G21 IO85NDB1 NC NC Rule 1 Rule 1 None G22 NC NC NC None None None H1 NC NC NC None None None H2 NC NC NC None None None H3 VCC VCC VCC None None None H4 IO217PDB3 IO166PDB3 IO150PDB3 None None None H5 IO218PDB3 IO167NPB3 IO08RSB0 None None None H6 IO221NDB3 IO172NDB3 IO153VDB3 None None None H7 IO221PDB3 IO169NDB3 IO152VDB3 None None None H8 VMV0 VMV0 VMV0 None None None H9 VCCIB0 VCCIB0 VCCIB0 None None None H10 VCCIB0 VCCIB0 VCCIB0 None None None H11 IO38RSB0 IO25RSB0 IO25RSB0 None None None H12 IO47RSB0 IO31RSB0 IO31RSB0 None None None H13 VCCIB0 VCCIB0 VCCIB0 None None None H14 VCCIB0 VCCIB0 VCCIB0 None None None H15 VMV1 VMV1 VMV1 None None None H16 GBC2/IO80PDB1 GBC2/IO62PDB1 GBC2/IO62PDB1 None None None H17 IO83PPB1 IO67PPB1 IO65RSB1 None None None H18 IO86PPB1 IO64PPB1 IO52RSB0 None None None H19 IO87PDB1 IO66PDB1 IO66PDB1 None None None H20 VCC VCC VCC None None None H21 NC NC NC None None None H22 NC NC NC None None None J1 IO212NDB3 NC NC Rule 1 Rule 1 None J2 IO212PDB3 NC NC Rule 1 Rule 1 None J3 NC NC NC None None None J4 IO217NDB3 IO166NDB3 IO150NDB3 None None None J5 IO218NDB3 IO168NPB3 IO149NPB3 None None None J6 IO216PDB3 IO167PPB3 IO09RSB0 None None None J7 IO216NDB3 IO169PDB3 IO152UDB3 None None None J8 VCCIB3 VCCIB3 VCCIB3 None None None J9 GND GND GND None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 - 31 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 J10 VCC VCC VCC None None None J11 VCC VCC VCC None None None J12 VCC VCC VCC None None None J13 VCC VCC VCC None None None J14 GND GND GND None None None J15 VCCIB1 VCCIB1 VCCIB1 None None None J16 IO83NPB1 IO62NDB1 IO62NDB1 None None None J17 IO86NPB1 IO64NPB1 IO49RSB0 None None None J18 IO90PPB1 IO65PPB1 IO64PPB1 None None None J19 IO87NDB1 IO66NDB1 IO66NDB1 None None None J20 NC NC NC None None None J21 IO89PDB1 IO68PDB1 NC None Rule 1 Rule 1 J22 IO89NDB1 IO68NDB1 NC None Rule 1 Rule 1 K1 IO211PDB3 IO157PDB3 NC None Rule 1 Rule 1 K2 IO211NDB3 IO157NDB3 NC None Rule 1 Rule 1 K3 NC NC NC None None None K4 IO210PPB3 IO165NDB3 IO148NDB3 None None None K5 IO213NDB3 IO165PDB3 IO148PDB3 None None None K6 IO213PDB3 IO168PPB3 IO149PPB3 None None None K7 GFC1/IO209PPB3 GFC1/IO164PPB3 GFC1/IO147PPB3 None None None K8 VCCIB3 VCCIB3 VCCIB3 None None None K9 VCC VCC VCC None None None K10 GND GND GND None None None K11 GND GND GND None None None K12 GND GND GND None None None K13 GND GND GND None None None K14 VCC VCC VCC None None None K15 VCCIB1 VCCIB1 VCCIB1 None None None K16 GCC1/IO91PPB1 GCC1/IO69PPB1 GCC1/IO67PPB1 None None None K17 IO90NPB1 IO65NPB1 IO64NPB1 None None None K18 IO88PDB1 IO75PDB1 IO73PDB1 None None None K19 IO88NDB1 IO75NDB1 IO73NDB1 None None None K20 IO94NPB1 NC NC Rule 1 Rule 1 None Pin Number 1 2 -3 2 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 K21 IO98NDB1 IO76NDB1 NC None Rule 1 Rule 1 K22 IO98PDB1 IO76PDB1 NC None Rule 1 Rule 1 L1 NC NC NC None None None L2 IO200PDB3 IO155PDB3 NC None Rule 1 Rule 1 L3 IO210NPB3 NC NC Rule 1 Rule 1 None L4 GFB0/IO208NPB3 GFB0/IO163NPB3 GFB0/IO146NPB3 None None None L5 GFA0/IO207NDB3 GFA0/IO162NDB3 GFA0/IO145NDB3 None None None L6 GFB1/IO208PPB3 GFB1/IO163PPB3 GFB1/IO146PPB3 None None None L7 VCOMPLF VCOMPLF VCOMPLF None None None L8 GFC0/IO209NPB3 GFC0/IO164NPB3 GFC0/IO147NPB3 None None None L9 VCC VCC VCC None None None L10 GND GND GND None None None L11 GND GND GND None None None L12 GND GND GND None None None L13 GND GND GND None None None L14 VCC VCC VCC None None None L15 GCC0/IO91NPB1 GCC0/IO69NPB1 GCC0/IO67NPB1 None None None L16 GCB1/IO92PPB1 GCB1/IO70PPB1 GCB1/IO68PPB1 None None None L17 GCA0/IO93NPB1 GCA0/IO71NPB1 GCA0/IO69NPB1 None None None L18 IO96NPB1 IO67NPB1 NC None Rule 1 Rule 1 L19 GCB0/IO92NPB1 GCB0/IO70NPB1 GCB0/IO68NPB1 None None None L20 IO97PDB1 IO77PDB1 NC None Rule 1 Rule 1 L21 IO97NDB1 IO77NDB1 NC None Rule 1 Rule 1 L22 IO99NPB1 IO78NPB1 NC None Rule 1 Rule 1 M1 NC NC NC None None None M2 IO200NDB3 IO155NDB3 NC None Rule 1 Rule 1 M3 IO206NDB3 IO158NPB3 NC None Rule 1 Rule 1 M4 GFA2/IO206PDB3 GFA2/IO161PPB3 GFA2/IO144PPB3 None None None M5 GFA1/IO207PDB3 GFA1/IO162PDB3 GFA1/IO145PDB3 None None None M6 VCCPLF VCCPLF VCCPLF None None None M7 IO205NDB3 IO160NDB3 IO143NDB3 None None None M8 GFB2/IO205PDB3 GFB2/IO160PDB3 GFB2/IO143PDB3 None None None M9 VCC VCC VCC None None None Pin Number v1.1 1 2 - 33 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 M10 GND GND GND None None None M11 GND GND GND None None None M12 GND GND GND None None None M13 GND GND GND None None None M14 VCC VCC VCC None None None M15 GCB2/IO95PPB1 GCB2/IO73PPB1 GCB2/IO71PPB1 None None None M16 GCA1/IO93PPB1 GCA1/IO71PPB1 GCA1/IO69PPB1 None None None M17 GCC2/IO96PPB1 GCC2/IO74PPB1 GCC2/IO72PPB1 None None None M18 IO100PPB1 IO80PPB1 NC None Rule 1 Rule 1 M19 GCA2/IO94PPB1 GCA2/IO72PDB1 GCA2/IO70PDB1 None None None M20 IO101PPB1 IO79PPB1 NC None Rule 1 Rule 1 M21 IO99PPB1 IO78PPB1 NC None Rule 1 Rule 1 M22 NC NC NC None None None N1 IO201NDB3 IO154NDB3 NC None Rule 1 Rule 1 N2 IO201PDB3 IO154PDB3 NC None Rule 1 Rule 1 N3 NC NC NC None None None N4 GFC2/IO204PDB3 GFC2/IO159PDB3 GFC2/IO142PDB3 None None None N5 IO204NDB3 IO161NPB3 IO144NPB3 None None None N6 IO203NDB3 IO156PPB3 IO141PPB3 None None None N7 IO203PDB3 IO129RSB2 IO120RSB2 None None None N8 VCCIB3 VCCIB3 VCCIB3 None None None N9 VCC VCC VCC None None None N10 GND GND GND None None None N11 GND GND GND None None None N12 GND GND GND None None None N13 GND GND GND None None None N14 VCC VCC VCC None None None N15 VCCIB1 VCCIB1 VCCIB1 None None None N16 IO95NPB1 IO73NPB1 IO71NPB1 None None None N17 IO100NPB1 IO80NPB1 IO74RSB1 None None None N18 IO102NDB1 IO74NPB1 IO72NPB1 None None None N19 IO102PDB1 IO72NDB1 IO70NDB1 None None None N20 NC NC NC None None None Pin Number 1 2 -3 4 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 N21 IO101NPB1 IO79NPB1 NC None Rule 1 Rule 1 N22 IO103PDB1 NC NC Rule 1 Rule 1 None P1 NC NC NC None None None P2 IO199PDB3 IO153PDB3 NC None Rule 1 Rule 1 P3 IO199NDB3 IO153NDB3 NC None Rule 1 Rule 1 P4 IO202NDB3 IO159NDB3 IO142NDB3 None None None P5 IO202PDB3 IO156NPB3 IO141NPB3 None None None P6 IO196PPB3 IO151PPB3 IO125RSB2 None None None P7 IO193PPB3 IO158PPB3 IO139RSB3 None None None P8 VCCIB3 VCCIB3 VCCIB3 None None None P9 GND GND GND None None None P10 VCC VCC VCC None None None P11 VCC VCC VCC None None None P12 VCC VCC VCC None None None P13 VCC VCC VCC None None None P14 GND GND GND None None None P15 VCCIB1 VCCIB1 VCCIB1 None None None P16 GDB0/IO112NPB1 GDB0/IO87NPB1 GDB0/IO78VPB1 None None None P17 IO106NDB1 IO85NDB1 IO76VDB1 None None None P18 IO106PDB1 IO85PDB1 IO76UDB1 None None None P19 IO107PDB1 IO84PDB1 IO75PDB1 None None None P20 NC NC NC None None None P21 IO104PDB1 IO81PDB1 NC None Rule 1 Rule 1 P22 IO103NDB1 NC NC Rule 1 Rule 1 None R1 NC NC NC None None None R2 IO197PPB3 NC NC Rule 1 Rule 1 None R3 VCC VCC VCC None None None R4 IO197NPB3 IO150PDB3 IO140PDB3 None None None R5 IO196NPB3 IO151NPB3 IO130RSB2 None None None R6 IO193NPB3 IO147NPB3 IO138NPB3 None None None R7 GEC0/IO190NPB3 GEC0/IO146NPB3 GEC0/IO137NPB3 None None None R8 VMV3 VMV3 VMV3 None None None R9 VCCIB2 VCCIB2 VCCIB2 None None None Pin Number v1.1 1 2 - 35 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 R10 VCCIB2 VCCIB2 VCCIB2 None None None R11 IO147RSB2 IO117RSB2 IO108RSB2 None None None R12 IO136RSB2 IO110RSB2 IO101RSB2 None None None R13 VCCIB2 VCCIB2 VCCIB2 None None None R14 VCCIB2 VCCIB2 VCCIB2 None None None R15 VMV2 VMV2 VMV2 None None None R16 IO110NDB1 IO94RSB2 IO83RSB2 None None None R17 GDB1/IO112PPB1 GDB1/IO87PPB1 GDB1/IO78UPB1 None None None R18 GDC1/IO111PDB1 GDC1/IO86PDB1 GDC1/IO77UDB1 None None None R19 IO107NDB1 IO84NDB1 IO75NDB1 None None None R20 VCC VCC VCC None None None R21 IO104NDB1 IO81NDB1 NC None Rule 1 Rule 1 R22 IO105PDB1 IO82PDB1 NC None Rule 1 Rule 1 T1 IO198PDB3 IO152PDB3 NC None Rule 1 Rule 1 T2 IO198NDB3 IO152NDB3 NC None Rule 1 Rule 1 T3 NC NC NC None None None T4 IO194PPB3 IO150NDB3 IO140NDB3 None None None T5 IO192PPB3 IO147PPB3 IO138PPB3 None None None T6 GEC1/IO190PPB3 GEC1/IO146PPB3 GEC1/IO137PPB3 None None None T7 IO192NPB3 IO140RSB2 IO131RSB2 None None None T8 GNDQ GNDQ GNDQ None None None T9 GEA2/IO187RSB2 GEA2/IO143RSB2 GEA2/IO134RSB2 None None None T10 IO161RSB2 IO126RSB2 IO117RSB2 None None None T11 IO155RSB2 IO120RSB2 IO111RSB2 None None None T12 IO141RSB2 IO108RSB2 IO99RSB2 None None None T13 IO129RSB2 IO103RSB2 IO94RSB2 None None None T14 IO124RSB2 IO99RSB2 IO87RSB2 None None None T15 GNDQ GNDQ GNDQ None None None T16 IO110PDB1 IO92RSB2 IO93RSB2 None None None T17 VJTAG VJTAG VJTAG None None None T18 GDC0/IO111NDB1 GDC0/IO86NDB1 GDC0/IO77VDB1 None None None T19 GDA1/IO113PDB1 GDA1/IO88PDB1 GDA1/IO79UDB1 None None None T20 NC NC NC None None None Pin Number 1 2 -3 6 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 T21 IO108PDB1 IO83PDB1 NC None Rule 1 Rule 1 T22 IO105NDB1 IO82NDB1 NC None Rule 1 Rule 1 U1 IO195PDB3 IO149PDB3 NC None Rule 1 Rule 1 U2 IO195NDB3 IO149NDB3 NC None Rule 1 Rule 1 U3 IO194NPB3 NC NC Rule 1 Rule 1 None U4 GEB1/IO189PDB3 GEB1/IO145PDB3 GEB1/IO136PDB3 None None None U5 GEB0/IO189NDB3 GEB0/IO145NDB3 GEB0/IO136NDB3 None None None U6 VMV2 VMV2 VMV2 None None None U7 IO179RSB2 IO138RSB2 IO129RSB2 None None None U8 IO171RSB2 IO136RSB2 IO128RSB2 None None None U9 IO165RSB2 IO131RSB2 IO122RSB2 None None None U10 IO159RSB2 IO124RSB2 IO115RSB2 None None None U11 IO151RSB2 IO119RSB2 IO110RSB2 None None None U12 IO137RSB2 IO107RSB2 IO98RSB2 None None None U13 IO134RSB2 IO104RSB2 IO95RSB2 None None None U14 IO128RSB2 IO97RSB2 IO88RSB2 None None None U15 VMV1 VMV1 IO84RSB2 None Rule 7 Rule 7 U16 TCK TCK TCK None None None U17 VPUMP VPUMP VPUMP None None None U18 TRST TRST TRST None None None U19 GDA0/IO113NDB1 GDA0/IO88NDB1 GDA0/IO79VDB1 None None None U20 NC NC NC None None None U21 IO108NDB1 IO83NDB1 NC None Rule 1 Rule 1 U22 IO109PDB1 NC NC Rule 1 Rule 1 None V1 NC NC NC None None None V2 NC NC NC None None None V3 GND GND GND None None None V4 GEA1/IO188PDB3 GEA1/IO144PDB3 GEA1/IO135PDB3 None None None V5 GEA0/IO188NDB3 GEA0/IO144NDB3 GEA0/IO135NDB3 None None None V6 IO184RSB2 IO139RSB2 IO127RSB2 None None None V7 GEC2/IO185RSB2 GEC2/IO141RSB2 GEC2/IO132RSB2 None None None V8 IO168RSB2 IO132RSB2 IO123RSB2 None None None V9 IO163RSB2 IO127RSB2 IO118RSB2 None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 - 37 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 V10 IO157RSB2 IO121RSB2 IO112RSB2 None None None V11 IO149RSB2 IO114RSB2 IO106RSB2 None None None V12 IO143RSB2 IO109RSB2 IO100RSB2 None None None V13 IO138RSB2 IO105RSB2 IO96RSB2 None None None V14 IO131RSB2 IO98RSB2 IO89RSB2 None None None V15 IO125RSB2 IO96RSB2 IO85RSB2 None None None V16 GDB2/IO115RSB2 GDB2/IO90RSB2 GDB2/IO81RSB2 None None None V17 TDI TDI TDI None None None V18 GNDQ GNDQ NC None Rule 8 Rule 8 V19 TDO TDO TDO None None None V20 GND GND GND None None None V21 NC NC NC None None None V22 IO109NDB1 NC NC Rule 1 Rule 1 None W1 NC NC NC None None None W2 IO191PDB3 IO148PDB3 NC None Rule 1 Rule 1 W3 NC NC NC None None None W4 GND GND GND None None None W5 IO183RSB2 IO137RSB2 IO126RSB2 None None None W6 GEB2/IO186RSB2 GEB2/IO142RSB2 GEB2/IO133RSB2 None None None W7 IO172RSB2 IO134RSB2 IO124RSB2 None None None W8 IO170RSB2 IO125RSB2 IO116RSB2 None None None W9 IO164RSB2 IO123RSB2 IO113RSB2 None None None W10 IO158RSB2 IO118RSB2 IO107RSB2 None None None W11 IO153RSB2 IO115RSB2 IO105RSB2 None None None W12 IO142RSB2 IO111RSB2 IO102RSB2 None None None W13 IO135RSB2 IO106RSB2 IO97RSB2 None None None W14 IO130RSB2 IO102RSB2 IO92RSB2 None None None W15 GDC2/IO116RSB2 GDC2/IO91RSB2 GDC2/IO82RSB2 None None None W16 IO120RSB2 IO93RSB2 IO86RSB2 None None None W17 GDA2/IO114RSB2 GDA2/IO89RSB2 GDA2/IO80RSB2 None None None W18 TMS TMS TMS None None None W19 GND GND GND None None None W20 NC NC NC None None None Pin Number 1 2 -3 8 v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Table 12-7 * Pin Compatibility and Migration Table for the FG484 Package (continued) A3P1000 Function A3P600 Function A3P400 Function Migration Rule between A3P1000 and A3P600 W21 NC NC NC None None None W22 NC NC NC None None None Y1 VCCIB3 VCCIB3 VCCIB3 None None None Y2 IO191NDB3 IO148NDB3 NC None Rule 1 Rule 1 Y3 NC NC NC None None None Y4 IO182RSB2 NC NC Rule 1 Rule 1 None Y5 GND GND GND None None None Y6 IO177RSB2 NC NC Rule 1 Rule 1 None Y7 IO174RSB2 NC NC Rule 1 Rule 1 None Y8 VCC VCC VCC None None None Y9 VCC VCC VCC None None None Y10 IO154RSB2 NC NC Rule 1 Rule 1 None Y11 IO148RSB2 NC NC Rule 1 Rule 1 None Y12 IO140RSB2 NC NC Rule 1 Rule 1 None Y13 NC NC NC None None None Y14 VCC VCC VCC None None None Y15 VCC VCC VCC None None None Y16 NC NC NC None None None Y17 NC NC NC None None None Y18 GND GND GND None None None Y19 NC NC NC None None None Y20 NC NC NC None None None Y21 NC NC NC None None None Y22 VCCIB1 VCCIB1 VCCIB1 None None None Pin Number v1.1 Migration Rule between A3P1000 and A3P400 Migration Rule between A3P600 and A3P400 1 2 - 39 Migrating Designs in ProASIC3 Devices from Higher-Density to Mid-Density Devices Conclusion This application note describes design migration among ProASIC3 family devices with an emphasis on package pin compatibility. The ProASIC3 family of devices shares numerous common architectural features. During a system migration, care should be taken regarding the architectural features of each core. Additionally, a key requirement is running functional simulation before and after the migration, using Actel tools. Actel will be updating this application note with additional packages in the future. Related Documents Handbook Documents I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/IGLOO_PA3_IO_HBs.pdf Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content. Part Number 51700094-017-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.1) Page v1.0 (January 2008) The part number for this document was changed from 51700094-016-0 to 51700094-017-1. N/A 51900143-1/10.07 In Table 12-4 * Pin Compatibility and Migration Table for the PQ208 Package, pin 107 was updated to include Rule 8. 12-5 51900143-0/7.06 The title of the document and the "Introduction" section were updated to clarify the topics covered in the application note. 12-1 The "Design Migration" section was updated to match and cross-reference the sections of the document in sequence. 12-1 The title of Table 12-1 * Device Information was updated. 12-1 Table 12-3 * Migration Rules from Higher-Density to Mid-Density Devices and Table 4 were combined and a table note was added to refer to the datasheet for I/O naming conventions. 12-3 In the "Power Supply and Board-Level Considerations" section, the following bullet was removed: 12-4 "Since each bank independently supports 1.5 V to 3.3 V, I/Os must be connected to the VCCIBx of their own banks." The "Related Documents" section was added. 1 2 -4 0 v1.1 12-40 Application Note AC313 13 - Migrating Designs from A3P250 to LowerLogic-Density Devices Introduction The purpose of this document is to assist you in migrating designs from a high-density ProASIC(R)3 device (A3P250) to lower-density devices (A3P125, A3P060, and A3P030). Since one of the key factors is pin compatibility for a given package among the devices within the family, the primary focus of this document will be to address the pin compatibility issue. Design Migration ProASIC3 family devices are architecturally compatible with each other. However, customers must pay attention to a few key areas when migrating a design. The specific issues discussed throughout this application note are as follows: * "Design and Device Evaluation" * "Device and Package Compatibility" on page 13-2 * "Migration and Implementation Methodologies" on page 13-2 * "I/O Banks and Standards" on page 13-3 * "Power Supply Considerations" on page 13-4 * "Pin Migration and Compatibility" on page 13-5 Design and Device Evaluation When migrating a design, the primary task should be to compare the available resources between two devices. You need to evaluate effective gate count, RAM size, I/O banks, and the number of I/Os. In addition, when porting designs to new ProASIC3 derivatives, timing analysis and simulations should also be validated. Table 13-1 gives a summary of device resources for the A3P250 device and its smaller migration targets. Table 13-1 * Device Information A3P250 A3P125 A3P060 A3P030 System Gates 250 k 125 k 60 k 30 k Tiles (D-flip-flops) 6,144 3,072 1,536 768 RAM (kbits) 36 36 18 - RAM Blocks (4,608 bits) 8 8 4 - I/O Banks (+ JTAG) 4 2 2 2 VQ100 68/13 71 71 77 QN132 87/19 84 80 81 100 91 96 User I/Os per Package: TQ144 FG144 97/24 97 PQ208 151/34 133 FG256 157/38 Note: User I/O is given as X (single-ended) or X/Y (single-ended/double-ended). v1.0 1 3 -1 Migrating Designs from A3P250 to Lower-Logic-Density Devices Device and Package Compatibility ProASIC3 devices and packaging were designed to allow considerable footprint compatibility for smoother migration. Common and Convertible I/Os among A3P030, A3P060, A3P125, and A3P250 Table 13-2 shows the number of I/Os that are common between any two of the above four devices. In addition, the table indicates the number of I/Os that require the necessary conversion (convertible I/Os) using suggested design migration rules in the "Migration and Implementation Methodologies" section. Table 13-2 * Common and Convertible I/Os Package Convertible I/Os Common I/Os Convertible I/Os Common I/Os Convertible I/Os Common I/Os Convertible I/Os A3P060 A3P030 Common I/Os A3P125 A3P030 Convertible I/Os A3P125 A3P060 Common I/Os A3P250 A3P030 Convertible I/Os A3P250 A3P060 Common I/Os A3P250 A3P125 VQ100 68 7 67 5 69 46 69 4 72 46 71 46 QN132 84 13 80 25 64 72 80 14 66 70 61 75 FG144 97 - 96 - N/A N/A 96 - N/A N/A N/A N/A PQ208 134 18 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A TQ144 N/A N/A N/A N/A N/A N/A 90 19 N/A N/A N/A N/A Migration and Implementation Methodologies Table 13-3 on page 13-3 lists some possible migration combinations and the recommended implementation rules for compatible design conversions from higher-density to lower-density devices. The "Pin Migration and Compatibility" section on page 13-5 contains tables that list the required rules for different pin combinations. If "Rule x" is mentioned for a pin combination, that combination requires the implementation methodology given in Table 13-3 on page 13-3. Note that many combinations of high-density/low-density pins require none of these rules; the pins have complete type compatibility. These pins are marked in the pin tables with "None." 1 3 -2 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-3 * Migration Rules from Higher-Density Device to Lower-Density Device Issue Migration Rule Higher Density Lower Density 1 Implementation Methodology I/O or Global I/O NC NC I/O or Global I/O 2 I/O Global I/O Instantiate the global I/O as an I/O buffer (works as a singleended I/O). 3 Global I/O I/O Use the PDC constraint to promote the single-ended I/O to a global pin. There will be some additional delay. 4 VCC or VCCI NC GNDQ NC The pin can remain connected to the board's VCC, VCCI , VMV, VCOMPLF, or GNDQ plane, as applicable. VMV NC VCOMPLF NC 5 6 Leave this pin floating OR program the I/O as unused (software cannot program NC to usable I/O). B(x)1 VCCI B(y)2 Make sure the two bank voltage levels are same. VMV(x)1 VMV(y)2 Tie the pin to the board's corresponding VCCI /VMV plane. VCCI VMV0 GNDQ GNDQ I/O or Global I/O Leave the pin connected to the board's VCC, VCCI , VMV, VCOMPLF, or GNDQ plane, as applicable. I/O Instantiate the I/O as a tristate buffer with OE = 0 and no weak Global I/O pull-ups/-downs. I/O VCC VCC I/O VCOMPLF I/O VCCPLF I/O Notes: 1. "x" is a bank number designator and can be 0-3 for ProASIC3 and 0-7 for ProASIC3E. 2. "y" is a bank number designator and can be 0-3 for ProASIC3 and 0-7 for ProASIC3E. I/O Banks and Standards ProASIC3 I/Os are partitioned into multiple I/O voltage banks. The number of banks is devicedependent. There are four I/O banks in the A3P250 device and two I/O banks in the A3P030, A3P060, and A3P125 devices. Package pins routed to banks 0 and 1 in the A3P250 device are routed to bank 0 in the A3P030, A3P060, and A3P125 devices, and banks 2 and 3 in the A3P250 device are routed to bank 1 in the A3P030, A3P060, and A3P125 devices. The banks have dedicated supplies; therefore, only I/Os with compatible voltage standards can be assigned to the same I/O voltage bank. Note that the A3P250 device supports double-ended I/Os; however, the A3P030, A3P060, and A3P125 devices do not support double-ended I/Os. v1.0 1 3 -3 Migrating Designs from A3P250 to Lower-Logic-Density Devices Power Supply Considerations I/O power supply requirements are very important for design migration. Since the migration is within the ProASIC3 family, there is no issue with respect to the core voltage VCC. Pins that must be appropriately connected are VCCIBx (bank supply voltage to I/O output buffer and I/O logic), VMVx (quiet I/O supply voltage), GNDQ (quiet GND), and GND. GNDQ and VMVx are important to decouple simultaneous switching noise (SSO) for I/Os--enhancing signal integrity and improving noise immunity. The key rules of migration for the above-mentioned pins are as follows: * VMV and VCCI values of the higher-density device in a given bank must correspond to the same VMV and VCCI values in the smaller device's migrating bank. * Since banks 0 and 1 are connected to bank 0 in the smaller device--and banks 2 and 3 are connected to bank 1 in the smaller device--this implies that banks 0 and 1 in the A3P250 device must have identical VMV and identical VCCI. Similarly, the VMV and VCCI voltages in banks 2 and 3 of the A3P250 device must be identical. * VCCIBx pins in unused banks and VMV pins in unused banks must be connected to GND. * Unused I/Os should be left alone, since the software automatically configures them as inputs with pull-ups. Any inappropriate connection during the migration may affect overall dynamic or inrush power consumption and might even result in device malfunction. Additionally, the I/O naming convention in ProASIC3 devices has significant embedded information (e.g., pin location, bank number, signal type, polarity, and clock conditioning). For a detailed explanation, refer to the "User I/O Naming Convention" section of I/O Structures in IGLOO and ProASIC3 Devices. For additional information on power issues, refer to the relevant datasheet. 1 3 -4 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Pin Migration and Compatibility VQ100 Package Table 13-4 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with VQ100 Packaging Pin A3P030 A3P060 A3P125 No. Function Function Function 1 GND 2 IO03RSB1 None None None None None None GAA2/ GAA2/ GAA2/ IO51RSB1 IO67RSB1 IO118UDB3 None None None Rule 3 Rule 3 Rule 3 3 IO02RSB1 IO52RSB1 IO68RSB1 IO118VDB3 None None None None None None 4 IO01RSB1 GAB2/ GAB2/ GAB2/ IO53RSB1 IO69RSB1 IO117UDB3 None None None Rule 3 Rule 3 Rule 3 5 IO00RSB1 IO95RSB1 IO132RSB1 IO117VDB3 None None None None None None 6 IO82RSB1 GAC2/ GAC2/ GAC2/ IO94RSB1 IO131RSB1 IO116UDB3 None None None Rule 3 Rule 3 Rule 3 7 IO81RSB1 IO93RSB1 IO130RSB1 IO116VDB3 None None None None None None 8 IO80RSB1 IO92RSB1 IO129RSB1 IO112PSB3 None None None None None None None None None None None None 9 GND GND GND GND Migration Migration Migration Migration Migration Migration Rule Rule Rule Rule Rule Rule between between between between between between A3P125 A3P250 A3P250 A3P060 A3P125 A3P250 A3P250 and and and and and and Function A3P060 A3P060 A3P125 A3P030 A3P030 A3P030 GND GND GND 10 IO79RSB1 GFB1/ GFB1/ GFB1/ IO87RSB1 IO124RSB1 IO109PDB3 None None None Rule 3 Rule 3 Rule 3 11 IO78RSB1 GFB0/ GFB0/ GFB0/ IO86RSB1 IO123RSB1 IO109NDB3 None None None Rule 3 Rule 3 Rule 3 None None None Rule 6 Rule 6 Rule 6 None None None None None None None None None Rule 6 Rule 6 Rule 6 VCOMPLF VCOMPLF 12 GEC0/ VCOMPLF IO77RSB1 13 GEA0/ GFA0/ GFA0/ GFA0/ IO76RSB1 IO85RSB1 IO122RSB1 IO108NPB3 14 GEB0/ IO75RSB1 VCCPLF VCCPLF VCCPLF 15 IO74RSB1 GFA1/ GFA1/ GFA1/ IO84RSB1 IO121RSB1 IO108PPB3 None None None Rule 3 Rule 3 Rule 3 16 IO73RSB1 GFA2/ GFA2/ GFA2/ IO83RSB1 IO120RSB1 IO107PSB3 None None None Rule 3 Rule 3 Rule 3 17 VCC VCC VCC VCC None None None None None None 18 VCCIB1 VCCIB1 VCCIB1 VCCIB3 None None None None None None None None None Rule 3 Rule 3 Rule 3 19 IO72RSB1 GEC1/ GEC0/ GFC2/ IO77RSB1 IO111RSB1 IO105PSB3 Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. v1.0 1 3 -5 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-4 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with VQ100 Packaging (continued) Pin A3P030 A3P060 A3P125 No. Function Function Function Migration Migration Migration Migration Migration Migration Rule Rule Rule Rule Rule Rule between between between between between between A3P125 A3P250 A3P250 A3P060 A3P125 A3P250 A3P250 and and and and and and Function A3P060 A3P060 A3P125 A3P030 A3P030 A3P030 20 IO71RSB1 GEB1/ GEB1/ GEC1/ IO75RSB1 IO110RSB1 IO100PDB3 None None None Rule 3 Rule 3 Rule 3 21 IO70RSB1 GEB0/ GEB0/ GEC0/ IO74RSB1 IO109RSB1 IO100NDB3 None None None Rule 3 Rule 3 Rule 3 22 IO69RSB1 GEA1/ GEA1/ GEA1/ IO73RSB1 IO108RSB1 IO98PDB3 None None None Rule 3 Rule 3 Rule 3 23 IO68RSB1 GEA0/ GEA0/ GEA0/ IO72RSB1 IO107RSB1 IO98NDB3 None None None Rule 3 Rule 3 Rule 3 24 IO67RSB1 VMV1 VMV1 VMV3 None None None Rule 6 Rule 6 Rule 6 25 IO66RSB1 GNDQ GNDQ GNDQ None None None Rule 6 Rule 6 Rule 6 26 IO65RSB1 GEA2/ GEA2/ GEA2/ IO71RSB1 IO106RSB1 IO97RSB2 None None None Rule 3 Rule 3 Rule 3 27 IO64RSB1 GEB2/ GEB2/ GEB2/ IO70RSB1 IO105RSB1 IO96RSB2 None None None Rule 3 Rule 3 Rule 3 28 IO63RSB1 GEC2/ GEC2/ GEC2/ IO69RSB1 IO104RSB1 IO95RSB2 None None None Rule 3 Rule 3 Rule 3 29 IO62RSB1 IO68RSB1 IO102RSB1 IO93RSB2 None None None None None None 30 IO61RSB1 IO67RSB1 IO100RSB1 IO92RSB2 None None None None None None 31 IO60RSB1 IO66RSB1 IO99RSB1 IO91RSB2 None None None None None None 32 IO59RSB1 IO65RSB1 IO97RSB1 IO90RSB2 None None None None None None 33 IO58RSB1 IO64RSB1 IO96RSB1 IO88RSB2 None None None None None None 34 IO57RSB1 IO63RSB1 IO95RSB1 IO86RSB2 None None None None None None 35 IO56RSB1 IO62RSB1 IO94RSB1 IO85RSB2 None None None None None None 36 IO55RSB1 IO61RSB1 IO93RSB1 IO84RSB2 None None None None None None 37 VCC VCC VCC VCC None None None None None None 38 GND GND GND GND None None None None None None 39 VCCIB1 VCCIB1 VCCIB1 VCCIB2 None None None None None None 40 IO53RSB1 IO60RSB1 IO87RSB1 IO77RSB2 None None None None None None 41 IO51RSB1 IO59RSB1 IO84RSB1 IO74RSB2 None None None None None None 42 IO50RSB1 IO58RSB1 IO81RSB1 IO71RSB2 None None None None None None 43 IO49RSB1 IO57RSB1 IO75RSB1 GDC2/ IO63RSB2 None Rule 2 Rule 3 None None Rule 3 Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. 1 3 -6 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-4 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with VQ100 Packaging (continued) Pin A3P030 A3P060 A3P125 No. Function Function Function Migration Migration Migration Migration Migration Migration Rule Rule Rule Rule Rule Rule between between between between between between A3P125 A3P250 A3P250 A3P060 A3P125 A3P250 A3P250 and and and and and and Function A3P060 A3P060 A3P125 A3P030 A3P030 A3P030 44 IO48RSB1 GDC2/ GDC2/ IO56RSB1 IO72RSB1 GDB2/ IO62RSB2 None None None Rule 3 Rule 3 Rule 3 45 IO47RSB1 GDB2/ GDB2/ IO55RSB1 IO71RSB1 GDA2/ IO61RSB2 None None None Rule 3 Rule 3 Rule 3 46 IO46RSB1 GDA2/ GDA2/ IO54RSB1 IO70RSB1 GNDQ None Rule 10 Rule 10 Rule 3 Rule 3 Rule 6 47 TCK TCK TCK TCK None None None None None None 48 TDI TDI TDI TDI None None None None None None 49 TMS TMS TMS TMS None None None None None None 50 NC VMV1 VMV1 VMV2 None None None Rule 4 Rule 4 Rule 4 51 GND GND GND GND None None None None None None 52 VPUMP VPUMP VPUMP VPUMP None None None None None None 53 NC NC NC NC None None None None None None 54 TDO TDO TDO TDO None None None None None None 55 TRST TRST TRST TRST None None None None None None 56 VJTAG VJTAG VJTAG VJTAG None None None None None None 57 IO45RSB0 GDA1/ GDA1/ GDA1/ IO49RSB0 IO65RSB0 IO60USB1 None None None Rule 3 Rule 3 Rule 3 58 IO44RSB0 GDC0/ GDC0/ GDC0/ IO46RSB0 IO62RSB0 IO58VDB1 None None None Rule 3 Rule 3 Rule 3 59 IO43RSB0 GDC1/ GDC1/ GDC1/ IO45RSB0 IO61RSB0 IO58UDB1 None None None Rule 3 Rule 3 Rule 3 60 IO42RSB0 GCC2/ GCC2/ IO52NDB1 IO43RSB0 IO59RSB0 None Rule 2 Rule 2 Rule 3 Rule 3 None 61 IO41RSB0 GCB2/ GCB2/ GCB2/ IO42RSB0 IO58RSB0 IO52PDB1 None None None Rule 3 Rule 3 Rule 3 62 IO40RSB0 GCA0/ GCA0/ GCA1/ IO40RSB0 IO56RSB0 IO50PDB1 None None None Rule 3 Rule 3 Rule 3 63 GDB0/ GCA1/ GCA1/ GCA0/ IO38RSB0 IO39RSB0 IO55RSB0 IO50NDB1 None None None None None None 64 GDA0/ GCC0/ GCC0/ GCC0/ IO37RSB0 IO36RSB0 IO52RSB0 IO48NDB1 None None None None None None 65 GDC0/ GCC1/ GCC1/ GCC1/ IO36RSB0 IO35RSB0 IO51RSB0 IO48PDB1 None None None None None None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. v1.0 1 3 -7 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-4 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with VQ100 Packaging (continued) Pin A3P030 A3P060 A3P125 No. Function Function Function Migration Migration Migration Migration Migration Migration Rule Rule Rule Rule Rule Rule between between between between between between A3P125 A3P250 A3P250 A3P060 A3P125 A3P250 A3P250 and and and and and and Function A3P060 A3P060 A3P125 A3P030 A3P030 A3P030 66 VCCIB0 VCCIB0 VCCIB0 VCCIB1 None None None None None None 67 GND GND GND GND None None None None None None 68 VCC VCC VCC VCC None None None None None None 69 IO35RSB0 IO31RSB0 IO47RSB0 IO43NDB1 None None None None None None 70 IO34RSB0 GBC2/ GBC2/ GBC2/ IO29RSB0 IO45RSB0 IO43PDB1 None None None Rule 3 Rule 3 Rule 3 71 IO33RSB0 GBB2/ GBB2/ IO27RSB0 IO43RSB0 GBB2/ IO42PSB1 None None None Rule 3 Rule 3 Rule 3 72 IO32RSB0 IO26RSB0 IO42RSB0 IO41NDB1 None None None None None None 73 IO31RSB0 None None None Rule 3 Rule 3 Rule 3 GBA2/ GBA2/ GBA2/ IO25RSB0 IO41RSB0 IO41PDB1 74 IO30RSB0 VMV0 VMV0 VMV1 None None None Rule 6 Rule 6 Rule 6 75 IO29RSB0 GNDQ GNDQ GNDQ None None None Rule 6 Rule 6 Rule 6 76 IO28RSB0 GBA1/ GBA1/ IO24RSB0 IO40RSB0 GBA1/ IO40RSB0 None None None Rule 3 Rule 3 Rule 3 77 IO27RSB0 GBA0/ GBA0/ IO23RSB0 IO39RSB0 GBA0/ IO39RSB0 None None None Rule 3 Rule 3 Rule 3 78 IO26RSB0 GBB1/ GBB1/ IO22RSB0 IO38RSB0 GBB1/ IO38RSB0 None None None Rule 3 Rule 3 Rule 3 79 IO25RSB0 GBB0/ GBB0/ IO21RSB0 IO37RSB0 GBB0/ IO37RSB0 None None None Rule 3 Rule 3 Rule 3 80 IO24RSB0 GBC1/ GBC1/ IO20RSB0 IO36RSB0 GBC1/ IO36RSB0 None None None Rule 3 Rule 3 Rule 3 81 IO23RSB0 GBC0/ GBC0/ IO19RSB0 IO35RSB0 GBC0/ IO35RSB0 None None None Rule 3 Rule 3 Rule 3 82 IO22RSB0 IO18RSB0 IO32RSB0 IO29RSB0 None None None None None None 83 IO21RSB0 IO17RSB0 IO28RSB0 IO27RSB0 None None None None None None 84 IO20RSB0 IO15RSB0 IO25RSB0 IO25RSB0 None None None None None None 85 IO19RSB0 IO13RSB0 IO22RSB0 IO23RSB0 None None None None None None 86 IO18RSB0 IO11RSB0 IO19RSB0 IO21RSB0 None None None None None None 87 VCCIB0 VCCIB0 VCCIB0 VCCIB0 None None None None None None 88 GND GND GND GND None None None None None None 89 VCC VCC VCC VCC None None None None None None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. 1 3 -8 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-4 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with VQ100 Packaging (continued) Pin A3P030 A3P060 A3P125 No. Function Function Function Migration Migration Migration Migration Migration Migration Rule Rule Rule Rule Rule Rule between between between between between between A3P125 A3P250 A3P250 A3P060 A3P125 A3P250 A3P250 and and and and and and Function A3P060 A3P060 A3P125 A3P030 A3P030 A3P030 90 IO16RSB0 IO10RSB0 IO15RSB0 IO15RSB0 None None None None None None 91 IO14RSB0 IO09RSB0 IO13RSB0 IO13RSB0 None None None None None None 92 IO12RSB0 IO08RSB0 IO11RSB0 IO11RSB0 None None None None None None 93 IO11RSB0 GAC1/ IO09RSB0 IO07RSB0 GAC1/ IO05RSB0 Rule 2 None Rule 3 Rule 3 None Rule 3 94 IO10RSB0 GAC0/ IO07RSB0 IO06RSB0 GAC0/ IO04RSB0 Rule 2 None Rule 3 Rule 3 None Rule 3 95 IO09RSB0 GAB1/ GAC1/ IO05RSB0 IO05RSB0 GAB1/ IO03RSB0 None None None Rule 3 Rule 3 Rule 3 96 IO08RSB0 GAB0/ GAC0/ IO04RSB0 IO04RSB0 GAB0/ IO02RSB0 None None None Rule 3 Rule 3 Rule 3 97 IO07RSB0 GAA1/ GAB1/ IO03RSB0 IO03RSB0 GAA1/ IO01RSB0 None None None Rule 3 Rule 3 Rule 3 98 IO06RSB0 GAA0/ GAB0/ IO02RSB0 IO02RSB0 GAA0/ IO00RSB0 None None None Rule 3 Rule 3 Rule 3 99 IO05RSB0 IO01RSB0 GAA1/ IO01RSB0 GNDQ Rule 3 Rule 9 Rule 10 None Rule 3 Rule 6 100 IO04RSB0 IO00RSB0 GAA0/ IO00RSB0 VMV0 Rule 3 Rule 8 Rule 8 None Rule 3 Rule 6 Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. v1.0 1 3 -9 Migrating Designs from A3P250 to Lower-Logic-Density Devices QFN132 Package Table 13-5 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with QFN132 Packaging Pin A3P030 A3P060 A3P125 No. Function Function Function A1 IO01RSB1 Migration Migration Migration Migration Migration Migration Rule Rule Rule Rule Rule Rule between between between between between between A3P250 A3P125 A3P250 A3P250 A3P125 A3P060 A3P250 and and and and and and Function A3P125 A3P060 A3P060 A3P030 A3P030 A3P030 GAB2/ GAB2/ GAB2/ IO00RSB1 IO69RSB1 IO117UPB3 None None None Rule 3 Rule 3 Rule 3 A2 IO81RSB1 IO93RSB1 IO130RSB1 IO117VPB3 None None None None None None Rule 5 None Rule 5 Rule 4 Rule 4 Rule 4 GFC1/ GFC1/ GFC1/ IO89RSB1 IO126RSB1 IO110PDB3 None None None Rule 3 Rule 3 Rule 3 GEC0/ GFB0/ GFB0/ GFB0/ IO77RSB1 IO86RSB1 IO123RSB1 IO109NPB3 None None None None None None None None None Rule 4 Rule 4 Rule 4 None None None None None None A3 NC A4 IO80RSB1 A5 A6 A7 NC VCCIB1 VCCPLF VCCIB1 VCCPLF VCCIB3 VCCPLF GEB0/ GFA1/ GFA1/ GFA1/ IO75RSB1 IO84RSB1 IO121RSB1 IO108PPB3 A8 IO73RSB1 GFC2/ GFC2/ GFC2/ IO81RSB1 IO118RSB1 IO105PPB3 None None None Rule 3 Rule 3 Rule 3 A9 NC IO78RSB1 IO115RSB1 IO103NDB3 None None None Rule 1 Rule 1 Rule 1 A10 VCC None None None None None None VCC VCC VCC A11 IO71RSB1 GEB1/ GEB1/ GEA1/ IO75RSB1 IO110RSB1 IO98PPB3 None None None Rule 3 Rule 3 Rule 3 A12 IO68RSB1 GEA0/ GEA0/ GEA0/ IO72RSB1 IO107RSB1 IO98NPB3 None None None Rule 3 Rule 3 Rule 3 A13 IO63RSB1 GEC2/ GEC2/ GEC2/ IO69RSB1 IO104RSB1 IO95RSB2 None None None Rule 3 Rule 3 Rule 3 A14 IO60RSB1 IO65RSB1 IO100RSB1 IO91RSB2 None None None None None None None None None None None None A16 IO59RSB1 IO64RSB1 IO99RSB1 IO90RSB2 None None None None None None A17 IO57RSB1 IO63RSB1 IO96RSB1 IO87RSB2 None None None None None None IO62RSB1 IO94RSB1 IO85RSB2 None None None Rule 6 Rule 6 Rule 6 A19 IO54RSB1 IO61RSB1 IO91RSB1 IO82RSB2 None None None None None None A20 IO52RSB1 IO58RSB1 IO85RSB1 IO76RSB2 None None None None None None A21 IO49RSB1 None Rule 2 Rule 2 None None Rule 3 A15 A18 NC VCC VCC VCC VCC GDB2/ IO79RSB1 IO70RSB2 IO55RSB1 Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. D pins are corner pins per the package specification. 3. "None" implies that the pins can be connected without any change. 1 3 -1 0 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-5 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with QFN132 Packaging (continued) Pin A3P030 A3P060 A3P125 No. Function Function Function A22 IO48RSB1 None Rule 4 Rule 4 Rule 6 Rule 6 Rule 1 A23 IO47RSB1 GDA2/ GDB2/ GDB2/ IO54RSB1 IO71RSB1 IO62RSB2 None None None Rule 3 Rule 3 Rule 3 A24 TDI TDI TDI TDI None None None None None None A25 TRST TRST TRST TRST None None None None None None None None None Rule 3 Rule 3 Rule 3 None None None Rule 4 Rule 4 Rule 4 A28 IO43RSB0 IO47RSB0 IO60RSB0 IO54NDB1 None None None None None None A29 IO42RSB0 GCC2/ GCC2/ IO52NDB1 IO46RSB0 IO59RSB0 None None Rule 2 None Rule 3 Rule 3 A30 IO40RSB0 GCA2/ GCA2/ GCA2/ IO44RSB0 IO57RSB0 IO51PPB1 None None None Rule 3 Rule 3 Rule 3 A31 IO39RSB0 GCA0/ GCA0/ GCA0/ IO43RSB0 IO56RSB0 IO50NPB1 None None None Rule 3 Rule 3 Rule 3 GDC0/ GCB1/ GCB1/ GCB1/ IO36RSB0 IO40RSB0 IO53RSB0 IO49PDB1 None None None None None None None None None Rule 1 Rule 1 Rule 1 None None None None None None A35 IO34RSB0 IO31RSB0 IO44RSB0 IO41NPB1 None None None None None None A36 IO31RSB0 GBA2/ GBA2/ GBA2/ IO28RSB0 IO41RSB0 IO41PPB1 None None None Rule 3 Rule 3 Rule 3 A37 IO26RSB0 GBB1/ GBB1/ GBB1/ IO25RSB0 IO38RSB0 IO38RSB0 None None None Rule 3 Rule 3 Rule 3 A38 IO23RSB0 GBC0/ GBC0/ GBC0/ IO22RSB0 IO35RSB0 IO35RSB0 None None None Rule 3 Rule 3 Rule 3 None None None Rule 4 Rule 4 Rule 4 A40 IO22RSB0 IO21RSB0 IO28RSB0 IO28RSB0 None None None None None None A41 IO20RSB0 IO18RSB0 IO22RSB0 IO22RSB0 None None None None None None A42 IO18RSB0 IO15RSB0 IO18RSB0 IO18RSB0 None None None None None None IO14RSB0 IO14RSB0 IO14RSB0 None None None Rule 6 Rule 6 Rule 6 A44 IO15RSB0 IO11RSB0 IO11RSB0 IO11RSB0 None None None None None None A26 IO44RSB0 A27 A32 NC A33 NC A34 VCC A39 A43 NC VCC NC VCC Migration Migration Migration Migration Migration Migration Rule Rule Rule Rule Rule Rule between between between between between between A3P250 A3P125 A3P250 A3P250 A3P125 A3P060 A3P250 and and and and and and Function A3P125 A3P060 A3P060 A3P030 A3P030 A3P030 VCC GDC1/ GDC1/ GDC1/ IO48RSB0 IO61RSB0 IO58UDB1 VCC VCC VCC IO36RSB0 IO49RSB0 IO47NSB1 VCC VCCIB0 VCC VCCIB0 VCC VCCIB0 Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. D pins are corner pins per the package specification. 3. "None" implies that the pins can be connected without any change. v1.0 1 3 - 11 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-5 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with QFN132 Packaging (continued) Pin A3P030 A3P060 A3P125 No. Function Function Function A45 IO12RSB0 Migration Migration Migration Migration Migration Migration Rule Rule Rule Rule Rule Rule between between between between between between A3P250 A3P125 A3P250 A3P250 A3P125 A3P060 A3P250 and and and and and and Function A3P125 A3P060 A3P060 A3P030 A3P030 A3P030 None Rule 2 Rule 2 None None Rule 3 None Rule 4 Rule 4 Rule 6 Rule 6 Rule 1 None None None Rule 3 Rule 3 Rule 3 None Rule 3 Rule 3 Rule 3 Rule 3 None B1 IO02RSB1 IO01RSB1 IO68RSB1 IO118VDB3 None None None None None None B2 IO82RSB1 None None None Rule 3 Rule 3 Rule 3 None None None None None None None None None Rule 3 Rule 3 Rule 3 A46 IO10RSB0 A47 IO09RSB0 GAB1/ IO07RSB0 IO07RSB0 IO08RSB0 NC GND B4 IO79RSB1 VCC GAB0/ GAC1/ GAC1/ IO07RSB0 IO05RSB0 IO05RSB0 A48 IO06RSB0 IO04RSB0 B3 VCC GAB0/ GAB0/ IO02RSB0 IO02RSB0 GAC2/ GAC2/ GAC2/ IO94RSB1 IO131RSB1 IO116UDB3 GND GND GND GFC0/ GFC0/ GFC0/ IO88RSB1 IO125RSB1 IO110NDB3 B5 NC VCOMPLF VCOMPLF VCOMPLF None None None Rule 4 Rule 4 Rule 4 B6 GND GND GND GND None None None None None None B7 IO74RSB1 GFB2/ GFB2/ GFB2/ IO82RSB1 IO119RSB1 IO106PSB3 None None None Rule 3 Rule 3 Rule 3 B8 NC IO79RSB1 IO116RSB1 IO103PDB3 None None None Rule 1 Rule 1 Rule 1 B9 GND None None None None None None None None None Rule 3 Rule 3 Rule 3 Rule 6 None Rule 5 Rule 6 Rule 6 Rule 6 GEB2/ GEB2/ GEB2/ IO70RSB1 IO105RSB1 IO96RSB2 None None None Rule 3 Rule 3 Rule 3 B13 IO61RSB1 IO67RSB1 IO101RSB1 IO92RSB2 None None None None None None B14 None None None None None None B10 IO70RSB1 B11 IO67RSB1 B12 IO64RSB1 GND GND GND GND GEB0/ GEB0/ GEB0/ IO74RSB1 IO109RSB1 IO99NDB3 VMV1 GND VMV1 GND VMV3 GND B15 IO58RSB1 NC IO98RSB1 IO89RSB2 None Rule 1 Rule 1 None None Rule 1 B16 IO56RSB1 NC IO95RSB1 IO86RSB2 None Rule 1 Rule 1 None None Rule 1 None None None None None None B18 IO53RSB1 IO59RSB1 IO87RSB1 IO78RSB2 None None None None None None B19 IO50RSB1 None Rule 2 Rule 2 None None Rule 3 B17 GND GND GND GND GDC2/ IO81RSB1 IO72RSB2 IO56RSB1 Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. D pins are corner pins per the package specification. 3. "None" implies that the pins can be connected without any change. 1 3 -1 2 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-5 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with QFN132 Packaging (continued) Pin A3P030 A3P060 A3P125 No. Function Function Function B20 GND B21 IO46RSB1 Migration Migration Migration Migration Migration Migration Rule Rule Rule Rule Rule Rule between between between between between between A3P250 A3P125 A3P250 A3P250 A3P125 A3P060 and A3P250 and and and and and Function A3P125 A3P060 A3P060 A3P030 A3P030 A3P030 GND GND GND None None None None None None GNDQ GNDQ GNDQ None None None Rule 6 Rule 6 Rule 8 B22 TMS TMS TMS TMS None None None None None None B23 TDO TDO TDO TDO None None None None None None None None None Rule 3 Rule 3 Rule 3 B24 IO45RSB0 GDC0/ GDC0/ GDC0/ IO49RSB0 IO62RSB0 IO58VDB1 B25 GND GND GND GND None None None None None None B26 NC NC NC IO54PDB1 Rule 1 None Rule 1 Rule 1 None None GCB2/ GCB2/ GCB2/ IO45RSB0 IO58RSB0 IO52PDB1 None None None Rule 3 Rule 3 Rule 3 None None None None None None None None None None None None None None None Rule 1 Rule 1 Rule 1 None None None None None None None None None Rule 3 Rule 3 Rule 3 Rule 5 None Rule 5 Rule 6 Rule 6 Rule 7 B27 IO41RSB0 B28 B29 GND GND GND GND GDA0/ GCB0/ GCB0/ GCB0/ IO37RSB0 IO41RSB0 IO54RSB0 IO49NDB1 B30 NC B31 GND B32 IO33RSB0 B33 IO30RSB0 GCC1/ GCC1/ GCC1/ IO38RSB0 IO51RSB0 IO48PDB1 GND GND GND GBB2/ GBB2/ GBB2/ IO30RSB0 IO43RSB0 IO42PDB1 VMV0 VMV0 VMV1 B34 IO27RSB0 GBA0/ GBA0/ GBA0/ IO26RSB0 IO39RSB0 IO39RSB0 None None None Rule 3 Rule 3 Rule 3 B35 IO24RSB0 GBC1/ GBC1/ GBC1/ IO23RSB0 IO36RSB0 IO36RSB0 None None None Rule 3 Rule 3 Rule 3 None None None None None None B37 IO21RSB0 IO20RSB0 IO26RSB0 IO26RSB0 None None None None None None B38 IO19RSB0 IO17RSB0 IO21RSB0 IO21RSB0 None None None None None None B39 None None None None None None B40 IO16RSB0 IO12RSB0 IO13RSB0 IO13RSB0 None None None None None None B41 IO13RSB0 None Rule 2 Rule 2 None None Rule 3 None None None None None None B36 B42 GND GND GND GND GND GND GND GND GND GAC0/ IO08RSB0 IO08RSB0 IO09RSB0 GND GND GND Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. D pins are corner pins per the package specification. 3. "None" implies that the pins can be connected without any change. v1.0 1 3 - 13 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-5 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with QFN132 Packaging (continued) Pin A3P030 A3P060 A3P125 No. Function Function Function Migration Migration Migration Migration Migration Migration Rule Rule Rule Rule Rule Rule between between between between between between A3P250 A3P125 A3P250 A3P250 A3P125 A3P060 A3P250 and and and and and and Function A3P125 A3P060 A3P060 A3P030 A3P030 A3P030 B43 IO08RSB0 GAA1/ GAC0/ GAC0/ IO06RSB0 IO04RSB0 IO04RSB0 None None None Rule 3 Rule 3 Rule 3 B44 IO05RSB0 None None None Rule 6 Rule 6 Rule 6 C1 IO03RSB1 GAA2/ GAA2/ GAA2/ IO02RSB1 IO67RSB1 IO118UDB3 None None None Rule 3 Rule 3 Rule 3 C2 IO00RSB1 IO95RSB1 IO132RSB1 IO116VDB3 None None None None None None C3 None None None Rule 4 Rule 4 Rule 4 GFB1/ GFB1/ GFB1/ IO87RSB1 IO124RSB1 IO109PPB3 None None None Rule 3 Rule 3 Rule 3 GEA0/ GFA0/ GFA0/ GFA0/ IO76RSB1 IO85RSB1 IO122RSB1 IO108NPB3 None None None None None None NC C4 IO78RSB1 C5 GNDQ VCC GNDQ VCC GNDQ VCC C6 NC GFA2/ GFA2/ GFA2/ IO83RSB1 IO120RSB1 IO107PSB3 None None None Rule 1 Rule 1 Rule 1 C7 NC IO80RSB1 IO117RSB1 IO105NPB3 None None None Rule 1 Rule 1 Rule 1 C8 VCCIB1 Rule 5 None Rule 5 Rule 5 Rule 5 Rule 5 None None None Rule 3 Rule 3 Rule 3 None None None Rule 6 Rule 6 Rule 6 GEA2/ GEA2/ GEA2/ IO71RSB1 IO106RSB1 IO97RSB2 None None None Rule 3 Rule 3 Rule 3 C12 IO62RSB1 IO68RSB1 IO103RSB1 IO94RSB2 None None None None None None Rule 5 None Rule 5 Rule 4 Rule 4 Rule 4 C9 IO69RSB1 C10 IO66RSB1 C11 IO65RSB1 VCCIB1 VCCIB1 VCCIB3 GEA1/ GEA1/ GEB1/ IO73RSB1 IO108RSB1 IO99PDB3 GNDQ GNDQ C13 NC VCCIB1 C14 NC NC IO97RSB1 IO88RSB2 None Rule 1 Rule 1 Rule 1 Rule 1 None NC IO93RSB1 IO84RSB2 None Rule 1 Rule 1 None None Rule 1 VCCIB1 IO60RSB1 IO89RSB1 IO80RSB2 None None None Rule 6 Rule 6 Rule 6 C17 IO51RSB1 IO57RSB1 IO83RSB1 IO74RSB2 None None None None None None C18 NC NC VCCIB1 VCCIB2 Rule 5 Rule 4 Rule 4 Rule 4 Rule 4 Rule 4 C19 TCK TCK TCK TCK None None None None None None C20 NC VMV1 VMV1 VMV2 None None None Rule 4 Rule 4 Rule 4 C21 VPUMP VPUMP VPUMP VPUMP None None None None None None C22 VJTAG VJTAG VJTAG VJTAG None None None None None None C15 IO55RSB1 C16 VCCIB1 GNDQ VCCIB2 Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. D pins are corner pins per the package specification. 3. "None" implies that the pins can be connected without any change. 1 3 -1 4 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-5 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with QFN132 Packaging (continued) Pin A3P030 A3P060 A3P125 No. Function Function Function Migration Migration Migration Migration Migration Migration Rule Rule Rule Rule Rule Rule between between between between between between A3P250 A3P125 A3P250 A3P250 A3P125 A3P060 A3P250 and and and and and and Function A3P125 A3P060 A3P060 A3P030 A3P030 A3P030 C23 NC VCCIB0 VCCIB0 VCCIB1 Rule 5 None Rule 5 Rule 4 Rule 4 Rule 4 C24 NC NC NC IO53NSB1 Rule 1 None Rule 1 Rule 1 None None C25 NC NC NC IO51NPB1 Rule 1 None Rule 1 Rule 1 None None GDB0/ GCA1/ GCA1/ GCA1/ IO38RSB0 IO42RSB0 IO55RSB0 IO50PPB1 None None None None None None None None None Rule 1 Rule 1 Rule 1 Rule 5 None Rule 5 Rule 5 Rule 5 None C29 IO32RSB0 IO29RSB0 IO42RSB0 IO42NDB1 None None None None None None C30 IO29RSB0 None None None Rule 6 Rule 6 Rule 6 C26 C27 NC C28 VCCIB0 GCC0/ GCC0/ GCC0/ IO39RSB0 IO52RSB0 IO48NDB1 VCCIB0 GNDQ VCCIB0 GNDQ VCCIB1 GNDQ C31 IO28RSB0 GBA1/ GBA1/ GBA1/ IO27RSB0 IO40RSB0 IO40RSB0 None None None Rule 3 Rule 3 Rule 3 C32 IO25RSB0 GBB0/ GBB0/ GBB0/ IO24RSB0 IO37RSB0 IO37RSB0 None None None Rule 3 Rule 3 Rule 3 VCC None None None Rule 4 Rule 4 Rule 4 IO19RSB0 IO24RSB0 IO24RSB0 None None None Rule 3 Rule 3 Rule 3 VCCIB0 IO16RSB0 IO19RSB0 IO19RSB0 None None None Rule 1 Rule 1 Rule 1 C36 IO17RSB0 IO13RSB0 IO16RSB0 IO16RSB0 None None None None None None C37 IO14RSB0 GAC1/ IO10RSB0 IO10RSB0 IO10RSB0 None Rule 2 Rule 2 None None Rule 3 VCCIB0 Rule 5 Rule 4 Rule 4 Rule 6 Rule 6 Rule 1 C39 IO07RSB0 GAA0/ GAB1/ GAB1/ IO05RSB0 IO03RSB0 IO03RSB0 None None None Rule 3 Rule 3 Rule 3 C40 IO04RSB0 C33 NC C34 NC C35 C38 IO11RSB0 VCC NC VCC VCCIB0 VMV0 VMV0 VMV0 None None None Rule 6 Rule 6 Rule 6 D1 GND GND GND GND None None None None None None D2 GND GND GND GND None None None None None None D3 GND GND GND GND None None None None None None D4 GND GND GND GND None None None None None None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. D pins are corner pins per the package specification. 3. "None" implies that the pins can be connected without any change. v1.0 1 3 - 15 Migrating Designs from A3P250 to Lower-Logic-Density Devices TQ144 Package Table 13-6 * Pin Compatibility and Migration Table for ProASIC3 A3P060 and A3P125 with TQ144 Packaging Migration Rule between A3P125 and A3P060 Pin Number A3P060 Function A3P125 Function 1 GAA2/IO51RSB1 GAA2/IO67RSB1 None 2 IO52RSB1 IO68RSB1 None 3 GAB2/IO53RSB1 GAB2/IO69RSB1 None 4 IO95RSB1 IO132RSB1 None 5 GAC2/IO94RSB1 GAC2/IO131RSB1 None 6 IO93RSB1 IO130RSB1 None 7 IO92RSB1 IO129RSB1 None 8 IO91RSB1 IO128RSB1 None 9 VCC VCC None 10 GND GND None 11 VCCIB1 VCCIB1 None 12 IO90RSB1 IO127RSB1 None 13 GFC1/IO89RSB1 GFC1/IO126RSB1 None 14 GFC0/IO88RSB1 GFC0/IO125RSB1 None 15 GFB1/IO87RSB1 GFB1/IO124RSB1 None 16 GFB0/IO86RSB1 GFB0/IO123RSB1 None 17 VCOMPLF VCOMPLF None 18 GFA0/IO85RSB1 GFA0/IO122RSB1 None 19 VCCPLF VCCPLF None 20 GFA1/IO84RSB1 GFA1/IO121RSB1 None 21 GFA2/IO83RSB1 GFA2/IO120RSB1 None 22 GFB2/IO82RSB1 GFB2/IO119RSB1 None 23 GFC2/IO81RSB1 GFC2/IO118RSB1 None 24 IO80RSB1 IO117RSB1 None 25 IO79RSB1 IO116RSB1 None 26 IO78RSB1 IO115RSB1 None 27 GND GND None 28 VCCIB1 VCCIB1 None 29 GEC1/IO77RSB1 GEC1/IO112RSB1 None 30 GEC0/IO76RSB1 GEC0/IO111RSB1 None 31 GEB1/IO75RSB1 GEB1/IO110RSB1 None 32 GEB0/IO74RSB1 GEB0/IO109RSB1 None 33 GEA1/IO73RSB1 GEA1/IO108RSB1 None 34 GEA0/IO72RSB1 GEA0/IO107RSB1 None 35 VMV1 VMV1 None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. 1 3 -1 6 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-6 * Pin Compatibility and Migration Table for ProASIC3 A3P060 and A3P125 with TQ144 Packaging (continued) A3P060 Function A3P125 Function Migration Rule between A3P125 and A3P060 36 GNDQ GNDQ None 37 NC NC None 38 GEA2/IO71RSB1 GEA2/IO106RSB1 None 39 GEB2/IO70RSB1 GEB2/IO105RSB1 None 40 GEC2/IO69RSB1 GEC2/IO104RSB1 None 41 IO68RSB1 IO103RSB1 None 42 IO67RSB1 IO102RSB1 None 43 IO66RSB1 IO101RSB1 None 44 IO65RSB1 IO100RSB1 None 45 VCC VCC None Pin Number 46 GND GND None 47 VCCIB1 VCCIB1 None 48 NC IO99RSB1 Rule 1 49 IO64RSB1 IO97RSB1 None 50 NC IO95RSB1 Rule 1 51 IO63RSB1 IO93RSB1 None 52 NC IO92RSB1 Rule 1 53 IO62RSB1 IO90RSB1 None 54 NC IO88RSB1 Rule 1 55 IO61RSB1 IO86RSB1 None 56 NC IO84RSB1 Rule 1 57 NC IO83RSB1 Rule 1 58 IO60RSB1 IO82RSB1 None 59 IO59RSB1 IO81RSB1 None 60 IO58RSB1 IO80RSB1 None 61 IO57RSB1 IO79RSB1 None 62 NC VCC Rule 4 63 GND GND None 64 NC VCCIB1 Rule 4 65 GDC2/IO56RSB1 GDC2/IO72RSB1 None 66 GDB2/IO55RSB1 GDB2/IO71RSB1 None 67 GDA2/IO54RSB1 GDA2/IO70RSB1 None 68 GNDQ GNDQ None 69 TCK TCK None 70 TDI TDI None 71 TMS TMS None 72 VMV1 VMV1 None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. v1.0 1 3 - 17 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-6 * Pin Compatibility and Migration Table for ProASIC3 A3P060 and A3P125 with TQ144 Packaging (continued) A3P060 Function A3P125 Function Migration Rule between A3P125 and A3P060 73 VPUMP VPUMP None 74 NC NC None Pin Number 75 TDO TDO None 76 TRST TRST None 77 VJTAG VJTAG None 78 GDA0/IO50RSB0 GDA0/IO66RSB0 None 79 GDB0/IO48RSB0 GDB0/IO64RSB0 None 80 GDB1/IO47RSB0 GDB1/IO63RSB0 None 81 VCCIB0 VCCIB0 None 82 GND GND None 83 IO44RSB0 IO60RSB0 None 84 GCC2/IO43RSB0 GCC2/IO59RSB0 None 85 GCB2/IO42RSB0 GCB2/IO58RSB0 None 86 GCA2/IO41RSB0 GCA2/IO57RSB0 None 87 GCA0/IO40RSB0 GCA0/IO56RSB0 None 88 GCA1/IO39RSB0 GCA1/IO55RSB0 None 89 GCB0/IO38RSB0 GCB0/IO54RSB0 None 90 GCB1/IO37RSB0 GCB1/IO53RSB0 None 91 GCC0/IO36RSB0 GCC0/IO52RSB0 None 92 GCC1/IO35RSB0 GCC1/IO51RSB0 None 93 IO34RSB0 IO50RSB0 None 94 IO33RSB0 IO49RSB0 None 95 NC NC None 96 NC NC None 97 NC NC None 98 VCCIB0 VCCIB0 None 99 GND GND None 100 VCC VCC None 101 IO30RSB0 IO47RSB0 None 102 GBC2/IO29RSB0 GBC2/IO45RSB0 None 103 IO28RSB0 IO44RSB0 None 104 GBB2/IO27RSB0 GBB2/IO43RSB0 None 105 IO26RSB0 IO42RSB0 None 106 GBA2/IO25RSB0 GBA2/IO41RSB0 None 107 VMV0 VMV0 None 108 GNDQ GNDQ None 109 NC GBA1/IO40RSB0 Rule 1 Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. 1 3 -1 8 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-6 * Pin Compatibility and Migration Table for ProASIC3 A3P060 and A3P125 with TQ144 Packaging (continued) A3P060 Function A3P125 Function Migration Rule between A3P125 and A3P060 110 NC GBA0/IO39RSB0 Rule 1 111 GBA1/IO24RSB0 GBB1/IO38RSB0 None 112 GBA0/IO23RSB0 GBB0/IO37RSB0 None 113 GBB1/IO22RSB0 GBC1/IO36RSB0 None 114 GBB0/IO21RSB0 GBC0/IO35RSB0 None 115 GBC1/IO20RSB0 IO34RSB0 Rule 2 116 GBC0/IO19RSB0 IO33RSB0 Rule 2 117 VCCIB0 VCCIB0 None 118 GND GND None 119 VCC VCC None 120 IO18RSB0 IO29RSB0 None 121 IO17RSB0 IO28RSB0 None 122 IO16RSB0 IO27RSB0 None 123 IO15RSB0 IO25RSB0 None 124 IO14RSB0 IO23RSB0 None 125 IO13RSB0 IO21RSB0 None 126 IO12RSB0 IO19RSB0 None 127 IO11RSB0 IO17RSB0 None Pin Number 128 NC IO16RSB0 Rule 1 129 IO10RSB0 IO14RSB0 None 130 IO09RSB0 IO12RSB0 None 131 IO08RSB0 IO10RSB0 None 132 GAC1/IO07RSB0 IO08RSB0 Rule 2 133 GAC0/IO06RSB0 IO06RSB0 Rule 2 134 NC VCCIB0 Rule 4 135 GND GND None 136 NC VCC Rule 4 137 GAB1/IO05RSB0 GAC1/IO05RSB0 None 138 GAB0/IO04RSB0 GAC0/IO04RSB0 None 139 GAA1/IO03RSB0 GAB1/IO03RSB0 None 140 GAA0/IO02RSB0 GAB0/IO02RSB0 None 141 IO01RSB0 GAA1/IO01RSB0 Rule 3 142 IO00RSB0 GAA0/IO00RSB0 Rule 3 143 GNDQ GNDQ None 144 VMV0 VMV0 None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. v1.0 1 3 - 19 Migrating Designs from A3P250 to Lower-Logic-Density Devices PQ208 Package Table 13-7 * Pin Compatibility and Migration Table for ProASIC3 A3P125 and A3P250 with PQ208 Packaging A3P125 Function A3P250 Function Migration Rule between A3P250 and A3P125 1 GND GND None 2 GAA2/IO67RSB1 GAA2/IO118UDB3 None 3 IO68RSB1 IO118VDB3 None 4 GAB2/IO69RSB1 GAB2/IO117UDB3 None 5 IO132RSB1 IO117VDB3 None 6 GAC2/IO131RSB1 GAC2/IO116UDB3 None 7 NC IO116VDB3 Rule 1 8 NC IO115UDB3 Rule 1 9 IO130RSB1 IO115VDB3 None 10 IO129RSB1 IO114UDB3 None 11 NC IO114VDB3 Rule 1 12 IO128RSB1 IO113PDB3 None 13 NC IO113NDB3 Rule 1 14 NC IO112PDB3 Rule 1 15 NC IO112NDB3 Rule 1 16 VCC VCC None 17 GND GND None 18 VCCIB1 VCCIB3 Rule 5 19 IO127RSB1 IO111PDB3 None 20 NC IO111NDB3 Rule 1 21 GFC1/IO126RSB1 GFC1/IO110PDB3 None 22 GFC0/IO125RSB1 GFC0/IO110NDB3 None 23 GFB1/IO124RSB1 GFB1/IO109PDB3 None 24 GFB0/IO123RSB1 GFB0/IO109NDB3 None 25 VCOMPLF VCOMPLF None 26 GFA0/IO122RSB1 GFA0/IO108NPB3 None 27 VCCPLF VCCPLF None 28 GFA1/IO121RSB1 GFA1/IO108PPB3 None 29 GND GND None 30 GFA2/IO120RSB1 GFA2/IO107PDB3 None 31 NC IO107NDB3 Rule 1 32 GFB2/IO119RSB1 GFB2/IO106PDB3 None 33 NC IO106NDB3 Rule 1 Pin Number Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. 1 3 -2 0 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-7 * Pin Compatibility and Migration Table for ProASIC3 A3P125 and A3P250 with PQ208 Packaging (continued) Migration Rule between A3P250 and A3P125 Pin Number A3P125 Function A3P250 Function 34 GFC2/IO118RSB1 GFC2/IO105PDB3 None 35 IO117RSB1 IO105NDB3 None 36 NC NC None 37 IO116RSB1 IO104PDB3 None 38 IO115RSB1 IO104NDB3 None 39 NC IO103PSB3 Rule 1 40 VCCIB1 VCCIB3 Rule 5 41 GND GND None 42 IO114RSB1 IO101PDB3 None 43 IO113RSB1 IO101NDB3 None 44 GEC1/IO112RSB1 GEC1/IO100PDB3 None 45 GEC0/IO111RSB1 GEC0/IO100NDB3 None 46 GEB1/IO110RSB1 GEB1/IO99PDB3 None 47 GEB0/IO109RSB1 GEB0/IO99NDB3 None 48 GEA1/IO108RSB1 GEA1/IO98PDB3 None 49 GEA0/IO107RSB1 GEA0/IO98NDB3 None 50 VMV1 VMV3 Rule 5 51 GNDQ GNDQ None 52 GND GND None 53 NC NC None 54 NC NC None 55 GEA2/IO106RSB1 GEA2/IO97RSB2 None 56 GEB2/IO105RSB1 GEB2/IO96RSB2 None 57 GEC2/IO104RSB1 GEC2/IO95RSB2 None 58 IO103RSB1 IO94RSB2 None 59 IO102RSB1 IO93RSB2 None 60 IO101RSB1 IO92RSB2 None 61 IO100RSB1 IO91RSB2 None 62 VCCIB1 VCCIB2 Rule 5 63 IO99RSB1 IO90RSB2 None 64 IO98RSB1 IO89RSB2 None 65 GND GND None 66 IO97RSB1 IO88RSB2 None 67 IO96RSB1 IO87RSB2 None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. v1.0 1 3 - 21 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-7 * Pin Compatibility and Migration Table for ProASIC3 A3P125 and A3P250 with PQ208 Packaging (continued) A3P125 Function A3P250 Function Migration Rule between A3P250 and A3P125 68 IO95RSB1 IO86RSB2 None 69 IO94RSB1 IO85RSB2 None 70 IO93RSB1 IO84RSB2 None 71 VCC VCC None Pin Number 72 VCCIB1 VCCIB2 Rule 5 73 IO92RSB1 IO83RSB2 None 74 IO91RSB1 IO82RSB2 None 75 IO90RSB1 IO81RSB2 None 76 IO89RSB1 IO80RSB2 None 77 IO88RSB1 IO79RSB2 None 78 IO87RSB1 IO78RSB2 None 79 IO86RSB1 IO77RSB2 None 80 IO85RSB1 IO76RSB2 None 81 GND GND None 82 IO84RSB1 IO75RSB2 None 83 IO83RSB1 IO74RSB2 None 84 IO82RSB1 IO73RSB2 None 85 IO81RSB1 IO72RSB2 None 86 IO80RSB1 IO71RSB2 None 87 IO79RSB1 IO70RSB2 None 88 VCC VCC None 89 VCCIB1 VCCIB2 Rule 5 90 IO78RSB1 IO69RSB2 None 91 IO77RSB1 IO68RSB2 None 92 IO76RSB1 IO67RSB2 None 93 IO75RSB1 IO66RSB2 None 94 IO74RSB1 IO65RSB2 None 95 IO73RSB1 IO64RSB2 None 96 GDC2/IO72RSB1 GDC2/IO63RSB2 None 97 GND GND None 98 GDB2/IO71RSB1 GDB2/IO62RSB2 None 99 GDA2/IO70RSB1 GDA2/IO61RSB2 None 100 GNDQ GNDQ None 101 TCK TCK None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. 1 3 -2 2 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-7 * Pin Compatibility and Migration Table for ProASIC3 A3P125 and A3P250 with PQ208 Packaging (continued) Pin Number A3P125 Function A3P250 Function Migration Rule between A3P250 and A3P125 102 TDI TDI None 103 TMS TMS None 104 VMV1 VMV2 Rule 5 105 GND GND None 106 VPUMP VPUMP None 107 NC NC None 108 TDO TDO None 109 TRST TRST None 110 VJTAG VJTAG None 111 GDA0/IO66RSB0 GDA0/IO60VDB1 None 112 GDA1/IO65RSB0 GDA1/IO60UDB1 None 113 GDB0/IO64RSB0 GDB0/IO59VDB1 None 114 GDB1/IO63RSB0 GDB1/IO59UDB1 None 115 GDC0/IO62RSB0 GDC0/IO58VDB1 None 116 GDC1/IO61RSB0 GDC1/IO58UDB1 None 117 NC IO57VDB1 Rule 1 118 NC IO57UDB1 Rule 1 119 NC IO56NDB1 Rule 1 120 NC IO56PDB1 Rule 1 121 NC IO55RSB1 Rule 1 122 GND GND None 123 VCCIB0 VCCIB1 Rule 5 124 NC NC None 125 NC NC None 126 VCC VCC None 127 IO60RSB0 IO53NDB1 None 128 GCC2/IO59RSB0 GCC2/IO53PDB1 None 129 GCB2/IO58RSB0 GCB2/IO52PSB1 None 130 GND GND None 131 GCA2/IO57RSB0 GCA2/IO51PSB1 None 132 GCA0/IO56RSB0 GCA1/IO50PDB1 None 133 GCA1/IO55RSB0 GCA0/IO50NDB1 None 134 GCB0/IO54RSB0 GCB0/IO49NDB1 None 135 GCB1/IO53RSB0 GCB1/IO49PDB1 None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. v1.0 1 3 - 23 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-7 * Pin Compatibility and Migration Table for ProASIC3 A3P125 and A3P250 with PQ208 Packaging (continued) A3P125 Function A3P250 Function Migration Rule between A3P250 and A3P125 136 GCC0/IO52RSB0 GCC0/IO48NDB1 None 137 GCC1/IO51RSB0 GCC1/IO48PDB1 None 138 IO50RSB0 IO47NDB1 None 139 IO49RSB0 IO47PDB1 None 140 VCCIB0 VCCIB1 Rule 5 141 GND GND None 142 VCC VCC None Pin Number 143 IO48RSB0 IO46RSB1 None 144 IO47RSB0 IO45NDB1 None 145 IO46RSB0 IO45PDB1 None 146 NC IO44NDB1 Rule 1 147 NC IO44PDB1 Rule 1 148 NC IO43NDB1 Rule 1 149 GBC2/IO45RSB0 GBC2/IO43PDB1 None 150 IO44RSB0 IO42NDB1 None 151 GBB2/IO43RSB0 GBB2/IO42PDB1 None 152 IO42RSB0 IO41NDB1 None 153 GBA2/IO41RSB0 GBA2/IO41PDB1 None 154 VMV0 VMV1 Rule 5 155 GNDQ GNDQ None 156 GND GND None 157 NC NC None 158 GBA1/IO40RSB0 GBA1/IO40RSB0 None 159 GBA0/IO39RSB0 GBA0/IO39RSB0 None 160 GBB1/IO38RSB0 GBB1/IO38RSB0 None 161 GBB0/IO37RSB0 GBB0/IO37RSB0 None 162 GND GND None 163 GBC1/IO36RSB0 GBC1/IO36RSB0 None 164 GBC0/IO35RSB0 GBC0/IO35RSB0 None 165 IO34RSB0 IO34RSB0 None 166 IO33RSB0 IO33RSB0 None 167 IO32RSB0 IO32RSB0 None 168 IO31RSB0 IO31RSB0 None 169 IO30RSB0 IO30RSB0 None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. 1 3 -2 4 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-7 * Pin Compatibility and Migration Table for ProASIC3 A3P125 and A3P250 with PQ208 Packaging (continued) A3P125 Function A3P250 Function Migration Rule between A3P250 and A3P125 170 VCCIB0 VCCIB0 None 171 VCC VCC None 172 IO29RSB0 IO29RSB0 None 173 IO28RSB0 IO28RSB0 None 174 IO27RSB0 IO27RSB0 None 175 IO26RSB0 IO26RSB0 None 176 IO25RSB0 IO25RSB0 None 177 IO24RSB0 IO24RSB0 None 178 GND GND None 179 IO23RSB0 IO23RSB0 None 180 IO22RSB0 IO22RSB0 None 181 IO21RSB0 IO21RSB0 None 182 IO20RSB0 IO20RSB0 None 183 IO19RSB0 IO19RSB0 None 184 IO18RSB0 IO18RSB0 None 185 IO17RSB0 IO17RSB0 None 186 VCCIB0 VCCIB0 None 187 VCC VCC None 188 IO16RSB0 IO16RSB0 None 189 IO15RSB0 IO15RSB0 None 190 IO14RSB0 IO14RSB0 None 191 IO13RSB0 IO13RSB0 None 192 IO12RSB0 IO12RSB0 None 193 IO11RSB0 IO11RSB0 None 194 IO10RSB0 IO10RSB0 None Pin Number 195 GND GND None 196 IO09RSB0 IO09RSB0 None 197 IO08RSB0 IO08RSB0 None 198 IO07RSB0 IO07RSB0 None 199 IO06RSB0 IO06RSB0 None 200 VCCIB0 VCCIB0 None 201 GAC1/IO05RSB0 GAC1/IO05RSB0 None 202 GAC0/IO04RSB0 GAC0/IO04RSB0 None 203 GAB1/IO03RSB0 GAB1/IO03RSB0 None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. v1.0 1 3 - 25 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-7 * Pin Compatibility and Migration Table for ProASIC3 A3P125 and A3P250 with PQ208 Packaging (continued) Pin Number A3P125 Function A3P250 Function Migration Rule between A3P250 and A3P125 204 GAB0/IO02RSB0 GAB0/IO02RSB0 None 205 GAA1/IO01RSB0 GAA1/IO01RSB0 None 206 GAA0/IO00RSB0 GAA0/IO00RSB0 None 207 GNDQ GNDQ None 208 VMV0 VMV0 None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. 1 3 -2 6 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices FG144 Package Table 13-8 * Pin Compatibility and Migration Table for ProASIC3 A3P060, A3P125, and A3P250 with FG144 Packaging Pin No. A3P060 Function A3P125 Function A3P250 Function Migration Migration Migration Rule between Rule between Rule between A3P125 and A3P250 and A3P250 and A3P060 A3P060 A3P125 A1 GNDQ GNDQ GNDQ None None None A2 VMV0 VMV0 VMV0 None None None A3 GAB0/IO04RSB0 GAB0/IO02RSB0 GAB0/IO02RSB0 None None None A4 GAB1/IO05RSB0 GAB1/IO03RSB0 GAB1/IO03RSB0 None None None A5 IO08RSB0 IO11RSB0 IO16RSB0 None None None A6 GND GND GND None None None A7 IO11RSB0 IO18RSB0 IO29RSB0 None None None A8 VCC VCC VCC None None None A9 IO16RSB0 IO25RSB0 IO33RSB0 None None None A10 GBA0/IO23RSB0 GBA0/IO39RSB0 GBA0/IO39RSB0 None None None A11 GBA1/IO24RSB0 GBA1/IO40RSB0 GBA1/IO40RSB0 None None None A12 GNDQ GNDQ GNDQ None None None B1 GAB2/IO53RSB1 GAB2/IO69RSB1 GAB2/IO117UDB3 None None None B2 GND GND GND None None None B3 GAA0/IO02RSB0 GAA0/IO00RSB0 GAA0/IO00RSB0 None None None B4 GAA1/IO03RSB0 GAA1/IO01RSB0 GAA1/IO01RSB0 None Rule 6 Rule 6 B5 IO00RSB0 IO08RSB0 IO14RSB0 None None None B6 IO10RSB0 IO14RSB0 IO19RSB0 None None None B7 IO12RSB0 IO19RSB0 IO22RSB0 None None None B8 IO14RSB0 IO22RSB0 IO30RSB0 None None None B9 GBB0/IO21RSB0 GBB0/IO37RSB0 GBB0/IO37RSB0 None None None B10 GBB1/IO22RSB0 GBB1/IO38RSB0 GBB1/IO38RSB0 None None None B11 GND GND GND None None None B12 VMV0 VMV0 VMV1 None None None C1 IO95RSB1 IO132RSB1 IO117VDB3 None None None C2 GFA2/IO83RSB1 GFA2/IO120RSB1 GFA2/IO107PPB3 None None None C3 GAC2/IO94RSB1 GAC2/IO131RSB1 GAC2/IO116UDB3 None None None C4 VCC VCC VCC None None None C5 IO01RSB0 IO10RSB0 IO12RSB0 None None None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. v1.0 1 3 - 27 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-8 * Pin Compatibility and Migration Table for ProASIC3 A3P060, A3P125, and A3P250 with FG144 Packaging (continued) Pin No. A3P060 Function A3P125 Function A3P250 Function Migration Migration Migration Rule between Rule between Rule between A3P125 and A3P250 and A3P250 and A3P060 A3P060 A3P125 C6 IO09RSB0 IO12RSB0 IO17RSB0 None None None C7 IO13RSB0 IO21RSB0 IO24RSB0 None None None C8 IO15RSB0 IO24RSB0 IO31RSB0 None None None C9 IO17RSB0 IO27RSB0 IO34RSB0 None None None C10 GBA2/IO25RSB0 GBA2/IO41RSB0 GBA2/IO41PDB1 None None None C11 IO26RSB0 IO42RSB0 IO41NDB1 None None None C12 GBC2/IO29RSB0 GBC2/IO45RSB0 GBC2/IO43PPB1 None None None D1 IO91RSB1 IO128RSB1 IO112NDB3 None None None D2 IO92RSB1 IO129RSB1 IO112PDB3 None None None D3 IO93RSB1 IO130RSB1 IO116VDB3 None None None D4 GAA2/IO51RSB1 GAA2/IO67RSB1 GAA2/IO118UPB3 None None None D5 GAC0/IO06RSB0 GAC0/IO04RSB0 GAC0/IO04RSB0 None None None D6 GAC1/IO07RSB0 GAC1/IO05RSB0 GAC1/IO05RSB0 None None None D7 GBC0/IO19RSB0 GBC0/IO35RSB0 GBC0/IO35RSB0 None None None D8 GBC1/IO20RSB0 GBC1/IO36RSB0 GBC1/IO36RSB0 None None None D9 GBB2/IO27RSB0 GBB2/IO43RSB0 GBB2/IO42PDB1 None None None D10 IO18RSB0 IO28RSB0 IO42NDB1 None None None D11 IO28RSB0 IO44RSB0 IO43NPB1 None None None D12 GCB1/IO37RSB0 GCB1/IO53RSB0 GCB1/IO49PPB1 None None None E1 VCC VCC VCC None None None E2 GFC0/IO88RSB1 GFC0/IO125RSB1 GFC0/IO110NDB3 None None None E3 GFC1/IO89RSB1 GFC1/IO126RSB1 GFC1/IO110PDB3 None None None E4 VCCIB1 VCCIB1 VCCIB3 None Rule 5 Rule 5 E5 IO52RSB1 IO68RSB1 IO118VPB3 None None None E6 VCCIB0 VCCIB0 VCCIB0 None None None E7 VCCIB0 VCCIB0 VCCIB0 None None None E8 GCC1/IO35RSB0 GCC1/IO51RSB0 GCC1/IO48PDB1 None None None E9 VCCIB0 VCCIB0 VCCIB1 None Rule 5 Rule 5 E10 VCC VCC VCC None None None E11 GCA0/IO40RSB0 GCA0/IO56RSB0 GCA0/IO50NDB1 None None None E12 IO30RSB0 IO46RSB0 IO51NDB1 None None None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. 1 3 -2 8 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-8 * Pin Compatibility and Migration Table for ProASIC3 A3P060, A3P125, and A3P250 with FG144 Packaging (continued) Pin No. A3P060 Function A3P125 Function A3P250 Function Migration Migration Migration Rule between Rule between Rule between A3P125 and A3P250 and A3P250 and A3P060 A3P060 A3P125 F1 GFB0/IO86RSB1 GFB0/IO123RSB1 GFB0/IO109NPB3 None None None F2 VCOMPLF VCOMPLF VCOMPLF None None None F3 GFB1/IO87RSB1 GFB1/IO124RSB1 GFB1/IO109PPB3 None None None F4 IO90RSB1 IO127RSB1 IO107NPB3 None None None F5 GND GND GND None None None F6 GND GND GND None None None F7 GND GND GND None None None F8 GCC0/IO36RSB0 GCC0/IO52RSB0 GCC0/IO48NDB1 None None None F9 GCB0/IO38RSB0 GCB0/IO54RSB0 GCB0/IO49NPB1 None None None F10 GND GND GND None None None F11 GCA1/IO39RSB0 GCA1/IO55RSB0 GCA1/IO50PDB1 None None None F12 GCA2/IO41RSB0 GCA2/IO57RSB0 GCA2/IO51PDB1 None None None G1 GFA1/IO84RSB1 GFA1/IO121RSB1 GFA1/IO108PPB3 None None None G2 GND GND GND None None None G3 VCCPLF VCCPLF VCCPLF None None None G4 GFA0/IO85RSB1 GFA0/IO122RSB1 GFA0/IO108NPB3 None None None G5 GND GND GND None None None G6 GND GND GND None None None G7 GND GND GND None None None G8 GDC1/IO45RSB0 GDC1/IO61RSB0 GDC1/IO58UPB1 None None None G9 IO32RSB0 IO48RSB0 IO53NDB1 None None None G10 GCC2/IO43RSB0 GCC2/IO59RSB0 GCC2/IO53PDB1 None None None G11 IO31RSB0 IO47RSB0 IO52NDB1 None None None G12 GCB2/IO42RSB0 GCB2/IO58RSB0 GCB2/IO52PDB1 None None None H1 VCC VCC VCC None None None H2 GFB2/IO82RSB1 GFB2/IO119RSB1 GFB2/IO106PDB3 None None None H3 GFC2/IO81RSB1 GFC2/IO118RSB1 GFC2/IO105PSB3 None None None H4 GEC1/IO77RSB1 GEC1/IO112RSB1 GEC1/IO100PDB3 None None None H5 VCC VCC VCC None None None H6 IO34RSB0 IO50RSB0 IO79RSB2 None None None H7 IO44RSB0 IO60RSB0 IO65RSB2 None None None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. v1.0 1 3 - 29 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-8 * Pin Compatibility and Migration Table for ProASIC3 A3P060, A3P125, and A3P250 with FG144 Packaging (continued) Migration Migration Migration Rule between Rule between Rule between A3P125 and A3P250 and A3P250 and A3P060 A3P060 A3P125 Pin No. A3P060 Function A3P125 Function A3P250 Function H8 GDB2/IO55RSB1 GDB2/IO71RSB1 GDB2/IO62RSB2 None None None H9 GDC0/IO46RSB0 GDC0/IO62RSB0 GDC0/IO58VPB1 None None None H10 VCCIB0 VCCIB0 VCCIB1 None Rule 5 Rule 5 H11 IO33RSB0 IO49RSB0 IO54PSB1 None None None H12 VCC VCC VCC None None None J1 GEB1/IO75RSB1 GEB1/IO110RSB1 GEB1/IO99PDB3 None None None J2 IO78RSB1 IO115RSB1 IO106NDB3 None None None J3 VCCIB1 VCCIB1 VCCIB3 None Rule 5 Rule 5 J4 GEC0/IO76RSB1 GEC0/IO111RSB1 GEC0/IO100NDB3 None None None J5 IO79RSB1 IO116RSB1 IO88RSB2 None None None J6 IO80RSB1 IO117RSB1 IO81RSB2 None None None J7 VCC VCC VCC None None None J8 TCK TCK TCK None None None J9 GDA2/IO54RSB1 GDA2/IO70RSB1 GDA2/IO61RSB2 None None None J10 TDO TDO TDO None None None J11 GDA1/IO49RSB0 GDA1/IO65RSB0 GDA1/IO60UDB1 None None None J12 GDB1/IO47RSB0 GDB1/IO63RSB0 GDB1/IO59UDB1 None None None K1 GEB0/IO74RSB1 GEB0/IO109RSB1 GEB0/IO99NDB3 None None None K2 GEA1/IO73RSB1 GEA1/IO108RSB1 GEA1/IO98PDB3 None None None K3 GEA0/IO72RSB1 GEA0/IO107RSB1 GEA0/IO98NDB3 None None None K4 GEA2/IO71RSB1 GEA2/IO106RSB1 GEA2/IO97RSB2 None None None K5 IO65RSB1 IO100RSB1 IO90RSB2 None None None K6 IO64RSB1 IO98RSB1 IO84RSB2 None None None K7 GND GND GND None None None K8 IO57RSB1 IO73RSB1 IO66RSB2 None None None K9 GDC2/IO56RSB1 GDC2/IO72RSB1 GDC2/IO63RSB2 None None None K10 GND GND GND None None None K11 GDA0/IO50RSB0 GDA0/IO66RSB0 GDA0/IO60VDB1 None None None K12 GDB0/IO48RSB0 GDB0/IO64RSB0 GDB0/IO59VDB1 None None None L1 GND GND GND None None None L2 VMV1 VMV1 VMV3 None Rule 5 Rule 5 Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. 1 3 -3 0 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices Table 13-8 * Pin Compatibility and Migration Table for ProASIC3 A3P060, A3P125, and A3P250 with FG144 Packaging (continued) Pin No. A3P060 Function A3P125 Function A3P250 Function Migration Migration Migration Rule between Rule between Rule between A3P125 and A3P250 and A3P250 and A3P060 A3P060 A3P125 L3 GEB2/IO70RSB1 GEB2/IO105RSB1 GEB2/IO96RSB2 None None None L4 IO67RSB1 IO102RSB1 IO91RSB2 None None None L5 VCCIB1 VCCIB1 VCCIB2 None Rule 5 Rule 5 L6 IO62RSB1 IO95RSB1 IO82RSB2 None None None L7 IO59RSB1 IO85RSB1 IO80RSB2 None None None L8 IO58RSB1 IO74RSB1 IO72RSB2 None None None L9 TMS TMS TMS None None None L10 VJTAG VJTAG VJTAG None None None L11 VMV1 VMV1 VMV2 None Rule 5 Rule 5 L12 TRST TRST TRST None None None M1 GNDQ GNDQ GNDQ None None None M2 GEC2/IO69RSB1 GEC2/IO104RSB1 GEC2/IO95RSB2 None None None M3 IO68RSB1 IO103RSB1 IO92RSB2 None None None M4 IO66RSB1 IO101RSB1 IO89RSB2 None None None M5 IO63RSB1 IO97RSB1 IO87RSB2 None None None M6 IO61RSB1 IO94RSB1 IO85RSB2 None None None M7 IO60RSB1 IO86RSB1 IO78RSB2 None None None M8 NC IO75RSB1 IO76RSB2 Rule 1 Rule 1 None M9 TDI TDI TDI None None None M10 VCCIB1 VCCIB1 VCCIB2 None Rule 5 Rule 5 M11 VPUMP VPUMP VPUMP None None None M12 GNDQ GNDQ GNDQ None None None Notes: 1. See Table 13-3 on page 13-3 for the high-density/low-density pin combination guidelines. 2. "None" implies that the pins can be connected without any change. v1.0 1 3 - 31 Migrating Designs from A3P250 to Lower-Logic-Density Devices Conclusion This application note describes the design migration among ProASIC3 family devices with an emphasis on package pin compatibility. Devices in the ProASIC3 family share numerous common architectural features. However, not all architectural features of family members are identical; use the datasheet to identify differences. Additionally, a key requirement is running functional simulation before and after the migration using Actel tools. Actel will continue to update this application note with additional packages. Related Documents Handbook Documents I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/IGLOO_PA3_IO_HBs.pdf Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content. Part Number 51700094-018-0 Revised January 2008 1 3 -3 2 v1.0 Migrating Designs from A3P250 to Lower-Logic-Density Devices List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version 51900135-2/12.06 51900135-1/12.06 51900135-0/5.06 Changes in Current Version (v1.0) Page In Table 13-1 * Device Information, A3P250 device information was updated. 13-1 In Table 13-2 * Common and Convertible I/Os, I/O counts for the VQ100 package were updated. 13-2 In Table 13-4 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with VQ100 Packaging, the A3P030 pin function information was updated. Several rules changed throughout the table. 13-5 Table 13-1 * Device Information was updated to include A3P030 device information. 13-1 Table 13-2 * Common and Convertible I/Os was updated. 13-2 The "Migration and Implementation Methodologies" section was updated. 13-2 Table 13-3 * Migration Rules from Higher-Density Device to Lower-Density Device was updated. 13-3 In Table 13-4 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with VQ100 Packaging, the A3P030 pin information was updated. Several rules changed throughout the table. 13-5 In Table 13-5 * Pin Compatibility and Migration Table for A3P030, A3P060, A3P125, and A3P250 with QFN132 Packaging, all pin data was updated. Several rules changed throughout the table. 13-10 In Table 13-7 * Pin Compatibility and Migration Table for ProASIC3 A3P125 and A3P250 with PQ208 Packaging, the rules were updated for the following pins: 50, 104, and 154. 13-20 In Table 13-8 * Pin Compatibility and Migration Table for ProASIC3 A3P060, A3P125, and A3P250 with FG144 Packaging, the rules were updated for the following pins: L2 and L11. 13-27 QN132 information was added to Table 13-1 * Device Information. 13-1 QN132 information was added to Table 13-2 * Common and Convertible I/Os. 13-2 Table 13-6 * Pin Compatibility and Migration Table for ProASIC3 A3P060 and A3P125 with TQ144 Packaging is new. 13-16 v1.0 1 3 - 33 Migrating Designs from A3P250 to Lower-Logic-Density Devices v1.0 1 3 - 35 Migrating Designs from A3P250 to Lower-Logic-Density Devices 1 3 -3 6 v1.0 Programming and Security Application Note AC315 14 - Programming Flash Devices Introduction This document provides an overview of the various programming options available for the Actel flash families. The electronic version of this document includes active links to all programming resources, which are available at http://www.actel.com/products/hardware/default.aspx. For Actel antifuse devices, refer to the Programming Antifuse Devices document. Summary of Programming Support FlashPro3 is a high-performance in-system programming (ISP) tool targeted at the latest generation of low-power flash devices offered by Actel: IGLOO,(R) Fusion, and ProASIC(R)3, including ARM(R)-enabled devices. FlashPro3 offers extremely high performance through the use of USB 2.0 and is high-speed compliant for full use of the 480 Mbps bandwidth. This newest programmer can program ProASIC3E devices in under 30 seconds; even the largest ProASIC3E devices take under two minutes to program. Powered exclusively via USB, FlashPro3 provides a VPUMP voltage of 3.3 V for programming these devices. Silicon Sculptor 3 is an easy-to-use, single-site programming tool for Actel FPGAs that delivers high data throughput and promotes ease of use while lowering the overall cost of ownership. Silicon Sculptor 3 includes a high-speed USB 2.0 interface that allows a customer to connect as many as 12 programmers to a single PC. Furthermore, Silicon Sculptor 3 is compatible with adapter modules from Silicon Sculptor II, thereby preserving a customer's investment and enabling a seamless upgrade to this latest generation of the tool. For details of programmer support for each device, refer to Table 14-5 on page 14-8. General Flash Programming Information Programming Basics When choosing a programming solution, there are a number of options available. This section provides a brief overview of those options. The next sections provide more detail on those options as they apply to Actel FPGAs. Reprogrammable or One-Time-Programmable (OTP) Depending on the technology chosen, devices may be reprogrammable or one-timeprogrammable. As the name implies, a reprogrammable device can be programmed many times. Generally, the contents of such a device will be completely overwritten when it is reprogrammed. All Actel flash devices are reprogrammable. An OTP device is programmable one time only. Once programmed, no more changes can be made to the contents. Actel flash devices provide the option of disabling the reprogrammability for security purposes. This combines the convenience of reprogrammability during design verification with the security of an OTP technology for highly sensitive designs. Device Programmer or In-System Programming There are two fundamental ways to program an FPGA: using a device programmer or, if the technology permits, using in-system programming. A device programmer is a piece of equipment in a lab or on the production floor that is used for programming devices. The devices are placed into a socket mounted in a programming adapter module, and the appropriate electrical interface is applied. The device can then be placed on the board. A typical programmer, used during v1.1 1 4 -1 Programming Flash Devices development, programs a single device at a time and is referred to as a single-site engineering programmer. With ISP, the device is already mounted onto the board when programming occurs, most typically via the JTAG pins. The JTAG pins can be controlled either by an on-board resource, such as a microprocessor, or by an off-board programmer through a header connection. Once mounted, it can be programmed repeatedly. If the application requires it, the system can be designed to reprogram itself using a microprocessor, without the use of any external programmer. For production, high-volume multi-site production programmers handle designs that require device programmers. In addition, Actel can preprogram devices for production, negating the need for further programming. This service is referred to as in-house programming (IHP). Live at Power-Up (LAPU) or Boot PROM Utilizing the technology of the FPGA significantly impacts board-level power-up considerations. Some technologies are nonvolatile and are considered functional, or "live," as soon as power reaches the operational level. All Actel FPGA technologies are live at power-up. By contrast, SRAM technology is volatile, and devices built using SRAM cells lose their contents when power cycling occurs. These devices must be reprogrammed every time power is applied. Such a design must include nonvolatile storage for the contents as well as the means to reprogram. There is a delay before SRAM devices are functional; other parts of the board must come alive first to reprogram these types of FPGAs. Therefore, such devices can never be part of critical boot circuits. Design Security Design security is a growing concern for systems designers. The choice of programming methodology and technology affects system security. Use of Actel programming technology is the most secure option available, providing much better protection than SRAM-based devices and ASICs. Actel provides a number of ways to ensure designs are protected. General information on design security can be found on the Actel website: http://www.actel.com/products/solutions/security/default.aspx Programming Features for Actel Devices Actel provides two types of FPGAs: flash and antifuse (Table 14-1). Some programming methods are common to both and some are exclusive to flash. This document describes only the programming solutions supported for flash devices. Table 14-1 * Programming Features for Actel Devices Feature Flash Antifuse Reprogrammable Yes No In-system programmable Yes No One-time programmable Yes (option) Yes Live at power-up Yes Yes Secure Yes Yes Single-site programmer support Yes Yes Multi-site programmer support Yes Yes In-house programming support Yes Yes Flash Devices The flash devices supplied by Actel are reprogrammable by either a generic device programmer or ISP. Actel supports ISP using JTAG, which is supported by the FlashPro3, FlashPro, FlashPro Lite, and Sculptor programmers. Levels of ISP support vary depending on the device chosen: 1 4 -2 * Fusion, ProASIC3, and ProASIC3E devices support ISP. * ProASIC3L devices operate using a 1.2 V core voltage and support ISP at 1.5 V only. Voltage switching is required in-system to switch from a 1.2 V core to 1.5 V core for programming. v1.1 Programming Flash Devices * IGLOO, IGLOO PLUS, and IGLOOe V5 devices can be programmed in-system when the device is using a 1.5 V supply voltage to the FPGA core. * IGLOO, IGLOO PLUS, and IGLOOe V2 devices can operate using either 1.2 V core voltage or 1.5 V core voltage. Although the device can operate at 1.2 V core voltage, the device can only be reprogrammed when the core voltage is 1.5 V. Voltage switching is required insystem to switch from a 1.2 V supply (VCC, VCCI, and VJTAG) to 1.5 V for programming. Since flash devices are nonvolatile, they are live at power-up. This is different from an SRAM-based device, which loads its programming information when it is powered up. SRAM devices require a time on the order of hundreds of milliseconds before the system is active. There are multiple levels of security available in flash devices. Use of a security key will lock the device. The device can then only be reprogrammed by first unlocking the device with the appropriate security key. It can also be locked permanently, which means there is no key that can access the device. The command to secure the device is embedded within the programming file, optionally enabled by the programming software. This is also referred to as the OTP version of flash, allowing for only a single programming instance. This is discussed in more detail in the Implementation of Security in Actel's ProASIC and ProASICPLUS Flash-Based FPGAs application note. For ProASIC3/E devices, refer to Security in Low-Power Flash Devices Flash devices can also be programmed using single-site or multi-site programmers as well as volume-programming services from Actel or other vendors. Types of Programming for Flash Devices The number of devices to be programmed will influence the optimal programming methodology. Those available are listed below: * * * In-system programming - Using a programmer - Using a microprocessor or microcontroller Device programmers - Single-site programmers - Multi-site programmers, batch programmers, or gang programmers - Automated production (robotic) programmers Volume programming services - Actel in-house programming - Programming centers In-System Programming Device Type Supported: Flash ISP refers to programming the FPGA after it has been mounted on the system board. The FPGA may be preprogrammed and later reprogrammed using ISP. The advantage of using ISP is the ability to update the FPGA design many times without any changes to the board. This eliminates the requirement of using a socket for the FPGA, saving cost and improving reliability. It also reduces programming hardware expenses, as the ISP methodology is die-/package-independent. There are two methods of in-system programming: external and internal. * Programmer ISP--Refer to In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 for more information. Using an external programmer and a cable, the device can be programmed through a header on the system board. In Actel documentation, this is referred to as external ISP. Actel provides FlashPro3, FlashPro Lite, FlashPro, or Silicon Sculptor 3 to perform external ISP. Note that Silicon Sculptor 3 can only provide ISP for ProASIC and ProASICPLUS(R) families, not for ProASIC3 or ProASIC3E. v1.1 1 4 -3 Programming Flash Devices * - Advantages: Allows local control of programming and data files for maximum security. The programming algorithms and hardware are available from Actel. The only hardware required on the board is a programming header. - Limitations: A negligible board space requirement for the programming header and JTAG signal routing Microprocessor ISP--Refer to MicroProcessor Programming of Actel's Low-Power Flash Devices for more information. Using a microprocessor and an external or internal memory, you can store the program in memory and use the microprocessor to perform the programming. In Actel documentation, this is referred to as internal ISP. Both the code for the programming algorithm and the FPGA programming file must be stored in memory on the board. Programming voltages must also be generated on the board. - Advantages: The programming code is stored in the system memory. An external programmer is not required during programming. - Limitations: This is the approach that requires the most design work, since some way of getting and/or storing the data is needed; a system interface to the device must be designed; and the low-level API to the programming firmware must be written and linked into the code provided by Actel. While there are benefits to this methodology, serious thought and planning should go into the decision. Device Programmers Device Type Supported: Flash and Antifuse Device programmers are used to program a device before it is mounted on the system board. The advantage of using device programmers is that no programming hardware is required on the system board. Therefore, no additional components or board space are required. If devices are to be reprogrammed multiple times, or if the quantity of devices to be programmed is relatively low, a single-site device programmer is the simplest solution. For applications in which design security is paramount (often the case in military or space designs), the use of on-site programing maintains design security at all times. Adapter modules are purchased with the programmers to support the FPGA packages used. The FPGA is placed in the adapter module and the programming software is run from a PC. Actel supplies the programming software for all of the Actel programmers. The software allows for the selection of the correct die/package and programming files. It will then program and verify the device. * Single-site programmers A single-site programmer programs one device at a time. Actel offers Silicon Sculptor 3 as a single-site programmer. * - Advantages: Lower cost than multi-site programmers. No additional overhead for programming on the system board. Allows local control of programming and data files for maximum security. Allows on-demand programming on-site. - Limitations: Only programs one device at a time. Multi-site programmers Often referred to as batch or gang programmers, multi-site programmers can program multiple devices at the same time using the same programming file. This is often used for large volume programming and by programming houses. The sites often have independent processors and memory enabling the sites to operate concurrently, meaning each site may start programming the same file independently. This enables the operator to change one device while the other sites continue programming, which increases throughput. Multiple adapter modules for the same package are required when using a multi-site programmer. Silicon Sculptor I, II, and 3 programmers can be cascaded to program multiple devices in a chain. Multi-site programmers can also be purchased from BP Microsystems. - 1 4 -4 Advantages: Provides the capability of programming multiple devices at the same time. No additional overhead for programming on the system board. Allows local control of programming and data files for maximum security. v1.1 Programming Flash Devices - * Limitations: More expensive than a single-site programmer Automated production (robotic) programmers Automated production programmers are based on multi-site programmers. They consist of a large input tray holding multiple parts and a robotic arm to select and place parts into appropriate programming sockets automatically. When the programming of the parts is complete, the parts are removed and placed in a finished tray. The automated programmers are often used in volume programming houses to program parts for which the programming time is small. Volume Programming Services Device Type Supported: Flash and Antifuse Once the design is stable for applications with large production volumes, preprogrammed devices can be purchased. Table 14-2 describes the volume programming services. Table 14-2 * Volume Programming Services Programmer Vendor In-House Programming Distributor Programming Centers Independent Programming Centers Availability Actel Contact Actel Sales Memec Unique Contact Distribution Various Contact Vendor Advantages: As programming is outsourced, this solution is easier to implement than creating a substantial in-house programming capability. As programming houses specialize in large-volume programming, this is often the most cost-effective solution. Limitations: There are some logistical issues with the use of a programming service provider, such as the transfer of programming files and the approval of first articles. By definition, the programming file must be released to a third-party programming house. Nondisclosure agreements (NDAs) can be signed to help ensure data protection; however, for extremely security-conscious designs, this may not be an option. * Actel In-House Programming When purchasing Actel devices in volume, IHP can be requested as part of the purchase. If this option is chosen, there is a small cost adder for each device programmed. Each device is marked with a special mark to distinguish it from blank parts. Programming files for the design will be sent to Actel. Sample parts with the design programmed, First Articles, will be returned for customer approval. Once approval of First Articles has been received, Actel will proceed with programming the remainder of the order. To request Actel IHP, contact your local Actel representative. * Distributor Programming Centers If purchases are made through a distributor, many distributors will provide programming for their customers. Consult with your preferred distributor about this option. * Independent Programming Centers There are many programming centers that specialize only in programming but are not directly affiliated with Actel or our distributors. These programming centers must follow the guidelines for programming Actel devices and use certified programmers to program Actel devices. Actel does not have recommendations for external programming centers. v1.1 1 4 -5 Programming Flash Devices Programming Solutions Details for the available programmers can be found in the programmer user's guides listed in the "Related Documents" section on page 14-12. Refer to Table 14-3 on page 14-6 for more information concerning programming solutions. All of the programmers except the FlashPro3, FlashPro Lite, and FlashPro require adapter modules, which are designed to support device packages. The modules are all listed on the Actel website at http://www.actel.com/products/hardware/program_debug/ss/modules.aspx. They are not listed in this document, since this list is updated frequently with new package options and any upgrades required to improve programming yield or support new families. Table 14-3 * Programming Solutions Programmer Vendor FlashPro3 ISP Actel FlashPro Lite Only Actel Only Single Device Multi-Device Availability Yes 1 Yes Available Yes Yes1 Available Available FlashPro Actel Only Yes Yes1 Silicon Sculptor 3 Actel Yes Yes Cascade option (up to two) Available Cascade option (up to two) Available Silicon Sculptor II Actel Yes Yes2 Silicon Sculptor Actel Yes Yes Cascade option (up to four) Discontinued Sculptor 6X Actel No Yes Yes Discontinued BP Microsystems No Yes Yes Contact BP Microsystems at www.bpmicro.com BP MicroProgrammers Notes: 1. Multiple devices can be connected in the same JTAG chain for programming. 2. Silicon Sculptor II can only provide ISP for ProASIC and ProASICPLUS families, not for ProASIC3/E. Programmer Ordering Codes The products shown in Table 14-4 can be ordered through Actel sales and will be shipped directly from Actel. Products can also be ordered from Actel distributors, but will still be shipped directly from Actel. Table 14-4 includes ordering codes for the full kit, as well as codes for replacement items and any related hardware. Some additional products can be purchased from external suppliers for use with the programmers. Ordering codes for adapter modules used with Silicon Sculptor are available on the Actel website at http://www.actel.com/products/hardware/program_debug/ss/modules.aspx. Table 14-4 * Programming Ordering Codes Description Vendor Ordering Code FlashPro3 ISP programmer Actel FLASHPRO 3 Comment FlashPro Lite ISP programmer Actel FLASHPRO LITE Supports small programming header or large header through header converter (not included) FlashPro ISP programmer Actel FLASH PRO Supports small programming header or large header through header converter (not included) Silicon Sculptor 3 Actel SILICON-SCULPTOR 3 USB 2.0 high-speed production programmer Silicon Sculptor II Actel SILICON-SCULPTOR II Requires add-on adapter modules to support devices Silicon Sculptor ISP module Actel SMPA-ISP-ACTEL-3-KIT Uses a 2x5, RA male header connector Ships with both large and small header support * A maximum of two Silicon Sculptor II programmers can be chained together using a standard IEEE 1284 parallel port cable. 1 4 -6 v1.1 Programming Flash Devices Table 14-4 * Programming Ordering Codes (continued) Vendor Ordering Code Comment Concurrent programming cable Description Actel SS-EXPANDER Used to cascade Silicon Sculptor I programmers together* Software for Silicon Sculptor Actel ISP cable for small header Actel ISP-CABLE-S Supplied with SMPA-ISP-ACTEL-3-KIT ISP cable for large header Actel PA-ISP-CABLE Supplied with SMPA-ISP-ACTEL-3-KIT Header converter Actel Header-Converter Converts from small to large header FTSH-113-01-L-D-K Supported by FlashPro, FlashPro Lite, and Silicon Sculptor Small programming Samtec header SCULPTOR-SOFTWARE-CD http://www.actel.com/download/program_debug/ss/ In migrating to ProASIC3/E devices, an FP3-26PINADAPTER is required. 10-pin 0.1" pitch cable header (rightangle PCB mount angle) AMP 103310-1 Supported by FlashPro3 10-pin 0.1" pitch cable header (straight PCB mount angle) 3M 2510-6002UB Supported by FlashPro3 Compact Samtec programming header (10-pin 0.05" pitch, 2 rows of 5 pins) Migration compact adapter Supported by FlashPro3, FP3-26PIN-ADAPTER required. Used for boards where space is at a premium. Actel FP3-26PIN-ADAPTER Large programming header 0.062" board thickness 3M 3429-6502 Supported by Silicon Sculptor by default, FlashPro, and FlashPro Lite, with header converter Large programming header 0.094" to 0.125" board thickness 3M 3429-6503 Supported by Silicon Sculptor by default, FlashPro, and FlashPro Lite, with header converter Actel SMPA-ISP-HEADER-S Required for small header for ProASIC only; not used for ProASICPLUS Plug-in header Actel SMPA-ISP-HEADER Required for large header for ProASIC only; not used for ProASICPLUS Vacuum pens for PQ, TQ, VQ; <208 pins Actel PENVAC Vacuum pens for PQ, TQ, VQ; 208 pins Actel PENVAC-HD Plug-in small and header FTSH-105-01-L-D-K header Required with the use of FTSH-105-01-L-D-K Heavy-duty, provides stronger vacuum * A maximum of two Silicon Sculptor II programmers can be chained together using a standard IEEE 1284 parallel port cable. v1.1 1 4 -7 Programming Flash Devices Programmer Device Support Refer to Table 14-5 to determine which general-purpose flash devices have programmer device support. To learn more about the different Actel families, refer to the Actel website: http://www.actel.com/products/devices.aspx. Data in Table 14-5 also applies to ARM-enabled M7 device versions of Fusion, IGLOO, and ProASIC3 devices. Refer to the appropriate family datasheets for information on die/package combinations available as ARM-enabled versions. Table 14-5 * Programmer Device Support Actel Family Fusion Device Silicon Silicon Silicon ARM- Silicon Sculptor Sculptor Sculptor FlashPro Enabled Sculptor 6X II 3 FlashPro Lite FlashPro3 AFS090 No No IGLOO AFS1500 AGL015 Yes. No No Yes. ISP support No No Yes. ISP support. No No Yes. ISP support No No Yes. ISP support No No Yes. No ISP No ISP support. support. AFS250 AFS600 Yes. No No Yes. Yes. No ISP No ISP support. support. AGL030 AGL060 AGL125 AGL250 AGL600 AGL1000 IGLOO PLUS AGLP030 No No AGLP125 IGLOOe ProASIC3L ProASIC3 Yes. Yes. No ISP No ISP support support. AGLP060 AGLE600 AGLE3000 A3P250L A3P600L A3P1000L A3PE3000L A3P015 No No Yes. Yes. No ISP No ISP support. support. No No Yes. Yes. No ISP No ISP support. support. No No Yes. Yes. ISP support. No No Yes. ISP support. No No Yes. ISP support. No ISP No ISP support. support. A3P030 A3P060 A3P125 ProASIC3E A3P250 A3P400 A3P600 A3P1000 A3PE600 A3PE1500 A3PE3000 No No Yes. Yes. No ISP No ISP support. support. * Refer to the "Certified Programming Solutions" section on page 14-9 for more information on programmer support. 1 4 -8 v1.1 Programming Flash Devices Table 14-5 * Programmer Device Support (continued) Actel Family Device ProASIC PLUS Silicon Silicon Silicon ARM- Silicon Sculptor Sculptor Sculptor FlashPro Enabled Sculptor 6X II 3 FlashPro Lite FlashPro3 APA075 APA150 APA300 Yes. Yes. Yes. Yes. Yes. Yes. ISP ISP ISP ISP ISP ISP support. support. support. support. support. support. No APA450 APA600 APA750 APA1000 ProASIC A500K50 Yes Yes Yes Yes Yes No No A500K130 A500K180 A500K270 * Refer to the "Certified Programming Solutions" section on page 14-9 for more information on programmer support. Certified Programming Solutions The Actel-certified programmers for flash devices are FlashPro3, FlashPro Lite, FlashPro, Silicon Sculptor I and II, and any programmer that is built by BP Microsystems. All other programmers are considered noncertified programmers. * FlashPro3, FlashPro Lite, FlashPro The Actel family of FlashPro device programmers provides in-system programming in an easy-to-use, compact system that supports all ProASIC families. Whether programming a board containing a single device or multiple devices connected in a chain, the Actel line of FlashPro programmers enables fast programming and reprogramming. Programming with the FlashPro series of programmers saves board space and money as it eliminates the need for sockets on the board. There are no built-in algorithms, so there is no delay between product release and programming support. * Silicon Sculptor II Silicon Sculptor II is a robust, compact, single-device programmer with standalone software for the PC. It is designed to enable concurrent programming of multiple units from the same PC with speeds equivalent to or faster than previous Actel programmers. It replaces Silicon Sculptor I as the Actel programmer of choice. * Silicon Sculptor I and Silicon Sculptor 6X Actel no longer offers Silicon Sculptor I or Silicon Sculptor 6X for sale. Both items have been discontinued. Actel does support Silicon Sculptor I and Silicon Sculptor 6X by continuing to release new software that enables improved programming of previously covered Actel devices; new Actel devices are only supported on Silicon Sculptor II. All software support for Silicon Sculptor I and Silicon Sculptor 6X programmers will be disconnected by the end of 2005; no support for these older programmers will be offered in 2006. Actel recommends that all customers upgrade to Silicon Sculptor II or a BP multi-site programmer. * Noncertified Programmers Actel does not test programming solutions from other vendors, and CANNOT guarantee programming yield. Also, Actel will not perform any failure analysis on devices programmed by hardware from other vendors. * Programming Centers Actel programming hardware policy also applies to programming centers. Actel expects all programming centers to use certified programmers to program Actel devices. If a programming center uses noncertified programmers to program Actel devices, the "Noncertified Programmers" policy applies. v1.1 1 4 -9 Programming Flash Devices Flash Programming Guidelines Preprogramming Setup Before programming, several steps are required to ensure an optimal programming yield. Use Proper Handling and Electrostatic Discharge (ESD) Precautions Actel FPGAs are sensitive electronic devices that are susceptible to damage from ESD and other types of mishandling. For more information about ESD, refer to the Actel Quality and Reliability Guide, beginning with page 41. Use the Latest Version of the Designer Software to Generate Your Programming File (recommended) The files used to program Actel flash devices (*.bit, *.stp) contain important information about the switches that will be programmed in the FPGA. Find the latest version and corresponding release notes at http://www.actel.com/download/software/designer/. Also, programming files must always be zipped during file transfer to avoid the possibility of file corruption. Use the Latest Version of the Programming Software The programming software is frequently updated to accommodate yield enhancements in FPGA manufacturing. These updates ensure maximum programming yield and minimum programming times. Before programming, always check the version of software being used to ensure it is the most recent. Depending on the programming software, refer to one of the following: * FlashPro: http://www.actel.com/download/program_debug/flashpro/ * Silicon Sculptor: http://www.actel.com/download/program_debug/ss/ Use the Most Recent Adapter Module with Silicon Sculptor Occasionally, Actel makes modifications to the adapter modules to improve programming yields and programming times. To identify the latest version of each module before programming, visit http://www.actel.com/products/hardware/program_debug/ss/modules.aspx. Perform Routine Hardware Self-Diagnostic Test * FlashPro The self-test is only applicable when programming with FlashPro and FlashPro3 programmers. It is not supported with FlashPro Lite. To run the self-diagnostic test, follow the instructions given in the "Performing a Self-Test" section of http://www.actel.com/documents/FlashPro_UG.pdf. * Silicon Sculptor The self-diagnostic test verifies correct operation of the pin drivers, power supply, CPU, memory, and adapter module. This test should be performed before every programming session. At minimum, the test must be executed every week. To perform self-diagnostic testing using the Silicon Sculptor software, perform the following steps, depending on the operating system: - DOS: From anywhere in the software, type ALT + D. - Windows: Click Device > choose Actel Diagnostic > select the Test tab > click OK. Programming Flash FPGAs Programming a flash device is a one-step process, whether programming is conducted with a socket adapter module or via ISP. The Execute function will automatically erase the device, program the flash cells, and verify that it is programmed correctly. Actel recommends confirming the security status is correct before programming. The following steps are required to program Actel flash FPGAs. 1 4 -1 0 v1.1 Programming Flash Devices Programming with FlashPro Setup Properly connect the FlashPro ribbon cable with the programming header and turn on the switch. Actel recommends running the self-test before programming any devices; see the "Perform Routine Hardware Self-Diagnostic Test" section on page 14-10. In the programming software, from the File menu, choose Connect. In the FlashPro Connect to Programmer dialog box that appears, select the port to which the FlashPro programmer is connected, and select the device family. Disable voltages from the programmer if they are available on the board. Click Connect. A successful connect or any errors appear in the Log window. Analyze Chain and Device Selection From the File menu, choose Analyze Chain. Chain details appear in the Log window. If any failures appear, refer to the error and troubleshooting section of the FlashPro User's Guide. Select the device to be programmed from the Device list. If only one device is present in the chain, performing Analyze Chain selects that device automatically from the Device list. Loading the STAPL file FlashPro3, FlashPro Lite, and FlashPro programmers use a STAPL (*.stp) file to program the device. To load the STAPL file, from the File menu, choose Open STAPL file, or click the Open File button in the toolbar. Selecting an Action After loading the STAPL file, select an action from the Action list. See the "Programming File Actions" section in the FlashPro User's Guide for a definition of each action. Programming the Device To program the device, in the Action list, select Program. Make the required selections and click Execute to start programming. The progress of the programming action displays in the Log window. The message "Exit 0" indicates that the device has successfully been programmed. Note: Do not interrupt the programming sequence; it may damage the device or programmer. Verify Correct Programming To verify the device is programmed with the correct STAPL file, load the STAPL file and in the Action list and click Verify. Click Execute to start the verification process. A successful verification results in "Exit 0." Note: Verification is also performed in the previous "Programming the Device" step; clicking Verify is an additional standalone option. Programming Failure Allowances Flash FPGAs are reprogrammable, so Actel tests the programmability for 100% of the devices shipped. Return Material Authorization (RMA) Policies Actel consistently strives to exceed customer expectations by continuing to improve the quality of our products and our quality management system. Actel has RMA procedures in place to address programming fallout. Customers should be mindful of the following RMA policies. All devices submitted for an RMA, must be within the Actel warranty period of one year from date of shipment. Actel will reject RMAs for devices that are no longer under warranty. RMAs will only be authorized for current Actel devices. Devices that have been discontinued will not receive RMAs. All functional failure analysis requests must be initiated by opening a case with Actel Technical Support. Devices returned for failure analysis against an RMA should be in their original packaging and must have an RMA number issued by Actel. v1.1 1 4 - 11 Programming Flash Devices Contacting the Customer Support Group Highly skilled engineers staff the Customer Applications Center from 7:00 A.M. to 6:00 P.M., Pacific time, Monday through Friday. You can contact the center by one of the following methods: Electronic Mail You can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. Actel monitors the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and contact information for efficient processing of your request. The technical support email address is tech@actel.com. Telephone Our Technical Support Hotline answers all calls. The center retrieves information, such as your name, company name, telephone number, and question. Once this is done, a case number is assigned. Then the center forwards the information to a queue where the first available applications engineer receives the data and returns your call. The phone hours are from 7:00 A.M. to 6:00 P.M., Pacific time, Monday through Friday. The Customer Applications Center number is (800) 262-1060. European customers can call +44 (0) 1256 305 600. Related Documents Below is a list of related documents, their location on the Actel website, and a brief summary of each document. Application Notes Programming Antifuse Devices http://www.actel.com/documents/AntifuseProgram_AN.pdf Implementation of Security in Actel's ProASIC and ProASICPLUS Flash-Based FPGAs http://www.actel.com/documents/Flash_Security_AN.pdf Handbook Documents Security in Low-Power Flash Devices http://www.actel.com/documents/LPD_Security_HBs.pdf In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 http://www.actel.com/documents/LPD_ISP_HBs.pdf MicroProcessor Programming of Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_Microprocessor_HBs.pdf User's Guides FlashPro Programmers FlashPro3, FlashPro Lite, and FlashPro http://www.actel.com/products/hardware/program_debug/flashpro/default.aspx FlashPro User's Guide http://www.actel.com/documents/FlashPro_UG.pdf The FlashPro User's Guide includes hardware and software setup, self-test instructions, use instructions, and a troubleshooting / error message guide. 1 4 -1 2 v1.1 Programming Flash Devices Silicon Sculptor 3 and Silicon Sculptor II http://www.actel.com/products/hardware/program_debug/ss/default.aspx Other Documents http://www.actel.com/products/solutions/security/default.aspx#flashlock The security resource center describes security in Actel Flash FPGAs. Actel Quality and Reliability Guide http://www.actel.com/documents/RelGuide.pdf Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content. Part Number 51700094-013-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) Changes in Current Version (v1.1) Page The "Flash Devices" section was updated to include the IGLOO PLUS family. The text, "Voltage switching is required in-system to switch from a 1.2 V core to 1.5 V core for programming" was revised to state, "Although the device can operate at 1.2 V core voltage, the device can only be reprogrammed when the core voltage is 1.5 V. Voltage switching is required in-system to switch from a 1.2 V supply (VCC, VCCI, and VJTAG) to 1.5 V for programming." 14-2 The ProASIC3L family was added to Table 14-5 * Programmer Device Support as a separate set of rows rather than combined with ProASIC3 and ProASIC3E devices. The IGLOO PLUS family was included, and AGL015 and A3P015 were added. 14-8 v1.1 1 4 - 13 Security in Low-Power Flash Devices 15 - Security in Low-Power Flash Devices Security in Programmable Logic The need for security on FPGA programmable logic devices (PLDs) has never been greater than today. If the contents of the FPGA can be read by an external source, the intellectual property (IP) of the system is vulnerable to unauthorized copying. Actel IGLOO,(R) Fusion, and ProASIC(R)3 devices contain state-of-the-art circuitry to make the flash-based devices secure during and after programming. Low-power flash devices have a built-in 128-bit Advanced Encryption Standard (AES) decryption core (except for 15 k and 30 k gate devices). The decryption core facilitates secure insystem programming (ISP) of the FPGA core array fabric, the FlashROM, and the Flash Memory Blocks (FBs) in Fusion devices. The FlashROM, Flash Blocks, and FPGA core fabric can be programmed independently of each other, allowing the FlashROM or Flash Blocks to be updated without the need for change to the FPGA core fabric. Actel has incorporated the AES decryption core into the low-power flash devices and has also included the Actel flash-based lock technology, FlashLock.(R) Together, they provide leading-edge security in a programmable logic device. Configuration data loaded into a device can be decrypted prior to being written to the FPGA core using the AES 128-bit block cipher standard. The AES encryption key is stored in on-chip, nonvolatile flash memory. This document outlines the security features offered in low-power flash devices, some applications and uses, as well as the different software settings for each application. Figure 15-1 * Overview on Security v1.1 1 5 -1 Security in Low-Power Flash Devices Security Support in Low-Power Devices The low-power flash families listed in Table 15-1 support the security feature and the functions described in this document. The family name links to the datasheet for each family. Any required timing details are linked from the Timing Numbers column to the relevant datasheet sections. Table 15-1 * Low-Power Flash Families Family1 IGLOO Timing Numbers2 Description Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*FreezeTM IGLOO DC and Switching technology Characteristics IGLOO PLUS Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO PLUS DC and Switching technology and enhanced I/O capabilities Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional IGLOOe DC and Switching PLLs, and additional I/O standards Characteristics ProASIC3L Low-power, high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and Switching technology Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, ProASIC3E DC and Switching and additional I/O standards Characteristics ProASIC3 DC and Switching Characteristics ProASIC3 Low-power, high-performance FPGAs qualified for automotive Automotive ProASIC3 DC and Automotive applications Switching Characteristics Fusion Low-power mixed-signal Programmable System Chip (PSC) Fusion DC and Power Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 15-1) provide a selection of low-power, secure, live-atpower-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. The Actel Fusion(R) family, based on the highly successful ProASIC3 flash FPGA architecture, has been designed as a high-performance, mixed-signal Programmable System Chip. Fusion supports many peripherals, including embedded flash memory, analog-to-digital converter (ADC), high-drive outputs, RC and crystal oscillators, and real-time counter (RTC). The total available on-chip memory, including the flash array blocks, is greater than that found in SRAM FPGAs. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 15-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 15-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 1 5 -2 v1.1 Security in Low-Power Flash Devices Security Architecture IGLOO, Fusion, and ProASIC3 devices have been designed with the most comprehensive programming logic design security in the industry. In the architecture of these devices, security has been designed into the very fabric. The flash cells are located beneath seven metal layers, and the use of many device design and layout techniques makes invasive attacks difficult. Since device layers cannot be removed without disturbing the charge on the programmed (or erased) flash gates, devices cannot be easily deconstructed to decode the design. Low-power flash devices are unique in being reprogrammable and having inherent resistance to both invasive and noninvasive attacks on valuable IP. Secure, remote ISP is now possible with AES encryption capability for the programming file during electronic transfer. Figure 15-2 shows a view of the AES decryption core inside an IGLOO device; Figure 15-3 on page 15-4 shows the AES decryption core inside a Fusion device. The AES core is used to decrypt the encrypted programming file when programming. Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 2 Note: ISP AES Decryption is not supported by 15 k and 30 k gate devices. For details of other architecture features by device, refer to the appropriate family datasheet. Figure 15-2 * Block Representation of the AES Decryption Core in IGLOO and ProASIC3 Devices v1.1 1 5 -3 Security in Low-Power Flash Devices Bank 0 Bank 1 CCC SRAM Block 4,608-Bit Dual-Port SRAM or FIFO Block OSC I/Os CCC/PLL Bank 2 Bank 4 VersaTile ISP AES Decryption User Nonvolatile FlashROM Flash Memory Blocks Analog Quad Analog Quad Analog Quad Analog Quad ADC Analog Quad Analog Quad Charge Pumps SRAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Flash Memory Blocks Analog Quad Analog Quad Analog Quad Analog Quad CCC Bank 3 Figure 15-3 * Block Representation of the AES Decryption Core in a Fusion AFS600 FPGA Security Features IGLOO and ProASIC3 devices have two entities inside: FlashROM and the FPGA core fabric. Fusion devices contain three entities: FlashROM, FBs, and the FPGA core fabric. The parts can be programmed or updated independently with a STAPL programming file. The programming files can be AES-encrypted or plaintext. This allows maximum flexibility in providing security to the entire device. Refer to FlashROM in Actel's Low-Power Flash Devices for information on the FlashROM structure. Unlike SRAM-based FPGA devices, which require a separate boot PROM to store programming data, low-power flash devices are nonvolatile, and the secured configuration data is stored in onchip flash cells that are part of the FPGA fabric. Once programmed, this data is an inherent part of the FPGA array and does not need to be loaded at system power-up. SRAM-based FPGAs load the configuration bitstream upon power-up; therefore, the configuration is exposed and can be read easily. The built-in FPGA core, FB, and FlashROM support programming files encrypted with the 128-bit AES (FIPS-192) block ciphers. The AES key is stored in dedicated, on-chip flash memory and can be programmed before the device is shipped to other parties (allowing secure remote field updates). Security in ARM-Enabled Low-Power Flash Devices There are slight differences between the regular flash devices and the ARM(R)-enabled flash devices, which have the M1 and M7 prefix. The AES key is used by Actel and preprogrammed into the device to protect the ARM IP. As a result, the design is encrypted along with the ARM IP, according to the details below. 1 5 -4 v1.1 Security in Low-Power Flash Devices CoreMP7 Device Security ARM7 (M7-enabled) devices are shipped with the following security features: * FPGA array enabled for AES-encrypted programming and verification * FlashROM enabled for plaintext Read and Write Cortex-M1 Device Security Cortex-M1-enabled devices are shipped with the following security features: * FPGA array enabled for AES-encrypted programming and verification * FlashROM enabled for AES-encrypted Write and Verify * Fusion Embedded Flash Memory enabled for AES-encrypted Write AES Encryption of Programming Files Low-power flash devices employ AES as part of the security mechanism that prevents invasive and noninvasive attacks. The mechanism entails encrypting the programming file with AES encryption and then passing the programming file through the AES decryption core, which is embedded in the device. The file is decrypted there, and the device is successfully programmed. The AES master key is stored in on-chip nonvolatile memory (flash). The AES master key can be preloaded into parts in a secure programming environment (such as the Actel In-House Programming center), and then "blank" parts can be shipped to an untrusted programming or manufacturing center for final personalization with an AES-encrypted bitstream. Late-stage product changes or personalization can be implemented easily and securely by simply sending a STAPL file with AES-encrypted data. Secure remote field updates over public networks (such as the Internet) are possible by sending and programming a STAPL file with AES-encrypted data. The AES key protects the programming data for file transfer into the device, with 128-bit AES encryption. If AES encryption is used, the AES key is stored or preprogrammed into the device. To program, you must use an AES-encrypted file, and the encryption used on the file must match the encryption key already in the device. The AES key is protected by a FlashLock security Pass Key that is also implemented in each device. The AES key is always protected by the FlashLock Key, and the AES-encrypted file does NOT contain the FlashLock Key. This FlashLock Pass Key technology is exclusive to the Actel flash-based device families. FlashLock Pass Key technology can also be implemented without the AES encryption option, providing a choice of different security levels. In essence, security features can be categorized into the following three options: * AES encryption with FlashLock Pass Key protection * FlashLock protection only (no AES encryption) * No protection Each of the above options is explained in more detail in the following sections with application examples and software implementation options. Advanced Encryption Standard The 128-bit AES standard (FIPS-192) block cipher is the NIST (National Institute of Standards and Technology) replacement for DES (Data Encryption Standard FIPS46-2). AES has been designed to protect sensitive government information well into the 21st century. It replaces the aging DES, which NIST adopted in 1977 as a Federal Information Processing Standard used by federal agencies to protect sensitive, unclassified information. The 128-bit AES standard has 3.4 x 1038 possible 128-bit key variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit AES cipher text using exhaustive techniques. Keys are stored (securely) in low-power flash devices in nonvolatile flash memory. All programming files sent to the device can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. All programming verification is performed on-chip, ensuring that the contents of low-power flash devices remain secure. Actel has implemented the 128-bit AES (Rijndael) algorithm in low-power flash devices. With this key size, there are approximately 3.4 x 1038 possible 128-bit keys. DES has a 56-bit key size, which provides approximately 7.2 x 1016 possible keys. In their AES fact sheet, the National Institute of v1.1 1 5 -5 Security in Low-Power Flash Devices Standards and Technology uses the following hypothetical example to illustrate the theoretical security provided by AES. If one were to assume that a computing system existed that could recover a DES key in a second, it would take that same machine approximately 149 trillion years to crack a 128-bit AES key. NIST continues to make their point by stating the universe is believed to be less than 20 billion years old.1 The AES key is securely stored on-chip in dedicated low-power flash device flash memory and cannot be read out. In the first step, the AES key is generated and programmed into the device (for example, at a secure or trusted programming site). The Actel Designer software tool provides AES key generation capability. After the key has been programmed into the device, the device will only correctly decrypt programming files that have been encrypted with the same key. If the individual programming file content is incorrect, a Message Authentication Control (MAC) mechanism inside the device will fail in authenticating the programming file. In other words, when an encrypted programming file is being loaded into a device that has a different programmed AES key, the MAC will prevent this incorrect data from being loaded, preventing possible device damage. See Figure 15-3 on page 15-4 and Figure 15-4 on page 15-7 for graphical representations of this process. It is important to note that the user decides what level of protection will be implemented for the device. When AES protection is desired, the FlashLock Pass Key must be set. The AES key is a content protection mechanism, whereas the FlashLock Pass Key is a device protection mechanism. When the AES key is programmed into the device, the device still needs the Pass Key to protect the FPGA and FlashROM contents and the security settings, including the AES key. Using the FlashLock Pass Key prevents modification of the design contents by means of simply programming the device with a different AES key. AES Decryption and MAC Authentication Low-power flash devices have a built-in 128-bit AES decryption core, which decrypts the encrypted programming file and performs a MAC check that authenticates the file prior to programming. MAC authenticates the entire programming data stream. After AES decryption, the MAC checks the data to make sure it is valid programming data for the device. This can be done while the device is still operating. If the MAC validates the file, the device will be erased and programmed. If the MAC fails to validate, then the device will continue to operate uninterrupted. This will ensure the following: 1. 1 5 -6 * Correct decryption of the encrypted programming file * Prevention of erroneous or corrupted data being programmed during the programming file transfer * Correct bitstream passed to the device for decryption National Institute of Standards and Technology, "ADVANCED ENCRYPTION STANDARD (AES) Questions and Answers," 28 January 2002, <http://csrc.nist.gov/CryptoToolkit/aes/aesfact.html> (10 January 2005). v1.1 Security in Low-Power Flash Devices IGLOO and ProASIC3 MAC Validation Actel Designer Software Decrypted Bitstream Programming File Generation with AES Encryption AES Key AES DecryptionCore FlashROM FPGA Core Transmit Medium / Public Network Encrypted Bistream Figure 15-4 * Example Application Scenario Using AES in IGLOO and ProASIC3 Devices Fusion MAC Validation Actel Designer Software Programming File Generation with AES Encryption Decrypted Bitstream AES Key AES DecryptionCore FlashROM FPGA Core FBs Transmit Medium / Public Network Encrypted Bistream Figure 15-5 * Example Application Scenario Using AES in Fusion Devices FlashLock Additional Options for IGLOO and ProASIC3 Devices The user also has the option of prohibiting Write operations to the FPGA array but allowing Verify operations on the FPGA array and/or Read operations on the FlashROM without the use of the FlashLock Pass Key. This option provides the user the freedom of verifying the FPGA array and/or reading the FlashROM contents after the device is programmed, without having to provide the FlashLock Pass Key. The user can incorporate AES encryption on the programming files to better enhance the level of security used. v1.1 1 5 -7 Security in Low-Power Flash Devices Permanent Security Setting Options In applications where a permanent lock is not desired, yet the security settings should not be modifiable, IGLOO and ProASIC3 devices can accommodate this requirement. This application is particularly useful in cases where a device is located at a remote location and must be reprogrammed with a design or data update. Refer to the "Application 3: Nontrusted Environment--Field Updates/Upgrades" section on page 15-10 for further discussion and examples of how this can be achieved. The user must be careful when considering the Permanent FlashLock or Permanent Security Settings option. Once the design is programmed with the permanent settings, it is not possible to reconfigure the security settings already employed on the device. Therefore, exercise careful consideration before programming permanent settings. Permanent FlashLock The purpose of the permanent lock feature is to provide the benefits of the highest level of security to IGLOO and ProASIC3 devices. If selected, the permanent FlashLock feature will create a permanent barrier, preventing any access to the contents of the device. This is achieved by permanently disabling Write and Verify access to the array, and Write and Read access to the FlashROM. After permanently locking the device, it has been effectively rendered one-timeprogrammable. This feature is useful if the intended applications do not require design or system updates to the device. 1 5 -8 v1.1 Security in Low-Power Flash Devices Security in Action This section illustrates some applications of the security advantages of Actel's devices (Figure 15-6). Plaintext Source File AES Encryption Cipher Text Source File Application 3 Application 2 Application 1 Public Domain AES Decryption Core FlashROM FPGA Core Flash Blocks Flash Device Note: Flash blocks are only used in Fusion devices. Figure 15-6 * Security Options Application 1: Trusted Environment As illustrated in Figure 15-7 on page 15-10, this application allows the programming of devices at design locations where research and development take place. Therefore, encryption is not necessary and is optional to the user. This is often a secure way to protect the design, since the design program files are not sent elsewhere. In situations where production programming is not available at the design location, programming centers (such as Actel In-House Programming) provide a way of programming designs at an alternative, secure, and trusted location. In this scenario, the user generates a STAPL programming file from the Designer software in plaintext format, containing information on the entire design or the portion of the design to be programmed. The user can choose to employ the FlashLock Pass Key feature with the design. Once the design is programmed to unprogrammed devices, the design is protected by this FlashLock Pass Key. If no future programming is needed, the user can consider permanently securing the IGLOO and ProASIC3 device, as discussed in the "Permanent FlashLock" section on page 15-8. Application 2: Nontrusted Environment--Unsecured Location Often, programming of devices is not performed in the same location as actual design implementation, to reduce manufacturing cost. Overseas programming centers and contract manufacturers are examples of this scenario. To achieve security in this case, the AES key and the FlashLock Pass Key can be initially programmed in-house (trusted environment). This is done by generating a programming file with only the security settings and no design contents. The design FPGA core, FlashROM, and (for Fusion) FB contents are generated in a separate programming file. This programming file must be set with the same AES key that was used to program to the device previously so the device will correctly decrypt this encrypted programming file. As a result, the encrypted design content programming file can v1.1 1 5 -9 Security in Low-Power Flash Devices be safely sent off-site to nontrusted programming locations for design programming. Figure 15-7 shows a more detailed flow for this application. OEM Trusted Environment Generates and Programs Security Settings Only (programming of the security keys) Generates Design Contents Encrypted with AES Flash Device Security Settings* Security Settings FPGA/FlashROM/FBs FPGA/FlashROM/FBs Flash Device AES and/or Pass Key Protected Programming File Sends File(s) to Manufacturer Ships Devices to Manufacturer Returns Programmed Devices to Vendor Ships Programmed Devices to End Customer Security Settings Programs Design Contents to Devices FPGA/FlashROM/FBs Contents Flash Device OEM Customers Nontrusted Manufacturing Environment Notes: 1. Programmed portion indicated with dark gray. 2. Programming of FBs applies to Fusion only Figure 15-7 * Application 2: Device Programming in a Nontrusted Environment Application 3: Nontrusted Environment--Field Updates/Upgrades Programming or reprogramming of devices may occur at remote locations. Reconfiguration of devices in consumer products/equipment through public networks is one example. Typically, the remote system is already programmed with particular design contents. When design update (FPGA array contents update) and/or data upgrade (FlashROM and/or FB contents upgrade) is necessary, an updated programming file with AES encryption can be generated, sent across public networks, and transmitted to the remote system. Reprogramming can then be done using this AES-encrypted programming file, providing easy and secure field upgrades. Low-power flash devices support this secure ISP using AES. The detailed flow for this application is shown in Figure 15-8 on page 15-11. Refer to Microprocessor Programming of Actel's Low-Power Flash Devices for more information. To prepare devices for this scenario, the user can initially generate a programming file with the available security setting options. This programming file is programmed into the devices before shipment. During the programming file generation step, the user has the option of making the security settings permanent or not. In situations where no changes to the security settings are necessary, the user can select this feature in the software to generate the programming file with permanent security settings. Actel recommends that the programming file use encryption with an AES key, especially when ISP is done via public domain. For example, if the designer wants to use an AES key for the FPGA array and the FlashROM, Permanent needs to be chosen for this setting. At first, the user would do this by choosing the options to use an AES key for the FPGA array and the FlashROM, and then choosing Permanently lock the security settings. A unique AES key would be chosen. Once this programming file is 1 5 -1 0 v1.1 Security in Low-Power Flash Devices generated and programmed to the devices, the AES key is permanently stored in the on-chip memory, where it is secured safely. The devices would be sent to distant locations for the intended application. When an update is needed, a new programming file must be generated. The programming file must use the same AES key for encryption; otherwise, the authentication will fail and the file will not get programmed in the device. Trusted Environment OEM Generates Updated Design Contents Encrypted with AES AES Encrypted Programming File Transmits to Remote System Update/Upgrade Flash Device Original Design Contents AES Encrypted and FlashLock Pass Key Protected Remote Environment / System Figure 15-8 * Application 3: Nontrusted Environment--Field Updates/Upgrades FlashROM Security Use Models Each of the subsequent sections describes in detail the available selections in Actel Designer as an aid to understanding security applications and generating appropriate programming files for those applications. Before proceeding, it is helpful to review Figure 15-7 on page 15-10, which gives a general overview of the programming file generation flow within the Designer software as well as what occurs during the device programming stage. Specific settings are discussed in the following sections. In Figure 15-7 on page 15-10, the flow consists of two sub-flows. Sub-flow 1 describes programming security settings to the device only, and sub-flow 2 describes programming the design contents only. In Application 1, described in the "Application 1: Trusted Environment" section on page 15-9, the user does not need to generate separate files but can generate one programming file containing both security settings and design contents. Then programming of the security settings and design contents is done in one step. Both sub-flow 1 and sub-flow 2 are used. In Application 2, described in the "Application 2: Nontrusted Environment--Unsecured Location" section on page 15-9, the trusted site should follow sub-flows 1 and 2 separately to generate two separate programming files. The programming file from sub-flow 1 will be used at the trusted site to program the device(s) first. The programming file from sub-flow 2 will be sent off-site for production programming. v1.1 1 5 - 11 Security in Low-Power Flash Devices In Application 3, described in the "Application 3: Nontrusted Environment--Field Updates/Upgrades" section on page 15-10, typically only sub-flow 2 will be used because only updates to the design content portion are needed and no security settings need to be changed. In the event that update of the security settings is necessary, see the "Reprogramming Devices" section on page 15-21 for details. For more information on programming low-power flash devices, refer to In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 User 1 Designer Software Program Security Settings Programming Software User Assigns Desired Security Settings To FPGA/FlashROM/FB/All: - AES Key and FlashLock Pass Key - FlashLock Pass Key Only Software Generates Programming File with Desired Security Settings: - Encrypted with AES and Protected with FlashLock Pass Key - Protected with FlashLock Pass Key Only Device Previously Programmed? No Software Programs Selected Security Settings into Device Yes Yes Software Performs Comparison of FlashLock Pass Key between Programming File and Device Does FlashLock Pass Key Match? No Returns Error 2 Program Design Contents Programming Previously Secured Device(s)? No Software Generates Programming File with Desired Design Contents (FPGA Array, FlashROM, FB, or All) Yes AES Key Used Previously? No User Must Reassign Exact FlashLock Pass Key Previously Programmed into the Device Design Content Programmed into Device Yes Software Performs Comparison of FlashLock Pass Key between Programming File and Device Does FlashLock Pass Key Match? No Yes Returns Error User Must Reassign Exact AES Key Previously Programmed into the Device Software Generates Programming File with FlashLock Pass Key and Design Contents No Encrypted Design Content Passes through MAC for Authentication Correct? Yes Software Generates Programming File with Encrypted Design Contents Design Content Decrypted and Programmed into Device Note: If programming the Security Header only, just perform sub-flow 1. If programming design content only, just perform sub-flow 2. Figure 15-9 * Security Programming Flows 1 5 -1 2 v1.1 Security in Low-Power Flash Devices Generating Programming Files Generation of the Programming File in a Trusted Environment-- Application 1 As discussed in the "Application 1: Trusted Environment" section on page 15-9, in a trusted environment, the user can choose to program the device with plaintext bitstream content. It is possible to use plaintext for programming even when the FlashLock Pass Key option has been selected. In this application, it is not necessary to employ AES encryption protection. For AES encryption settings, refer to the next sections. The generated programming file will include the security setting (if selected) and the plaintext programming file content for the FPGA array, FlashROM, and/or FB. These options are indicated in Table 15-2 and Table 15-3. Table 15-2 * IGLOO and ProASIC3 Plaintext Security Options, No AES FlashROM Only FPGA Core Only Both FlashROM and FPGA No AES / No FlashLock FlashLock only AES and FlashLock - - - Security Protection Table 15-3 * Fusion Plaintext Security Options Security Protection FlashROM Only FPGA Core Only FB Core Only All No AES / No FlashLock FlashLock AES and FlashLock - - - - Note: For all instructions, the programming of Flash Blocks refers to Fusion only. For this scenario, generate the programming file as follows: 1. Select the Silicon features to be programmed (Security Settings, FPGA Array, FlashROM, Flash Memory Block), as shown in Figure 15-10 on page 15-14 and Figure 15-11 on page 15-14. Click Next. If Security Settings is selected (i.e., the FlashLock security Pass Key feature), an additional dialog will be displayed to prompt you to select the security level setting. If no security setting is selected, you will be directed to Step 3. v1.1 1 5 - 13 Security in Low-Power Flash Devices Figure 15-10 * All Silicon Features Checked for IGLOO and ProASIC3 Devices Figure 15-11 * All Silicon Features Checked for Fusion 1 5 -1 4 v1.1 Security in Low-Power Flash Devices 2. Choose the appropriate security level setting and enter a FlashLock Pass Key. The default is the Medium security level (Figure 15-12). Click Next. If you want to select different options for the FPGA and/or FlashROM, this can be set by clicking Custom Level. Refer to the "Advanced Options" section on page 15-22 for different custom security level options and descriptions of each. Figure 15-12 * Medium Security Level Selected for Low-Power Flash Devices v1.1 1 5 - 15 Security in Low-Power Flash Devices 3. Choose the desired settings for the FlashROM configurations to be programmed (Figure 15-13). Click Finish to generate the STAPL programming file for the design. Figure 15-13 * FlashROM Configuration Settings for Low-Power Flash Devices Generation of Security Header Programming File Only-- Application 2 As mentioned in the "Application 2: Nontrusted Environment--Unsecured Location" section on page 15-9, the designer may employ FlashLock Pass Key protection or FlashLock Pass Key with AES encryption on the device before sending it to a nontrusted or unsecured location for device programming. To achieve this, the user needs to generate a programming file containing only the security settings desired (Security Header programming file). Note: If AES encryption is configured, FlashLock Pass Key protection must also be configured. The available security options are indicated in Table 15-4 and Table 15-5 on page 15-17. Table 15-4 * FlashLock Security Options for IGLOO and ProASIC3 FlashROM Only FPGA Core Only Both FlashROM and FPGA No AES / No FlashLock - - - FlashLock only AES and FlashLock Security Option 1 5 -1 6 v1.1 Security in Low-Power Flash Devices Table 15-5 * FlashLock Security Options for Fusion Security Option FlashROM Only FPGA Core Only FB Core Only All No AES / No FlashLock - - - - FlashLock AES and FlashLock For this scenario, generate the programming file as follows: 1. Select only the Security settings option, as indicated in Figure 15-14 and Figure 15-15 on page 15-18. Click Next. Figure 15-14 * Programming IGLOO and ProASIC3 Security Settings Only v1.1 1 5 - 17 Security in Low-Power Flash Devices Figure 15-15 * Programming Fusion Security Settings Only 2. Choose the desired security level setting and enter the key(s). - The High security level employs FlashLock Pass Key with AES Key protection. - The Medium security level employs FlashLock Pass Key protection only. Figure 15-16 * High Security Level to Implement FlashLock Pass Key and AES Key Protection 1 5 -1 8 v1.1 Security in Low-Power Flash Devices Table 15-6 and Table 15-7 show all available options. If you want to implement custom levels, refer to the "Advanced Options" section on page 15-22 for information on each option and how to set it. 3. When done, click Finish to generate the Security Header programming file. Table 15-6 * All IGLOO and ProASIC3 Header File Security Options FlashROM Only FPGA Core Only Both FlashROM and FPGA No AES / No FlashLock FlashLock only AES and FlashLock Security Option Note: = options that may be used Table 15-7 * All Fusion Header File Security Options Security Option FlashROM Only FPGA Core Only FB Core Only All No AES / No FlashLock FlashLock AES and FlashLock Generation of Programming Files with AES Encryption-- Application 3 This section discusses how to generate design content programming files needed specifically at unsecured or remote locations to program devices with a security header (FlashLock Pass Key and AES key) already programmed ("Application 2: Nontrusted Environment--Unsecured Location" section on page 15-9 and "Application 3: Nontrusted Environment--Field Updates/Upgrades" section on page 15-10). In this case, the encrypted programming file must correspond to the AES key already programmed into the device. If AES encryption was previously selected to encrypt the FlashROM, FB, and FPGA array, AES encryption must be set when generating the programming file for them. AES encryption can be applied to the FlashROM only, the FB only, the FPGA array only, or all. The user must ensure both the FlashLock Pass Key and the AES key match those already programmed to the device(s), and all security settings must match what was previously programmed. Otherwise, the encryption and/or device unlocking will not be recognized when attempting to program the device with the programming file. The generated programming file will be AES-encrypted. In this scenario, generate the programming file as follows: 1. Deselect the Security settings and select the portion of the device to be programmed (Figure 15-17 on page 15-20). Select Programming previously secured device(s). Click Next. v1.1 1 5 - 19 Security in Low-Power Flash Devices Note: The settings in this figure are used to show the generation of an AES-encrypted programming file for the FPGA array, FlashROM, and FB contents. One or all locations may be selected for encryption. Figure 15-17 * Settings to Program a Device Secured with FlashLock and using AES Encryption Choose the High security level to reprogram devices using both the FlashLock Pass Key and AES key protection (Figure 15-18 on page 15-21). Enter the AES key and click Next. A device that has already been secured with FlashLock and has an AES key loaded must recognize the AES key to program the device and generate a valid bitstream in authentication. The FlashLock Key is only required to unlock the device and change the security settings. This is what makes it possible to program in an untrusted environment. The AES key is protected inside the device by the FlashLock Key, so you can only program if you have the correct AES key. In fact, the AES key is not in the programming file either. It is the key used to encrypt the data in the file. The same key previously programmed with the FlashLock Key matches to decrypt the file. If you had an AES-encrypted file programmed to a device without FlashLock, this would not be secure, since without FlashLock to protect the AES key, you could simply reprogram the AES key first, then program with any AES key you wanted or no AES key at all. This option is therefore not available in the software. 1 5 -2 0 v1.1 Security in Low-Power Flash Devices Figure 15-18 * Security Level Set High to Reprogram Device with AES Key Programming with this file is intended for an unsecured environment. The AES key encrypts the programming file with the same AES key already used in the device and utilizes it to program the device. Reprogramming Devices Previously programmed devices can be reprogrammed using the steps in the "Generation of the Programming File in a Trusted Environment--Application 1" section on page 15-13 and "Generation of Security Header Programming File Only--Application 2" section on page 15-16. In the case where a FlashLock Pass Key has been programmed previously, the user must generate the new programming file with a FlashLock Pass Key that matches the one previously programmed into the device. The software will check the FlashLock Pass Key in the programming file against the FlashLock Pass Key in the device. The keys must match before the device can be unlocked to perform further programming with the new programming file. Figure 15-10 on page 15-14 and Figure 15-11 on page 15-14 show the option Programming previously secured device(s), which the user should select before proceeding. Upon going to the next step, the user will be notified that the same FlashLock Pass Key needs to be entered, as shown in Figure 15-19 on page 15-22. v1.1 1 5 - 21 Security in Low-Power Flash Devices Figure 15-19 * FlashLock Pass Key, Previously Programmed Devices It is important to note that when the security settings need to be updated, the user also needs to select the Security settings check box in Step 1, as shown in Figure 15-10 on page 15-14 and Figure 15-11 on page 15-14, to modify the security settings. The user must consider the following: * If only a new AES key is necessary, the user must re-enter the same Pass Key previously programmed into the device in Designer and then generate a programming file with the same Pass Key and a different AES key. This ensures the programming file can be used to access and program the device and the new AES key. * If a new Pass Key is necessary, the user can generate a new programming file with a new Pass Key (with the same or a new AES key if desired). However, for programming, the user must first load the original programming file with the Pass Key that was previously used to unlock the device. Then the new programming file can be used to program the new security settings. Advanced Options As mentioned, there may be applications where more complicated security settings are required. The "Custom Security Levels" section in the FlashPoint User's Guide describes different advanced options available to aid the user in obtaining the best available security settings. 1 5 -2 2 v1.1 Security in Low-Power Flash Devices Programming File Header Definition In each STAPL programming file generated, there will be information about how the AES key and FlashLock Pass Key are configured. Table 15-8 shows the header definitions in STAPL programming files for different security levels. Table 15-8 * STAPL Programming File Header Definitions by Security Level Security Level STAPL File Header Definition No security (no FlashLock Pass Key or AES key) NOTE "SECURITY" "Disable"; FlashLock Pass Key with no AES key NOTE "SECURITY" "KEYED "; FlashLock Pass Key with AES key NOTE "SECURITY" "KEYED ENCRYPT "; Permanent Security Settings option enabled NOTE "SECURITY" "PERMLOCK ENCRYPT "; AES-encrypted FPGA array (for programming updates) NOTE "SECURITY" "ENCRYPT CORE "; AES-encrypted FlashROM (for programming updates) NOTE "SECURITY" "ENCRYPT FROM "; AES-encrypted FPGA array and FlashROM (for programming NOTE "SECURITY" "ENCRYPT FROM CORE "; updates) Example File Headers STAPL Files Generated with FlashLock Key and AES Key Contain Key Information * FlashLock Key / AES key indicated in STAPL file header definition * Intended ONLY for secured/trusted environment programming applications ============================================= NOTE "CREATOR" "Designer Version: 6.1.1.108"; NOTE "DEVICE" "A3PE600"; NOTE "PACKAGE" "208 PQFP"; NOTE "DATE" "2005/04/08"; NOTE "STAPL_VERSION" "JESD71"; NOTE "IDCODE" "$123261CF"; NOTE "DESIGN" "counter32"; NOTE "CHECKSUM" "$EDB9"; NOTE "SAVE_DATA" "FRomStream"; NOTE "SECURITY" "KEYED ENCRYPT "; NOTE "ALG_VERSION" "1"; NOTE "MAX_FREQ" "20000000"; NOTE "SILSIG" "$00000000"; NOTE "PASS_KEY" "$00123456789012345678901234567890"; NOTE "AES_KEY" "$ABCDEFABCDEFABCDEFABCDEFABCDEFAB"; ============================================== v1.1 1 5 - 23 Security in Low-Power Flash Devices STAPL File with AES Encryption * Does not contain AES key / FlashLock Key information * Intended for transmission through web or service to unsecured locations for programming ============================================= NOTE "CREATOR" "Designer Version: 6.1.1.108"; NOTE "DEVICE" "A3PE600"; NOTE "PACKAGE" "208 PQFP"; NOTE "DATE" "2005/04/08"; NOTE "STAPL_VERSION" "JESD71"; NOTE "IDCODE" "$123261CF"; NOTE "DESIGN" "counter32"; NOTE "CHECKSUM" "$EF57"; NOTE "SAVE_DATA" "FRomStream"; NOTE "SECURITY" "ENCRYPT FROM CORE "; NOTE "ALG_VERSION" "1"; NOTE "MAX_FREQ" "20000000"; NOTE "SILSIG" "$00000000"; Conclusion The new and enhanced security features offered in Actel IGLOO, Fusion, and ProASIC3 devices provide state-of-the-art security to designs programmed into these flash-based devices. Actel lowpower flash devices employ the encryption standard used by NIST and the U.S. government--AES using the 128-bit Rijndael algorithm. The combination of an on-chip AES decryption engine and Actel FlashLock technology provides the highest level of security against invasive attacks and design theft, implementing the most robust and secure ISP solution. These security features protect IP within the FPGA and protect the system from cloning, wholesale "black box" copying of a design, invasive attacks, and explicit IP or data theft. Glossary Term Security Header programming file Explanation Programming file used to program the FlashLock Pass Key and/or AES key into the device to secure the FPGA, FlashROM, and/or FBs. AES (encryption) key 128-bit key defined by the user when the AES encryption option is set in the Actel Designer software when generating the programming file. FlashLock Pass Key 128-bit key defined by the user when the FlashLock option is set in the Actel Designer software when generating the programming file. The FlashLock Key protects the security settings programmed to the device. Once a device is programmed with FlashLock, whatever settings were chosen at that time are secure. FlashLock 1 5 -2 4 The combined security features that protect the device content from attacks. These features are the following: * Flash technology that does not require an external bitstream to program the device * FlashLock Pass Key that secures device content by locking the security settings and preventing access to the device as defined by the user * AES key that allows secure, encrypted device reprogrammability v1.1 Security in Low-Power Flash Devices References National Institute of Standards and Technology. "ADVANCED ENCRYPTION STANDARD (AES) Questions and Answers." 28 January 2002. <http://csrc.nist.gov/CryptoToolkit/aes/aesfact.html> (10 January 2005). Related Documents Handbook Documents FlashROM in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_FlashROM_HBs.pdf Programming ProASIC3/E Using a Microprocessor http://www.actel.com/documents/LPD_Microprocessor_HBs.pdf In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 http://www.actel.com/documents/LPD_ISP_HBs.pdf User's Guides FlashPoint User's Guide\ http://www.actel.com/documents/flashpoint_ug.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information. Part Number 51700094-014-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) Changes in Current Version (v1.1) Page The chapter was updated to include the IGLOO PLUS family and information regarding 15 k gate devices. N/A The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 15-2 v1.1 1 5 - 25 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 16 - In-System Programming (ISP) of Actel's LowPower Flash Devices Using FlashPro3 Introduction Actel's low-power flash devices are all in-system programmable. This document describes the general requirements for programming a device and specific requirements for the FlashPro3 programmer. IGLOO,(R) Fusion, and ProASIC(R)3 devices offer a low-power, single-chip, live-at-power-up solution with the ASIC advantages of security and low unit cost through nonvolatile flash technology. Each device contains 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications such as Internet Protocol (IP) addressing, user system preference storage, device serialization, or subscription-based business models. Fusion, IGLOO, and ProASIC3 devices offer the best in-system programming (ISP) solution, FlashLock(R) security features, and AESdecryption-based ISP. ISP Architecture Low-power flash devices support ISP via JTAG and require a single VPUMP voltage of 3.3 V during programming. In addition, programming via a microcontroller in a target system is also supported. Refer to Microprocessor Programming of Actel's Low-Power Flash Devices. Family-specific support: * Fusion, ProASIC3, and ProASIC3E devices support ISP. * ProASIC3L devices operate using a 1.2 V core voltage and support ISP at 1.5 V only. Voltage switching is required in-system to switch from a 1.2 V core to 1.5 V core for programming. * IGLOO and IGLOOe V5 devices can be programmed in-system when the device is using a 1.5 V supply voltage to the FPGA core. IGLOO, IGLOO PLUS, and IGLOOe V2 devices can operate using either a 1.2 V core voltage or a 1.5 V core voltage. Although the device can operate at 1.2 V core voltage, the device can only be reprogrammed when all supplies (VCC, VCCI, and VJTAG) are at 1.5 V. Voltage switching is required in-system to switch from a 1.2 V core to 1.5 V core for programming. IGLOO devices cannot be programmed in-system when the device is in Flash*Freeze mode. The device should exit Flash*Freeze mode and be in normal operation for programming to start. Programming operations in IGLOO devices can be achieved when the device is in normal operating mode and a 1.5 V core voltage is used. JTAG 1532 IGLOO and ProASIC3 devices support the JTAG-based IEEE 1532 standard for ISP. To start JTAG operations, the IGLOO device should exit Flash*FreezeTM mode and be in normal operation before starting to send JTAG commands to the device. As part of this support, when a device is in an unprogrammed state, all user I/O pins are disabled. This is achieved by keeping the global IO_EN signal deactivated, which also has the effect of disabling the input buffers. The SAMPLE/PRELOAD instruction captures the status of pads in parallel and shifts them out as new data is shifted in for loading into the Boundary Scan Register (BSR). When the device is in an unprogrammed state, the SAMPLE/PRELOAD instruction has no effect on I/O status; however, it will continue to shift in new data to be loaded into the BSR. Therefore, when SAMPLE/PRELOAD is used on an unprogrammed device, the BSR will be loaded with undefined data. For JTAG timing information on setup, hold, and fall times, refer to the FlashPro User's Guide. v1.1 1 6 -1 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 ISP Support in Low-Power Devices The low-power flash families listed in Table 16-1 support the ISP feature and the functions described in this document. Table 16-1 * Low-Power Flash Families Family1 IGLOO Timing Numbers2 Description Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO DC and Switching technology Characteristics IGLOO PLUS Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO PLUS DC and technology and enhanced I/O capabilities Switching Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional IGLOOe DC and Switching PLLs, and additional I/O standards Characteristics ProASIC3L Low-power, high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and Switching technology Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, and ProASIC3E DC and Switching additional I/O standards Characteristics ProASIC3 DC and Switching Characteristics ProASIC3 Low-power, high-performance FPGAs qualified for automotive Automotive ProASIC3 DC and Automotive applications Switching Characteristics Fusion Low-power mixed-signal Programmable System Chip (PSC) Fusion DC and Power Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 16-1) provide a selection of low-power, secure, live-atpower-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. The Actel Fusion(R) family, based on the highly successful ProASIC3 flash FPGA architecture, has been designed as a high-performance, mixed-signal Programmable System Chip. Fusion supports many peripherals, including embedded flash memory, analog-to-digital converter (ADC), high-drive outputs, RC and crystal oscillators, and real-time counter (RTC). The total available on-chip memory, including the flash array blocks, is greater than that found in SRAM FPGAs. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 16-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 16-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 1 6 -2 v1.1 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 Programming Voltage (VPUMP) and VJTAG Low-power flash devices support on-chip charge pumps, and therefore require only a single 3.3 V programming voltage for the VPUMP pin during programming. When the device is not being programmed, the VPUMP pin can be left floating or can be tied (pulled up) to any voltage between 0 V and 3.6 V. During programming, the target board or the FlashPro3 programmer can provide VPUMP. FlashPro3 is capable of supplying VPUMP to a single device. If more than one device is to be programmed using FlashPro3 on a given board, FlashPro3 should not be relied on to supply the VPUMP voltage. Low-power flash device I/Os support a bank-based, voltage-supply architecture that simultaneously supports multiple I/O voltage standards (Table 16-2 on page 16-3). By isolating the JTAG power supply in a separate bank from the user I/Os, low-power flash devices provide greater flexibility with supply selection and simplify power supply and printed circuit board (PCB) design. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Actel recommends that TCK be tied to GND or VJTAG when not used. This prevents a possible totempole current on the input buffer stage. For TDI, TMS, and TRST pins, the devices provide an internal nominal 10 k pull-up resistor. During programming, all I/O pins, except for JTAG interface pins, are tristated and weakly pulled up to VCCI. This isolates the part and prevents the signals from floating. The JTAG interface pins are driven by the FlashPro3 during programming, including the TRST pin, which is driven HIGH. Table 16-2 * Power Supplies Programming Mode Current during Programming VCC 1.5 V < 70 mA VCCI 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-selectable) I/Os are weakly pulled up. VJTAG 1.5 V / 1.8 V / 2.5 V / 3.3 V < 20 mA VPUMP 3.0 V to 3.6 V < 80 mA Power Supply Note: All supply voltages should be at 1.5 V or higher, regardless of the setting during normal operation. IEEE 1532 (JTAG) Interface The supported industry-standard IEEE 1532 programming interface builds on the IEEE 1149.1 (JTAG) standard. IEEE 1532 defines the standardized process and methodology for ISP. Both silicon and software issues are addressed in IEEE 1532 to create a simplified ISP environment. Any IEEE 1532-compliant programmer can be used to program low-power flash devices. However, only limited security and FlashROM features are supported when using the IEEE 1532 standard. The Actel FlashPro3 programmer was developed exclusively for these devices and will support all the security and device serialization features. Refer to the standard for detailed information about IEEE 1532. Security Unlike SRAM-based FPGAs that require loading at power-up from an external source such as a microcontroller or boot PROM, Actel nonvolatile devices are live at power-up, and there is no bitstream required to load the device when power is applied. The unique flash-based architecture prevents reverse engineering of the programmed code on the device, because the programmed data is stored in nonvolatile memory cells. Each nonvolatile memory cell is made up of small capacitors and any physical deconstruction of the device will disrupt stored electrical charges. Each low-power flash device has a built-in 128-bit Advanced Encryption Standard (AES) decryption core, except for the 15 k and 30 k gate devices. Any FPGA core or FlashROM content loaded into the device can optionally be sent as encrypted bitstream and decrypted as it is loaded. This is v1.1 1 6 -3 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 particularly suitable for applications where device updates must be transmitted over an unsecured network such as the Internet. The embedded AES decryption core can prevent sensitive data from being intercepted (Figure 16-1 on page 16-4). A single 128-bit AES Key (32 hex characters) is used to encrypt FPGA core programming data and/or FlashROM programming data in the Actel tools. The low-power flash devices also decrypt with a single 128-bit AES Key. In addition, low-power flash devices support a Message Authentication Code (MAC) for authentication of the encrypted bitstream on-chip. This allows the encrypted bitstream to be authenticated and prevents erroneous data from being programmed into the device. The FPGA core, FlashROM, and Flash Memory Blocks (FBs), in Fusion only, can be updated independently using a programming file that is AES-encrypted (cipher text) or uses plain text. Security in ARM-Enabled Low-Power Flash Devices There are slight differences between the regular flash device and the ARM(R)-enabled flash devices, which have the M1 and M7 prefix. The AES key is used by Actel and pre-programmed into the device to protect the ARM IP. As a result, the design will be encrypted along with the ARM IP, according to the details below. CoreMP7 Device Security ARM7TM (M7-enabled) devices are shipped with the following security features: * FPGA Array enabled for AES encrypted programming and verification * FlashROM enabled for plaintext read and write Cortex-M1 Device Security Cortex-M1-enabled devices are shipped with the following security features: * FPGA Array enabled for AES-encrypted programming and verification * FlashROM enabled for AES-encrypted write and verify Fusion Embedded Flash Memory enabled for AES encrypted write. Flash Device Actel Designer Software MAC Validation User Encryption AES Key Decrypted Bitstream Programming File Generation with AES Encryption AES Decryption FPGA Core, FlashROM, FBs Transmit Medium / Public Network Encrypted Bistream Figure 16-1 * AES-128 Security Features Figure 16-2 on page 16-5 shows different applications for ISP programming. 1 6 -4 v1.1 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 1. In a trusted programming environment, you can program the device using the unencrypted (plaintext) programming file. 2. You can program the AES Key in a trusted programming environment and finish the final programming in an untrusted environment using the AES-encrypted (cipher text) programming file. 3. For the remote ISP updating/reprogramming, the AES Key stored in the device enables the encrypted programming bitstream to be transmitted through the untrusted network connection. Actel low-power flash devices also provide the unique Actel FlashLock feature, which protects the Pass Key and AES Key. Unless the original FlashLock Pass Key is used to unlock the device, security settings cannot be modified. Low-power flash devices do not support read-back of FPGA coreprogrammed data; however, the FlashROM contents can selectively be read back (or disabled) via the JTAG port based on the security settings established by the Actel Designer software. Refer to Security in Low-Power Flash Devices for more information. Source Plain Text AES Encryption Source Encrypted Bitstream FlashROM Option 3 Option 2 Option 1 TCP/IP AES Decryption FPGA Core IGLOO or ProASIC3 Device Figure 16-2 * Different ISP Use Models FlashROM and Programming Files Each low-power flash device has 1 kbit of on-chip, nonvolatile flash memory that can be accessed from the FPGA core. This nonvolatile FlashROM is arranged in eight pages of 128 bits (Figure 16-3). Each page can be programmed independently, with or without the 128-bit AES encryption. The FlashROM can only be programmed via the IEEE 1532 JTAG port and cannot be programmed from the FPGA core. In addition, during programming of the FlashROM, the FPGA core is powered down automatically by the on-chip programming control logic. Using FlashROM combined with AES, many subscription-based applications or device serialization applications are possible. SmartGen supports easy management of the FlashROM contents even over large numbers of devices. SmartGen can support FlashROM contents that contain the following: * Static values v1.1 1 6 -5 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 Page Number 15 14 13 12 Byte Number in Page 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 16-3 * FlashROM Architecture * Random numbers * Values read from a file * Independent updates of each page In addition, auto-incrementing of fields is possible. In applications where the FlashROM content is different for each device, you have the option to generate a single STAPL file for all the devices or individual serialization files for each device. For more information on how to generate the FlashROM content for device serialization, refer to FlashROM in Actel's Low-Power Flash Devices. Actel Libero(R) Integrated Designed Environment (IDE) includes a unique tool to support the generation and management of FlashROM and FPGA programming files. This tool is called FlashPoint. Depending on the applications, designers can use the FlashPoint software to generate a STAPL file with different contents. In each case, optional AES encryption and/or different security settings can be set. In Designer, when you click the Programming File icon, FlashPoint launches, and you can generate STAPL file(s) with four different cases (Figure 16-4 on page 16-7). When the serialization feature is used during the configuration of FlashROM in SmartGen, you can generate a single STAPL file that will program all the devices or an individual STAPL file for each device. The following cases present the FPGA core and FlashROM programming file combinations that can be used for different applications. In each case, you can set the optional security settings (FlashLock Pass Key and/or AES Key) depending on the application. 1. A single STAPL file or multiple STAPL files with multiple FlashROM contents and the FPGA core content. A single STAPL file will be generated if the device serialization feature is not used. You can program the whole FlashROM or selectively program individual pages. 2. A single STAPL file for the FPGA core content 3. A single STAPL file or multiple STAPL files with multiple FlashROM contents. A single STAPL file will be generated if the device serialization feature is not used. You can program the whole FlashROM or selectively program individual pages. 4. A single STAPL file to configure the security settings for the device, such as the AES Key and/or Pass Key. 1 6 -6 v1.1 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 SmartGen Actel's Designer Software Suite Netlist Programming File (FlashPoint) 1 2 FlashROM Configuration File (*.ufc) 3 Security Settings Security Settings Security Settings Single/Multiple FlashROM Content(s) FPGA Core Content Single/Multiple FlashROM Content(s) 4 Security Settings FPGA Core Content Figure 16-4 * Flexible Programming File Generation for Different Applications Programming Solution For device programming, any IEEE 1532-compliant programmer can be used; however, the FlashPro3 programmer must be used to control the low-power flash device's rich security features and FlashROM programming options. The FlashPro3 programmer is a low-cost portable programmer for the Actel flash families. It can also be used with a powered USB hub for parallel programming. General specifications for the FlashPro3 programmer are as follows: * Programming clock - TCK is used with a maximum frequency of 20 MHz, and the default frequency is 4 MHz. * Programming file - STAPL * Daisy chain - Supported. You can use the ChainBuilder software to build the programming file for the chain. * Parallel programming - Supported. Multiple FlashPro3 programmers can be connected together using a powered USB hub or through the multiple USB ports on the PC. * Power supply - The target board must provide VCC, VCCI, VPUMP, and VJTAG during programming. However, if there is only one device on the target board, the FlashPro3 programmer can generate the required VPUMP voltage from the USB port. v1.1 1 6 -7 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 ISP Programming Header Information The FlashPro3 programming cable connector can be connected with a 10-pin, 0.1"-pitch programming header. The recommended programming headers are manufactured by AMP (103310-1) and 3M (2510-6002UB). If you have limited board space, you can use a compact programming header manufactured by Samtec (FTSH-105-01-L-D-K). Using this compact programming header, you are required to order an additional header adapter manufactured by Actel (FP3-26PIN-ADAPTER). Existing ProASICPLUS family customers who are using the Samtec Small Programming Header (FTSH113-01-L-D-K) and are planning to migrate to IGLOO or ProASIC3 devices can order a separate adapter kit from Actel (FP3-10PIN-ADAPTER-KIT), which contains a compact 10-pin adapter kit as well as 26-pin migration capability. Table 16-3 * Programming Header Ordering Code Manufacturer AMP 3M Samtec Part Number Description 103310-1 10-pin, 0.1"-pitch cable header (right-angle PCB mount angle) 2510-6002UB 10-pin, 0.1"-pitch cable header (straight PCB mount angle) FTSH-113-01-L-D-K Small programming header supported by FlashPro and Silicon Sculptor Samtec FTSH-105-01-L-D-K Samtec FFSD-05-D-06.00-01-N Actel Compact programming header 10-pin cable with 50 mil pitch sockets; included in FP310PIN-ADAPTER-KIT. FP3-10PIN-ADAPTER-KIT Compact header and migration kit TCK TDO TMS VPUMP TDI 1 3 5 7 9 2 4 6 8 10 GND NC VJTAG TRST GND Figure 16-5 * Programming Header (top view) Table 16-4 * Programming Header Pin Numbers and Description Pin Signal 1 TCK Source Programmer 1 Description JTAG Clock 2 GND - 3 TDO Target Board 4 NC - 5 TMS Programmer Test Mode Select 6 VJTAG Target Board JTAG Supply Voltage 2 Signal Reference Test Data Output No Connect Programmer/Target Board Programming Supply Voltage 7 VPUMP 8 nTRST Programmer JTAG Test Reset (Hi-Z with 10 k pull-down, HIGH, LOW, or toggling) 9 TDI Programmer Test Data Input 10 1 GND - Signal Reference Notes: 1. Both GND pins must be connected. 2. FlashPro3 can provide VPUMP if there is only one device on the target board. 1 6 -8 v1.1 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 Board-Level Considerations A bypass capacitor is required from VPUMP to GND for all low-power flash devices during programming. This bypass capacitor protects the devices from voltage spikes that may occur on the VPUMP supplies during the erase and programming cycles. Refer to Pin Descriptions for specific recommendations. For proper programming, 0.01 F and 0.33 F capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. The bypass capacitor must be placed within 2.5 cm of the device pins. VJTAG from the target board VCCI from the target board VCC from the target board VCC VCCI Polarizing Notch VJTAG Low-Power Flash Device GND TCK TDO TMS VPUMP 1 TCK 3 TDO 5 TMS 7 VPUMP TDI TRST 9 TDI 2 GND 4 NC 6 VJTAG 8 TRST 10 GND Figure 16-6 * Board Layout and Programming Header Top View Troubleshooting Signal Integrity Symptoms of a Signal Integrity Problem A signal integrity problem can manifest itself in many ways. The problem may show up as extra or dropped bits during serial communication, changing the meaning of the communication. There is a normal variation of threshold voltage and frequency response between parts even from the same lot. Because of this, the effects of signal integrity may not always affect different devices on the same board in the same way. Sometimes, replacing a device appears to make signal integrity problems go away, but this is just masking the problem. Different parts on identical boards will exhibit the same problem sooner or later. It is important to fix signal integrity problems early. Unless the signal integrity problems are severe enough to completely block all communication between the device and the programmer, they may show up as subtle problems. Some of the FlashPro3 exit codes that are caused by signal integrity problems are listed below. Signal integrity problems are not the only possible cause of these errors, but this list is intended to show where problems can occur. FlashPro3 allows TCK to be lowered from 24 MHz down to 1 MHz to allow you to address some signal integrity problems that may occur with impedance mismatching at higher frequencies. Chain Integrity Test Error or Analyze Chain Failure Normally, the FlashPro3 Analyze Chain command expects to see 0x2 on the TDO pin. If the command reports reading 0x0 or 0x3, it is seeing the TDO pin stuck at 0 or 1. The only time the TDO pin comes out of tristate is when the JTAG TAP state machine is in the Shift-IR or Shift-DR state. If v1.1 1 6 -9 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 noise or reflections on the TCK or TMS lines have disrupted the correct state transitions, the device's TAP state controller might not be in one of these two states when the programmer tries to read the device. When this happens, the output is floating when it is read and does not match the expected data value. This can also be caused by a broken TDO net. Only a small amount of data is read from the device during the Analyze Chain command, so marginal problems may not always show up during this command. Exit 11 This error occurs during the verify stage of programming a device. After programming the design into the ProASIC3/E device, the device is verified to ensure it is programmed correctly. The verification is done by shifting the programming data into the device. An internal comparison is performed within the device to verify that all switches are programmed correctly. Noise induced by poor signal integrity can disrupt the writes and reads or the verification process and produce a verification error. While technically a verification error, the root cause is often related to signal integrity. Refer to the FlashPro User's Guide for other error messages and solutions. For the most up-to-date known issues and solutions, refer to http://www.actel.com/support. Conclusion IGLOO, Fusion, and ProASIC3 devices offer a low-cost, single-chip solution that is live at power-up through nonvolatile flash technology. The FlashLock Pass Key and 128-bit AES Key security features enable secure ISP in an untrusted environment. On-chip FlashROM enables a host of new applications, including device serialization, subscription-based applications, and IP addressing. Additionally, as the FlashROM is nonvolatile, all of these services can be provided without battery backup. Related Documents Handbook Documents Microprocessor Programming of Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_Microprocessor_HBs.pdf Security in Low-Power Flash Devices http://www.actel.com/LPD_Security_HBs.pdf FlashROM in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_FlashROM_HBs.pdf Pin Descriptions http://www.actel.com/documents/LPD_PinDescriptions_HBs.pdf User's Guides FlashPro User's Guide http://www.actel.com/documents/flashpro_ug.pdf 1 6 -1 0 v1.1 In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content. Part Number 51700094-015-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.1) Page The "ISP Architecture" section was updated to included the IGLOO PLUS family in the discussion of family-specific support. The text, "When 1.2 V is used, the device can be reprogrammed in-system at 1.5 V only" was revised to state, "Although the device can operate at 1.2 V core voltage, the device can only be reprogrammed when all supplies (VCC, VCCI, and VJTAG) are at 1.5 V." 16-1 The "ISP Support in Low-Power Devices" section and Table 16-1 * Low-Power Flash Families were updated to include the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 16-2 The "Security" section was updated to mention that 15 k gate devices do not have a built-in 128-bit decryption core. 16-3 Table 16-2 * Power Supplies was revised to remove the Normal Operation column and add a table note stating, "All supply voltages should be at 1.5 V or higher, regardless of the setting during normal operation." 16-3 The "ISP Programming Header Information" section was revised to change FP3-26PIN-ADAPTER to FP3-10PIN-ADAPTER-KIT. Table 16-3 * Programming Header Ordering Code was updated with the same change, as well as adding the part number FFSD-05-D-06.00-01-N, a 10-pin cable with 50-mil-pitch sockets. 16-8 The "Board-Level Considerations" section was updated to describe connecting two capacitors in parallel across VPUMP and GND for proper programming. 16-9 51900055-2/7.06 Information was added to the "Programming Voltage (VPUMP) and VJTAG" section about the JTAG interface pin. 16-3 51900055-1/1.05 ACTgen was changed to SmartGen. N/A In Figure 16-6 * Board Layout and Programming Header Top View, the order of the text was changed to: 16-9 v1.0 (January 2008) VJTAG from the target board VCCI from the target board VCC from the target board v1.1 1 6 - 11 Microprocessor Programming of Actel's Low-Power Flash Devices 17 - Microprocessor Programming of Actel's LowPower Flash Devices Introduction The IGLOO,(R) Fusion, and ProASIC(R)3 families of flash FPGAs support in-system programming (ISP) with the use of a microprocessor. Flash-based FPGAs store their configuration information in the actual cells within the FPGA fabric. SRAM-based devices need an external configuration memory, and hybrid nonvolatile devices store the configuration in a flash memory inside the same package as the SRAM FPGA. Since the programming of a true flash FPGA is simpler, requiring only one stage, it makes sense that programming with a microprocessor in-system should be simpler than with other SRAM FPGAs. This reduces bill-of-materials costs and printed circuit board (PCB) area, and increases system reliability. Nonvolatile flash technology also gives the low-power flash devices the advantage of a secure, lowpower, live-at-power-up, and single-chip solution. Low-power flash devices are reprogrammable and offer time-to-market benefits at an ASIC-level unit cost. These features enable engineers to create high-density systems using existing ASIC or FPGA design flows and tools. This document is an introduction to microprocessor programming only. To explain the difference between the options available, user's guides for DirectC and STAPL provide more detail on implementing each style. Microprocessor Internal/External Memory Running DirectC Internal RAM On Board Memory Device .dat file I/O Functions JTAG Bus Flash Device Figure 17-1 * ISP Using Microprocessor v1.1 1 7 -1 Microprocessor Programming of Actel's Low-Power Flash Devices Microprocessor Programming Support in Low-Power Devices The low-power flash families listed in Table 17-1 support programming with a microprocessor and the functions described in this document. Table 17-1 * Low-Power Flash Families Family1 Timing Numbers2 Description IGLOO Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*FreezeTM IGLOO DC and Switching technology Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional IGLOOe DC and Switching PLLs, and additional I/O standards Characteristics ProASIC3L Low-power, high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and Switching technology Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, ProASIC3E DC and Switching and additional I/O standards Characteristics ProASIC3 Automotive Low-power, high-performance FPGAs qualified for Automotive Automotive ProASIC3 DC and applications Switching Characteristics Fusion Low-power mixed-signal Programmable System Chip (PSC) ProASIC3 DC and Switching Characteristics Fusion DC and Power Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 17-1) provide a selection of low-power, secure, live-atpower-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. The Actel Fusion(R) family, based on the highly successful ProASIC3 flash FPGA architecture, has been designed as a high-performance, mixed-signal Programmable System Chip. Fusion supports many peripherals, including embedded flash memory, analog-to-digital converter (ADC), high-drive outputs, RC and crystal oscillators, and real-time counter (RTC). The total available on-chip memory, including the flash array blocks, is greater than that found in SRAM FPGAs. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 17-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 17-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 1 7 -2 v1.1 Microprocessor Programming of Actel's Low-Power Flash Devices Programming Algorithm JTAG Interface The low-power flash families are fully compliant with the IEEE 1149.1 (JTAG) standard. They support all the mandatory boundary scan instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS) as well as six optional public instructions (USERCODE, IDCODE, HIGHZ, and CLAMP). IEEE 1532 The low-power flash families are also fully compliant with the IEEE 1532 programming standard. The IEEE 1532 standard adds programming instructions and associated data registers to devices that comply with the IEEE 1149.1 standard (JTAG). These instructions and registers extend the capabilities of the IEEE 1149.1 standard such that the Test Access Port (TAP) can be used for configuration activities. The IEEE 1532 standard greatly simplifies the programming algorithm, reducing the amount of time needed to implement microprocessor ISP. Implementation Overview To implement device programming with a microprocessor, the user should first download the Cbased STAPL player or DirectC code from the Actel website. (See the Actel website for future updates regarding the STAPL player and DirectC code). Using the easy-to-follow Actel user's guide, create the low-level application programming interface (API) to provide the necessary basic functions. These API functions act as the interface between the programming software and the actual hardware (Figure 17-2). Programming algorithm and data STAPL File STAPL Player or DirectC Programming software I/O and memory functions API Figure 17-2 * Device Programming Code Relationship The API is then linked with the STAPL player or DirectC and compiled using the microprocessor's compiler. Once the entire code is compiled, the user must download the resulting binary into the MCU system's program memory (such as ROM, EEPROM, or flash). The system is now ready for programming. To program a design into the FPGA, the user creates a bitstream or STAPL file using the Actel Designer software, downloads it into the MCU system's volatile memory, and activates the stored programming binary file (Figure 17-3 on page 17-4). Once the programming is completed, the bitstream or STAPL file can be removed from the system, as the configuration profile is stored in the flash FPGA fabric and does not need to be reloaded at every system power-on. v1.1 1 7 -3 Microprocessor Programming of Actel's Low-Power Flash Devices Programming Software Source Code Programming File Microprocessor Compiler BIN File Download to System Program Device Figure 17-3 * MCU FPGA Programming Model FlashROM Actel low-power flash devices have 1 kbit of user-accessible, nonvolatile, FlashROM on-chip. This nonvolatile FlashROM can be programmed along with the core or on its own using the standard IEEE 1532 JTAG programming interface. The FlashROM is architected as eight pages of 128 bits. Each page can be individually programmed (erased and written). Additionally, on-chip AES security decryption can be used selectively to load data securely into the FlashROM (e.g., over public or private networks, such as the Internet). Refer to FlashROM in Actel's Low-Power Flash Devices. 1 7 -4 v1.1 Microprocessor Programming of Actel's Low-Power Flash Devices STAPL vs. DirectC Programming the low-power flash devices is performed using DirectC or the STAPL player. Both tools use the STAPL file as an input. DirectC is a compiled language, whereas STAPL is an interpreted language. Microprocessors will be able to load the FPGA using DirectC much more quickly than STAPL. This speed advantage becomes more apparent when lower clock speeds of 8or 16-bit microprocessors are used. DirectC also requires less memory than STAPL, since the programming algorithm is directly implemented. STAPL does have one advantage over DirectC-- the ability to upgrade. When a new programming algorithm is required, the STAPL user simply needs to regenerate a STAPL file using the latest version of the Designer software and download it to the system. The DirectC user must download the latest version of DirectC from Actel, compile everything, and download the result into the system (Figure 17-4 on page 17-5). STAPL Flow DirectC Flow Generate the New STAPL File DirectC Source Code Download to System Microprocessor Compiler Program Device BIN File Input STAPL File Download to System Program Device Figure 17-4 * STAPL vs. DirectC v1.1 1 7 -5 Microprocessor Programming of Actel's Low-Power Flash Devices Remote Upgrade via TCP/IP Transmission Control Protocol (TCP) provides a reliable bitstream transfer service between two endpoints on a network. TCP depends on Internet Protocol (IP) to move packets around the network on its behalf. TCP protects against data loss, data corruption, packet reordering, and data duplication by adding checksums and sequence numbers to transmitted data and, on the receiving side, sending back packets and acknowledging the receipt of data. The system containing the low-power flash device can be assigned an IP address when deployed in the field. When the device requires an update (core or FlashROM), the programming instructions along with the new programming data (AES-encrypted cipher text) can be sent over the Internet to the target system via the TCP/IP protocol. Once the MCU receives the instruction and data, it can proceed with the FPGA update. Low-power flash devices support Message Authentication Code (MAC), which can be used to validate data for the target device. More details are given in the "Message Authentication Code (MAC) Validation/Authentication" section on page 17-6. Hardware Requirement To facilitate the programming of the low-power flash families, the system must have a microprocessor (with access to the device JTAG pins) to process the programming algorithm, memory to store the programming algorithm, programming data, and the necessary programming voltage. Refer to the relevant datasheet for programming voltages. Security Read-Back Prevention The low-power flash devices are designed with security in mind. Even without any security measures (such as FlashLock with AES), it is not possible to read back the programming data from a programmed device. Upon programming completion, the programming algorithm will reload the programming data into the device. The device will then use built-in circuitry to determine if it was programmed correctly. As an additional security measure, the devices are equipped with AES decryption. AES works in two steps. The first step is to program a key into the devices in a secure or trusted programming center (such as Actel In-House Programming (IHP) center). The second step is to encrypt any programming files with the same encryption key. The encrypted programming file will only work with the devices that have the same key. The AES used in the low-power flash families is the 128-bit AES decryption engine (Rijndael algorithm). Message Authentication Code (MAC) Validation/Authentication As part of the AES decryption flow, the devices are equipped with a MAC validation/authentication system. MAC is an authentication tag, also called a checksum, derived by applying an on-chip authentication scheme to a STAPL file as it is loaded into the FPGA. MACs are computed and verified with the same key so they can only be verified by the intended recipient. When the MCU system receives the AES-encrypted programming data (cipher text), it can validate the data by loading it into the FPGA and performing a MAC verification prior to loading the data, via a second programming pass, into the FPGA core cells. This prevents erroneous or corrupt data from getting into the FPGA. Low-power flash devices with AES and MAC are superior to devices with only DES or 3DES encryption. Because the MAC verifies the correctness of the data, the FPGA is protected from erroneous loading of invalid programming data that could damage a device (Figure 17-5 on page 17-7). The AES with MAC enables field updates over public networks without fear of having the design stolen. An encrypted programming file can only work on devices with the correct key, rendering 1 7 -6 v1.1 Microprocessor Programming of Actel's Low-Power Flash Devices any stolen files useless to the thief. To learn more about the low-power flash devices' security features, refer to Security in Low-Power Flash Devices. ProASIC3/E MAC Validation Designer Software AES KEY AES Encryption Decrypted Stream AES Decryption Programming Control TCP/IP Public Network Encrypted Stream Encrypted Stream Figure 17-5 * ProASIC3 Device Encryption Flow Conclusion The Actel IGLOO, Fusion, and ProASIC3 FPGAs are ideal for applications that require field upgrades. The single-chip devices save board space by eliminating the need for EEPROM. The built-in AES with MAC enables transmission of programming data over any network without fear of design theft. IGLOO, Fusion, and ProASIC3 FPGAs are IEEE 1532-compliant and support STAPL, making the target programming software easy to implement. v1.1 1 7 -7 Microprocessor Programming of Actel's Low-Power Flash Devices Related Documents Handbook Documents FlashROM in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_FlashROM_HBs.pdf Security in Low-Power Flash Devices http://www.actel.com/documents/LPD_Security_HBs.pdf Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content. Part Number 51700094-016-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) 1 7 -8 Changes in the Current Version (v1.1) Page The "Microprocessor Programming Support in Low-Power Devices" section was updated to include information on the IGLOO PLUS family. The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 17-2 v1.1 Boundary Scan and UJTAG Boundary Scan in Low-Power Flash Devices 18 - Boundary Scan in Low-Power Flash Devices Boundary Scan Low-power flash devices are compatible with IEEE Standard 1149.1, which defines a hardware architecture and the set of mechanisms for boundary scan testing. JTAG operations are used during boundary scan testing. The basic boundary scan logic circuit is composed of the TAP controller, test data registers, and instruction register (Figure 18-2 on page 18-4). Low-power flash devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (LSB, ID number, part number, and version). The boundary scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary scan register cells, each with serial-in, serial-out, parallel-in, and parallel-out pins. TAP Controller State Machine The TAP controller is a 4-bit state machine (16 states) that operates as shown in Figure 18-1. The 1s and 0s represent the values that must be present on TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the TestLogic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain HIGH for five TCK cycles. The TRST pin can also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. 1 TEST_LOGIC_RESET 0 0 1 1 RUN_TEST_IDLE 1 SELECT_DR SELECT_IR 0 0 CAPTURE_DR 1 1 CAPTURE_IR 0 0 0 SHIFT_DR 0 SHIFT_IR 1 1 1 1 EXIT1_DR EXIT1_IR 0 0 0 PAUSE_DR 1 1 EXIT2_DR 0 0 EXIT2_IR 1 1 UPDATE_DR 1 0 PAUSE_IR 0 UPDATE_IR 1 0 Figure 18-1 * TAP Controller State Machine v1.1 1 8 -1 Boundary Scan in Low-Power Flash Devices Actel's Flash Families Support the JTAG Feature The low-power flash families listed in Table 18-1 support the JTAG feature and the functions described in this document. Table 18-1 * Low-Power Flash Families Family1 Timing Numbers2 Description IGLOO(R) Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*FreezeTM IGLOO DC and Switching technology Characteristics IGLOO PLUS Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO PLUS DC and Switching technology and enhanced I/O capabilities Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional IGLOOe DC and Switching PLLs, and additional I/O standards Characteristics ProASIC(R)3L Low-power high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and Switching technology Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, and ProASIC3E DC and Switching additional I/O standards Characteristics ProASIC3 Automotive Low-power, high-performance FPGAs qualified for automotive Automotive ProASIC3 DC and applications Switching Characteristics Fusion Low-power mixed-signal Programmable System Chip (PSC) ProASIC3 DC and Switching Characteristics Fusion DC and Power Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 18-1) provide a selection of low-power, secure, live-atpower-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. The Actel Fusion(R) family, based on the highly successful ProASIC3 flash FPGA architecture, has been designed as a high-performance, mixed-signal Programmable System Chip. Fusion supports many peripherals, including embedded flash memory, analog-to-digital converter (ADC), high-drive outputs, RC and crystal oscillators, and real-time counter (RTC). The total available on-chip memory, including the flash array blocks, is greater than that found in SRAM FPGAs. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 18-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 18-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 1 8 -2 v1.1 Boundary Scan in Low-Power Flash Devices Boundary Scan Support in Low-Power Devices The information in this document applies to all IGLOO, Fusion, and ProASIC3 devices. For IGLOO, IGLOO PLUS, and ProASIC3L devices, the Flash*Freeze pin must be deasserted for successful boundary scan operations. Devices cannot enter JTAG mode directly from Flash*Freeze mode. Boundary Scan Opcodes Low-power flash devices support all mandatory IEEE 1149.1 instructions SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction (Table 18-2). (EXTEST, Table 18-2 * Boundary Scan Opcodes Hex Opcode EXTEST 00 HIGHZ 07 USERCODE 0E SAMPLE/PRELOAD 01 IDCODE 0F CLAMP 05 BYPASS FF Boundary Scan Chain The serial pins are used to serially connect all the boundary scan register cells in a device into a boundary scan register chain (Figure 18-2 on page 18-4), which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic I/O tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI, TDO (test data input and output), TMS (test mode selector), and TRST (test reset input). TMS, TDI, and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary scan test usage. Refer to the "JTAG Pins" description in Pin Descriptions for pull-up/-down recommendations for TDO and TCK pins. v1.1 1 8 -3 Boundary Scan in Low-Power Flash Devices I/O I/O I/O I/O I/O TDI Test Data Registers Instruction Register TAP Controller Device Logic TDO I/O TRST I/O TMS I/O TCK I/O Bypass Register I/O I/O I/O I/O I/O Figure 18-2 * Boundary Scan Chain Board Level Recommendations Table 18-3 gives pull-down recommendations for the TRST and TCK pins. Table 18-3 * TRST and TCK Pull-Down Recommendations VJTAG Tie-Off Resistance* VJTAG at 3.3 V 200 to 1 k VJTAG at 2.5 V 200 to 1 k VJTAG at 1.8 V 500 to 1 k VJTAG at 1.5 V 500 to 1 k * Equivalent parallel resistance if more than one device is on JTAG chain (Figure 18-3) 1 8 -4 v1.1 Boundary Scan in Low-Power Flash Devices 1.5 V VJTAG JTAG Header TRST GND TCK 2 k TDO TDI Actel FPGA 1 TDO TDI Actel FPGA 2 1.5 k 2 k 1.5 k 2 k TDO TDI Actel FPGA 3 TDO TDI Actel FPGA 4 1.5 k 2 k 1.5 k Note: TCK is correctly wired with an equivalent tie-off resistance of 500 , which satisfies the table for VJTAG of 1.5 V. The resistor values for TRST are not appropriate in this case, as the tie-off resistance of 375 is below the recommended minimum for VJTAG = 1.5 V, but would be appropriate for a VJTAG setting of 2.5 V or 3.3 V. Figure 18-3 * Parallel Resistance on JTAG Chain of Devices Related Documents Handbook Documents Pin Descriptions http://www.actel.com/documents/LPD_PinDescriptions_HBs.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet. To improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage information. No technical changes were made to the content unless explicitly listed. Part Number 51700094-019-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) Changes in Current Version (v1.1) Page The chapter was updated to include the IGLOO PLUS family and information regarding 15 k gate devices. N/A The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 18-2 v1.1 1 8 -5 UJTAG Applications in Actel's Low-Power Flash Devices 19 - UJTAG Applications in Actel's Low-Power Flash Devices Introduction In IGLOO,(R) Fusion, and ProASIC(R)3 devices, there is bidirectional access from the JTAG port to the core VersaTiles during normal operation of the device (Figure 19-1). User JTAG (UJTAG) is the ability for the design to use the JTAG ports for access to the device for updates, etc. While regular JTAG is used, the UJTAG tiles, located at the southeast area of the die, are directly connected to the JTAG Test Access Port (TAP) Controller in normal operating mode. As a result, all the functional blocks of the device, such as Clock Conditioning Circuits (CCC) with PLLs, SRAM blocks, embedded FlashROM, flash memory blocks, and I/O tiles, can be reached via the JTAG ports. The UJTAG functionality is available by instantiating the UJTAG macro directly in the source code of a design. Access to the FPGA core VersaTiles from the JTAG ports enables users to implement different applications using the TAP Controller (JTAG port). This document introduces the UJTAG tile functionality and discusses a few application examples. However, the possible applications are not limited to what is presented in this document. UJTAG can serve different purposes in many designs as an elementary or auxiliary part of the design. For detailed usage information, refer to Boundary Scan in Low-Power Flash Devices. UJTAG Address Generation and Data Serlialization UIREG[7:0] Enable FROM RESET TDO TDI TMS TCK TRST URSTB UDRUPD Control UDRCK CLK UDRCAP SDI UDRSH Addr[6:0] Addr [6:0] Data[7:0] Data[7:0] SDO UTDI UTDO Figure 19-1 * Block Diagram of Using UJTAG to Read FlashROM Contents v1.1 1 9 -1 UJTAG Applications in Actel's Low-Power Flash Devices UJTAG Support in Low-Power Devices The low-power flash families listed in Table 19-1 support the UJTAG feature and the functions described in this document. The family name links to the datasheet for each family. Any required timing details are linked from the Timing Numbers column to the relevant datasheet sections. Table 19-1 * Low-Power Flash Families Family1 IGLOO Timing Numbers2 Description Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*FreezeTM IGLOO DC and Switching technology Characteristics IGLOO PLUS Ultra-low-power 1.2 V and 1.5 V FPGAs with Flash*Freeze IGLOO PLUS DC and technology and enhanced I/O capabilities Switching Characteristics IGLOOe IGLOO devices enhanced with higher density, five additional IGLOOe DC and Switching PLLs, and additional I/O standards Characteristics ProASIC3L Low-power, high-performance 1.2 V FPGAs with Flash*Freeze ProASIC3L DC and Switching technology Characteristics ProASIC3 Low-power, high-performance 1.5 V FPGAs ProASIC3E ProASIC3 enhanced with higher density, five additional PLLs, and ProASIC3E DC and Switching additional I/O standards Characteristics ProASIC3 Automotive Low-power, high-performance FPGAs qualified for Automotive Automotive ProASIC3 DC and applications Switching Characteristics Fusion Low-power mixed-signal Programmable System Chip (PSC) ProASIC3 DC and Switching Characteristics Fusion DC and Power Characteristics Notes: 1. The family names are linked to the appropriate product brief. 2. The timing number links go to the relevant timing numbers in the datasheet. Actel's low-power flash devices (listed in Table 19-1) provide a selection of low-power, secure, live-atpower-up, single-chip solutions. The nonvolatile flash-based devices do not require a boot PROM and incorporate FlashLock(R) technology, which provides a unique combination of reprogrammability and design security without external overhead. Only low-power flash FPGAs can offer these advantages. Actel IGLOO PLUS FPGAs are the industry-leading 1.2 V ultra-low-power programmable logic devices (PLDs) and consume 90% less static power and over 50% less dynamic power than PLD alternatives, while ProASIC3L devices offer a balance of low power and higher performance. Flash*Freeze technology used in IGLOO, IGLOO PLUS, and ProASIC3L devices enables easy entry to and exit from the ultra-low power mode, which consumes as little as 5 W, while retaining SRAM and register data. IGLOO PLUS also offers the ability to hold I/O state in Flash*Freeze mode. Flash*Freeze technology simplifies power management through I/O and clock management without the need to turn off voltages, I/Os, or clocks at the system level. Entering and exiting Flash*Freeze mode takes less than 1 s. The Actel Fusion(R) family, based on the highly successful ProASIC3 flash FPGA architecture, has been designed as a high-performance, mixed-signal Programmable System Chip. Fusion supports many peripherals, including embedded flash memory, analog-to-digital converter (ADC), high-drive outputs, RC and crystal oscillators, and real-time counter (RTC). The total available on-chip memory, including the flash array blocks, is greater than that found in SRAM FPGAs. IGLOO Terminology In documentation, the term IGLOO families or IGLOO devices refers to all IGLOO families as listed in Table 19-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. ProASIC3 Terminology In documentation, the term ProASIC3 families or ProASIC3 devices refers to all ProASIC3 families as listed in Table 19-1. Where the information applies to only one family or limited devices, these exclusions will be explicitly stated. 1 9 -2 v1.1 UJTAG Applications in Actel's Low-Power Flash Devices UJTAG Macro The UJTAG tiles can be instantiated in a design using the UJTAG macro from the IGLOO, Fusion, or ProASIC3 macro library. Note that "UJTAG" is a reserved name and cannot be used for any other user-defined blocks. A block symbol of the UJTAG tile macro is presented in Figure 19-2. In this figure, the ports on the left side of the block are connected to the JTAG TAP Controller, and the right-side ports are accessible by the FPGA core VersaTiles. The TDI, TMS, TDO, TCK, and TRST ports of UJTAG are only provided for design simulation purposes and should be treated as external signals in the design netlist. However, these ports must NOT be connected to any I/O buffer in the netlist. Figure 19-3 on page 19-4 illustrates the correct connection of the UJTAG macro to the user design netlist. Actel Designer software will automatically connect these ports to the TAP during place-and-route. Table 19-2 gives the port descriptions for the rest of the UJTAG ports: Table 19-2 * UJTAG Port Descriptions Port Description UIREG [7:0] This 8-bit bus carries the contents of the JTAG Instruction Register of each device. Instruction Register values 16 to 127 are not reserved and can be employed as user-defined instructions. URSTB URSTB is an active-low signal and will be asserted when the TAP Controller is in Test-Logic-Reset mode. URSTB is asserted at power-up, and a power-on reset signal resets the TAP Controller. URSTB will stay asserted until an external TAP access changes the TAP Controller state. UTDI This port is directly connected to the TAP's TDI signal. UTDO This port is the user TDO output. Inputs to the UTDO port are sent to the TAP TDO output MUX when the IR address is in user range. UDRSH Active-high signal enabled in the ShiftDR TAP state UDRCAP Active-high signal enabled in the CaptureDR TAP state UDRCK This port is directly connected to the TAP's TCK signal. UDRUPD Active-high signal enabled in the UpdateDR TAP state TDO TDI TMS UIREG0 UIREG1 UIREG2 UIREG3 UIREG4 UIREG5 UIREG6 UIREG7 URSTB UDRUPD TCK TRST UDRCK UDRCAP UDRSH UTDI UTDO Figure 19-2 * UJTAG Tile Block Symbol v1.1 1 9 -3 UJTAG Applications in Actel's Low-Power Flash Devices a) CORRECT Instantiation UIREG[7:0] TDO URSTB TDI INPUTS UDRUPD UDRCK TMS UDRCAP TCK FPGA VersaTiles UDRSH TRST UTDI UTDO OUTPUTS b) INCORRECT Instantiation UIREG[7:0] TDO URSTB TDI INPUTS UDRUPD UDRCK TMS UDRCAP TCK FPGA VersaTiles UDRSH TRST UTDI UTDO OUTPUTS Note: Do not connect JTAG pins (TDO, TDI, TMS, TCK, or TRST) to I/Os in the design. Figure 19-3 * Connectivity Method of UJTAG Macro UJTAG Operation There are a few basic functions of the UJTAG macro that users must understand before designing with it. The most important fundamental concept of the UJTAG design is its connection with the TAP Controller state machine. TAP Controller State Machine The 16 states of the Tap Controller state machine are shown in Figure 19-4 on page 19-5. The 1s and 0s, shown adjacent to the state transitions, represent the TMS values that must be present at the time of a rising TCK edge for a state transition to occur. In the states that include the letters "IR," the instruction register operates; in the states that contain the letters "DR," the test data register operates. The TAP Controller receives two control inputs, TMS and TCK, and generates control and clock signals for the rest of the test logic. On power-up (or the assertion of TRST), the TAP Controller enters the Test-Logic-Reset state. To reset the controller from any other state, TMS must be held HIGH for at least five TCK cycles. After reset, the TAP state changes at the rising edge of TCK, based on the value of TMS. 1 9 -4 v1.1 UJTAG Applications in Actel's Low-Power Flash Devices 1 Test_Logic_Reset 0 0 Run_Test/ Idle 1 1 Select_ DR_Scan 0 1 1 Capture_DR Capture_IR 0 0 0 Shift_DR 1 Exit1_DR 1 1 Exit1_IR 0 0 Pause_DR 0 Pause_IR 1 0 1 Exit2_DR 0 Exit2_IR 1 1 Update_DR 1 0 Shift_IR 1 0 1 Select_ IR_Scan 0 0 Update_IR 1 0 Figure 19-4 * TAP Controller State Diagram UJTAG Port Usage UIREG[7:0] hold the contents of the JTAG instruction register. The UIREG vector value is updated when the TAP Controller state machine enters the Update_IR state. Instructions 16 to 127 are userdefined and can be employed to encode multiple applications and commands within an application. Loading new instructions into the UIREG vector requires users to send appropriate logic to TMS to put the TAP Controller in a full IR cycle starting from the Select IR_Scan state and ending with the Update_IR state. UTDI, UTDO, and UDRCK are directly connected to the JTAG TDI, TDO, and TCK ports, respectively. The TDI input can be used to provide either data (TAP Controller in the Shift_DR state) or the new contents of the instruction register (TAP Controller in the Shift_IR state). UDRSH, UDRUPD, and UDRCAP are HIGH when the TAP Controller state machine is in the Shift_DR, Update_DR, and Capture_DR states, respectively. Therefore, they act as flags to indicate the stages of the data shift process. These flags are useful for applications in which blocks of data are shifted into the design from JTAG pins. For example, an active UDRSH can indicate that UTDI contains the data bitstream, and UDRUPD is a candidate for the end-of-data-stream flag. As mentioned earlier, users should not connect the TDI, TDO, TCK, TMS, and TRST ports of the UJTAG macro to any port or net of the design netlist. The Designer software will automatically handle the port connection. v1.1 1 9 -5 UJTAG Applications in Actel's Low-Power Flash Devices Typical UJTAG Applications Bidirectional access to the JTAG port from VersaTiles--without putting the device into test mode-- creates flexibility to implement many different applications. This section describes a few of these. All are based on importing/exporting data through the UJTAG tiles. Clock Conditioning Circuitry--Dynamic Reconfiguration In low-power flash devices, CCCs, which include PLLs, can be configured dynamically through either an 81-bit embedded shift register or static flash programming switches. These 81 bits control all the characteristics of the CCC: routing MUX architectures, delay values, divider values, etc. Table 19-3 lists the 81 configuration bits in the CCC. Table 19-3 * Configuration Bits of IGLOO and ProASIC3 CCC Blocks Bit Number Control Function 80 RESET ENABLE 79 DYNCSEL 78 DYNBSEL 77 DYNASEL <76:74> VCOSEL [2:0] 73 STATCSEL 72 STATBSEL 71 STATASEL <70:66> DLYC [4:0] <65:61> DLYB {4:0] <60:56> DLYGLC [4:0] <55:51> DLYGLB [4:0] <50:46> DLYGLA [4:0] 45 XDLYSEL <44:40> FBDLY [4:0] <39:38> FBSEL <37:35> OCMUX [2:0] <34:32> OBMUX [2:0] <31:29> OAMUX [2:0] <28:24> OCDIV [4:0] <23:19> OBDIV [4:0] <18:14> OADIV [4:0] <13:7> FBDIV [6:0] <6:0> FINDIV [6:0] The embedded 81-bit shift register (for the dynamic configuration of the CCC) is accessible to the VersaTiles, which, in turn, have access to the UJTAG tiles. Therefore, the CCC configuration shift register can receive and load the new configuration data stream from JTAG. Dynamic reconfiguration eliminates the need to reprogram the device when reconfiguration of the CCC functional blocks is needed. The CCC configuration can be modified while the device continues to operate. Employing the UJTAG core requires the user to design a module to provide the configuration data and control the CCC configuration shift register. In essence, this is a userdesigned TAP Controller requiring chip resources. 1 9 -6 v1.1 UJTAG Applications in Actel's Low-Power Flash Devices Similar reconfiguration capability exists in the Actel ProASICPLUS(R) family. The only difference is the number of shift register bits controlling the CCC (27 in ProASICPLUS and 81 in IGLOO, ProASIC3, and Fusion). Fine Tuning In some applications, design constants or parameters need to be modified after programming the original design. The tuning process can be done using the UJTAG tile without reprogramming the device with new values. If the parameters or constants of a design are stored in distributed registers or embedded SRAM blocks, the new values can be shifted onto the JTAG TAP Controller pins, replacing the old values. The UJTAG tile is used as the "bridge" for data transfer between the JTAG pins and the FPGA VersaTiles or SRAM logic. Figure 19-5 shows a flow chart example for finetuning application steps using the UJTAG tile. In Figure 19-5, the TMS signal sets the TAP Controller state machine to the appropriate states. The flow mainly consists of two steps: a) shifting the defined instruction and b) shifting the new data. If the target parameter is constantly used in the design, the new data can be shifted into a temporary shift register from UTDI. The UDRSH output of UJTAG can be used as a shift-enable signal, and UDRCK is the shift clock to the shift register. Once the shift process is completed and the TAP Controller state is moved to the Update_DR state, the UDRUPD output of the UJTAG can latch the new parameter value from the temporary register into a permanent location. This avoids any interruption or malfunctioning during the serial shift of the new value. TAP Controller in Test_Logic_Reset State Set TAP state to SHIFT_DR Set TAP state to SHIFT_IR Shift data into TDI and record UTDI in a shift register Shift the user-defined instruction of tuning application Set TAP state in Update_DR Set TAP state to Update_IR UIREG Equal to the user-defined instruction Yes Latch the recorded data onto the location of stored parameter No Figure 19-5 * Flow Chart Example of Fine-Tuning an Application Using UJTAG v1.1 1 9 -7 UJTAG Applications in Actel's Low-Power Flash Devices Silicon Testing and Debugging In many applications, the design needs to be tested, debugged, and verified on real silicon or in the final embedded application. To debug and test the functionality of designs, users may need to monitor some internal logic (or nets) during device operation. The approach of adding design test pins to monitor the critical internal signals has many disadvantages, such as limiting the number of user I/Os. Furthermore, adding external I/Os for test purposes may require additional or dedicated board area for testing and debugging. The UJTAG tiles of low-power flash devices offer a flexible and cost-effective solution for silicon test and debug applications. In this solution, the signals under test are shifted out to the TDO pin of the TAP Controller. The main advantage is that all the test signals are monitored from the TDO pin; no pins or additional board-level resources are required. Figure 19-6 illustrates this technique. Multiple test nets are brought into an internal MUX architecture. The selection of the MUX is done using the contents of the TAP Controller instruction register, where individual instructions (values from 16 to 127) correspond to different signals under test. The selected test signal can be synchronized with the rising or falling edge of TCK (optional) and sent out to UTDO to drive the TDO output of JTAG. The test and debug procedure is not limited to the example in Figure 19-5 on page 19-7. Users can customize the debug and test interface to make it appropriate for their applications. For example, multiple test signals can be registered and then sent out through UTDO, each at a different edge of TCK. In other words, n signals are sampled with an FTCK / n sampling rate. The bandwidth of the information sent out to TDO is always proportional to the frequency of TCK. Internal Test Nets Instruction Decode UIREG[7:0] To Scope Channel TDO TDI URSTB UDRUPD UDRCK TMS TCK TRST D Q UDRCAP CLK UDRSH UTDI UTDO Figure 19-6 * UJTAG Usage Example in Test and Debug Applications SRAM Initialization Users can also initialize embedded SRAMs of the low-power flash devices. The initialization of the embedded SRAM blocks of the design can be done using UJTAG tiles, where the initialization data is imported using the TAP Controller. Similar functionality is available in ProASICPLUS devices using JTAG. The guidelines for implementation and design examples are given in the RAM Initialization and ROM Emulation in ProASICPLUS Devices application note. SRAMs are volatile by nature; data is lost in the absence of power. Therefore, the initialization process should be done at each power-up if necessary. 1 9 -8 v1.1 UJTAG Applications in Actel's Low-Power Flash Devices FlashROM Read-Back Using JTAG The low-power flash architecture contains a dedicated nonvolatile FlashROM block, which is formatted into eight 128-bit pages. For more information on FlashROM, refer to FlashROM in Actel's Low-Power Flash Devices. The contents of FlashROM are available to the VersaTiles during normal operation through a read operation. As a result, the UJTAG macro can be used to provide the FlashROM contents to the JTAG port during normal operation. Figure 19-7 illustrates a simple block diagram of using UJTAG to read the contents of FlashROM during normal operation. The FlashROM read address can be provided from outside the FPGA through the TDI input or can be generated internally using the core logic. In either case, data serialization logic is required (Figure 19-7) and should be designed using the VersaTile core logic. FlashROM contents are read asynchronously in parallel from the flash memory and shifted out in a synchronous serial format to TDO. Shifting the serial data out of the serialization block should be performed while the TAP is in UDRSH mode. The coordination between TCK and the data shift procedure can be done using the TAP state machine by monitoring UDRSH, UDRCAP, and UDRUPD. UJTAG Address Generation and Data Serlialization UIREG[7:0] Enable FROM RESET TDO TDI TMS TCK TRST URSTB UDRUPD Control UDRCK CLK UDRCAP SDI UDRSH Addr[6:0] Addr [6:0] Data[7:0] Data[7:0] SDO UTDI UTDO Figure 19-7 * Block Diagram of Using UJTAG to Read FlashROM Contents Conclusion Actel low-power flash FPGAs offer many unique advantages, such as security, nonvolatility, reprogrammablity, and low power--all in a single chip. In addition, IGLOO, Fusion, and ProASIC3 devices provide access to the JTAG port from core VersaTiles while the device is in normal operating mode. A wide range of available user-defined JTAG opcodes allows users to implement various types of applications, exploiting this feature of these devices. The connection between the JTAG port and core tiles is implemented through an embedded and hardwired UJTAG tile. A UJTAG tile can be instantiated in designs using the UJTAG library cell. This document presents multiple examples of UJTAG applications, such as dynamic reconfiguration, silicon test and debug, finetuning of the design, and RAM initialization. Each of these applications offers many useful advantages. v1.1 1 9 -9 UJTAG Applications in Actel's Low-Power Flash Devices Related Documents Application Notes RAM Initialization and ROM Emulation in ProASICPLUS Devices http://www.actel.com/documents/APA_RAM_Initd_AN.pdf Handbook Documents Boundary Scan in Low-Power Flash Devices http://www.actel.com/documents/LPD_BoundaryScan_HBs.pdf FlashROM in Actel's Low-Power Flash Devices http://www.actel.com/documents/LPD_FlashROM_HBs.pdf Part Number and Revision Date This document contains content extracted from the Device Architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the device. To improve usability for customers, the device architecture information has now been combined with usage information, to reduce duplication and possible inconsistencies in published information. No technical changes were made to the datasheet content unless explicitly listed. Changes to the application note content were made only to be consistent with existing datasheet information Part Number 51700094-020-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 (January 2008) 1 9 -1 0 Changes in Current Version (v1.1) Page The chapter was updated to include the IGLOO PLUS family and information regarding 15 k gate devices. N/A The "IGLOO Terminology" section and "ProASIC3 Terminology" section are new. 19-2 v1.1 Board-Level Requirements Application Note AC318 20 - Power-Up/-Down Behavior of ProASIC3/E Devices Introduction Actel ProASIC(R)3/E devices are flash-based FPGAs manufactured on a 0.13 m process node. ProASIC3/E FPGAs offer a single-chip, reprogrammable solution and support Level 0 live at powerup (LAPU) due to their nonvolatile architecture. Three main voltage pins are used by ProASIC3/E devices during normal operation:1 * VCC: Voltage supply to the FPGA core * VCCIBx: Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. * VMVx: Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. The I/O bank VMV pin must be tied to the VCCI pin of the same bank. Therefore, the supplies that need to be powered up/down during normal operation are VCC and VCCI. These power supplies can be powered up/down in any sequence during normal operation of ProASIC3/E FPGAs. During power-up, I/Os in each bank will remain tristated until the last supply (being either VCCIBx or VCC) reaches its functional activation voltage. Similarly, during power-down, I/Os of each bank are tristated once the first supply reaches its brownout deactivation voltage. ProASIC3/E devices exhibit very low transient current on each power supply during power-up. The peak value of the transient current depends on the device size, temperature, voltage levels, and power-up sequence. ProASIC3/E device inputs can be driven while the device is not powered. The driven I/Os do not pull up power planes, and the current draw is limited to very small leakage current. Therefore, ProASIC3/E FPGAs are suitable for applications in which cold-sparing is required. All ProASIC3E devices and the A3P030 device in the ProASIC3 family are also designed to be compatible with hotswap applications.2 Transient Current The source of transient current, also known as inrush current, varies depending on the FPGA technology. Due to their volatile technology, the internal registers in SRAM FPGAs must be initialized before configuration can start. This initialization is the source of significant inrush current in SRAM FPGAs during power-up. Due to the nonvolatile nature of flash technology, ProASIC3/E devices do not require any initialization at power-up, and there is very little or no crossbar current through PMOS and NMOS devices. Therefore, the transient current at power-up is significantly less than for SRAM FPGAs. Figure 20-1 on page 20-2 illustrates the types of power consumption by SRAM FPGAs vs. Actel's antifuse and flash FPGAs. 1. 2. For more information on ProASIC3/E device voltage supplies, refer to the appropriate datasheet located at http://www.actel.com/techdocs/ds. For more details on the levels of hot-swap compatibility in ProASCI3/E devices, refer to the "Hot-Swap Support" section in the I/O Structures chapter of the handbook for the device you are using. v1.3 2 0 -1 Power-Up/-Down Behavior of ProASIC3/E Devices Current Power-On Inrush SRAM FPGAs SRAM Actel FPGAs Active Frequency Dependent System Supply Voltage Configuration SRAM FPGAs Static Time (or frequency) Figure 20-1 * Types of Power Consumption in SRAM FPGAs and Actel Nonvolatile FPGAs Transient Current on VCC3 The preliminary characterization of the transient current on VCC has been performed on A3PE600PQ208 EAS devices. The transient current measurements are performed on two A3PE600-PQ208 EAS parts while all the device I/Os were internally pulled down. The preliminary measurements at typical conditions show that the maximum transient current on VCC, when the power supply is powered at ramp rates ranging from 15 V/ms to 0.15 V/ms, does not exceed the maximum standby current specified in the device datasheets. Refer to ProASIC3 DC and Switching Characteristics and ProASIC3E DC and Switching Characteristics for more information. Transient Current on VCCI3 The preliminary characterization of the transient current on VCCI has been performed on A3PE600PQ208 EAS devices, similar to VCC transient current measurements. The preliminary measurements at typical conditions show that the maximum transient current on VCCI, when the power supply is powered at ramp rates ranging from 33 V/ms to 0.33 V/ms, does not exceed the maximum standby current specified in the device datasheet. Refer to ProASIC3 DC and Switching Characteristics and ProASIC3E DC and Switching Characteristics for more information. 3. 2 0 -2 The "Transient Current on VCC" section will be updated after the full characterization of ProASIC3/E has been completed. v1.3 Power-Up/-Down Behavior of ProASIC3/E Devices I/O Behavior at Power-Up/-Down This section discusses the behavior of device I/Os, used and unused, during power-up/-down of VCC and VCCI. As mentioned earlier, VMVx and VCCIBx are tied together, and therefore, inputs and outputs are powered up/down at the same time. I/O State during Power-Up/-Down This section discusses the characteristics of I/O behavior during device power-up and power-down. Before the start of power-up, all I/Os are in tristate mode. The I/Os will remain tristated during power-up until the last voltage supply (VCC or VCCI) is powered to its functional level (power supply functional levels are discussed in the "Power-Up to Functional Time" section on page 20-4). After the last supply reaches the functional level, the outputs will exit the tristate mode and drive the logic at the input of the output buffer. Similarly, the input buffers will pass the external logic into the FPGA fabric once the last supply reaches the functional level. The behavior of user I/Os is independent of the VCC and VCCI sequence or the state of other voltage supplies of the FPGA (VPUMP and VJTAG). Figure 20-2 shows the output buffer behavior during power-up with 10 k external pull-down. In Figure 20-2, VCC is powered first, and VCCI is powered 5 ms after VCC. Figure 20-3 on page 20-4 shows the state of the I/O when VCCI is powered about 5 ms before VCC. In the circuitry shown in Figure 20-3 on page 20-4, the output is externally pulled down. During power-down, device I/Os become tristated once the first power supply (VCC or VCCI) drops below its brownout voltage level. The I/O behavior during power-down is also independent of voltage supply sequencing. Figure 20-2 * I/O State when VCC Is Powered before VCCI v1.3 2 0 -3 Power-Up/-Down Behavior of ProASIC3/E Devices Figure 20-3 * I/O State when VCCI Is Powered before VCC Power-Up to Functional Time At power-up, device I/Os exit the tristate mode and become functional once the last voltage supply in the power-up sequence (VCCI or VCC) reaches its functional activation level. Typical I/O behavior during power-up to functional time is illustrated in Figure 20-2 on page 20-3 and Figure 20-3. The functional level of the voltage supplies at power-up is designed to be 0.85 V 0.25 V for VCC and 0.9 V 0.3 V for the VCCI supply. Once the last voltage supply in the power-up sequence exceeds its functional level, the device I/Os will transition into a functional state. Therefore, the power-up-to-functional time is the time it takes for the last supply to power up from zero to its functional level. However, the functional level of the power supply during power-up may vary slightly within the specification in different ramp rates. ProASIC3/E devices meet Level 0 LAPU, i.e., can be functional prior to VCC reaching the regulated voltage required. This important advantage distinguishes ProASIC3/E flash devices from their SRAM-based counterparts. SRAM-based FPGAs, due to their volatile technology, require hundreds of milliseconds after power-up to configure the design bitstream before they become functional. Refer to Figure 20-4 on page 20-5 for more information. 2 0 -4 v1.3 Power-Up/-Down Behavior of ProASIC3/E Devices VCC =VCCI + VT Where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specifcation. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH /VOL , etc. VCC = 1.425 V Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCCI Figure 20-4 * I/O State as a Function of VCCI and VCC Voltage Levels v1.3 2 0 -5 Power-Up/-Down Behavior of ProASIC3/E Devices Brownout Voltage Brownout is a condition in which the voltage supplies are lower than normal, causing the device to malfunction as a result of insufficient power. In general, Actel does not guarantee the functionality of the design inside ProASIC3/E devices if voltage supplies are below their minimum recommended operating condition. Actel has performed measurements to characterize the brownout levels of FPGA power supplies. The brownout levels of the power supplies for ProASIC3/E devices are designed to be 0.75 V 0.25 V for VCC and 0.8 V 0.3 V for VCCI. For the purpose of characterization, a direct path from the device input to output is monitored while voltage supplies are lowered gradually. The brownout point is defined as the voltage level at which the output stops following the input. Characterization tests performed on two A3PE600-PQ208 EAS devices in typical operating conditions showed the brownout voltage levels to be within the specification. During device power-down, the device I/Os become tristated once the first supply in the powerdown sequence drops below its brownout deactivation voltage. PLL Behavior at Brownout Condition When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. The following sections explain PLL behavior during and after the brownout condition. VCCPLL and VCC Tied Together In this condition, both VCC and VCCPLL drop below the 0.75 V 0.25 V brownout level. During the brownout recovery, once VCCPLL and VCC reach the activation point (0.85 0.25 V) again, the PLL output lock signal may still remain low with the PLL output clock signal toggling. If this condition occurs, there are two ways to recover the PLL output lock signal: 1) Recycle the power supplies of the PLL (power off and on) by using the PLL POWNDOWN signal; 2) Turn off the input reference clock to the PLL and then turn it back on. Only VCCPLL Is at Brownout In this case, only VCCPLL drops below the 0.75 V 0.25 V brownout level and the VCC supply remains at nominal recommended operating voltage (1.5 V 0.075 V). In this condition, the PLL behavior after brownout recovery is similar to initial power-up condition, and the PLL will regain lock automatically after VCCPLL is ramped up above the activation level (0.85 0.25 V). No intervention is necessary in this case. Only VCC Is at Brownout In this condition, VCC drops below the 0.75 V 0.25 V brownout level and VCCPLL remains at nominal recommended operating voltage (1.5 V 0.075 V). During the brownout recovery, once VCC reaches the activation point again (0.85 0.25 V), the PLL output lock signal may still remain low with the PLL output clock signal toggling. If this condition occurs, there are two ways to recover the PLL output lock signal: 1) Recycle the power supplies of the PLL (power off and on) by using the PLL POWNDOWN signal; 2) Turn off the input reference clock to the PLL and then turn it back on. It is important to note that Actel recommends using a monotonic power supply or voltage regulator to ensure proper power-up behavior. Internal Pull-Up and Pull-Down ProASIC3/E device I/Os are equipped with internal weak pull-up/-down resistors that can be used by designers. If used, these internal pull-up/-down resistors will be activated during power-up, once both VCC and VCCI are passed their functional activation level. Similarly, during power-down, these internal pull-up/-down resistors will turn off once the first supply voltage falls below its brownout deactivation level. 2 0 -6 v1.3 Power-Up/-Down Behavior of ProASIC3/E Devices Cold-Sparing In cold-sparing applications, voltage can be applied to device I/Os before and during power-up. Cold-sparing applications rely on three important characteristics of the device: 1. I/Os must be tristated before and during power-up. 2. Voltage applied to the I/Os must not power up any part of the device. 3. Device reliability must not be compromised if voltage is applied to I/Os before or during power-up. As described in the "Power-Up to Functional Time" section on page 20-4, ProASIC3/E I/Os are tristated before and during power-up until the last voltage supply (VCC or VCCI) is powered up past its functional level. Furthermore, applying voltage to the ProASIC3/E I/Os does not pull up VCC or VCCI and, therefore, does not partially power up the device. Table 20-1 includes the cold-sparing test results on A3PE600-PQ208 EAS devices. In this test, leakage current on the device I/O and residual voltage on the power supply rails were measured while voltage was applied to the I/O before power-up. Table 20-1 * Cold-Sparing Test Results for A3PE600 Devices Residual Voltage (V) VCC VCCI Leakage Current Input 0 0.003 <1 A Output 0 0.003 <1 A Device I/O The reliability of ProASIC3/E I/Os is guaranteed if the voltage level, applied to the device I/Os, is less than 3.6 V, as specified in the product datasheets. Therefore, ProASIC3/E devices meet all three requirements stated earlier in this section and are suitable for cold-sparing applications. Hot-Swap Hot-swapping is the operation of hot insertion or hot removal of a card in a powered-up system. The I/Os need to be configured in hot-insertion mode if hot-swapping compliance is required. All ProASIC3E devices support hot-swapping, and the only ProASIC3 device supporting hot-swapping is the A3P030. For more details on the levels of hot-swap compatibility in ProASIC3/E devices, refer to the "Hot-Swap Support" section in the I/O Structures chapter of the handbook for the device you are using. Conclusion Actel's ProASIC3/E flash FPGAs provide an excellent programmable logic solution for a broad range of applications. In addition to high performance, low cost, security, nonvolatility, and single chip, they are live at power-up (meet Level 0 of the LAPU classification) and offer clear and easy-to-use power-up/-down characteristics. Unlike SRAM FPGAs, ProASIC3/E devices do not require any specific power-up/-down sequencing and have extremely low power-up inrush current in any power-up sequence. ProASIC3/E FPGAs also support both cold-sparing and hot-swapping for applications requiring these capabilities. v1.3 2 0 -7 Power-Up/-Down Behavior of ProASIC3/E Devices Related Documents Datasheets ProASIC3 DC and Switching Characteristics http://www.actel.com/documents/PA3GenSpecs_DS.pdf ProASIC3E DC and Switching Characteristics http://www.actel.com/documents/PA3EGenSpecs_DS.pdf Handbook Documents I/O Structures in IGLOO PLUS Devices http://www.actel.com/documents/IGLOOPLUS_IO_HBs.pdf I/O Structures in IGLOO and ProASIC3 Devices http://www.actel.com/documents/IGLOO_PA3_IO_HBs.pdf I/O Structures in IGLOOe and ProASIC3E Devices http://www.actel.com/documents/IGLOOe_PA3E_IO_HBs.pdf Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content Part Number 51700094-021-3 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.3) Page v1.2 (January 2008) The "Handbook Documents" section was updated to include the three different I/O Structure handbook chapters. 20-8 v1.1 (January 2008) The first sentence of the "PLL Behavior at Brownout Condition" section was updated to read, "When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V), the PLL output lock signal goes low and/or the output clock is lost." 20-6 v1.0 (January 2008) The "PLL Behavior at Brownout Condition" section was added. 20-6 2 0 -8 v1.3 ProASIC3/E SSO and Pin Placement Guidelines 21 - ProASIC3/E SSO and Pin Placement Guidelines Introduction Ground bounce and VCC bounce have always been present in digital integrated circuits (ICs). With the advance of technology and shrinking CMOS features, the speed of designs, I/O slew rates, and the size of I/O busses have increased significantly in the past few years. As a result, simultaneously switching outputs (SSOs) and their effects on signal integrity have become an important factor in any digital IC design. When SSOs are not properly designed into a board layout or digital IC, data corruption and system failure may result. To prevent SSO-induced issues in modern digital systems, designers must compromise an elegant board layout for reliability. An elegant board layout may include practices such as placing all inputs on one side of a chip, outputs on the opposite side, and all bus pins next to each other to make board layout simple. In today's digital systems, utilizing modern FPGAs such as Actel ProASIC(R)3/E may result in data corruption due to ground bounce, VCC bounce, or crosstalk. To design a reliable system for ProASIC3/E FPGAs, follow three simple rules: 1. Identify the SSOs in a design as early in the design cycle as possible, and spread them out across the entire die periphery. Avoid clusters of more than four adjacent SSO pins. 2. Identify sensitive (and usually asynchronous) system signals, and shield them from the effects of SSO (specific shielding techniques are discussed later in this document). 3. Use the lowest possible I/O slew rate and drive strength the design timing will support. Furthermore, relatively large lead inductance in PQ, TQ, and VQ packages makes these packages more vulnerable to SSOs and hence undesirable for high-speed designs or designs with a considerable number of SSOs. FG or BG packages are preferred in such designs because they show much better SSO performance. By following the above three rules, you will create reliable systems free from the effects of SSOs. The following sections cover specific SSO recommendations and mitigation techniques for designs that do not comply with these recommendations. SSO Effects The total number of SSOs for each bus is determined by identifying the outputs that are synchronous to a single clock domain, have their clock-to-out times within 200 ps of each other, and are placed next to each other on die pads that are on both sides of a sensitive I/O, as shown in Figure 21-1 on page 21-2. The sensitive I/O affected by SSO is sometimes referred to as the victim I/O or quiet I/O. SSOs may affect the victim I/O if the total number of SSOs on both sides of the victim I/O exceeds the ProASIC3/E SSO recommendation. It is important to note that the SSOs should be referenced to the die pads and not package pins, since neighboring package pins are not necessarily next to each other on the die (e.g., for BG and FG packages). This can be determined by using MultiView Navigator (MVN) in the Designer software, or die/package bonding diagrams provided by Actel. However, when routing traces on the board, it is important to note that SSOs on neighboring traces on the board may affect the quiet I/O surrounded by the SSO traces due to crosstalk or coupling. v1.0 2 1 -1 ProASIC3/E SSO and Pin Placement Guidelines Quiet I/O SSO Bus Figure 21-1 * Basic Block Diagram of Quiet I/O Surrounded by SSO Bus SSO Effect on Power and Ground for Quiet Outputs If SSOs toggle in one direction (either HIGH to LOW or LOW to HIGH), a significant amount of current quickly begins to flow to the ground or VCCI pins. This current is the sum of the simultaneous sink or source currents of the CMOS output buffers. The quick jump in current causes a voltage drop on the parasitic inductance between the board and die VCCI and ground (V = L x di/dt). For more information about the ground and VCCI bounce phenomenon, refer to the Simultaneous Switching Noise application note. The local fluctuations of the VCCI and ground levels may cause the signals on quiet outputs (measured with respect to the fluctuating VCCI and ground) to be misinterpreted as unwanted logic glitches. SSO Effect on Inputs SSOs may also affect quiet inputs due to the mutual inductance and capacitance on the package in addition to possible crosstalk of signal traces on the board. SSOs can cause logic glitches on any quiet inputs they surround. The unwanted glitches may cause functional failures if they are propagated through the input buffer. In SSO characterization of ProASIC3/E devices, glitches are considered errors if they cause internal latches in the design to trigger. SSO Effect on Output Delay (push-out) As the speed and I/O slew rate of digital ICs increase, effects of ground and VCCI bounce start to surface in digital system designs. One of these effects is output delay or push-out. The ground bounce and VCCI dip induced by SSO transitions creates a temporary collapse of internal VCCI and/or GND supply levels in the output buffers. This change in supply level increases the output buffer propagation delay time. It is important to note that push-out occurs on the SSO bus itself as well as on the victim outputs. Multiple factors, such as SSO bus frequency, drive strength, and slew rate, contribute to push-out. These factors can be adjusted to mitigate the push-out phenomenon. If the clock-to-out time of the victim output is important, the push-out delay should be considered in the timing budget of the design. SSO Effect on Minimum Input Slew Rate (input maximum rise/fall time) If the SSOs surrounding an input exceed the Actel recommendation, the minimum slew rate requirement for that input may be affected. The minimum input slew rate is the slowest signal transition time (from 0 to 1 or vice versa) at the input that does not cause unwanted logic glitches during signal transition. Figure 21-2 on page 21-3 illustrates the unwanted logic glitches with slow transition times. As shown, the logic glitch due to the slow input transition time may cause logic malfunction at edge-sensitive inputs (i.e., clock signals). If the sensitive inputs are affected by the SSO bus, the input minimum slew rate (maximum rise and fall time) should be reduced from what is listed in the device datasheet. Usually, synchronous, level-sensitive inputs are not prone to malfunction due to this phenomenon because their logic value is important only when sampled by a clock. 2 1 -2 v1.0 ProASIC3/E SSO and Pin Placement Guidelines Board-Level Input Input to Core Board-Level Input Input to Core Logic Time Figure 21-2 * Slow Rise/Fall Time Causing Glitches at the Output of an Input Buffer Shielding from SSOs When exposure of sensitive signals (e.g., asynchronous reset) to SSOs is inevitable, these signals need to be shielded from the SSOs to mitigate the unwanted effects. Shielding is basically separating the sensitive signals from SSOs using neighboring pins. Figure 21-3 shows a basic block diagram depicting a victim output in the presence of an SSO bus. Quiet I/O Shielding SSO Bus Figure 21-3 * Shielding Scheme There are different shielding techniques that can be used to protect the victim I/O from the SSO bus. Before describing these techniques, the concept of virtual ground and virtual VCCI should be understood. Virtual Ground Virtual ground, also known as soft ground, is used to improve noise performance. As opposed to a real ground, which is connected to planes within the package, a virtual ground is connected to the planes through the impedance of an I/O buffer. A virtual ground is a ground pin implemented using regular I/O ports. To implement a virtual ground, instantiate an output buffer (with highest drive strength and slew rate) in the design. Tie the input of this output buffer to zero within the design so the output buffer is constantly driving to the ground level. Virtual VCCI Virtual VCCI is similar to virtual ground. The only difference is that in the case of virtual VCCI, the output buffer is permanently driving to logic HIGH. In general, there are two shielding methods recommended by Actel: a) using GND pins or virtual grounds and b) using any VCCII, GND, VCCI, unused I/O, used (but not sensitive) I/O, or any combination of these pins. Shielding Using GND or Virtual Ground Pins When shielding sensitive I/Os from the SSO bus, GND or virtual ground pins can be used if required. In this case, two or three GND or virtual ground pins should be placed on each side of the quiet I/O. The shielding pins should be connected externally to the board-level ground. To prevent any board-level coupling or crosstalk noise on the sensitive I/Os, the shielding pins should be routed on v1.0 2 1 -3 ProASIC3/E SSO and Pin Placement Guidelines the board alongside the SSO bus for the whole length of the SSO traces and on the same board layer. These shielding traces should be connected to board ground at both ends of their length. Shielding Using Other Pins The type of shielding pins is not restricted to GND or virtual grounds. The shielding pins can also be VCCI, VCCII, virtual VCCI, unused I/Os, or used I/Os that are not sensitive to SSO effects (e.g., outputs driving LEDs). How to Use This Document The rest of this document is divided based on three different SSO effects: on outputs, on inputs, and on Clock Conditioning Circuits (CCCs). Each section includes tables that identify the recommended maximum number of SSOs and the required shielding if the number of SSOs exceeds the recommendation. The tables are categorized by device/package type (e.g., A3P600-FG484) and I/O configuration of the SSO bus (i.e., drive strength and slew rate). If the desired device/package combination cannot be found in the tables, choose the SSO recommendation for the closest package type and the next smaller die size. The following example describes two scenarios in which the SSO recommendation for another device/package can be used for a member of the ProASIC3/E family: 1. SSO guidelines for A3P250-PQ208 can be used when designing for A3P400-PQ208. 2. SSO guidelines for A3PE600-FG484 can be used when designing for A3PE1500-FG676. You should study this entire document, consider the desired device/package combination, define the worst-case SSO scenario, and use the SSO guidelines or shielding recommendations described in the tables. At the end of each section, guidelines are given on how to mitigate the effects of SSOs. Note that the data presented in this document is collected at nominal operating conditions (1.5 V core voltage and room temperature). CMOS transistors switch faster when cold, and therefore the edge rates become faster, so SSO effects are usually worse at lower temperatures. At the end of this document, some general board-level design guidelines are included. Actel recommends that you follow these guidelines when designing boards. SSO Effects on Outputs This section describes the SSO effects on other outputs. As stated in the "Shielding from SSOs" section on page 21-3, in ProASIC3 and ProASIC3E devices, the effects of SSOs on quiet outputs are categorized by ground bounce, VCCI bounce, and push-out. The following sections give the characteristics of SSO effects on outputs and provide guidelines on how to mitigate these effects. Ground and VCCI Bounce The most widely known effects of SSOs are ground and VCCI bounce. This section characterizes ProASIC3/E ground and VCCI bounce in the presence of SSOs. Since outputs with higher drive strength or faster slew rate source/sink higher current at the time of switching, SSOs are more disruptive when they are configured at higher drive strength and high slew rate. Table 21-1 on page 21-5 lists the number of SSOs causing specified levels of ground and VCCI bounce for various device, package, and SSO bus configurations. A disruptive ground bounce is one with a 1.25 V peak and 1 ns width--enough to trigger a high-speed input to change its value from zero to one. Similarly, a disruptive VCCI bounce causes oscillations on the quiet output (driving HIGH) with a magnitude of 2 V and width of 1 ns. These values are chosen based on Actel bench experiments using typical CMOS input sensitivity. 2 1 -4 v1.0 ProASIC3/E SSO and Pin Placement Guidelines Table 21-1 * Number of SSOs Causing Specified Ground and VCCI Bounce Device A3P250-PQ208 Drive Strength (mA) Slew Rate SSOs Causing GND Bounce SSOs Causing VCCI Bounce 24 High 4 2 Low 4 6 High 8 12 Low 16 16 High 6 4 Low 8 8 High 10 12 Low 14 16 High 24 10 Low 56 16 High >64 32 Low >64 >64 12 A3PE600-PQ208 24 12 A3PE600-FG484 24 12 Output Push-Out As described in the "SSO Effect on Output Delay (push-out)" section on page 21-2, if an output is surrounded by SSOs, the propagation delay of that output may be increased due to the noise on ground or VCCI. Figure 21-4 shows a simple diagram of the push-out effect. As shown, the push-out effect occurs only if the affected output toggles at the same time as the SSO bus. If the outputs surrounded by the SSO bus are not switching simultaneously (within 200 ps of each other) with the SSOs, the outputs are not affected by the push-out phenomenon. SSO Bus Without SSO Switching Output With SSO SSO Bus Figure 21-4 * SSO Push-Out Effect v1.0 2 1 -5 ProASIC3/E SSO and Pin Placement Guidelines Table 21-2 lists the increase in output delay for various SSO widths and configurations. Table 21-2 * SSO Push-Out Effect on an Output Surrounded by SSOs Package PQ208 Drive Strength (mA) Slew Rate 5 < SSOs < 10 SSOs 10 24 High <1.1 ns <1.8 ns Low <600 ps <1.2 ns High <900 ps <1.5 ns Low Negligible Negligible 8 Any Negligible Negligible Any Any Negligible Negligible 12 FG484 Notes: 1. Table data obtained when output load is 30 pF. 2. Larger output load increases the push-out effect. As an example, increasing the output load from 30 pF to 50 pF increases the push-out effect by 40%. Mitigating SSO Effects on Outputs Any effort to mitigate the SSO effect starts with eliminating the SSOs themselves. As described in "Introduction" on page 21-1, the SSOs should be spread across the die pads to avoid a large SSO bus concentrated in one area of the die. If possible, the clock-to-out timing of output busses should be staggered to reduce the number of SSOs in vicinity of sensitive outputs. If placement of sensitive outputs close to an SSO bus is inevitable, such outputs should be shielded from the bus. The shielding scheme to protect delay-sensitive outputs is similar to the guidelines presented in Table 21-3 on page 21-7. Whenever shielding is required, it is recommended to use GND or virtual ground pins as shielding. However, it is acceptable to use other shielding pins to protect sensitive outputs from SSOs. Segmenting SSO busses into smaller sections helps mitigate the SSO effect. The SSO bus can be segmented by inserting spacers among the SSO bus pins when placed on the die pads, as shown in Figure 21-5. The spacers can be GND or virtual ground, VCCI or virtual VCCI, unused I/O, or used I/Os that are not assigned to sensitive signals and do not toggle frequently or synchronously with the SSOs (e.g., signals driving LEDs). Quiet I/O Quiet I/O GND / Virtual GND SSO Bus Consolidated Unused/Used I/O SSO Bus Segmented Figure 21-5 * Example of Consolidated and Segmented SSO Bus Also, as described in Table 21-1 on page 21-5 and Table 21-2, FG and BG packages show much better characteristics with respect to SSO effects than PQ, TQ, or VQ packages. Therefore, for relatively high-speed designs or designs that have a significant number of wide output busses, FG or BG packages are strongly recommended. In addition to the logic design and device package type, board-level design is a key parameter in mitigating SSO effects. A well-designed PCB, capable of providing clean voltage supplies to the FPGA, is less susceptible to noise and therefore performs better. 2 1 -6 v1.0 ProASIC3/E SSO and Pin Placement Guidelines Board-Level Timing Analysis with Push-Out Since the push-out effect changes the clock-to-out timing of the signal surrounded by SSOs, designers should take care when performing board-level timing analysis for such outputs. The following are the Actel recommendations for calculating the clock-to-out timing of signals affected by push-out phenomena: * For board-level setup time calculations: Clock-to-out = worst-case clock-to-out reported by SmartTime + push-out delay * For board-level hold time calculations: Clock-to-out = best-case clock-to-out reported by SmartTime SSO Effects on Inputs As described in the "Virtual VCCI" section on page 21-3, if a quiet input is surrounded by SSOs, the logic driven by that input may experience a glitch when the SSO bus is switching. In ProASIC3/E devices in FG or BG packages, the inputs are not affected by an SSO bus. However, in PQ, TQ, and VQ packages, due to larger lead inductance, the SSOs may affect the inputs as described in the "SSO Effect on Inputs" section on page 21-2 and the "SSO Effect on Minimum Input Slew Rate (input maximum rise/fall time)" section on page 21-2. Table 21-3 describes the input shielding required for various SSO sizes with different I/O configurations. For example, in a PQ208 package, if a sensitive input (e.g., asynchronous reset) is surrounded by an SSO bus configured with 16 mA drive strength and low slew rate, two shielding pins are required on each side of the sensitive input to prevent any logic glitch on the reset line during transition of the SSO bus. Table 21-3 * Shielding Requirement Protecting Inputs from SSO1 Package PQ208 Slew Rate Shielding Required2 for 4 < SSO < 8 Shielding Required2 for SSO > 8 High 2 3 Low 2 2 High 2 3 Low 2 2 High 0 1 Low 0 0 8 Any 0 0 Any Any 0 0 Drive Strength (mA) 24 16 12 FG484 Notes: 1. Measurements were performed with a 3.3 V swing on the SSO bus. 2. Shielding pins required on the side of the sensitive input adjacent to the SSO bus. In PQ, TQ, and VQ packages, the sensitive inputs may be affected by SSOs as described in the "SSO Effect on Minimum Input Slew Rate (input maximum rise/fall time)" section on page 21-2. If the edge-sensitive inputs surrounded by an SSO bus rise or fall at the same time as an SSO transition, the maximum rise and fall times of those inputs should be less than 3 ns to avoid any glitches, as described the "SSO Effect on Minimum Input Slew Rate (input maximum rise/fall time)" section on page 21-2. Mitigating SSO Effects on Inputs As illustrated in Table 21-1 on page 21-5, in PQ, TQ, and VQ packages, inputs may be affected by a surrounding SSO bus, depending on the configuration and number of the SSOs. FG and BG packages show much better SSO characteristics due to smaller lead inductance. Therefore, designers are encouraged to use these packages in designs that have SSOs and are sensitive to v1.0 2 1 -7 ProASIC3/E SSO and Pin Placement Guidelines noise. It is also recommended that designers use the general guidelines described in "Introduction" on page 21-1 to eliminate SSO conditions that may cause system signal integrity problems. In addition, experiments at Actel show that in ProASIC3/E devices, inputs configured with the Schmitt Trigger option are slightly more tolerant to the noise induced by an SSO bus. Therefore, Actel recommends that designers select the Schmitt Trigger option for critical inputs surrounded by SSOs whenever possible. Whenever shielding is required by Table 21-3 on page 21-7, it is recommended to use GND or virtual ground pins as shielding (described in the "Shielding Using GND or Virtual Ground Pins" section on page 21-3); however, it is acceptable to use other shielding pins (as described in the "Shielding Using Other Pins" section on page 21-4) to protect the sensitive inputs from SSOs. Mitigating SSO Effects on Clock Conditioning Circuits In general, analog circuitry is more sensitive to noise than digital signals. As described in the "Shielding from SSOs" section on page 21-3, any sensitive signal surrounded by an SSO bus is affected by the noise induced by SSO activity. Therefore, if the analog power supply of the ProASIC3/E PLL (i.e., the VCCPLX pin) is surrounded by SSOs, the noise induced by the SSOs in the analog supply will cause an increase in the PLL output jitter. Experiments at Actel show that if the analog supply pin of the PLL is surrounded by two or more SSOs, the output jitter of the corresponding PLL will be increased beyond the jitter specification in the ProASIC3/E datasheet. Therefore, if PLLs are used in ProASIC3/E devices, the analog supplies of the PLLs used should be shielded from any SSOs by avoiding the placement of SSOs in neighboring I/O banks. Refer to Figure 21-6, Figure 21-7 on page 21-9, and Figure 21-8 on page 21-9 for more information about the I/O bank neighboring the PLL. Bank 0 Bank 1 Bank 0 A3P030 A3P060 A3P125 CCC/PLL "F" Bank 1 Bank 0 Bank 1 Note: The A3P030 device does not support a PLL (VCOMPLF and VCCPLF pins). Figure 21-6 * Naming Conventions of ProASIC3 Devices with Two I/O Banks 2 1 -8 v1.0 ProASIC3/E SSO and Pin Placement Guidelines Bank 0 Bank 3 Bank 1 A3P250 A3P400 A3P600 A3P1000 CCC/PLL "F" Bank 3 Bank 1 Bank 2 Figure 21-7 * Naming Conventions of ProASIC3 Devices with Four I/O Banks Bank 0 Bank 0 CCC/PLL 'B' "B" Bank 1 Bank 1 A3PE600 A3PE1500 A3PE600 A3PE3000 Bank 3 CCC/PLL 'C' "C" Bank 6 CCC/PLL "F" 'F' Bank 2 Bank 7 CCC/PLL "A" 'A' Bank55 Bank Bank 4 JTAG JTAG CCC/PLL 'E' "E" JTAG CCC/PLL 'D' "D" Figure 21-8 * User I/O Naming Conventions of ProASIC3E Devices v1.0 2 1 -9 ProASIC3/E SSO and Pin Placement Guidelines Conclusion As digital designs get faster and larger, SSOs and their effects become a more critical part of system signal integrity analysis. This application note provides data characterizing and predicting the effects of SSOs on sensitive inputs and outputs in ProASIC3/E FPGAs. SSO effects should be mitigated to ensure the functionality of the design; this application note provides specific techniques for doing so. SSO mitigation techniques should be conducted in parallel with chip-level and board-level design, as they play important roles in providing a clean digital system. For board-level design guidelines, refer to the Board-Level Considerations application note. Due to the nature of SSOs, FG and BG packages are more tolerant to SSO effects than PQ or TQ packages. Therefore, for high-speed designs or designs with large numbers of SSOs, FG and BG packages are strongly recommended. Related Documents Application Notes Simultaneous Switching Noise http://www.actel.com/documents/SSN_AN.pdf Board-Level Considerations http://www.actel.com/documents/BoardLevelCons_AN.pdf Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content. Part Number 51700094-022-0 Revised January 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version 51900140-1/6.05 2 1 -1 0 Changes in Current Version (v1.0) Page Figure 21-6 * Naming Conventions of ProASIC3 Devices with Two I/O Banks, 21-8 - 21-9 Figure 21-7 * Naming Conventions of ProASIC3 Devices with Four I/O Banks, and Figure 21-8 * User I/O Naming Conventions of ProASIC3E Devices were updated. v1.0 Application Note AC312 22 - Metastability Characterization Report for Actel Flash FPGAs Introduction Whenever asynchronous data is registered by a clocked flip-flop, there is a probability of setup or hold time violation on that flip-flop. In applications such as synchronization or data recovery, due to the asynchronous nature of the data input to the flip-flops, the data transition time is unpredictable with respect to the active edge of the clock. The susceptibility of a circuit to reaching this metastable state can be described using a probabilistic equation. Setup or hold violations cause the output of the flip-flop to enter a symmetrically balanced transient state, called a metastable state. The metastable state is manifested in a bistable device by the outputs glitching, going into an undefined state somewhere between 1 and 0, oscillating, or by the output transition being delayed for an indeterminable time. Once the flip-flop has entered the metastable state, the probability that it will still be metastable later has been shown to be an exponentially decreasing function of time. Because of this property, a designer should simply wait for additional time after the specified propagation delay before sampling the flip-flop output so that the designer can be assured that the likelihood of metastable failure is remote enough to be tolerable. The additional time of waiting becomes shorter, even though still more than zero, as the technology improves and semiconductor devices reach higher ranges of speed. This document discusses a description of metastability equations followed by metastability characterization of ProASIC,(R) ProASICPLUS(R), ProASIC3, and ProASIC3E FPGAs. This application note also provides examples on the usage of metastability equations. Theory of Metastability In general, the mean time between failures (MTBF) should be defined statically. Figure 22-1 on page 22-2 depicts a simple circuit, used to synchronize asynchronous data with the system clock. EQ 22-1 shows the relation between MTBF and the clock-to-out settling time of a flip-flop: MTBF = e (Ts / ) / (To x fd x fc) EQ 22-1 Ts = Tco + Tmet EQ 22-2 In EQ 22-1 and EQ 22-2: Ts = Total flip-flop output settling time Tco = Flip-flop clock-to-out delay Tmet = Additional settling time added to the normal clock-to-out delay of the flip-flop before sampling the output of the flip-flop t = Metastable decay constant. T0 = Metastability aperture at Tco = 0 ns (this parameter represents the likelihood that a flipflop will enter a metastable state) fd = Data transition rate (twice the data frequency for periodic signals, since there are two transitions per period) fc = Clock frequency v1.0 2 2 -1 Metastability Characterization Report for Actel Flash FPGAs Async Data Sync Data Tco fd D fc Q D CLK Q CLK Figure 22-1 * Example of Synchronization Circuit As mentioned earlier, the aperture represents the likelihood of the flip-flop entering a metastable state. The aperture is defined as a time window within the clock period. Data transitioning inside the aperture will cause the flip-flop output settling time to be greater than Tco + Tmet. The aperture is calculated by recording the number of instances in which the settling time exceeds the specified Tco + Tmet. The metastability aperture decreases exponentially as the allowed settling time (Tco + Tmet) increases: Aperture = To x e-(Tco + Tmet)/ EQ 22-3 If the data transition occurs within the aperture, the flip-flop will stay metastable beyond the allocated settling time (Tco + Tmet); and therefore, the second flip-flop would register invalid data (Figure 22-1). The probability of an asynchronous data transition is uniformly distributed over the clock period. Therefore, the probability of a single data transition occurring in the metastable aperture is calculated by EQ 22-4: p = aperture / Tc EQ 22-4 where Tc is the clock period. In each clock cycle, the failure occurs if the data transition time is within the aperture. Therefore, the number of failures in one clock cycle can be derived by EQ 22-5: ne = n x p = n x (aperture / Tc) EQ 22-5 where ne represents the number of errors per clock cycle, and n is the number of data transitions per clock period (fd / fc). The number of clock cycles in the operation time (N) is the total time divided by the clock period, or N = Toperation / Tc EQ 22-6 Combining EQ 22-5 and EQ 22-6 results in the total number of failures per operation time (Ne): Ne = N x ne = (Toperation / Tc) x (fd / fc) x (aperture / Tc) EQ 22-7 Since Tc = 1 / fc, EQ 22-7 can be simplified to Ne = Toperation x fd x fc x aperture EQ 22-8 MTBF is defined as the operation time divided by the number of failures, or MTBF = 1/ (fd x fc x aperture) = 1/ (T0 x e-(Tco + Tmet) / x fd x fc) EQ 22-9 2 2 -2 v1.0 Metastability Characterization Report for Actel Flash FPGAs FPGA Metastability Characterization Like other FGPA manufacturers, to absorb the fixed value the of eTco term, Actel simplifies EQ 22-9 on page 22-2 to the following form: MTBF = eC2 * Tmet / (C1 x fd x fc) EQ 22-10 where C2 is a constant inversely proportional to the metastability decay constant, and C1 is the proportionality constant, which is similar to aperture. The FPGA metastability characterization is a series of tests conducted to identify the value of C1 and C2. There are several environmental and test condition factors that influence the characterization. These factors include but are not limited to the rise time of data and clock signals, input voltage levels, and operating voltage and temperature. Moreover, increased system noise due to switching of both internal nodes and I/Os can influence the metastability results. Therefore, it is essential to provide a suitable environment for testing. Test Design Description Figure 22-2 shows a schematic of the test circuit used to characterize the metastability in Actel devices. The propagation delay, operating under specified setup and hold time, is measured from the output of flip-flop DFF#1 to the input of flip-flop DFF#3. This value is denoted by EQ 22-11: Tmin = Tcof(DFF#1) + Tdelay + Tsu(DFF#3) EQ 22-11 where Tdelay is the propagation delay from output of DFF#1 to input of DFF#3, Tcof is the clock-toout delay of DFF#3, and Tsu represents the setup time requirement of DFF#3. Tmin corresponds to the Tco in EQ 22-9 on page 22-2 and is the reference time to which the additional settling time, Tmet, is added for characterization of metastability. Asynchronous Data DFF#1 DFF#2 D D Q CLK A B Q CLK Observation Node Wired to I/Os Enable DFF#3 Y Inverting Delay Buff Metastability Event Counter (20 bits) A CLOCK Y D Q CLK RESET Metastable Catching Dff 30-bit (billion cycle) Measurement Timer Figure 22-2 * Test Circuit DFF#2 is clocked on the same edge as DFF#1. Conversely, DFF#3 must resolve the signal driven from the metastable DFF#1 before the falling clock edge. As can be seen in the design in Figure 22-2, v1.0 2 2 -3 Metastability Characterization Report for Actel Flash FPGAs Tmin + Tmet is the difference between the rising and falling edge of the clock. Therefore, it can be easily set or measured by adjusting the duty cycle of the clock signal. A detectable metastable event occurs when DFF#2 and DFF#3 are in the SAME state. In the expected operation, DFF#2 and DFF#3 are in opposite states due to the inverter in the DFF#3 input data path. The XNOR gate allows the event counter to record these metastable events. After a billion clock cycles, the counter is read and the MTBF is calculated. In this test, Tmin was resolved to within 0.01% of the duty cycle at 10 MHz. This translates to an error of 10 ps. The other test setup parameters were as follows: * Clock and data inputs were driven from independent pulse generators (<1 ns rise time). * Clock input levels were from 0 V to 2.5 V. These levels were required due to the impedance matching of Actel's test fixture. Data input levels were 0 V to 3.3 V. * FPGA power supplies for all tests were at VDDP = 3.3 V and VDD = 2.5 V. Metastability Measurement Results EQ 22-10 on page 22-3 can be reformed into EQ 22-12: ln(MTBF) = C2 x Tmet - ln(C1 x fd x fc) EQ 22-12 The plot of EQ 22-12 is a linear relationship between ln(MTBF) and Tmet, where C2 is the slope of the line. Figure 22-3 shows the plot of EQ 22-12 for Actel ProASIC and ProASICPLUS FPGA families. C1 and C2 can be calculated from any two data points. 6 4 ln(MTBF) 2 0 -2 0 0.2 0.4 0.6 0.8 -4 1.2 1.4 PLUS 1.6 ProASIC (0.22 m) ProASIC (0.25 m) -6 -8 -10 -12 Tmet Figure 22-3 * Metastability Comparison of Actel FPGA Families 2 2 -4 1 v1.0 Metastability Characterization Report for Actel Flash FPGAs The metastability theory indicates that C1 and C2 are independent of the test clock and data frequency. The test results concur within experimental tolerances. The calculations of C1 and C2 are given in Table 22-1. Table 22-1 * Metastability Coefficients for Actel Flash FPGAs fc = 10 MHz Device Family C1 (s) C2 (s) ProASIC 9.95E-11 1.03E+10 ProASICPLUS 1.56E-11 9.148E+09 ProASIC3/E Core Registers 9.11E-12 1.57E+10 ProASIC3/E I/O Registers 2.25E-12 1.91E+10 Examples of Metastability Coefficients Usage Metastability shows a statistical nature, and designers should allow enough additional time (Tmet) that the likelihood of metastable failure is remote enough to be tolerable by the design specification. For example, consider that the simple circuit in Figure 22-1 on page 22-2 is implemented in a ProASICPLUS device to synchronize an asynchronous data input to the FPGA. The following parameters are given to designer by either design specification or post-layout timing analysis: Tco = 10 ns, corresponding to a clock frequency of 100 MHz Asynchronous data transition rate = 12.5 MHz Tolerable MTBF = 1 year If the designer does not allow additional sampling time (Tmet = 0 ns) and run the clock at the rate of 100 MHz, EQ 22-12 on page 22-4 will result in MTBF = 51.2 s. This means that a metastability error will occur at the output of the second flip-flop every 51.2 s. This value exceeds the required MTBF of one year indicated in the design specification. To meet this requirement, the designer needs to allow additional Tmet in the sampling time, which can be calculated as follows: 1 year = 365 x 24 x 3,600 = 31,536,000 seconds ln 31,536,000 = 9.148E+09 x Tmet - ln (1.56E-11 x 100E6 x 12.5E6) Tmet = 2.96 ns Therefore, an additional 3 ns sampling time will fulfill the required MTBF. Part Number and Revision Date This document was previously published as an application note describing features and functions of the device, and as such has now been incorporated into the device handbook format. No technical changes have been made to the content. Part Number 51700094-023-0 Revised January 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.0) Page 5190062-1/5.04 Table 22-1 * Metastability Coefficients for Actel Flash FPGAs was updated to include ProASIC3/E information. 22-5 5190062-0 This document was updated to provide a detailed description of the calculations being made. v1.0 2 2 -5 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. w w w. a c t e l . c o m Actel Corporation Actel Europe Ltd. Actel Japan Actel Hong Kong 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 EXOS Ebisu Buillding 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn 51700097-004-3/3.08