74LVCH16244ADGG - Philips Semiconductors / NXP Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of 2002 Oct 30 2003 Jan 30

INTEGRATED CIRCUITS

74LVC16244A; 74LVCH16244A

16-bit buffer/line driver; 5 V

input/output tolerant (3-state)

2003 Jan 30 2

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

FEATURES

•5 V tolerant inputs/outputs for interfacing with 5 V logic

•Wide supply voltage range from 1.2 to 3.6 V

•CMOS low power consumption

•MULTIBYTETM flow-through standard pin-out

architecture

•Low inductance multiple power and ground pins for

minimum noise and ground bounce

•Direct interface with TTL levels

•All data inputs have bushold (74LVCH16244A only).

•Complies with JEDEC standard no. 8-1A

•ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

DESCRIPTION

The 74LVC(H)16244A is a high-performance, low power,

low voltage, Si-gate CMOS device, superior to most

advanced CMOS compatible TTL families. Inputs can be

driven from either 3.3 or 5 V devices. In 3-state operation,

outputs can handle 5 Volt. These features allow the use of

these devices as a mixed 3.3 and 5 V environment.

The 74LVC(H)16244A is a 16-bit non-inverting buffer/line

driver with 3-state outputs. The device can be used as four

4-bit buffers, two 8-bit buffers or one 16-bit buffer. The

3-state outputs are controlled by the output enable inputs

1OE and 2OE. A HIGH on nOE causes the outputs to

assume a high-impedance OFF-state.

The 74LVC(H)16244A is identical to the 74LVC16240A

but has non-inverting outputs.

The 74LVCH16244A bushold data inputs eliminates the

need for external pull-up resistors to hold unused inputs.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25°C; tr=t

f≤2.5 ns.

Note

1. CPD is used to determine the dynamic power dissipation (PDin µW).

PD=C

PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in Volts;

N = total switching outputs;

Σ(CL×VCC2×fo) = sum of the outputs.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

tPHL/tPLH propagation delay nAnto nYnCL= 50 pF; VCC = 3.3 V 3.0 ns

CIinput capacitance 5.0 pF

CPD power dissipation capacitance per gate VI= GND to VCC; note 1 25 pF

2003 Jan 30 3

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

ORDERING INFORMATION

FUNCTION TABLE

See note 1.

Note

1. H = HIGH voltage level;

L = LOW voltage level;

X = don’t care;

Z = high-impedance OFF-state.

TYPE NUMBER PACKAGE

TEMPERATURE

RANGE PINS PACKAGE MATERIAL CODE

74LVC16244ADL −40 to +85 °C 48 SSOP48 plastic SOT370-1

74LVCH16244ADL −40 to +85 °C 48 SSOP48 plastic SOT370-1

74LVC16244ADGG −40 to +85 °C 48 TSSOP48 plastic SOT362-1

74LVCH16244ADGG −40 to +85 °C 48 TSSOP48 plastic SOT362-1

74LVC16244AEV −40 to +85 °C 56 VFBGA56 plastic SOT702-1

74LVCH16244AEV −40 to +85 °C 56 VFBGA56 plastic SOT702-1

INPUT OUTPUT

nOE nAnnYn

LLL

LHH

HXZ

2003 Jan 30 4

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

PINNING

SYMBOL PINS BALLS DESCRIPTION

1OE 1 A1 output enable input (active LOW)

n.c. −A2, A3, A4, A5, E3, E4, F3,

F4, K2, K3, K4, K5 not connected

1Y02 B2 data output

1Y13 B1 data output

GND 4, 10, 15, 21, 28, 34, 39, 45 B3, B4, D3, D4, G3, G4, J3, J4 ground (0 V)

1Y25 C2 data output

1Y36 C1 data output

VCC 7, 18, 31, 42 C3, H3, C4, H4 supply voltage

2Y08 D2 data output

2Y19 D1 data output

2Y211 E2 data output

2Y312 E1 data output

3Y013 F1 data output

3Y114 F2 data output

3Y216 G1 data output

3Y317 G2 data output

4Y019 H1 data output

4Y120 H2 data output

4Y222 J1 data output

4Y323 J2 data output

4OE 24 K1 output enable input (active LOW)

3OE 25 K6 output enable input (active LOW)

4A326 J5 data input

4A227 J6 data input

4A129 H5 data input

4A030 H6 data input

3A332 G5 data input

3A233 G6 data input

3A135 F5 data input

3A036 F6 data input

2A337 D6 data input

2A238 E5 data input

2A140 D6 data input

2A041 D5 data input

1A343 C6 data input

1A244 C5 data input

1A146 B6 data input

1A047 B5 data input

2OE 48 A6 output enable input (active LOW)

2003 Jan 30 5

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

handbook, halfpage

16244

MNA706

1Y0

1Y1

GND

1Y2

1Y3

VCC

2Y0

2Y1

GND

2Y2

2Y3

3Y0

3Y1

GND

3Y2

3Y3

VCC

4Y0

4Y1

GND

4Y2

4Y3

4OE

1A0

1A1

GND

1A2

1A3

VCC

2A0

2A1

GND

2A2

2A3

3A0

3A1

GND

3A2

3A3

VCC

4A0

4A1

GND

4A2

4A3

3OE

1OE 2OE

Fig.1 Pin configuration SSOP/TSSOP48.

MNA702

1OE

1Y1

1Y3

2Y1

2Y3

3Y0

3Y2

4Y0

4Y2

4OE

1Y0

1Y2

2Y0

2Y2

3Y1

3Y3

4Y1

4Y3

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

1A0

1A2

2A0

2A2

3A1

3A3

4A1

4A3

2OE

1A1

1A3

2A1

2A3

3A0

3A2

4A0

4A2

123456

3OE

Fig.2 Pin configuration VFBGA56.

2003 Jan 30 6

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

handbook, full pagewidth

1A3

1A2

1A1

1A01Y0

1Y1

1Y2

1Y3

1OE

2A3

2A2

2A1

2A02Y0

2Y1

2Y2

2Y3

2OE

3A3

3A2

3A1

3A03Y0

3Y1

3Y2

3Y3

3OE

4A3

4A2

4A1

4A04Y0

4Y1

4Y2

4Y3

4OE

MNA703

Fig.3 Logic symbol.

2003 Jan 30 7

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

handbook, halfpage

MNA704

37 12

2A3

1A0

1A1

1A2

1A3

2A0

2A1

2A2

2Y3

2Y2

2Y1

2Y0

1Y3

1Y2

1Y0

1Y1

4A3

3A0

3A1

3A2

3A3

4A0

4A1

4A2

4Y3

4Y2

4Y1

4Y0

3Y3

3Y2

3Y0

3Y1

4OE 4EN

3OE 3EN

1OE 11EN

2OE 48 2EN

Fig.4 Logic symbol (IEEE/IEC).

handbook, halfpage

to internal circuit

MNA705

VCC

data input

Fig.5 Bushold circuit.

2003 Jan 30 8

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

RECOMMENDED OPERATING CONDITIONS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. Above 60 °C the value of PD derates linearly with 5.5 mW/K.

3. Above 70 °C the value of PD derates linearly with 1.8 mW/K.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCC supply voltage for maximum speed performance 2.7 3.6 V

for low voltage applications 1.2 3.6 V

VIinput voltage 0 5.5 V

VOoutput voltage output HIGH or LOW state 0 VCC V

output 3-state 0 5.5 V

Tamb operating ambient temperature in free air −40 +85 °C

tr,t

finput rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V

VCC = 2.7 to 3.6 V 0 10 ns/V

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCC supply voltage −0.5 +6.5 V

IIK input diode current VI<0 −−50 mA

VIinput voltage note 1 −0.5 +6.5 V

IOK output diode current VO>V

CC or VO<0 −±50 mA

VOoutput voltage output HIGH or LOW state;

note 1 −0.5 VCC + 0.5 V

output 3-state; note 1 −0.5 +6.5 V

IOoutput source or sink current VO=0toV

CC −±50 mA

ICC, IGND VCC or GND current −±100 mA

Tstg storage temperature −65 +150 °C

Ptot power dissipation;

SSOP and TSSOP package temperature range from

−40 to +85 °C; note 2 −500 mW

VFBGA package temperature range from

−40 to +85 °C; note 3 −1000 mW

2003 Jan 30 9

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

DC CHARACTERISTICS

At recommended operating conditions; voltage are referenced to GND (ground=0V).

Notes

1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.

2. For bushold parts, the bushold circuit is switched off when VI>V

CC allowing 5.5 V on the input terminal.

3. Valid for data inputs of bushold parts (74LVCH16244A) only.

4. For data inputs only, control inputs do not have a bushold circuit.

5. The specified sustaining current at the data input holds the input below the specified VI level.

6. The specified overdrive current at the data input forces the data input to the opposite input state.

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT

OTHER VCC (V)

Tamb =−40 to +85 °C

VIH HIGH-level input voltage 1.2 VCC −−V

2.7 to 3.6 2.0 −−V

IL LOW-level input voltage 1.2 −−GND V

2.7 to 3.6 −−0.8 V

VOH HIGH-level output voltage VI=V

IH or VIL

IO=−12 mA 2.7 VCC −0.5 −−V

=−100 µA 3.0 VCC −0.2 VCC −V

IO=−18 mA 3.0 VCC −0.6 −−V

=−24 mA 3.0 VCC −0.8 −−V

OL LOW-level output voltage VI=V

IH or VIL

IO=12mA 2.7 −−0.40 V

IO= 100 µA 3.0 −−0.20 V

IO=24mA 3.0 −−0.55 V

IIinput leakage current VI= 5.5 Vor GND; note 2 3.6 −±0.1 ±5µA

IOZ 3-state output OFF-state

current VI=V

IH or VIL;

VO= 5.5 Vor GND 3.6 −0.1 ±5µA

Ioff power off leakage supply VIor VO= 5.5 V 0.0 −0.1 ±10 µA

ICC quiescent supply current VI=V

CC or GND; IO= 0 3.6 −0.1 20 µA

∆ICC additional quiescent supply

current per pin VI=V

CC−0.6V; IO= 0 2.7 to 3.6 −5 500 µA

IBHL bushold LOW sustaining

current VI= 0.8 V; notes 3, 4 and 5 3.0 75 −−µA

BHH bushold HIGH sustaining

current VI= 2.0 V; notes 3, 4 and 5 3.0 −75 −−µA

BHLO bushold LOW overdrive

current notes 3, 4 and 6 3.6 500 −−µA

BHHO bushold HIGH overdrive

current notes 3, 4 and 6 3.6 −500 −−µA

2003 Jan 30 10

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

AC CHARACTERISTICS

GND = 0 V; tr=t

f≤2.5 ns.

Note

1. Typical values are measured at VCC = 3.3 V and Tamb =25°C.

AC WAVEFORMS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

WAVEFORMS VCC (V)

Tamb =−40 to +85 °C

tPHL/tPLH propagation delay nAnto nYnsee Figs 6 and 8 1.2 −11.0 −ns

2.7 1.5 −5.5 ns

3.0 to 3.6 1.5 3.0(1) 4.5 ns

tPZH/tPZL 3-state output enable time nOE to nYnsee Figs 7 and 8 1.2 −15.0 −ns

2.7 1.5 −6.5 ns

3.0 to 3.6 1.5 3.5(1) 5.5 ns

tPHZ/tPLZ 3-state output disable time nOE to nYnsee Figs 7 and 8 1.2 −10.0 −ns

2.7 1.5 −6.2 ns

3.0 to 3.6 1.5 3.7(1) 5.2 ns

handbook, halfpage

MNA171

nAn input

nYn output

tPLH tPHL

GND

VOH

VOL

Fig.6 The input nAn to output nYn propagation delays.

VOL and VOH are typical output voltage drop that occur with the output load.

VCC VMINPUT

VItr=t

1.2 V 0.5 ×VCC VCC ≤2.5 ns

2.7 V 1.5 V 2.7 V ≤2.5 ns

3.0 to 3.6 V 1.5 V 2.7 V ≤2.5 ns

2003 Jan 30 11

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

handbook, full pagewidth

MNA362

tPLZ

tPHZ

outputs

disabled outputs

enabled

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

nOE input

VOL

VOH

VCC

GND

tPZL

tPZH

Fig.7 3-state enable and disable times.

VOL and VOH are typical output voltage drop that occur with the output load.

VCC VMINPUT

VItr=t

1.2 V 0.5 ×VCC VCC ≤2.5 ns

2.7 V 1.5 V 2.7 V ≤2.5 ns

3.0 to 3.6 V 1.5 V 2.7 V ≤2.5 ns

VX=V

OL +0.3VatV

CC ≥2.7 V;

VX=V

OL +0.1VatV

CC < 2.7 V;

VY=V

OH −0.3VatV

CC ≥2.7 V;

VY=V

OH −0.1VatV

CC < 2.7 V.

2003 Jan 30 12

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

handbook, full pagewidth

VEXT

VCC

VIVO

MNA616

D.U.T.

PULSE

GENERATOR

Fig.8 Load circuitry for switching times.

Definitions for test circuits:

RL= Load resistor.

CL= Load capacitance including jig and probe capacitance.

RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.

VCC VICLRLVEXT

tPLH/tPHL tPZH/tPHZ tPZL/tPLZ

1.2 V VCC 50 pF 500 Ωopen GND 2 ×VCC

2.7 V 2.7 V 50 pF 500 Ωopen GND 2 ×VCC

3.0 to 3.6 V 2.7 V 50 pF 500 Ωopen GND 2 ×VCC

2003 Jan 30 13

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

PACKAGE OUTLINES

UNIT A

(1)

QZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 0.4

0.2 2.35

2.20 0.25 0.3

0.2 0.22

0.13 16.00

15.75 7.6

7.4 0.635 1.4 0.25

10.4

10.1 1.0

0.6 1.2

1.0 0.85

0.40 8

0.18 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT370-1 95-02-04

99-12-27

(1)

48 25

MO-118

detail X

(A )

pin 1 index

0 5 10 mm

scale

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1

max.

2.8

2003 Jan 30 14

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

UNIT A

(1)

(2)

QZywvθ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 0.15

0.05 0.2

0.1 8

0.1

DIMENSIONS (mm are the original dimensions).

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

SOT362-1 95-02-10

99-12-27

detail X

(A )

0.25

124

48 25

pin 1 index

1.05

0.85 0.28

0.17 0.2

0.1 12.6

12.4 6.2

6.0 0.5 1 0.25

8.3

7.9 0.50

0.35 0.8

0.4

0.08

0.8

0.4

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1

max.

1.2

2.5

5 mm

scale

MO-153

2003 Jan 30 15

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

0.65

A1bA2

UNIT D ye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

01-06-25

02-08-08

IEC JEDEC JEITA

mm 10.3

0.2 0.7

0.6 4.6

4.4

7.1

6.9

0.45

0.35 0.08 0.1

3.25

5.85

DIMENSIONS (mm are the original dimensions)

SOT702-1 MO-225

0.15

0.08

w0 2.5 5 mm

scale

SOT702-1

VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm

max.

AA2

detail X

y1C

246135

ball A1

index area

1/2 e

∅ vM

∅ wM

ball A1

index area

2003 Jan 30 16

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

SOLDERING

Introduction to soldering surface mount packages

Thistextgivesaverybriefinsighttoacomplextechnology.

A more in-depth account of soldering ICs can be found in

our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certainsurfacemountICs,butitisnotsuitableforfinepitch

SMDs. In these situations reflow soldering is

recommended.

Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

totheprinted-circuit board by screenprinting,stencilling or

pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

Wave soldering

Conventional single wave soldering is not recommended

forsurface mount devices (SMDs) orprinted-circuitboards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

•Forpackages with leads on foursides,thefootprintmust

be placed at a 45°angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

2003 Jan 30 17

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

Suitability of surface mount IC packages for wave and reﬂow soldering methods

Notes

1. Formoredetailedinformation on the BGApackagesreferto the

“(LF)BGAApplicationNote

”(AN01026);ordera copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,

the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE(1) SOLDERING METHOD

WAVE REFLOW(2)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable

DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,

HTSSOP, HVQFN, HVSON, SMS not suitable(3) suitable

PLCC(4), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(4)(5) suitable

SSOP, TSSOP, VSO, VSSOP not recommended(6) suitable

2003 Jan 30 18

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVEL DATA SHEET

STATUS(1) PRODUCT

STATUS(2)(3) DEFINITION

I Objective data Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

DEFINITIONS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

attheseoratanyotherconditionsabovethose given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Application information  Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

norepresentation orwarrantythatsuchapplications willbe

suitable for the specified use without further testing or

modification.

DISCLAIMERS

Life support applications  These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductorscustomersusingorsellingthese products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes  Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

products, conveys no licence or title under any patent,

makes no representations or warranties that these

products are free from patent, copyright, or mask work

right infringement, unless otherwise specified.

2003 Jan 30 19

Philips Semiconductors Product speciﬁcation

16-bit buffer/line driver; 5 V input/output tolerant

(3-state) 74LVC16244A;

74LVCH16244A

NOTES

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Philips Semiconductors – a world wide company

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands 613508/06/pp20 Date of release: 2003 Jan 30 Document order number: 9397 750 10748