2K x 8 Reprog ramm able R egiste red PR O
M
CY7C245
A
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-04007 Rev. *D Revised November 4, 2003
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
—15-ns address set-up
—10-ns clock to output
• Low power
—330 mW (commercial) for -25 ns
—660 mW (military)
• Programmable synchronous or asynchronous output
enable
• On-chip edge -triggered registers
• Programmable asynchronous register (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
•5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically
prog rammable , read- only me mory p ack aged in a sli m 300-m il
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
The CY7C245A replaces bipolar devices and offers the advan-
tages of lower power, reprogrammability, superior perfor-
mance and high programming yield. The EPROM cell requires
only 12 .5V for the supe rvolta ge, and low cu rrent requirem ents
allow gang programming. The EPROM cells allow each
memory l oc ati on to be tested 10 0%, be ca us e each l oca tio n i s
written into, erased, and repeatedly exercised prior to encap-
sulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or m ay be used as a PRESET or CLEAR function on the
outputs. INIT is triggered by a low level, not an edge.
Logic Block Diagram Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A8
A9
INIT
CP
O7
O6
O4
O5
O3
PROGRAMMABLE
ARRAY MULTIPLEXER
15
8-BIT
EDGE-
REGISTER
TRIGGERED
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
CP
CP
E/E S
E/ES
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
11
12 19
A5
V
CC
GND A6
A7
O3
O1
O018
O4
O5
NC
A0
A4
A3A10
NC
NC
NC
INIT
E/ES
O7
O6
A2
A1CP
O2
A8
INIT
INITIALIZE WORD
PROGRAMMABLE
A9
PROGRAMMABLE
MULTIPLEXER
DQ
C
A10
ADDRESS
DECODER
A0
A1
A2
A3
A4
A5
A6
A8
A9
A10
A7
COLUMN
ADDRESS
ROW
ADDRESS
DIP To p V iew
LCC/PLCC ( Opaque only) Top View
Selection Guide
7C245A-15 7C245A-18 7C245A-25 7C245A-35 Unit
Minimum Address Set-up Time 15 18 25 35 ns
Maximum Clock to Output 10 12 12 15 ns
Maximu m Operat ing Current S t andard Commer cial 120 120 90 90 mA
Military 120 120 120 mA
CY7C245
A
Document #: 38-04007 Rev. *D Page 2 of 12
Operating Modes
The CY7C245A is a CMOS electrically programmable read
only memory organized as 2048 words x 8 bits and is a
pin-for-pin replacement for bipolar TTL fusible link PROMs.
The CY7C245A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with a programmable synchronous (ES) or
asynchronous (E) output enable and asynchronous initial-
ization (INIT).
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (ES or E). If the
synchronous enable (ES) has been programmed, the register
will be i n the set condition caus ing the outputs (O0–O7) to be
in the OFF or high-impedance state. If the asynchronous
enable (E) is being used, the outputs will come up in the OFF
or high-impedance state only if the enable (E) input is at a
HIGH logic level. Data is read by applying the me mory location
to t he address i nputs (A0–A10) an d a logi c LOW to the enab le
input. The s tored d ata is a cces sed and loade d into the m aster
flip-flo ps of the data reg ister during the address se t-up time. At
the next LOW-to-HIGH transition of the clock (CP), data is
transferred to the slave flip-flops, which drive the output
buffers, and the accessed data will appear at the outputs
(O0–O7).
If th e asynchron ous enab le (E) is be ing used , the outp uts ma y
be disabled at any time by switching the enable to a logic
HIGH, and may be returned to the active state by switching the
enable to a logic LOW.
If the synchronous enable (ES) is being used, the outputs will
go to th e O FF o r hi gh-i mp ed anc e state up on the nex t p os itiv e
clock edge after the synchronous enable input is switched to
a HIGH level. If the sy nchronou s enabl e pin is switched t o a
logic LOW, the subsequent positive clock edge will return the
output to the active st a te. Fol low i ng a po si tiv e c lo ck edg e, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
low-to-high transition of the clock. This unique feature allows
the CY7C245A decoders and sense amplifiers to access the
next location while previously addressed data remains stable
on the outputs.
System timing is simplified in that the on-chip edge triggered
regi ster allows the PROM clock to be der ived directl y from the
syste m cloc k withou t introduc ing rac e condi tions . The on -chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C245A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementation of other sophis-
ticated func tions such as a buil t-in “j ump sta rt” address. When
acti vated, the initia lize contr ol inp ut ca uses t he co ntents o f a
user-programmed 2049th 8-bit word to be loaded into the
on-chip register. Each bit is programmable and the initialize
function can be used to load any desired combination of 1s
and 0s into the reg ister . In the unprogra mmed stat e, activating
INIT will generate a register CLEAR (all outputs LOW). If all
the bits of the initialize word are programmed, activating INIT
performs a register PRESET (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load
of the programmed initialize word into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). The initialize data will appear at the
device outputs after the outputs are enabled by bringing the
asynchronous enable (E) LOW.
Erasure Characteristics
W avelen gths of light less than 4000 Angstroms beg in to erase
the 7C245A. For this reason, an opaque label should be
placed over th e window if t he PROM is ex po se d to sunlight or
fluorescent lighting for extended periods of time.
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV
intens ity m ultiplied by ex posu re time ) of 25 Wsec /cm2. For an
ultraviolet lamp with a 12 mW/cm2 power ratin g the exposure
time would be approximately 35 minutes. The 7C245A needs
to be within 1 inch of the lamp during erasure. Permanent
damage may result if the PROM is exposed to high-intensity
UV ligh t for an ext ended perio d of time. 725 8 Wsec/cm 2 is the
recommended maximum dosage.
Programming Informat ion
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress repr esentative.
Bit Map Data
Programmer Address RAM Data
Decimal Hex Contents
00 Data
.
.
.
.
.
.
.
.
.
2047 7FF Data
2048 800 Init Byte
2049 801 Control Byte
Control Byte
00 Asynchronous output enable (default state)
01 Synchronous output enable
CY7C245
A
Document #: 38-04007 Rev. *D Page 3 of 12
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Note:
1. X = “don’t care” but not to exceed VCC + 5%.
Table 1. Mod e Selection
Mode
Read or Output Disable
Pin Function[1]
A10–A4A3A2–A1A0CP E, ESINIT O7–O0
Other A10–A4A3A2–A1A0PGM VFY VPP D7–D0
Read A10–A4A3A2–A1A0VIL/VIH VIL VIH O7–O0
Output Di sable A10–A4A3A2–A1A0XV
IH VIH High Z
Initialize A10–A4A3A2–A1A0XV
IL VIL Init. Byte
Program A10–A4A3A2–A1A0VILP VIHP VPP D7–D0
Program Verify A10–A4A3A2–A1A0VIHP VILP VPP O7–O0
Program Inhibit A10–A4A3A2–A1A0VIHP VIHP VPP High Z
Intelligent Program A10–A4A3A2–A1A0VILP VIHP VPP D7–D0
Program Synchronous Enable A10–A4VIHP A2–A1VPP VILP VIHP VPP High Z
Program Initialization Byte A10–A4VILP A2–A1VPP VILP VIHP VPP D7–D0
Blank C hec k Zero s A10–A4A3A2–A1A0VIHP VILP VPP Zeros
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
VCC
D7
D6
D4
D5
D3
15
A9
A10
VPP
VFY
PGM
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19
A5
VCC
GND A6
A7
D3
D1
D018
D4
D5
NC
A0
A4
A3
A8
NC
NC
D7
D6
A2
A1
D2
A10
VPP
VFY
PGM
NC
A9
DIP To p View LCC/PLCC (Opaque Only) Top View
Figure 1. Programming Pinouts
DC Characterist ics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
SMD Cross Reference
SMD Number Suffix Cypre ss Nu mbe r
5962-88735 033X CY7C245A-25LMB
5962-88735 04LX CY7C245A-25DMB
Switching Characteristics
Parameter Subgroups
tSA 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tCO 7, 8, 9, 10, 11
CY7C245
A
Document #: 38-04007 Rev. *D Page 4 of 12
Maximum Ratings[2]
(Abov e wh ic h th e us eful life ma y be imp aire d. For user gui de-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Pow er Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input Volta ge.................................................−3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20)...........................13.0V
UV Erasure....... ...... ...... ................ ...... ...... ....7258 Wse c/c m2
Static Discharge Vo ltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient Temperatu re VCC
Commercial 0°C to +70°C 5V ±10%
Military[3] −55°C to +125°C 5V ±10%
Industrial –40°C to +85°C 5V ±10%
Electri cal Characteristics Over the Operating Range[4,5]
Parameter Description Test Conditions 7C245A-15 7C245A-18
7C245A-25
7C245A-35
7C245A-45 UnitMin. Max. Min. Max. Min. Max.
VOH Output HI GH Volt age VCC = Min ., IOH = −4.0 mA
VIN = VIH or VIL 2.4 2.4 2.4 V
VOL Output LO W Voltage VCC = Min., IOL = 16 mA
VIN = VIH or VIL 0.4 0.4 0.4 V
VIH Input HIGH Level Guaranteed Input Logical
HIGH Voltage for All Inputs 2.0 VCC 2.0 VCC 2.0 VCC V
VIL Input LOW Level Guaranteed Input Logical
LOW Voltage for All Inputs 0.8 0.8 0.8 V
IIX Input Leakage Current GND < VIN < VCC −10 +10 −10 +10 −10 +10 µA
VCD Input Clamp Diode Voltage Note 5
IOZ Output Lea ka ge Cu rren t GND < VO < VCC Output
Disabled[6] −10 +10 −10 +10 −10 +10 µA
IOS Output Short Circuit Current VCC = Max., VOUT = 0.0V[7] −20 −90 −20 −90 −20 −90 mA
ICC Power Supply Current VCC = Max.,
IOUT = 0 mA Com’l 120 120 90 mA
Mil 120 120
VPP Prog rammi ng Supply Voltage 12 13 12 13 1 2 13 V
IPP Programming Suppl y Current 50 50 50 mA
VIHP Input HI GH Programming Volta ge 3.0 3.0 3.0 V
VILP Input LOW Programming Voltage 0.4 0.4 0.4 V
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output Capacitance 10 pF
Notes:
2. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
3. TA i s the “instant on” case t emperatu re.
4. See page 3 of this data sheet for Group A subgroup testing information.
5. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing.
6. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
7. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
CY7C245
A
Document #: 38-04007 Rev. *D Page 5 of 12
AC Test Loads and Waveforms[4, 5]
Switching Characteristics Over Op erating Range [4, 5]
Parameter Description 7C245A-15 7C245A-18 7C245A-35 7C245A-25 7C245A-35 UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tSA Address Set-Up to Clock HIGH 15 18 25 35 45 ns
tHA Address Hold from Clo ck HIGH 0 0 0 0 0 ns
tCO Clock HIGH to Valid Output 10 12 12 15 25 ns
tPWC Clock Pulse Width 10 12 15 20 20 ns
tSES ES Set-Up to Clock HIGH 10 10 12 15 15 ns
tHES ES Hold from Clock HIGH 5 5 5 5 5 ns
tDI Delay from INIT to Va li d O ut p ut 15 20 20 20 35 ns
tRI INIT Recovery to Clock HIGH 10 12 15 20 20 ns
tPWI INIT Pulse Width 10 12 15 20 25 ns
tCOS Valid Output from Clock HIGH[8] 15 15 15 20 30 ns
tHZC Inactive Output from Clock
HIGH[8] 15 15 15 20 30 ns
tDOE Valid Output from E LO W[9] 12 15 15 20 30 ns
tHZE Inactive Output from E HIGH[9] 15 15 15 20 30 ns
Notes:
8. Applies only when the synchronous (ES) funct ion i s used.
9. Applies only when the asynchronous (E) function i s used.
3.0V
5V
OUTPUT
R1 250Ω
R2
167Ω
50 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10%
90%
10%
5ns 5ns
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
(b) HighZ Load
OUTPUT 2.0V
Equivalent to: TH ÉVENINEQUIVALENT
100Ω
R1 250Ω
(a) Normal Load
R2
167Ω
ALL INPUT PULSES
≤≤
CY7C245
A
Document #: 38-04007 Rev. *D Page 6 of 12
Switching Waveforms[5]
tDI
tCO tDOE
tHZE
tHZC
tSA tHA
tHES
tSES
tPWC tPWC
tPWC tPWC
tPWC tPWC
tHA
tCO tCOS
O0−O7
A0−A10
INIT
CP
ES
E
tRI
tPWI
tHES
tSES
tHES
tSES
CY7C245
A
Document #: 38-04007 Rev. *D Page 7 of 12
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0 −55 25 125
1.2
1.1
1.6
4.04.55.05.56.0
NORMALIZED CLOCK-TO-OUTP UT TIME
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUP PLY VOLTAGE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBI EN T TEMPERATU R E (°C) SUPPLY VO LTAG E (V )
CLOCK TO OUTPUT TIME
vs. VCC
0.6
1.2
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED SET-UP TIME
AMBI EN T TEMPERATU R E (°C)
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
150
175
125
75
50
25
0.01.02.03.0
OUTPUT SINK CURRENT (mA)
0
100
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
NORMALIZED I CC
NORMAL IZ ED I
CC
VCC =5.0V
TA=25°C
TA=25°C
0.6
0.6
1.02
1.00
0.98
0.96
0.94
0.92
025 5075
CLOCK PERIOD (ns)
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITA NCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
100 0.0 1000
TA=25°C
VCC =4.5V
TA=25°C
f= f
MAX
25
0.88
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
4.0
1.4
1.2
1.0
0.8
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED SE T-U P TIME
0.6 25
AMBIENT TEMPERATURE (°C)
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.2
4.04.55.05.56.0
NORMALIZED CLOCK-TO-OUTPUT TIME
0.4
SUPPLY VOLTAGE (V)
NORMALIZED SET-UP TIME
vs. SUPPLYVOLTAGE
TA=25°C
1.0
0.8
0.6
NORMALIZED I
CC
0.90
VCC =5.5V
TA=25°C
Ordering Information
Spe e d (ns) ICC
(mA) Ordering
Code Package
Type Package Type Operating
RangetSA tCO
15 10 120 CY7C245A-15JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
15 10 120 CY7C245A-15JI J64 28-Lead Plastic Leaded Chip Carrier Industrial
18 12 120 CY7C245A-18JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7C245A-18PC P13 24-Lead (300-Mil) Molded DIP
CY7C245A-18WC W14 24-Lead (300-Mil) Windowed CerDIP
CY7C245
A
Document #: 38-04007 Rev. *D Page 8 of 12
18 12 120 CY7C245A-18DMB D14 24-Lead (300-Mil) CerDIP Military
CY7C245A-18QMB Q64 28- Pin Windowed Leadl ess Chip Carrier
CY7C245A-18WMB W14 24-Lead (300-Mil) Windowed CerDIP
25 15 60 CY7C245A-25PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C245A-25WC W14 24-Lead (300-Mil) Windowed CerDIP
90 CY7C245A-25JC J64 28-Lead Plastic Leaded Chip Carrier
CY7C245A-25SC S13 24-Lead Molded SOIC
35 20 60 CY7C245A-35WC W14 24-Lead (300-Mil) Windowed CerDIP Commercial
90 CY7C245A-35JC J64 28-Lead Plastic Leaded Chip Carrier
120 CY7C245A-35DMB D14 24-Lead (300-Mil) CerDIP Military
CY7C245A-35QMB Q64 28- Pin Windowed Leadl ess Chip Carrier
Ordering Information (continued)
Spe e d (ns) ICC
(mA) Ordering
Code Package
Type Package Type Operating
RangetSA tCO
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D-9 Config.A
51-80031-**
CY7C245
A
Document #: 38-04007 Rev. *D Page 9 of 12
Package Diagrams (continued)
28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
51-85013-*B
24-Lead (300-Mil) PDIP P13
CY7C245
A
Document #: 38-04007 Rev. *D Page 10 of 12
Package Diagrams (continued)
28-Pin Windowed Leadless Chip Carrier Q64
MIL–STD–1835 C–4
51-80102-**
PIN 1 ID
SEATING PLANE
0.597[15.163]
0.615[15.621]
24 Lead (300 Mil) SOIC - S13
112
13 24
*
*
*
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.291[7.391]
0.300[7.620]
0.394[10.007]
0.419[10.642]
0.050[1.270]
TYP.
0.092[2.336]
0.105[2.667]
0.004[0.101]
0.0118[0.299]
0.0091[0.231]
0.0125[0.317]
0.015[0.381]
0.050[1.270]
0.013[0.330]
0.019[0.482]
0.026[0.660]
0.032[0.812]
0.004[0.101]
REFERENCE JEDEC MO-119
PART #
S24.3 STANDARD PKG.
SZ24.3 LEAD FREE PKG.
PACKAGE WEIGHT 0.65gms
51-85025-*B
24-Lead (300-M il) SOIC S13
CY7C245
A
Document #: 38-04007 Rev. *D Page 11 of 12
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. C ypress Semicond uctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
51-80086-**
24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835 D-9 Config. A
CY7C245
A
Document #: 38-04007 Rev. *D Page 12 of 12
Document History Page
Document Title: CY7C245A 2K x 8 Reprogrammable Registered PROM
Document Number: 38-04007
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 113863 3/6/02 DSG Changed from Spec number: 38-00074 to 38-04007
*A 118894 10/09/02 GBI Updated ordering information
*B 122248 12/27/02 RBI Added power-up requirements to Operating Conditions information
*C 130688 10/30/03 LSY Added CY7C245A-15JI part number
*D 130942 11/10/03 KKV Minor change: soft copy became corrupted after signoff and before Tech
Pubs. Replaced with co rrec t copy.
