 
  
   
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D2-V to 6-V VCC Operation
DHigh-Current 3-State Parallel Register
Outputs Can Drive Up To 15 LSTTL Loads
DLow Power Consumption, 80-µA Max ICC
DTypical tpd = 14 ns
D±6-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
D8-Bit Counter With Register
DCounter Has Direct Clear
SN54HC590A ...J OR W PACKAGE
SN74HC590A . . . D, DW, OR N PACKAGE
(TOP VIEW)
SN54HC590A . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QB
QC
QD
QE
QF
QG
QH
GND
VCC
QA
OE
RCLK
CCKEN
CCLK
CCLR
RCO
3212019
910111213
4
5
6
7
8
18
17
16
15
14
OE
RCLK
NC
CCKEN
CCLK
QD
QE
NC
QF
QG
Q
NC
RCO
CCLR
H
GND
NC
C
QB
VCC
QA
Q
description/ordering information
The ’HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register
has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary
counter features direct clear (CCLR) and count-enable (CCKEN) inputs. A ripple-carry output (RCO) is provided
for cascading. Expansion is accomplished easily for two stages by connecting RCO of the first stage to CCKEN
of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage
to the counter clock (CCLK) input of the following stage.
CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together,
the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock
enable.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74HC590AN SN74HC590AN
Tube of 40 SN74HC590AD
−40°C to 85°C
SOIC − D Reel of 2500 SN74HC590ADR HC590A
−40°C to 85°C
SOIC − D
Reel of 250 SN74HC590ADT
HC590A
SOIC − DW
Tube of 40 SN74HC590ADW
HC590A
SOIC − DW Reel of 2000 SN74HC590ADWR HC590A
CDIP − J Tube of 25 SNJ54HC590AJ SNJ54HC590AJ
−55°C to 125°CCFP − W Tube of 150 SNJ54HC590AW SNJ54HC590AW
−55 C to 125 C
LCCC - FK Tube of 55 SNJ54HC590AFK SNJ54HC590AFK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
  !"# $ %&'# "$  (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$  '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1  "** (""!'#'$,
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
 (+&%#$ %!(*"# # 234 "** (""!'#'$ "' #'$#'+
&*'$$ #-'/$' #'+,  "** #-' (+&%#$ (+&%#
(%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1  "** (""!'#'$,
 
  
   
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing diagram
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
RCO
QA−QH
CCKEN
CCLR
OE
CCLK
COUNTER
(internal)
RCLK
Hex 01 Hex 02 Hex 03 Hex 04 Hex 05 Hex FD Hex FE Hex FF Hex 00 Hex01
Hex 00 Hex 01 Hi-Z Hex 01 Hex 05 Hex 00
TIMING SEQUENCE
1. Clear Counter (asynchronous).
2. Count up: 0x01. Store 0x00 in register.
3. Inhibit counter clock (CCKEN = HIGH). Store 0x01 in register.
4. Count 0x02, 0x03.
5. 3-state the outputs
6. Count up: 0x04
7. Enable outputs.
8. Continue up: 0x05
9. Store 0x05 in register.
10.Continue counting: 0x06...0xFD, 0xFE, 0xFF, 0x00, etc.
11. Store 0x00 in register.
Don’t
Care
ÎÎÎ
ÎÎÎ
ÎÎÎ
Hex 00
Don’t
Care
 
  
   
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
14
13
12
11
10
9
15
1
2
3
4
5
6
7
OE
RCLK
CCKEN
CCLK
CCLR
RCO
QA
QB
QC
QD
QE
QF
QG
QH
Pin numbers shown are for the D, DW, J, N, and W packages.
 
  
   
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 57°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, a nd
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC590A SN74HC590A
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage VCC = 4.5 V 3.15 3.15 V
VIH
VCC = 6 V 4.2 4.2
V
VCC = 2 V 0.5 0.5
V
IL
Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VIL
VCC = 6 V 1.8 1.8
V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
t
t
‡Input transition (rise and fall) time VCC = 4.5 V 500 500 ns
tt‡
VCC = 6 V 400 400
ns
TAOperating free-air temperature −55 125 −40 85 °C
‡If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CCLK and RCLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
 
  
   
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC590A SN74HC590A
UNIT
PARAMETER
TEST CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
I
OH
= −20 µA4.5 V 4.4 4.499 4.4 4.4
IOH = −20 µA
6 V 5.9 5.999 5.9 5.9
V
OH
V
I
= V
IH
or V
IL
RCO, IOH = −4 mA
4.5 V
3.98 4.3 3.7 3.84 V
VOH
VI = VIH or VIL
QA−QH, IOH = −6 mA 4.5 V 3.98 4.3 3.7 3.84
V
RCO, IOH = −5.2 mA
6 V
5.48 5.8 5.2 5.34
QA−QH, IOH = −7.8 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
I
OL
= 20 µA4.5 V 0.001 0.1 0.1 0.1
IOL = 20 µA
6 V 0.001 0.1 0.1 0.1
V
OL
V
I
= V
IH
or V
IL
RCO, IOL = 4 mA
4.5 V
0.17 0.26 0.4 0.33 V
VOL
VI = VIH or VIL
QA−QH, IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33
V
RCO, IOL = 5.2 mA
6 V
0.15 0.26 0.4 0.33
QA−QH, IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
IOZ VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5µA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
Ci2 V
to 6 V 3 10 10 10 pF
 
  
   
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C SN54HC590A SN74HC590A
UNIT
V
CC MIN MAX MIN MAX MIN MAX
UNIT
2 V 4 2.5 3.2
f
clock
Clock frequency 4.5 V 20 13 16 MHz
fclock
Clock frequency
6 V 24 16 19
MHz
2 V 125 200 155
CCLK or RCLK high or low 4.5 V 25 38 31
tw
Pulse duration
CCLK or RCLK high or low
6 V 21 32 26
ns
twPulse duration 2 V 100 150 125 ns
CCLR low 4.5 V 20 30 25
CCLR low
6 V 17 26 21
2 V 100 150 125
CCKEN low before CCLK↑4.5 V 20 30 25
CCKEN low before CCLK↑
6 V 17 26 21
2 V 100 150 125
t
su
Setup time CCLR high (inactive) before CCLK↑4.5 V 20 30 25 ns
tsu
Setup time
CCLR high (inactive) before CCLK↑
6 V 17 26 21
ns
2 V 100 150 125
CCLK↑ before RCLK↑†4.5 V 20 30 25
CCLK↑ before RCLK↑†
6 V 17 26 21
2 V 50 75 60
t
h
Hold time CCKEN low after CCLK↑4.5 V 10 15 12 ns
th
Hold time
CCKEN low after CCLK
6 V 9 13 11
ns
†This setup time ensures that the register gets stable data from the counter outputs. The clocks may be tied together, in which case the register
is one clock pulse behind the counter.
 
  
   
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM
TO
SN54HC590A
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
V
CC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN TYP MAX
MIN
MAX
UNIT
2 V 4 8 2.5
f
max
4.5 V 20 35 13 MHz
fmax
6 V 24 40 16
MHz
2 V 80 150 225
t
pd
CCLK↑RCO 4.5 V 20 31 45 ns
tpd
CCLK↑
RCO
6 V 15 26 38
ns
2 V 70 130 195
t
PLH
CCLR↓RCO 4.5 V 18 28 39 ns
tPLH
CCLR↓
RCO
6 V 14 23 33
ns
2 V 70 140 210
t
pd
RCLK↑Q4.5 V 18 31 42 ns
tpd
RCLK↑
Q
6 V 14 25 36
ns
2 V 80 125 185
t
en
OE↓Q4.5 V 20 30 37 ns
ten
OE↓
Q
6 V 15 28 31
ns
2 V 80 125 185
t
dis
OE↑Q4.5 V 20 30 37 ns
tdis
OE↑
Q
6 V 15 28 31
ns
2 V 38 75 110
RCO 4.5 V 8 15 22
tt*
RCO
6 V 6 13 19
ns
t
t
*
2 V 38 60 90
ns
Q4.5 V 8 12 18
Q
6 V 6 10 15
* This parameter is not production tested for the SN54HC590A.
 
  
   
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM
TO
SN74HC590A
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
V
CC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN TYP MAX
MIN
MAX
UNIT
2 V 4 8 3.2
f
max
4.5 V 20 35 16 MHz
fmax
6 V 24 40 19
MHz
2 V 80 150 190
t
pd
CCLK↑RCO 4.5 V 20 30 38 ns
tpd
CCLK↑
RCO
6 V 15 26 33
ns
2 V 70 130 165
t
PLH
CCLR↓RCO 4.5 V 18 26 33 ns
tPLH
CCLR↓
RCO
6 V 14 22 28
ns
2 V 70 140 175
t
pd
RCLK↑Q4.5 V 18 28 35 ns
tpd
RCLK↑
Q
6 V 14 24 30
ns
2 V 80 125 155
t
en
OE↓Q4.5 V 20 25 31 ns
ten
OE↓
Q
6 V 15 21 26
ns
2 V 80 125 155
t
dis
OE↑Q4.5 V 20 25 31 ns
tdis
OE↑
Q
6 V 15 21 26
ns
2 V 38 75 95
RCO 4.5 V 8 15 19
tt
RCO
6 V 6 13 16
ns
t
t2 V 38 60 75
ns
Q4.5 V 8 12 15
Q
6 V 6 10 13
 
  
   
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM
TO
SN54HC590A
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
V
CC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN TYP MAX
MIN
MAX
UNIT
2 V 100 300 447
t
pd
RCLK↑Q4.5 V 24 60 90 ns
tpd
RCLK↑
Q
6 V 20 51 77
ns
2 V 90 200 300
t
en
OE Q 4.5 V 23 40 60 ns
ten
OE
Q
6 V 19 34 51
ns
2 V 45 210 315
t
t
*Q4.5 V 17 42 63 ns
tt
Q
6 V 13 36 53
ns
* This parameter is not production tested for the SN54HC590A.
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM
TO
SN74HC590A
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
V
CC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN TYP MAX
MIN
MAX
UNIT
2 V 100 300 380
t
pd
RCLK↑Q4.5 V 24 60 76 ns
tpd
RCLK↑
Q
6 V 20 51 65
ns
2 V 90 200 250
t
en
OE Q 4.5 V 23 40 50 ns
ten
OE
Q
6 V 19 34 43
ns
2 V 45 210 265
t
t
Q4.5 V 17 42 53 ns
tt
Q
6 V 13 36 45
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 250 pF
 
  
   
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
High-Level
Pulse
VCC
0 V
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-
Phase
Output
VCC
≈VCC
VOL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
tPZL tPLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOH
≈0 V
tPZH tPHZ
Output
Waveform 2
(See Note B)
≈VCC
Test
Point
From Output
Under Test
RL
V
CC
S1
S2
LOAD CIRCUIT
PARAMETER CL
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
RLS1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF Open Open−−
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
CL
(see Note A)
50% 50%
50% 50%
50%
50%
10%
90%
50%
10% 90%
50% 50%
50%
50%
90%
10%
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-89603012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
89603012A
SNJ54HC
590AFK
5962-8960301EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8960301EA
SNJ54HC590AJ
5962-8960301FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8960301FA
SNJ54HC590AW
SN54HC590AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC590AJ
SN74HC590AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590ADE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590ADT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590ADTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590ADTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590ADW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590ADWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HC590ADWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC590A
SN74HC590AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC590AN
SN74HC590AN3 OBSOLETE PDIP N 16 TBD Call TI Call TI -40 to 85
SN74HC590ANE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC590AN
SNJ54HC590AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
89603012A
SNJ54HC
590AFK
SNJ54HC590AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8960301EA
SNJ54HC590AJ
SNJ54HC590AW ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8960301FA
SNJ54HC590AW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC590A, SN74HC590A :
•Catalog: SN74HC590A
•Military: SN54HC590A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC590ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC590ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC590ADR SOIC D 16 2500 333.2 345.9 28.6
SN74HC590ADWR SOIC DW 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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