REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
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may result from its use. No license is granted by implication or otherwise
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Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
OP97
Low Power, High Precision
Operational Amplifier
FEATURES
Low Supply Current: 600 A Max
OP07 Type Performance
Offset Voltage: 20 V Max
Offset Voltage Drift: 0.6 V/ⴗC Max
Very Low Bias Current
25ⴗC: 100 pA Max
–55ⴗC to +125ⴗC: 250 pA Max
High Common-Mode Rejection: 114 dB Min
Extended Industrial Temperature Range: –40ⴗC to +85ⴗC
PIN CONNECTIONS
8-Lead PDIP (P Suffix)
8-Lead SOIC (S Suffix)
1
2
3
4
8
7
6
5
OP97
NULL
OVER
COMP
OUT
V+
NULL
–IN
+IN
V–
GENERAL DESCRIPTION
The OP97 is a low power alternative to the industry-standard
OP07 precision amplifier. The OP97 maintains the standards of
performance set by the OP07 while utilizing only 600 µA supply
current, less than 1/6 that of an OP07. Offset voltage is an ultralow
25 µV, and drift over temperature is below 0.6 µV/°C. External
offset trimming is not required in the majority of circuits.
Improvements have been made over OP07 specifications in
several areas. Notable is bias current, which remains below 250
pA over the full military temperature range. The OP97 is ideal
for use in precision long-term integrators or sample-and-hold
circuits that must operate at elevated temperatures.
Common-mode rejection and power supply rejection are also
improved with the OP97, at 114 dB minimum over wider ranges
of common-mode or supply voltage. Outstanding PSR, a supply
range specified from ±2.25 V to ±20 V and the OP97’s minimal
power requirements combine to make the OP97 a preferred
device for portable and battery-powered instruments.
The OP97 conforms to the OP07 pinout, with the null potenti-
ometer connected between Pins 1 and 8 with the wiper to V+.
The OP97 will upgrade circuit designs using 725, OP05, OP07,
OP12, and 1012 type amplifiers. It may replace 741-type ampli-
fiers in circuits without nulling or where the nulling circuitry has
been removed.
REV. E–2–
OP97–SPECIFICATIONS
(@ VS = ⴞ15 V, VCM = 0 V, TA = 25ⴗC, unless otherwise noted.)
OP97E OP97F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
Input Offset Voltage V
OS
10 25 30 75 µV
Long-Term Offset
Voltage Stability ∆V
OS
/Time 0.3 0.3 µV/Month
Input Offset Current I
OS
30 100 30 150 pA
Input Bias Current I
B
±30 ±100 ±30 ±150 pA
Input Noise Voltage e
n
p-p 0.1 Hz to 10 Hz 0.5 0.5 µV p-p
Input Noise Voltage Density e
n
f
O
= 10 Hz
1
17 30 17 30 nV/√Hz
f
O
= 1000 Hz
2
14 22 14 22 nV/√Hz
Input Noise Current Density i
n
f
O
= 10 Hz 20 20 fA/√Hz
Large-Signal Voltage Gain A
VO
V
O
= ±10 V; R
L
= 2 kΩ300 2000 200 2000 V/mV
Common-Mode Rejection CMR V
CM
= ±13.5 V 114 132 110 132 dB
Power-Supply Rejection PSR VS = ±2 V to ±20 V 114 132 110 132 dB
Input Voltage Range
3
IVR ±13.5 ±14.0 ±13.5 ±14.0 V
Output Voltage Swing V
O
R
L
= 10 kΩ±13 ±14 ±13 ±14 V
Slew Rate SR 0.1 0.2 0.1 0.2 V/µs
Differential Input Resistance
4
R
IN
30 30 MΩ
Closed-Loop Bandwidth BW A
VCL
= 1 0.4 0.9 0.4 0.9 MHz
Supply Current I
SY
380 600 380 600 µA
Supply Voltage V
S
Operating Range ±2±15 ±20 ±2±15 ±20 V
NOTES
1
10 Hz noise voltage density is sample tested. Devices 100% tested for noise are available on request.
2
Sample tested.
3
Guaranteed by CMR test.
4
Guaranteed by design.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
(@ VS = ⴞ15 V, VCM = 0 V, –40ⴗC ≤ TA ≤ +85ⴗC for the OP97E/F, unless otherwise noted.)
OP97E OP97F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
Input Offset Voltage V
OS
25 60 60 200 µV
Average Temperature TCV
OS
S-Package 0.2 0.6 0.3 2.0 µV/°C
Coefficient of V
OS
0.3
Input Offset Current I
OS
60 250 80 750 pA
Average Temperature TCI
OS
0.4 2.5 0.6 7.5 pA/°C
Coefficient of I
OS
Input Bias Current I
B
±60 ±250 ±80 ±750 pA
Average Temperature
Coefficient of I
B
TCI
B
0.4 2.5 0.6 7.5 pA/°C
Large Signal Voltage Gain A
VO
V
O
= 10 V; R
L
= 2 kΩ200 1000 150 1000 V/mV
Common-Mode Rejection CMR V
CM
= ±13.5 V 108 128 108 128 dB
Power Supply Rejection PSR V
S
= ±2.5 V to ±20 V 108 126 108 128 dB
Input Voltage Range*IVR ±13.5 ±14.0 ±13.5 ±14.0 V
Output Voltage Swing V
O
R
L
= 10 kΩ±13 ±14 ±13 ±14 V
Slew Rate SR 0.05 0.15 0.05 0.15 V/µs
Supply Current I
SY
400 800 400 800 µA
Supply Voltage V
S
Operating Range ±2.5 ±15 ±20 ±2.5 ±15 ±20 V
*Guaranteed by CMR test.
Specifications subject to change without notice.
REV. E
OP97
–3–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
OP97 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V
Input Voltage
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V
Differential Input Voltage
3
. . . . . . . . . . . . . . . . . . . . . . . . ±1 V
Differential Input Current
3
. . . . . . . . . . . . . . . . . . . . ±10 mA
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Operating Temperature Range
OP97E, OP97F (P, S) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
Package Type
JA4
JC
Unit
8-Lead PDIP (P) 103 43 °C/W
8-Lead SOIC (S) 158 43 °C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For supply voltages less than ±20 V, the absolute maximum input voltage is equal
to the supply voltage.
3
The OP97’s inputs are protected by back-to-back diodes. Current-limiting resis-
tors are not used in order to achieve low noise. Differential input voltages greater
than 1 V will cause excessive current to flow through the input protection diodes
unless limiting resistance is used.
4
JA
is specified for worst-case mounting conditions, i.e.,
JA
is specified for device
in socket for PDIP package;
JA
is specified for device soldered to printed circuit
board for SOIC package.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option*
OP97EP –40°C to +85°C8-Lead PDIP N-8
OP97FP –40°C to +85°C8-Lead PDIP N-8
OP97FS –40°C to +85°C8-Lead SOIC R-8
OP97FS-REEL –40°C to +85°C8-Lead SOIC R-8
OP97FS-REEL7 –40°C to +85°C8-Lead SOIC R-8
*For outline information, see Package Information section.
REV. E–4–
OP97–Typical Performance Characteristics
INPUT OFFSET VOLTAGE (V)
NUMBER OF UNITS
0
–40
100
200
300
400
–20 0 20 40
1894 UNITS V
S
= ⴞ15V
T
A
= 25ⴗC
V
CM
= 0V
TPC 1. Typical Distribution of
Input Offset Voltage
TEMPERATURE (
C)
INPUT CURRENT (pA)
–60
–75 –25 0 25 50–50 75
TA = 25ⴗC
VCM = 0V
IB–
IOS
IB+
–40
–20
0
20
40
60
100 125
TPC 4. Input Bias, Offset
Current vs. Temperature
SOURCE RESISTANCE (⍀)
EFFECTIVE OFFSET VOLTAGE (V)
1000
1
1k
100
10
3k 10k 30k 100k 1M300k 3M 10M
BALANCED OR UNBALANCED
VS = ⴞ15V
VCM = 0V
–55ⴗC TA +125ⴗC
TA = 25ⴗC
TPC 7. Effective Offset Volt-
age vs. Source Resistance
INPUT BIAS CURRENT (pA)
NUMBER OF UNITS
0
–100
100
200
300
400
–50 0 50 100
1920 UNITS V
S
= ⴞ15V
T
A
= 25ⴗC
V
CM
= 0V
TPC 2. Typical Distribution of
Input Bias Current
COMMON-MODE VOLTAGE (V)
INPUT CURRENT (pA)
–60
–15 –5 0 5 10–10 15
T
A
= 25ⴗC
V
S
= ⴞ15V
I
B
–
I
OS
I
B
+
–40
–20
0
20
40
60
TPC 5. Input Bias, Offset Current vs.
Common-Mode Voltage
SOURCE RESISTANCE (⍀)
EFFECTIVE OFFSET VOLTAGE DRIFT (V/ C)
100
0.1
1k
10
1
10k 100k 1M 10M
BALANCED OR UNBALANCED
VS = ⴞ15V
VCM = 0V
100M
TPC 8. Effective TCV
OS
vs.
Source Resistance
INPUT OFFSET CURRENT (pA)
NUMBER OF UNITS
0
–60
100
200
300
400
–20 0 20 40
1894 UNITS V
S
= ⴞ15V
T
A
= 25
ⴗ
C
V
CM
= 0V
–40 60
500
TPC 3. Typical Distribution of
Input Offset Current
TIME AFTER POWER APPLIED (Minutes)
DEVIATION FROM FINAL VALUE (V)
0
0
ⴞ1
ⴞ2
ⴞ3
ⴞ4
234 5
TA = 25ⴗC
VS = ⴞ15V
VCM = 0V
1
ⴞ5
J PACKAGES
Z, P PACKAGES
TPC 6. Input Offset Voltage
Warm-Up Drift
TIME FROM OUTPUT SHORT (Minutes)
SHORT-CIRCUIT CURRENT (mA)
–20
0
–15
–10
–5
10
20
123
0
15
5
VS = ⴞ15V
OUTPUT SHORTED TO GROUND
TA = +125ⴗC
TA = +25ⴗC
TA = –55ⴗC
TA = +125ⴗC
TA = +25ⴗC
TA = –55ⴗC
TPC 9. Short-Circuit Current
vs. Time, Temperature
REV. E
OP97
–5–
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (A)
300
0
325
375
400
450
ⴞ5
NO LOAD
T
A
= +125ⴗC
T
A
= –55ⴗC
T
A
= +25ⴗC
350
425
ⴞ10 ⴞ15 ⴞ20
TPC 10. Supply Current vs.
Supply Voltage
LOAD RESISTANCE (k⍀)
OPEN-LOOP GAIN (V/mV)
10000
1
1000
100
251020
T
A
= +125ⴗC
T
A
= –55ⴗC
T
A
= +25ⴗC
V
S
= ⴞ15V
V
O
= ⴞ10V
TPC 13. Open-Loop Gain vs.
Load Resistance
OUTPUT VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (10V/DIV)
–15 –5 0 5 10
RL = 10k⍀
VS = ⴞ15V
VCM = 0V
–10 15
TA = +125ⴗC
TA = –55ⴗC
TA = +25ⴗC
TPC 16. Open-Loop Gain
Linearity
FREQUENCY (Hz)
COMMON-MODE REJECTION (dB)
0
1
100
10 100 1k 10k
T
A
= 25ⴗC
V
S
= ⴞ15V
V
CM
= ⴞ10V
20
40
60
80
120
140
100k 1M
TPC 11. Common-Mode
Rejection vs. Frequency
FREQUENCY (Hz)
100
1
10
1
10 100 1000
CURRENT NOISE
1/f CORNER
120Hz
VOLTAGE NOISE
1/f CORNER
2.5Hz
TA = 25ⴗC
VS = ⴞ2V TO ⴞ20V
1000
VOLTAGE NOISE DENSITY (nV/ Hz)
CURRENT NOISE DENSITY (FA/ Hz)
100
10
1
1000
TPC 14. Noise Density vs.
Frequency
LOAD RESISTANCE (⍀)
OUTPUT SWING (V p-p)
35
1
10
30
10k1k100
T
A
= 25ⴗC
V
S
= ⴞ15V
A
VCL
= +1
1% THD
f
O
= 1kHz
25
20
15
10
5
TPC 17. Maximum Output
Swing vs. Load Resistance
FREQUENCY (Hz)
POWER-SUPPLY REJECTION (dB)
20
0.1
40
60
80
100
10 100 1k 10k
–PSR
TA = 25ⴗC
VS = ⴞ15V
⌬VS = 10V p–p
1 100k
140
+PSR
120
1M
TPC 12. Power-Supply
Rejection vs. Frequency
SOURCE RESISTANCE (⍀)
10
0.01
10
2
1
0.1
T
A
= 25ⴗC
V
S
= ⴞ2V TO ⴞ20V
TOTAL NOISE DENSITY (V/ Hz)
RESISTOR NOISE
1kHz
10Hz
R
R
R
S
= 2R
10
3
10
4
10
5
10
6
10
7
10
8
1kHz
10Hz
TPC 15. Total Noise Density
vs. Source Resistance
FREQUENCY (Hz)
OUTPUT SWING (V p-p)
35
1
30
100k1k100
T
A
= 25ⴗC
V
S
= ⴞ15V
A
VCL
= 1
1% THD
R
l
= 10k⍀
25
20
15
10
5
10k
TPC 18. Maximum Output
Swing vs. Frequency
REV. E–6–
OP97
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
80
–60
100
60
10M1k 100k
40
10k 1M
–40
–20
0
20
PHASE
PHASE SHIFT (Degrees)
225
180
135
90
TA = +125ⴗC
TA = –55ⴗC
TA = –55ⴗC
TA = +125ⴗC
VS = 15V
CL = 20pF
RL = 1M⍀
100pF OVERCOMPENSATION
GAIN
VS = ⴞ15V
CL = 20pF
RL = 1M⍀
100pF OVERCOMPENSATION
TPC 19. Open-Loop Gain, Phase vs.
Frequency (COC = 0 pF)
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
80
–60
100
60
10M1k 100k
40
10k 1M
–40
–20
0
20
PHASE
PHASE SHIFT (Degrees)
225
180
135
90
T
A
= +125ⴗC
T
A
= –55ⴗC
GAIN
V
S
= ⴞ15V
C
L
= 20pF
R
L
= 1M⍀
100pF OVERCOMPENSATION
T
A
= –55ⴗC
T
A
= +125ⴗC
TPC 22. Open-Loop Gain, Phase vs.
Frequency (C
OC
= 100 pF)
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
80
–60
100
60
10M1k 100k
40
10k 1M
–40
–20
0
20
PHASE
PHASE SHIFT (Degrees)
225
180
135
90
T
A
= –55ⴗC
T
A
= +25ⴗC
T
A
= +125ⴗC
GAIN
V
S
= ⴞ15V
C
L
= 20pF
R
L
= 1M⍀
100pF OVERCOMPENSATION
T
A
= –55ⴗC
T
A
= +125ⴗC
TPC 25. Open-Loop Gain, Phase vs.
Frequency (C
OC
= 1000 pF)
FREQUENCY (Hz)
THD + N (%)
0.0001
10 10k1k100
TA = 25ⴗC
VS = ⴞ15V
RL = 10k⍀
1% THD
VOUT = 3V RMS
AVCL = 100
AVCL = 10
AVCL = 1
0.001
0.01
0.1
1
10
TPC 20. Total Harmonic Distortion
Plus Noise vs. Frequency
OVERCOMPENSATION CAPACITOR (pF)
0.1
1
0.01
0.001
10 100 10000
1
SLEW RATE (V/s)
R
l
= 10k⍀
V
S
= ⴞ15V
C
L
= 100pF
T
A
= +125ⴗC
T
A
= –55ⴗC
1000
TPC 23. Slew Rate vs.
Overcompensation
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
80
–60
100
60
10M1k 100k
40
10k 1M
–40
–20
0
20
PHASE
PHASE SHIFT (Degrees)
225
180
135
90
T
A
= –55ⴗC
T
A
= +25ⴗC
T
A
= +125ⴗC
GAIN
V
S
= ⴞ15V
C
L
= 20pF
R
L
= 1M⍀
100pF OVERCOMPENSATION
T
A
= +125ⴗC
T
A
= –55ⴗC
TPC 26. Open-Loop Gain, Phase vs.
Frequency (C
OC
= 10,000 pF)
LOAD CAPACITANCE (pF)
OVERSHOOT (%)
70
0
10
60
10000
1000100
TA = 25ⴗC
VS = ⴞ15V
AVCL = +1
VOUT = 100mV p-p
COC = 0pF
50
40
30
20
10
+EDGE
–EDGE
TPC 21. Small Signal Overshoot vs.
Capacitive Load
OVERCOMPENSATION CAPACITOR (pF)
100
1
10
1
10 100 10000
1000
GAIN BANDWIDTH (kHz)
V
S
= ⴞ15V
C
L
= 20pF
R
L
= 1M⍀
A
V
= 100
T
A
= –55ⴗC
1000
T
A
= +125ⴗC
TPC 24. Gain Bandwidth Product vs.
Overcompensation
FREQUENCY (Hz)
OUTPUT IMPEDANCE (⍀)
0.001
10 100 1k 10k
T
A
= 25ⴗC
V
S
= ⴞ15V
1
A
VCL
= 1000
100k
A
VCL
= 1
0.01
0.1
1
10
100
1000
TPC 27. Closed-Loop Output
Resistance vs. Frequency
REV. E
OP97
–7–
APPLICATION INFORMATION
The OP97 is a low power alternative to the industry-standard
precision op amp, the OP07. The OP97 may be substituted
directly into OP07, OP77, 725, 112/312, and 1012 sockets with
improved performance and/or less power dissipation and may be
inserted into sockets conforming to the 741 pinout if nulling
circuitry is not used. Generally, nulling circuitry used with ear-
lier generation amplifiers is rendered superfluous by the OP97’s
extremely low offset voltage and may be removed without com-
promising circuit performance.
Extremely low bias current over the full military temperature
range makes the OP97 attractive for use in sample-and-hold
amplifiers, peak detectors, and log amplifiers that must operate
over a wide temperature range. Balancing input resistances is
not necessary with the OP97. Offset voltage and TCV
OS
are
degraded only minimally by high source resistance, even when
unbalanced.
The input pins of the OP97 are protected against large differential
voltage by back-to-back diodes. Current-limiting resistors are
not used so that low noise performance is maintained. If differ-
ential voltages above ±1 V are expected at the inputs, series
resistors must be used to limit the current flow to a maximum of
10 mA. Common-mode voltages at the inputs are not restricted
and may vary over the full range of the supply voltages used.
The OP97 requires very little operating headroom about the
supply rails and is specified for operation with supplies as low
OP97
R
POT
= 5k
⍀
TO 100k
⍀
C
OC
–V
+V
Figure 1. Optional Input Offset Voltage Nulling
and Overcompensation Circuits
Figure 2. Small-Signal Transient Response
(C
LOAD
= 100 pF, A
VCL
= 1)
as ±2 V. Typically, the common-mode range extends to within
1 V of either rail. The output typically swings to within 1 V of
the rails when using a 10 kΩ load.
Offset nulling is achieved utilizing the same circuitry as an OP07.
A potentiometer between 5 kΩ and 100 kΩ is connected between
Pins 1 and 8 with the wiper connected to the positive supply.
The trim range is between 300 µV and 850 µV, depending upon
the internal trimming of the device.
AC PERFORMANCE
The OP97’s ac characteristics are highly stable over its full
operating temperature range. Unity-gain small-signal response
is shown in Figure 2. Extremely tolerant of capacitive loading
on the output, the OP97 displays excellent response even with
1000 pF loads (Figure 3). In large-signal applications, the input
protection diodes effectively short the input to the output during
the transients if the amplifier is connected in the usual unity-
gain configuration. The output enters short-circuit current limit,
with the flow going through the protection diodes. Improved
large-signal transient response is obtained by using a feedback
resistor between the output and the inverting input. Figure 4
shows the large-signal response of the OP97 in unity gain with a
10 kΩ feedback resistor. The unity-gain follower circuit is shown
in Figure 5.
The overcompensation pin may be used to increase the phase
margin of the OP97 or to decrease gain-bandwidth product at
gains greater than 10.
Figure 3. Small-Signal Transient Response
(C
LOAD
= 1000 pF, A
VCL
= 1)
Figure 4. Large-Signal Transient Response (A
VCL
= 1)
REV. E–8–
OP97
OP97
10k⍀
VOUT
2
3
6
VIN
Figure 5. Unity-Gain Follower
Figure 6. Small-Signal Transient Response with Over-
compensation (C
LOAD
= 1000 pF, A
VCL
= 1, C
OC
= 220 pF)
GUARDING AND SHIELDING
To maintain the extremely high input impedances of the OP97,
care must be taken in circuit board layout and manufacturing.
Board surfaces must be kept scrupulously clean and free of
moisture. Conformal coating is recommended to provide a
humidity barrier. Even a clean PC board can have 100 pA of
leakage currents between adjacent traces, so that guard rings
should be used around the inputs. Guard traces are operated at
a voltage close to that on the inputs, so that leakage currents
become minimal. In noninverting applications, the guard ring
should be connected to the common-mode voltage at the invert-
ing input (Pin 2). In inverting applications, both inputs remain
at ground, so that the guard trace should be grounded. Guard
traces should be made on both sides of the circuit board.
OP97
2
3
6
UNITY-GAIN FOLLOWER
OP97
2
3
6
NONINVERTING AMPLIFIER
OP97
2
3
6
INVERTING AMPLIFIER
18
PDIP
BOTTOM VIEW
Figure 9. Guard Ring Layout and Connections
OP97
VOUT
2
3
6
IO
IO
DIGITAL
INPUTS
30pF
RFB
PM7548
Figure 7. DAC Output Amplifier
OP97
R5
10k⍀
V
OUT
2
3
6
V
1
R1
10k⍀
R2
10k⍀
R3
10k⍀
R4
10k⍀–15V
+15V
7
4
R
L
I
L
Figure 8. Current Monitor
High impedance circuitry is extremely susceptible to RF pickup,
line frequency hum, and radiated noise from switching power
supplies. Enclosing sensitive analog sections within grounded
shields is generally necessary to prevent excessive noise pickup.
Twisted-pair cable will aid in rejection of line frequency hum.
The OP97 is an excellent choice as an output amplifier for
higher resolution CMOS DACs. Its tightly trimmed offset volt-
age and minimal bias current result in virtually no degradation
of linearity, even over wide temperature ranges.
Figure 8 shows a versatile monitor circuit that can typically
sense current at any point between the ±15 V supplies. This
makes it ideal for sensing current in applications such as full
bridge drivers where bidirectional current is associated with
large common-mode voltage changes. The 114 dB CMRR of
the OP97 makes the amplifier’s contribution to common-mode
error negligible, leaving only the error due to the resistor ratio
inequality. Ideally, R2/R4 = R3/R5.
REV. E
OP97
–9–
The digitally programmable gain amplifier shown in Figure 10
has 12-bit gain resolution with 10-bit gain linearity over the
range of –1 to –1024. The low bias current of the OP97 main-
tains this linearity, while C1 limits the noise voltage bandwidth
allowing accurate measurement down to microvolt levels.
DIGITAL IN GAIN (Av)
4095 –1.00024
2048 –2
1024 –4
512 –8
256 –16
128 –32
64 –64
32 –128
16 –256
8–512
4–1024
2–2048
1–4096
0Open Loop
Many high speed amplifiers suffer from less-than-perfect low
frequency performance. A combination amplifier consisting of a
high precision, slow device like the OP97 and a faster device
such as the OP44 results in uniformly accurate performance
from dc to the high frequency limit of the OP44, which has a
gain-bandwidth product of 23 MHz. The circuit shown in
Figure 11 accomplishes this, with the OP44 providing high
frequency amplification and the OP97 operating on low fre-
quency signals and providing offset correction. Offset voltage
and drift of the circuit are controlled by the OP97.
VOUT
OP97
2
3
6
0.1F
+15V
C1
220pF
17
16
PM7541
VREF
RFB
1
2
3
18
ⴞ2.5mV TO ⴞ10V
RANGE DEPENDING
ON GAIN SETTING
VIN
–15V
0.1F
+15V
IOUT 1
IOUT 2
0.1F
Figure 10. Precision Programmable Gain Amplifier
OP44
V
OUT
2
3
6
OP97
2
3
6
R2
20k⍀
5
10k⍀
1F
R1
2k⍀
V
IN
0.1F
10k⍀
5pF
R2
R1
A
V
=
Figure 11. Combination High-Speed, Precision Amplifier
Figure 12. Combination Amplifier Transient Response
REV. E–10–
OP97
OUTLINE DIMENSIONS
8-Lead Plastic Dual In-Line Package [PDIP]
P-Suffix
(N-8)
Dimensions shown in inches and (millimeters)
SEATING
PLANE
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79) 0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
8
14
5
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.100 (2.54)
BSC
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
0.015
(0.38)
MIN
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
S-Suffix
(R-8)
Dimensions shown in millimeters and (inches)
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) ⴛ 45ⴗ
8ⴗ
0ⴗ
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
85
41
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
REV. E
OP97
–11–
Revision History
Location Page
7/03—Data Sheet changed from REV. D to REV. E.
Deleted H-08A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Deleted Q-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Deleted E-20A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Deleted DIE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated TPC 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1/02—Data Sheet changed from REV. C to REV. D.
Edits to Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
C00299–0–7/03(E)
–12–
