DataSheeT - enpirion(R) power solutions EN6347QA 4A PowerSoC Step-Down DC-DC Switching Converter with Integrated Inductor DESCRIPTION FEATURES The EN6347QA is a Power System on a Chip (PowerSoC) DC-DC converter that is AEC-Q100 qualified for automotive applications. It integrates MOSFET switches, small-signal circuits, compensation, and the inductor in an advanced 4mm x 7mm x 1.85mm 38-pin QFN package. * Integrated Inductor, MOSFETs, Controller The EN6347QA is specifically designed to meet the precise voltage and fast transient requirements of present and future high-performance, low-power processor, DSP, FPGA, memory boards and system level applications in distributed power architectures. The device's advanced circuit techniques, high switching frequency, and proprietary integrated inductor technology deliver high-quality, ultra compact, non-isolated DC-DC conversion. Intel Enpirion Power Solutions significantly help in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements In addition, a reduction in the number of vendors required for the complete power solution helps to enable an overall system cost savings. All Enpirion products are RoHS compliant and leadfree manufacturing environment compatible. EN6347QA 560 * AEC-Q100 Qualified for Automotive Applications * Up to 4A Continuous Operating Current * High Efficiency (Up to 95%) * Frequency Synchronization to External Clock * Input Voltage Range (2.5V to 6.6V) * Programmable Light Load Mode * Optimized Total Solution Size (90mm2) * Output Enable Pin and Power OK * Programmable Soft-Start * Thermal Shutdown, Over-Current, Short Circuit, and Under-Voltage Protection * RoHS Compliant, MSL Level 3, 260C Reflow APPLICATIONS * Automotive Applications * Point of Load Regulation for Low-Power, ASICs Multi-Core and Communication Processors, DSPs, FPGAs and Distributed Power Architectures * Beat Frequency/Noise Sensitive Applications Efficiency vs. Output Current VOUT VIN PVIN * -40C to +105C Ambient Temperature Range 100 VOUT 90 RA AVIN 80 PG 22F 1206 X7R PGND VFB CA 47F 1210 X7R PGND LLM/ SS AGND SYNC EFFICIENCY (%) Optional RB CSS 70 60 50 40 30 CONDITIONS VIN = 5V 20 VOUT = 3.3V LLM 10 VOUT = 3.3V PWM 0 0.01 0.1 1 10 OUTPUT CURRENT (A) Figure 1: Simplified Applications Circuit Figure 2: Highest Efficiency in Smallest Solution Size Page 1 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA ORDERING INFORMATION Part Number Package Markings TJ Rating Package Description EN6347QA N6347A -40C to +125C 38-pin (4mm x 7mm x 1.85mm) QFN T&R EVB-EN6347QA N6347A QFN Evaluation Board Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html NC(SW) NC(SW) NC(SW) NC(SW) AVIN AGND VFB SS RLLM POK ENABLE LLM / SYNC 37 36 35 34 33 32 31 30 29 28 27 26 KEEP OUT NC(SW) 12 13 14 15 16 17 18 19 PGND PGND PGND PGND PGND PGND PVIN 6 NC(SW) VOUT 11 5 VOUT VOUT 10 4 VOUT NC 39 PGND KEEP OUT 9 3 VOUT NC 8 2 VOUT NC(SW) 7 1 VOUT NC(SW) 38 PIN FUNCTIONS 25 BGND 24 VDDB 23 BTMP 22 PG 21 PVIN 20 PVIN Figure 3: Pin Diagram (Top View) NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically connected to the PCB. Refer to Figure 11 for details. NOTE C: White `dot' on top left is pin 1 indicator on top of the device package. Page 2 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA PIN DESCRIPTIONS PIN 1,2, 12, 34-38 NAME NC(SW) TYPE FUNCTION - NO CONNECT - These pins are internally connected to the common switching node of the internal MOSFETs. They are not to be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may result in damage to the device. 3,4 NC - NO CONNECT - These pins may be internally connected. Do not connect to each other or to any other electrical signal. Failure to follow this guideline may result in device damage. 5- 11 VOUT Power Regulated converter output. Connect to the load and place output filter capacitor(s) between these pins and PGND pins. Refer to the Layout Recommendation section. 13-18 PGND Ground Input/Output power ground. Connect to the ground electrode of the input and output filter capacitors. See VOUT and PVIN pin descriptions for more details. 19-21 PVIN Power Input power supply. Connect to input power supply. Decouple with input capacitor to PGND pin. Refer to the Layout Recommendation section. 22 PG Analog PMOS gate. Connect a 560 Ohm resistor from PVIN to PG. An optional capacitor (22nF) may be placed from PG to BGND to help filter PG in noisy environments. 23 BTMP Analog Bottom plate ground. 24 VDDB Power Internal regulated voltage used for the internal control circuitry. An optional capacitor (220nF) may be placed from VDDB to BGND to help filter the VDDB output in noisy environments. 25 BGND Power Ground for VDDB. Do not connect BGND to any other ground. See pin 24 description. 26 LLM/SYNC Analog Dual function pin providing LLM Enable and External Clock Synchronization (see Application Section). At static Logic HIGH, device will allow automatic engagement of light load mode. At static logic LOW, the device is forced into PWM only. A clocked input to this pin will synchronize the internal switching frequency to the external signal. If this pin is left floating, it will pull to a static logic high, enabling LLM. 27 ENABLE Analog Input Enable. Applying logic high enables the output and initiates a softstart. Applying logic low discharges the output through a soft-shutdown. Digital Power OK is an open drain transistor used for power system state indication. POK is logic high when VOUT is within 10% of VOUT nominal and has an internal 100k pull-up resistance to AVIN. Analog Programmable LLM engage resistor to AGND allows for adjustment of load current at which Light-Load Mode engages. Can be left open for PWM only operation. 28 29 POK RLLM Page 3 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA PIN NAME 30 SS TYPE FUNCTION Analog A soft-start capacitor is connected between this pin and AGND. The value of the capacitor controls the soft-start interval. Refer to Soft-Start Operation in the Functional Description section for more details. 31 VFB Analog External Feedback Input. The feedback loop is closed through this pin. A voltage divider at VOUT is used to set the output voltage. The midpoint of the divider is connected to VFB. A phase lead capacitor from this pin to VOUT is also required to stabilize the loop. 32 AGND Power Ground for internal control circuits. Connect to the power ground plane with a via right next to the pin. 33 AVIN Power Input power supply for the controller. Connect to input voltage at a quiet point. Refer to the Layout Recommendation section. Ground Power ground thermal pad. Not a perimeter pin. Connect thermal pad to the system GND plane for heat-sinking purposes. Refer to the Layout Recommendation section. 39 PGND ABSOLUTE MAXIMUM RATINGS CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Absolute Maximum Pin Ratings PARAMETER SYMBOL MIN MAX UNITS PVIN, AVIN, VOUT -0.3 7.0 V ENABLE, POK -0.3 VIN+0.3 V VFB, SS -0.3 2.5 V MIN MAX UNITS +150 C +150 C +260 C MAX UNITS Absolute Maximum Thermal Ratings PARAMETER CONDITION Maximum Operating Junction Temperature Storage Temperature Range Reflow Peak Body Temperature -65 (10 Sec) MSL3 JEDEC J-STD-020A Absolute Maximum ESD Ratings PARAMETER CONDITION MIN HBM (Human Body Model) 2000 V CDM (Charged Device Model) 500 V Page 4 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX VIN 2.5 6.6 Output Voltage Range VOUT 0.75 Output Current Range IOUT Operating Ambient Temperature Range TA Operating Junction Temperature TJ Input Voltage Range VIN - VDO UNITS V V (1) 4 A -40 +105 C -40 +125 C THERMAL CHARACTERISTICS PARAMETER SYMBOL TYPICAL UNITS TSD 160 C TSDHYS 35 C Thermal Resistance: Junction to Ambient (0 LFM) (2) JA 30 C/W Thermal Resistance: Junction to Case (0 LFM) JC 3 C/W Thermal Shutdown Thermal Shutdown Hysteresis (1) VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table. (2) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high thermal conductivity boards. Page 5 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA ELECTRICAL CHARACTERISTICS NOTE: VIN = 6.6V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted. Typical values are at TA = 25C. PARAMETER Operating Input Voltage SYMBOL TEST CONDITIONS VIN MIN TYP 2.5 MAX UNITS 6.6 V Under Voltage LockOut - VIN Rising VUVLOR Voltage above which UVLO is not asserted 2.3 V Under Voltage LockOut - VIN Falling VUVLOF Voltage below which UVLO is asserted 2.075 V Shut-Down Supply Current IS ENABLE = 0V 100 A Operating Quiescent Current IQ LLM/SYNC = High 650 mA Feedback Pin Voltage EN6347QA (3) VFB Feedback Pin Voltage EN6347QA VFB Feedback pin Input Leakage Current (4) IFB VFB pin input leakage current -5 tRISE Measured from when VIN > VUVLOR & ENABLE pin voltage crosses its logic high threshold to when VOUT reaches its final value. CSS = 15 nF 0.9 10 VOUT Rise Time Range (4) Soft Start Capacitance Range VIN = 5V, ILOAD = 0, TA = 25C 3.0V VIN 6.0V 0A ILOAD 4A CSS_RANGE 0.7425 0.75 0.7575 V 0.735 0.75 0.765 V 5 nA 1.2 1.5 ms 47 68 nF Drop-Out Voltage (4) VDO VINMIN - VOUT at full load 240 360 mV Drop-Out Resistance (4) RDO Input to output resistance 60 90 m Continuous Output Current IOUT Over Current Trip Level IOCP Precision Disable Threshold VDISABLE Precision Enable Threshold VEN PMM mode 0 4 LLM mode (5) 0.002 4 5 VIN = 5V, VOUT = 1.2V ENABLE pin logic going low ENABLE pin logic going high A A 0 0.6 V 1.8 VIN V 2.5V VIN 6.6V Page 6 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA PARAMETER SYMBOL ENABLE Lockout Time TENLOCKOUT ENABLE Pin Input Current (4) Switching Frequency (Free Running) TEST CONDITIONS MIN TYP MAX UNITS 3.2 ms IENABLE ENABLE pin has ~180k pull down 40 A FSW Free running frequency of oscillator 3 MHz External SYNC Clock Frequency Lock Range FPLL_LOCK Range of frequency SYNC Input Threshold - Low (LLM/SYNC PIN) VSYNC_LO SYNC Clock Logic Level SYNC Input Threshold - High (LLM/SYNC PIN) (6) VSYNC_HI SYNC Clock Logic Level POK Lower Threshold POKLT Output voltage as a fraction of expected output voltage POK Low Voltage VPOKL With 4mA current sink into POK 0.4 V POK High Voltage VPOKH 2.5V VIN 6.6V VIN V POK Pin Leakage Current (4) IPOKH POK is high 1 A SYNC 2.5 1.8 LLM Logic Low (LLM/SYNC PIN) VLLM_LO LLM Static Logic Level LLM Logic High (LLM/SYNC PIN) VLLM_HI LLM Static Logic Level 3.5 MHz 0.8 V 2.5 V 90 Minimum VIN-VOUT to ensure proper LLM operation LLM Engage Headroom LLM/SYNC Pin Current clock % 800 mV 0.3 1.5 LLM/SYNC Pin is <2.5V V V <100 nA (3) The VFB pin is a sensitive node. Do not touch VFB while the device is in regulation. (4) Parameter not production tested but is guaranteed by design. (5) LLM operation is normally only guaranteed above the minimum specified output current. (6) For proper operation of the synchronization circuit, the high-level amplitude of the SYNC signal should not be above 2.5V. Page 7 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA PWM Efficiency vs. IOUT (VIN = 3.3V) 100 90 80 70 60 50 40 30 20 10 0 PWM Efficiency vs. IOUT (VIN = 5.0V) 100 90 80 EFFICIENCY (%) EFFICIENCY (%) TYPICAL PERFORMANCE CURVES VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V CONDITIONS CONDITIONS VIN = 3.3V V IN = 3.3V 0 0.5 1 1.5 2 3.5 VOUT = 3.3V 50 VOUT = 2.5V 40 VOUT = 1.8V 30 VOUT = 1.5V CONDITIONS VIN = 5V 10 VOUT = 1.0V 3 60 20 VOUT = 1.2V 2.5 70 4 0 0.5 1 100 2 2.5 3 3.5 4 LLM Efficiency vs. IOUT (VIN = 5.0V) 90 80 EFFICIENCY (%) EFFICIENCY (%) 1.5 OUTPUT CURRENT (A) LLM Efficiency vs. IOUT (VIN = 3.3V) VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V CONDITIONS VIN = 3.3V 0.1 60 VOUT = 3.3V 50 VOUT = 2.5V 40 VOUT = 1.8V 30 VOUT = 1.5V 20 VOUT = 1.2V CONDITIONS VIN = 5V 10 VOUT = 1.0V 1 70 0 0.01 10 0.1 OUTPUT CURRENT (A) VOUT = 1.2V VOUT = 1.0V 1 10 OUTPUT CURRENT (A) Output Voltage vs. Output Current Output Voltage vs. Output Current 1.020 1.220 1.015 VIN = 3.3V 1.010 VIN = 5.0V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) VOUT = 1.0V 0 OUTPUT CURRENT (A) 100 90 80 70 60 50 40 30 20 10 0 0.01 VOUT = 1.2V 1.005 1.000 0.995 0.990 CONDITIONS VOUT = 1.0V 0.985 0.5 1 1.5 2 2.5 3 3.5 VIN = 3.3V 1.210 VIN = 5.0V 1.205 1.200 1.195 1.190 CONDITIONS VOUT = 1.2V 1.185 1.180 0.980 0 1.215 4 0 0.5 1 1.5 2 2.5 3 3.5 4 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Page 8 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA TYPICAL PERFORMANCE CURVES (CONTINUED) Output Voltage vs. Output Current Output Voltage vs. Output Current 1.820 1.515 VIN = 3.3V 1.510 VIN = 5.0V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.520 1.505 1.500 1.495 1.490 CONDITIONS VOUT = 1.5V 1.485 1.480 0 0.5 1 1.5 2 2.5 3 3.5 1.815 VIN = 3.3V 1.810 VIN = 5.0V 1.805 1.800 1.795 1.790 CONDITIONS VOUT = 1.8V 1.785 1.780 0 4 0.5 1 2.5 3 3.5 4 3.320 2.515 VIN = 3.3V 2.510 VIN = 5.0V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2 Output Voltage vs. Output Current Output Voltage vs. Output Current 2.520 2.505 2.500 2.495 2.490 CONDITIONS VOUT = 2.5V 2.485 2.480 0 0.5 1 1.5 2 2.5 3 3.5 3.315 VIN = 5.0V 3.310 3.305 3.300 3.295 3.290 CONDITIONS VOUT = 3.3V 3.285 3.280 0 4 0.5 Output Voltage vs. Input Voltage 1.815 1.815 OUTPUT VOLTAGE (V) 1.820 1.810 1.805 1.800 1.795 CONDITIONS VOUT_NOM = 1.8V Load = 0A 1.785 1.780 2.5 3 3.5 4 4.5 5 1.5 2 2.5 3 3.5 4 Output Voltage vs. Input Voltage 1.820 1.790 1 OUTPUT CURRENT (A) OUTPUT CURRENT (A) OUTPUT VOLTAGE (V) 1.5 OUTPUT CURRENT (A) OUTPUT CURRENT (A) 1.810 1.805 1.800 1.795 1.790 CONDITIONS VOUT_NOM = 1.8V Load = 1A 1.785 1.780 5.5 6 2.5 3 3.5 4 4.5 5 5.5 6 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Page 9 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA TYPICAL PERFORMANCE CURVES (CONTINUED) Output Voltage vs. Input Voltage 1.820 1.820 1.815 1.815 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Output Voltage vs. Input Voltage 1.810 1.805 1.800 1.795 1.790 CONDITIONS VOUT_NOM = 1.8V Load = 2A 1.785 1.810 1.805 1.800 1.795 CONDITIONS CONDITIONS VOUT_NOM = 1.8V Load = A Load = 3A 1.790 1.785 1.780 1.780 2.5 3 3.5 4 4.5 5 5.5 2.5 6 3 3.5 Output Voltage vs. Input Voltage 1.830 1.815 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4.5 1.810 1.805 1.800 1.795 CONDITIONS CONDITIONS VOUT_NOM = 1.8V Load = A Load = 4A 1.790 1.785 3 3.5 4 4.5 5 5.5 1.820 LOAD = 1A LOAD = 0A 1.790 -40 -20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (C) Output Voltage vs. Temperature LOAD = 4A LOAD = 3A LOAD = 2A LOAD = 1A 1.810 LOAD = 2A 1.800 6 LOAD = 0A 1.800 1.790 1.780 1.830 OUTPUT VOLTAGE (V) 1.820 LOAD = 3A 1.810 Output Voltage vs. Temperature CONDITIONS VIN = 5.0V VOUT_NOM = 1.8V 6 LOAD = 4A CONDITIONS VIN = 3.3V VOUT_NOM = 1.8V INPUT VOLTAGE (V) 1.830 5.5 1.780 1.780 2.5 5 Output Voltage vs. Temperature 1.820 OUTPUT VOLTAGE (V) 4 INPUT VOLTAGE (V) INPUT VOLTAGE (V) CONDITIONS VIN = 6.0V VOUT_NOM = 1.8V 1.820 LOAD = 4A LOAD = 3A LOAD = 2A LOAD = 1A 1.810 LOAD = 0A 1.800 1.790 1.780 -40 -20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (C) -40 -20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (C) Page 10 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA TYPICAL PERFORMANCE CHARACTERISTICS EMI Performance (Horizontal Scan) 100.0 3.5 90.0 3.0 80.0 LEVEL (dBV/m) MAXIMUM OUTPUT CURRENT (A) Output Current De-rating 4.0 2.5 2.0 1.5 VOUT = 1.8V 1.0 VOUT = 2.5V 0.5 VOUT = 3.3V CONDITIONS VIN = 5.0V TJMAX = 125C JA = 30C/W No Air Flow CONDITIONS VIN = 5.0V VOUT_NOM = 1.5V LOAD = 0.5 70.0 60.0 50.0 CISPR 22 Class B 3m 40.0 30.0 20.0 0.0 10.0 55 60 65 70 75 80 85 90 95 100 105 AMBIENT TEMPERATURE (C) 30 300 FREQUENCY (MHz) EMI Performance (Vertical Scan) 100.0 CONDITIONS VIN = 5.0V VOUT_NOM = 1.5V LOAD = 0.5 LEVEL (dBV/m) 90.0 80.0 70.0 60.0 50.0 CISPR 22 Class B 3m 40.0 30.0 20.0 10.0 30 300 FREQUENCY (MHz) Page 11 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) Output Ripple at 20MHz Bandwidth CONDITIONS VIN = 3.3V VOUT = 1V IOUT = 4A CIN = 22F (1206) COUT = 47 F (1210) + 10F (1206) VOUT (AC Coupled) Output Ripple at 20MHz Bandwidth CONDITIONS VIN = 5V VOUT = 1V IOUT = 4A CIN = 22F (1206) COUT = 47 F (1210) + 10F (1206) VOUT (AC Coupled) LLM Output Ripple at 100mA CONDITIONS VIN = 5V VOUT = 1V IOUT = 100mA CIN = 22F (1206) COUT = 2 x 47 F (1210) Output Ripple at 500MHz Bandwidth CONDITIONS VIN = 3.3V VOUT = 1V IOUT = 4A CIN = 22F (1206) COUT = 47 F (1210) + 10F (1206) VOUT (AC Coupled) Output Ripple at 500MHz Bandwidth CONDITIONS VIN = 5.0V VOUT = 1V IOUT = 4A CIN = 22F (1206) COUT = 47 F (1210) + 10F (1206) VOUT (AC Coupled) LLM Output Ripple at 100mA VOUT (AC Coupled) CONDITIONS VIN = 5V VOUT = 3V IOUT = 100mA CIN = 22F (1206) COUT = 2 x 47 F (1210) VOUT (AC Coupled) Page 12 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) Enable Power Up/Down Enable Power Up/Down ENABLE ENABLE VOUT VOUT POK POK CONDITIONS VIN = 5.5V, VOUT = 3.3V NO LOAD, Css = 47nF CIN = 22F (1206) COUT = 47 F (1210) LOAD LOAD CONDITIONS VIN = 5.0V, VOUT = 3.3V, LOAD=0.825, Css = 47nF CIN = 22F (1206), COUT = 47 F (1210) LLM Load Transient from 0.01 to 4A VOUT (AC Coupled) LOAD VOUT (AC Coupled) CONDITIONS LLM = ENABLED VIN = 5V VOUT = 1V CIN = 22F (1206) COUT = 2 x 47F (1210) CONDITIONS LLM = ENABLED VIN = 5V VOUT = 3V CIN = 22F (1206) COUT = 2 x 47F (1210) LOAD PWM Load Transient from 0 to 4A VOUT (AC Coupled) LOAD LLM Load Transient from 0.01 to 4A PWM Load Transient from 0 to 4A VOUT (AC Coupled) CONDITIONS LLM = DISABLED VIN = 5V VOUT = 1V CIN = 22F (1206) COUT = 47F (1210) + 10F (1206) LOAD CONDITIONS LLM = DISABLED VIN = 5V VOUT = 3V CIN = 22F (1206) COUT = 47F (1210) + 10F (1206) Page 13 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA FUNCTIONAL BLOCK DIAGRAM RLLM BTMP PG PVIN UVLO Thermal Limit P-Drive Current Limit NC(SW) Mode Logic VOUT N-Drive BGND (-) PWM Comp (+) LLM/SYNC PGND Compensation Network PLL/Sawtooth Generator (-) Error Amp (+) ENABLE VDDB VFB Power Good Logic POK AVIN SS Soft Start Voltage Reference Regulated Voltage AGND Figure 4: Functional Block Diagram FUNCTIONAL DESCRIPTION Synchronous DC-DC Step-Down PowerSoC The EN6347QA is a synchronous, programmable power supply with integrated power MOSFET switches and integrated inductor. The nominal input voltage range is 2.5V to 6.6V. The output voltage is programmed using an external resistor divider network. The control loop is voltage-mode with a type III compensation network. Much of the compensation circuitry is internal to the device. However, a phase lead capacitor is required along with the output voltage feedback resistor divider to complete the type III compensation network. The device uses a low-noise PWM topology and also integrates a unique light-load mode (LLM) to improve efficiency at light output load currents. LLM can be disabled with a logic pin. Up to 4A of continuous output current can be drawn from this converter. The 3MHz switching frequency allows the use of small size input / output capacitors, and enables wide loop bandwidth within a small foot print. Page 14 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA Protection Features: The power supply has the following protection features: * Over-current protection (to protect the IC from excessive load current) * Thermal shutdown with hysteresis. * Under-voltage lockout circuit to keep the converter output off while the input voltage is less than 2.3V. Additional Features: * The switching frequency can be phase-locked to an external clock to eliminate or move beat frequency tones out of band. * Soft-start circuit allowing controlled startup when the converter is initially powered up. The soft start time is programmable with an appropriate choice of soft start capacitor. * Power good circuit indicating the output voltage is greater than 90% of programmed value as long as feedback loop is closed. * To maintain high efficiency at low output current, the device incorporates automatic light load mode operation. Precision Enable Operation The ENABLE pin provides a means to enable normal operation or to shut down the device. When the ENABLE pin is asserted (high) the device will undergo a normal soft-start. A logic low on this pin will power the device down in a controlled manner. From the moment ENABLE goes low, there is a fixed lock out time before the output will respond to the ENABLE pin re-asserted (high). This lock out is activated for even very short logic low pulses on the ENABLE pin. The ENABLE signal must be pulled high at a slew rate faster than 1V/5s in order to meet startup time specifications; otherwise, the device may experience a delay of 4.2ms (lock-out time) before startup occurs. See the Electrical Characteristics Table for technical specifications for the ENABLE pin. LLM/SYNC Pin This is a dual function pin providing LLM Enable and External Clock Synchronization. At static Logic HIGH, device will allow automatic engagement of light load mode. At static logic LOW, the device is forced into PWM only. A clocked input to this pin will synchronize the internal switching frequency - LLM mode is not available if this input is clocked. If this pin is left floating, it will pull to a static logic high, enabling LLM. Frequency Synchronization The switching frequency of the DC-DC converter can be phase-locked to an external clock source to move unwanted beat frequencies out of band. To avail this feature, the clock source should be connected to the LLM/SYNC pin. An activity detector recognizes the presence of an external clock signal and automatically phase-locks the internal oscillator to this external clock. Phase-lock will occur as long as the clock frequency is in the range specified in the Electrical Characteristics Table. For proper operation of the synchronization circuit, the high-level amplitude of the SYNC signal should not be above 2.5V. Please note LLM is not available when synchronizing to an external frequency. Page 15 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA Spread Spectrum Mode The external clock frequency may be swept between the limits specified in the Electrical Characteristics Table at repetition rates of up to 10kHz in order to reduce EMI frequency components. Soft-Start Operation During Soft-start, the output voltage is ramped up gradually upon start-up. The output rise time is controlled by the choice of soft-start capacitor, which is placed between the SS pin (30) and the AGND pin (32). Rise Time: TR (CSS* 80k) 25% During start-up of the converter, the reference voltage to the error amplifier is linearly increased to its final level by an internal current source of approximately 10A. Typical soft-start rise time is ~3.8ms with SS capacitor value of 47nF. The rise time is measured from when VIN > VUVLOR and ENABLE pin voltage crosses its logic high threshold to when VOUT reaches its programmed value. Please note LLM function is disabled during the soft-start ramp-up time. POK Operation The POK signal is an open drain signal (requires a pull up resistor to VIN or similar voltage) from the converter indicating the output voltage is within the specified range. The POK signal will be logic high (V IN) when the output voltage is above 90% of programmed VOUT. If the output voltage goes below this threshold, the POK signal will be logic low. Light Load Mode (LLM) Operation The EN6347QA uses a proprietary light load mode to provide high efficiency at low output currents. When the LLM/SYNC pin is high, the device is in automatic LLM "Detection" mode. When the LLM/SYNC pin is low, the device is forced into PWM mode. In automatic LLM "Detection" mode (LLM connected to AVIN with 50k), when a light load condition is detected, the device will: (1) Step VOUT up by approximately 1.0% above the nominal operating output voltage setting, V NOM and as low as -0.5% below VNOM, and then (2) Shut down unnecessary circuitry, and then (3) Monitor VOUT. When VOUT falls below VNOM, the device will repeat (1), (2), and (3). The voltage step up, or pre-positioning, improves transient droop when a load transient causes a transition from LLM mode to PWM mode. If a load transient occurs, causing VOUT to fall below the threshold VMIN, the device will exit LLM operation and begin normal PWM operation. Figure 5 demonstrates VOUT behavior during transition into and out of LLM operation. Many multi-mode DC-DC converters suffer from a condition that occurs when the load current increases only slowly so that there is no load transient driving VOUT below the VMIN threshold. In this condition, the device would never exit LLM operation. This could adversely affect efficiency and cause unwanted ripple. To prevent this from occurring, the EN6347QA periodically exits LLM mode into PWM mode and measures the load current. If the load current is above the LLM threshold current, the device will remain in PWM mode. If the load current is below the LLM threshold, the device will re-enter LLM operation. There may be a small overshoot or undershoot in VOUT when the device exits and re-enters LLM. Page 16 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA MAX NOM OUT MIN OUT Figure 5. VOUT behavior in LLM operation The load current at which the device will enter LLM mode is a function of input and output voltage, inductance variation and the RLLM pin resistor. The lower the RLLM resistor value, the lower the current when the device transitions from LLM into PWM mode. A 60k resistor from RLLM to ground is recommended for most applications. For PWM only operation, the RLLM pin can be left open. LLM to PWM Current vs. RLLM LLM TO PWM CURRENT (A) 2.000 VIN = 5V, VOUT = 3.3V 1.800 VIN = 3.3V, VOUT = 2.5V 1.600 VIN = 5V, VOUT = 1V 1.400 VIN = 3.3V, VOUT = 1V 1.200 CONDITIONS TA = 25 C Typical Values 1.000 0.800 0.600 0.400 0.200 0.000 0 10 20 30 40 50 60 70 RLLM RESISTOR (k) 80 90 100 Figure 6. Typical LLM to PWM Current vs. RLLM To ensure normal LLM operation, LLM mode should be enabled and disabled with specific sequencing. For applications with explicit LLM pin control, enable LLM after VIN ramp up is complete. For applications with only ENABLE controlled, tie LLM to ENABLE. Enable the device after V IN ramps up into regulation and disable the device before VIN ramps. For designs with ENABLE and LLM tied to VIN, make sure the device soft-start time is longer than the VIN ramp-up time. LLM will start operating after the soft-start time is completed. NOTE: For proper LLM operation the EN6347QA requires a minimum difference between VIN and VOUT, and a minimum LLM load requirement as specified in the Electrical Characteristics Table. Page 17 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA Over-Current Protection (OCP) The current limit function is achieved by sensing the current flowing through the Power PFET. When the sensed current exceeds the over current trip point, both power FETs are turned off for the remainder of the switching cycle. If the over-current condition is removed, the over-current protection circuit will enable normal PWM operation. If the over-current condition persists, the soft start capacitor will gradually discharge causing the output voltage to fall. When the OCP fault is removed, the output voltage will ramp back up to the desired voltage. This circuit is designed to provide high noise immunity. Thermal Protection Thermal shutdown circuit will disable device operation when the Junction temperature exceeds approximately 150C. After a thermal shutdown event, when the junction temperature drops by approximately 20C, the converter will re-start with a normal soft-start. Input Under-Voltage Lock-Out (UVLO) Internal circuits ensure that the converter will not start switching until the input voltage is above the specified minimum voltage. Hysteresis and input de-glitch circuits ensure high noise immunity and prevent false UVLO triggers. Page 18 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA APPLICATION INFORMATION Output Voltage Setting The EN6347QA uses a Type III voltage mode control compensation network. As noted earlier, a piece of the compensation network is the phase lead capacitor CA in Figure 7. This network is optimized for use with about 50-100F of output capacitance and will provide wide loop bandwidth and excellent transient performance for most applications. Voltage mode operation provides high noise immunity at light load. In some applications, modifications to the compensation may be required. For more information, contact Power Applications support. EN6347QA VOUT VOUT PGND VFB COUT (47F to 1000F) RA 200k CA (10pF to 47pF) VFB = 0.75V RB = VFB x RA VOUT - VFB AGND Figure 7. VOUT Resistor Divider & Compensation Capacitor The EN6347QA output voltage is programmed using a simple resistor divider network. Since VFB is a sensitive node, do not touch the VFB node while the device is in operation as doing so may introduce parasitic capacitance into the control loop that causes the device to behave abnormally and damage may occur. Figure 7 shows the resistor divider configuration. An additional compensation capacitor CA is also required in parallel with the upper resistor. Input Capacitor Selection The EN6347QA requires at least a 22F 1206 case size X7R ceramic input capacitor. Additional input capacitors may be used in parallel to reduce input voltage spikes caused by parasitic line inductance. For applications where the input of the EN6347QA is far from the input power source, be sure to use sufficient bulk capacitors to mitigate the extra line inductance. Low-cost, low-ESR ceramic capacitors should be used as input capacitors for this converter. The dielectric must be X7R rated. Y5V or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. In some applications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling. Page 19 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA Table 1: Recommended Input Capacitors Description 22F, 10V, X7R, 1206 MFG P/N Murata GRM31CR71A226ME15 Taiyo Yuden LMK316AB7226KL-TR AVX 1206ZC226KAT2A Output Capacitor Selection The EN6347QA requires at least one 47F 1210 case size X7R or two 22F 1206 case size X7R ceramic output capacitor. Additional output capacitors may be used in parallel near the load (>4m away) to improve transient response as well as lower output ripple. In some cases modifications to the compensation or output filter capacitance may be required to optimize device performance such as transient response, ripple, or hold-up time. The EN6347QA provides the capability to modify the control loop response to allow for customization for such applications. Note that in Type III Voltage Mode Control, the double pole of the output filter is around 1/2LO Cout , where Cout is the equivalent capacitance of all the output capacitors including the minimum required output capacitors that Altera recommended and the extra bulk capacitors customers added based on their design requirement. While the compensation network was designed based on the capacitors that Altera recommended, increasing the output capacitance will shift the double pole to the direction of lower frequency, which will lower the loop bandwidth and phase margin. In most cases, this will not cause the instability due to adequate phase margin already in the design. In order to maintain a higher bandwidth as well as adequate phase margin, a slight modification of the external compensation is necessary. This can be easily implemented by increasing the leading capacitor value, CA. In addition the ESR of the output capacitors also helps since the ESR and output capacitance forms a zero which also helps to boost the phase Table 2: CA for Output Capacitors Ranges Total COUT Range Recommended CA Minimum ESR 2x22F 10pF 0 100F to 250F 27pF 0 250F to 450F 33pF 0 450F to 1000F 47pF >4m Low ESR ceramic capacitors are required with X7R rated dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. Output ripple voltage is determined by the aggregate output capacitor impedance. Output impedance, denoted as Z, is comprised of effective series resistance, ESR, and effective series inductance, ESL: Z = ESR + ESL Placing output capacitors in parallel reduces the impedance and will hence result in lower PWM ripple voltage. In addition, higher output capacitance will improve overall regulation and ripple in light-load mode. 1 Z Total 1 1 1 ... Z1 Z 2 Zn Page 20 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA Table 3: Recommended Output Capacitors Description 47F, 6.3V, X7R, 1210 22F, 10V, X7R, 1206 10F, 10V, X7R, 0805 MFG P/N Murata GRM32ER70J476ME20 Taiyo Yuden LMK325B7476KM-TR Murata GRM31CR71A226ME15 Taiyo Yuden LMK316AB7226KL-TR AVX 1206ZC226KAT2A Murata GRM21BR71A106KE51 Taiyo Yuden LMK212AB7106MG-T AVX 0805ZC106KAT2A Table 4: Typical PWM Ripple Voltages Output Capacitor Configuration Typical Output Ripple (mVp-p) (as measured on EN6347QA Evaluation Board)* 1 x 47 F 25 47 F + 10 F 14 * Note: 20 MHz BW limit For best LLM performance, we recommend using just 2x47F capacitors mentioned in the above table, and no 10F capacitor. The VOUT sense point should be just after the last output filter capacitor right next to the device. Additional bulk output capacitance beyond the above recommendations can be used on the output node of the EN6347QA as long as the bulk capacitors are far enough from the VOUT sense point such that they don't interfere with the control loop operation. Power-Up Sequencing During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN. Tying all three pins together meets these requirements. Pre-Bias Start-up The EN6347QA supports startup into a pre-biased output of up to 1.5V. The output of the EN6347QA can be pre-biased with a voltage up to 1.5V when it is first enabled Page 21 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA THERMAL CONSIDERATIONS Thermal considerations are important power supply design facts that cannot be avoided in the real world. Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. The Enpirion PowerSoC helps alleviate some of those concerns. The Enpirion EN6347QA DC-DC converter is packaged in a 4x7x1.85mm 38-pin QFN package. The QFN package is constructed with copper lead frames that have exposed thermal pads. The exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to act as a heat sink. The recommended maximum junction temperature for continuous operation is 125C. Continuous operation above 125C may reduce long-term reliability. The device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 160C. The following example and calculations illustrate the thermal performance of the EN6347QA. Example: VIN = 5V VOUT = 3.3V IOUT = 4A First calculate the output power. POUT = 3.3V x 4A = 13.2W Next, determine the input power based on the efficiency () shown in Figure 8. 100 PWM Efficiency vs. IOUT (VIN = 5.0V) 90 EFFICIENCY (%) 80 ~92% 70 60 50 40 30 20 CONDITIONS VIN = 5V 10 VOUT = 3.3V 0 0 0.5 1 1.5 2 2.5 3 3.5 4 OUTPUT CURRENT (A) Figure 8: Efficiency vs. Output Current Page 22 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA For VIN = 5V, VOUT = 3.3V at 4A, 92% = POUT / PIN = 92% = 0.92 PIN = POUT / PIN 13.2W / 0.92 14.35W The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output power from the input power. PD = PIN - POUT 14.35W - 13.2W 1.148W With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA value (JA). The JA parameter estimates how much the temperature will rise in the device for every watt of power dissipation. The EN6347QA has a JA value of 30 C /W without airflow. Determine the change in temperature (T) based on PD and JA. T = PD x JA T 1.148W x 30C/W = 34.43C 35C The junction temperature (TJ) of the device is approximately the ambient temperature (T A) plus the change in temperature. We assume the initial ambient temperature to be 25C. TJ = TA + T TJ 25C + 35C 60C The maximum operating junction temperature (TJMAX) of the device is 125C, so the device can operate at a higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated. TAMAX = TJMAX - PD x JA 125C - 35C 90C The maximum ambient temperature (before de-rating) the device can reach is 90C given the input and output conditions. Note that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate. Page 23 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA APPLICATION CIRCUITS Figure 9: Engineering Schematic with Engineering Notes Page 24 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA LAYOUT RECOMMENDATIONS Figure 10 shows critical components and layer 1 traces of a typical EN6347QA layout with ENABLE tied to VIN in PWM mode. Alternate ENABLE configurations and other small signal pins need to be connected and routed according to specific customer application. Please see the Gerber files on the Altera website www.altera.com/powersoc for exact dimensions and other layers. Please refer to this Figure while reading the layout recommendations in this section. Figure 10: Top PCB Layer Critical Components and Copper for Minimum Footprint (Top View) Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EN6347QA package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EN6347QA should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: Three PGND pins are dedicated to the input circuit, and three to the output circuit. The slit in Figure 10 separating the input and output GND circuits helps minimize noise coupling between the converter input and output switching loops. Recommendation 3: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Please see the Gerber files on the Altera website www.altera.com/powersoc. Recommendation 4: The large thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the path for heat dissipation from the converter. Recommendation 5: Multiple small vias (the same size as the thermal vias discussed in recommendation 4 should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. It is preferred to put these vias under the capacitors along the edge of the GND copper closest to the +V copper. Please see Figure 10. These vias connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops. If the vias cannot be placed under C IN and COUT, then put them just outside the capacitors along the GND slit separating the two components. Do not use thermal reliefs or spokes to connect these vias to the ground plane. Page 25 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA Recommendation 6: AVIN is the power supply for the internal small-signal control circuits. It should be connected to the input voltage at a quiet point. In Figure 10 this connection is made at the input capacitor close to the VIN connection. Recommendation 7: The layer 1 metal under the device must not be more than shown in Figure 10. See the section regarding exposed metal on bottom of package. As with any switch-mode DC-DC converter, try not to run sensitive signal or control lines underneath the converter package on other layers. Recommendation 8: The VOUT sense point should be just after the last output filter capacitor. Keep the sense trace as short as possible in order to avoid noise coupling into the control loop. Recommendation 9: Keep RA, CA, and RB close to the VFB pin (see Figures 7). The VFB pin is a high-impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect RB directly to the AGND pin instead of going through the GND plane. Page 26 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES Exposed Metal on Bottom of Package Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. However, they do require some special considerations. In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package, as shown in Figure 11. Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board. The PCB top layer under the EN6347QA should be clear of any metal (copper pours, traces, or vias) except for the thermal pad. The "shaded-out" area in Figure 10 represents the area that should be clear of any metal on the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted connections even if it is covered by soldermask. The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from causing bridging between adjacent pins or other exposed metal under the package. Figure 11: Lead-Frame exposed metal (Bottom View) Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB. Page 27 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA Figure 12: EN6347QA PCB Footprint (Top View) The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing specifications. Page 28 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA PACKAGE DIMENSIONS Figure 13: EN6347QA Package Dimensions Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html Page 29 10318 September 4, 2018 Rev I Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6347QA REVISION HISTORY Rev Date Change(s) I August 2018 Changed datasheet into Intel format. WHERE TO GET MORE INFORMATION For more information about Intel(R) and Enpirion(R) PowerSoCs, visit: www.altera.com/enpirion (c) 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. * Other marks and brands may be claimed as the property of others. Page 30 10318 September 4, 2018 Rev I