OP27GSREEL7 - ANALOG DEVICES - Datasheet.Directory

3.75 kV, 7-Channel,

SPIsolator Digital Isolators for SPI

Data Sheet

ADuM3151/ADuM3152/ADuM3153

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Supports up to 17 MHz SPI clock speed

4 high speed, low propagation delay, SPI signal isolation

channels

Three 250 kbps data channels

20-lead SSOP package with 5.1 mm creepage

High temperature operation: 125°C

High common-mode transient immunity: >25 kV/µs

Safety and regulatory approvals

UL recognition per UL 1577

3750 V rms for 1 minute

CSA Component Acceptance Notice 5A

VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

VIORM = 565 V peak

APPLICATIONS

Industrial programmable logic controllers (PLCs)

Sensor isolation

GENERAL DESCRIPTION

The ADuM3151/ADuM3152/ADuM31531 are 7-channel,

SPIsolator™ digital isolators optimized for isolated serial peripheral

interfaces (SPIs). Based on the Analog Devices, Inc., iCoupler®

chip scale transformer technology, the low propagation delay in

the CLK, MO/SI, MI/SO, and SS SPI bus signals supports SPI

clock rates of up to 17 MHz. These channels operate with 14 ns

propagation delay and 1 ns jitter to optimize timing for SPI.

The ADuM3151/ADuM3152/ADuM3153 isolators also provide

three additional independent low data rate isolation channels in

three different channel direction combinations. Data in the slow

channels is sampled and serialized for a 250 kbps data rate with

up to 2.5 µs of jitter in the low speed channels.

FUNCTIONAL BLOCK DIAGRAMS

ENCODE

CONTROL

BLOCK

DECODE

DECODE ENCODE

ENCODE DECODE

DD1

GND

MCLK

MSS

DD2

GND

SCLK

SSS

GND

ADuM3151

12368-001

CONTROL

BLOCK

Figure 1. ADuM3151 Functional Block Diagram

ENCODE DECODE

DECODE ENCODE

ENCODE DECODE

DD1

GND

MCLK

MSS

DD2

GND

SCLK

SSS

GND

ADuM3152

12368-002

CONTROL

BLOCK CONTROL

BLOCK

Figure 2. ADuM3152 Functional Block Diagram

ENCODE DECODE

DECODE ENCODE

ENCODE DECODE

DD1

GND

MCLK

MSS

DD2

GND

SCLK

SSS

GND

ADuM3153

12368-003

CONTROL

BLOCK CONTROL

BLOCK

Figure 3. ADuM3153 Functional Block Diagram

1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.

ADuM3151/ADuM3152/ADuM3153 Data Sheet

Rev. B | Page 2 of 22

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagrams ............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3.3 V Operation ............................ 5

Electrical Characteristics—Mixed 5 V/3.3 V Operation ........ 7

Electrical Characteristics—Mixed 3.3 V/5 V Operation ........ 9

Package Characteristics ............................................................. 10

Regulatory Information ............................................................. 11

Insulation and Safety Related Specifications .......................... 11

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

Insulation Characteristics .......................................................... 12

Recommended Operating Conditions .................................... 12

Absolute Maximum Ratings ......................................................... 13

ESD Caution................................................................................ 13

Pin Configurations and Function Descriptions ......................... 14

Typical Performance Characteristics ........................................... 17

Applications Information .............................................................. 18

Introduction ................................................................................ 18

Printed Circuit Board (PCB) Layout ....................................... 19

Propagation Delay Related Parameters ................................... 19

DC Correctness and Magnetic Field Immunity ..................... 19

Power Consumption .................................................................. 20

Insulation Lifetime ..................................................................... 20

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 22

REVISION HISTORY

6/2017—Rev. A to Rev. B

Change to Logic High Output Voltages Parameter, Table 6 .............. 6

Changes to Logic High Output Voltages Parameter, Table 9 ............. 8

Changes to Logic High Output Voltages Parameter, Table 12 ........ 10

Change to Table 20 ..................................................................................... 14

Change to Table 21 ..................................................................................... 15

Change to Table 22 ..................................................................................... 16

3/2015—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Changes to Table 2 ............................................................................ 3

Changes to Table 3 ............................................................................ 4

Changes to Table 5 ............................................................................ 5

Changes to Table 6 ............................................................................ 6

Changes to Table 8 ............................................................................. 7

Changes to Table 9 ............................................................................. 8

Changes to Table 11 .......................................................................... 9

Changes to Table 12 ....................................................................... 10

Changes to Regulatory Information Section and Table 14 ....... 11

Changes to Table 16 and Figure 4................................................. 12

Changes to Figure 8, Figure 9, Figure 11, and Figure 12 ........... 17

Changes to High Speed Channels Section .................................. 18

Changes to Power Consumption Section .................................... 20

6/2014—Revision 0: Initial Version

Data Sheet ADuM3151/ADuM3152/ADuM3153

Rev. B | Page 3 of 22

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All typical specifications are at TA = 25°C and VDD1 = VDD2 = 5 V. Minimum and maximum specifications apply over the entire

recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching

specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.

Table 1. Switching Specifications

Parameter Symbol

A Grade

B Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

MCLK, MO, SO

SPI Clock Rate SPIMCLK 1 17 MHz

Data Rate Fast (MO, SO) DRFAS T 2 34 Mbps Within PWD limit

Propagation Delay tPHL, tPLH 25 12 14 ns 50% input to 50% output

Pulse Width PW 100 12.5 ns Within PWD limit

Pulse Width Distortion PWD 3 2 ns |tPLH − tPHL|

Codirectional Channel Matching1 tPSKCD 3 2 ns

Jitter, High Speed JHS 1 1 ns

MSS

Data Rate Fast DRFAS T 2 34 Mbps Within PWD limit

Propagation Delay tPHL, tPLH 21 25 21 25 ns 50% input to 50% output

Pulse Width PW 100 12.5 ns Within PWD limit

Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|

Setup Time2 MSSSETUP 1.5 10 ns

Jitter, High Speed JHS 1 1 ns

, V

Data Rate Slow

SLOW

250

kbps

Within PWD limit

Propagation Delay tPHL, tPLH 0.1 2.6 0.1 2.6 µs 50% input to 50% output

Pulse Width PW 4 4 µs Within PWD limit

Jitter, Low Speed JLS 2.5 2.5 µs

VIx3 Minimum Input Skew4 tVIx SKEW3 10 10 ns

1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output

ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.

3 VIx = VIA, VIB, or VIC.

4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the

leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.

Table 2. Supply Current

Device Number Symbol

1 MHz, A Grade 17 MHz, B Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

ADuM3151 IDD1 4.0 8.5 14.0 22 mA CL = 0 pF, low speed channels

IDD2 6.0 10.5 13.5 23 mA CL = 0 pF, low speed channels

ADuM3152

DD1

4.8

14.0

21.5

= 0 pF, low speed channels

IDD2 6.5 10.5 14.0 22.5 mA CL = 0 pF, low speed channels

ADuM3153 IDD1 4.0 6.5 14.0 21.5 mA CL = 0 pF, low speed channels

IDD2 6.0 12 13.3 21 mA CL = 0 pF, low speed channels

ADuM3151/ADuM3152/ADuM3153 Data Sheet

Rev. B | Page 4 of 22

Table 3. For All Models1, 2, 3

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

MCLK, MSS, MO, SO, VIA, VIB, VIC

Logic High Input Threshold VIH 0.7 × VDDx V

Logic Low Input Threshold VIL 0.3 × VDDx V

Input Hysteresis VIHYST 500 mV

Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VINPUT ≤ VDDx

SCLK, SSS, MI, SI, VOA, VOB, VOC

Logic High Output Voltages VOH VDDx − 0.1 5.0 V IOUTPUT = −20 µA, VINPUT = VIH

DDx

− 0.4

4.8

OUTPUT

= −4 mA, V

INPUT

= V

Logic Low Output Voltages

0.0

0.1

OUTPUT

= 20 µA, V

INPUT

= V

0.2 0.4 V IOUTPUT = 4 mA, VINPUT = VIL

VDD1, VDD2 Undervoltage Lockout UVLO 2.6 V

Supply Current for High Speed Channel

Dynamic Input Supply Current IDDI(D) 0.080 mA/Mbps

Dynamic Output Supply Current IDDO(D) 0.046 mA/Mbps

Supply Current for All Low Speed Channels

Quiescent Side 1 Current IDD1(Q) 4.3 mA

Quiescent Side 2 Current IDD2(Q) 6.1 mA

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%

Common-Mode Transient Immunity4 |CM| 25 35 kV/µs VINPUT = VDDx, VCM = 1000 V,

transient magnitude = 800 V

1 VDDx = VDD1 or VDD2.

2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, VIB, or VIC pins.

3 IOUTPUT is the output current of any of the SCLK, SSS, MI, SI, VOA, VOB, or VOC pins.

4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges.

Data Sheet ADuM3151/ADuM3152/ADuM3153

Rev. B | Page 5 of 22

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3 . 3 V. Minimum and maximum specifications apply over the entire

recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching

specifications are tested with CL =15 pF and CMOS signal levels, unless otherwise noted.

Table 4. Switching Specifications

Parameter Symbol

A Grade B Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

MCLK, MO, SO

SPI Clock Rate SPIMCLK 1 12.5 MHz

Data Rate Fast (MO, SO) DRFAS T 2 34 Mbps Within PWD limit

Propagation Delay tPHL, tPLH 30 20 ns 50% input to 50% output

Pulse Width PW 100 12.5 ns Within PWD limit

Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|

Codirectional Channel Matching1 tPSKCD 4 2 ns

Jitter, High Speed

MSS

Data Rate Fast DRFAS T 2 34 Mbps Within PWD limit

Propagation Delay tPHL, tPLH 30 30 ns 50% input to 50% output

Pulse Width PW 100 12.5 ns Within PWD limit

Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|

Setup Time2 MSSSETUP 1.5 10 ns

Jitter, Low Speed JLS 2.5 2.5 ns

VIA, VIB, VIC

Data Rate Slow DRSLOW 250 250 kbps Within PWD limit

Propagation Delay tPHL, tPLH 0.1 2.6 0.1 2.6 µs 50% input to 50% output

Pulse Width PW 4 4 µs Within PWD limit

Jitter, Low Speed JLS 2.5 2.5 µs |tPLH − tPHL|

VIx3 Minimum Input Skew4 tVIx SKEW3 10 10 ns

1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output

ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.

3 VIx = VIA, VIB, or VIC.

4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the

leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.

Table 5. Supply Current

Device Number Symbol

1 MHz, A Grade/B Grade 17 MHz, B Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

ADuM3151 IDD1 2.8 6.5 10.5 18 mA CL = 0 pF, low speed channels

IDD2 4.6 8 9.0 17 mA CL = 0 pF, low speed channels

ADuM3152 IDD1 3.4 6 11.7 18 mA CL = 0 pF, low speed channels

IDD2 5.0 8 10.0 16 mA CL = 0 pF, low speed channels

ADuM3153 IDD1 2.8 5.5 11.7 18 mA CL = 0 pF, low speed channels

IDD2 3.5 9 10.0 15 mA CL = 0 pF, low speed channels

ADuM3151/ADuM3152/ADuM3153 Data Sheet

Rev. B | Page 6 of 22

Table 6. For All Models1, 2, 3

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

MCLK, MSS, MO, SO, VIA, VIB, VIC

Logic High Input Threshold VIH 0.7 × VDDx V

Logic Low Input Threshold VIL 0.3 × VDDx V

Input Hysteresis VIHYST 500 mV

Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VINPUT ≤ VDDx

SCLK, SSS, MI, SI, VOA, VOB, VOC

Logic High Output Voltages VOH VDDx − 0.1 3.3 V IOUTPUT = −20 µA, VINPUT = VIH

DDx

− 0.4

3.1

OUTPUT

= −4 mA, V

INPUT

= V

Logic Low Output Voltages

0.0

0.1

OUTPUT

= 20 µA, V

INPUT

= V

0.2 0.4 V IOUTPUT = 4 mA, VINPUT = VIL

VDD1, VDD2 Undervoltage Lockout UVLO 2.6 V

Supply Current for High Speed Channel

Dynamic Input Supply Current IDDI(D) 0.086 mA/Mbps

Dynamic Output Supply Current IDDO(D) 0.019 mA/Mbps

Supply Current for All Low Speed Channels

Quiescent Side 1 Current IDD1(Q) 2.9 mA

Quiescent Side 2 Current IDD2(Q) 4.7 mA

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%

Common-Mode Transient Immunity4 |CM| 25 35 kV/µs VINPUT = VDDx, VCM = 1000 V,

transient magnitude = 800 V

1 VDDx = VDD1 or VDD2.

2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, VIB, or VIC pins.

3 IOUTPUT is the output current of any of the SCLK, SSS, MI, SI, VOA, VOB, or VOC pins.

4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges.

Data Sheet ADuM3151/ADuM3152/ADuM3153

Rev. B | Page 7 of 22

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION

All typical specifications are at TA = 25°C, VDD1 = 5 V, a n d V DD2 = 3.3 V. Minimum and maximum specifications apply over the entire

recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching

specifications are tested with CL =15 pF and CMOS signal levels, unless otherwise noted.

Table 7. Switching Specifications

Parameter Symbol

A Grade B Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

MCLK, MO, SO

SPI Clock Rate SPIMCLK 1 15.6 MHz 1/(4 × tPHL)

Data Rate Fast (MO, SO) DRFAS T 2 34 Mbps Within PWD limit

Propagation Delay tPHL, tPLH 27 16 ns 50% input to 50% output

Pulse Width PW 100 12.5 ns Within PWD limit

Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|

Codirectional Channel Matching1 tPSKCD 3 2 ns

Jitter, High Speed

MSS

Data Rate Fast DRFAS T 2 34 Mbps Within PWD limit

Propagation Delay tPHL, tPLH 27 26 ns 50% input to 50% output

Pulse Width PW 100 12.5 ns Within PWD limit

Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|

Setup Time2 MSSSETUP 1.5 10 ns

Jitter, High Speed JHS 1 1 ns

VIA, VIB, VIC

Data Rate Slow DRSLOW 250 250 kbps Within PWD limit

Propagation Delay tPHL, tPLH 0.1 2.6 0.1 2.6 µs 50% input to 50% output

Pulse Width PW 4 4 µs Within PWD limit

Jitter, Low Speed JLS 2.5 2.5 µs

VIx3 Minimum Input Skew4 tVIx SKEW3 10 10 ns

1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output

ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.

3 VIx = VIA, VIB, or VIC.

4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the

leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.

Table 8. Supply Current

Device Number Symbol

1 MHz, A Grade/B Grade 17 MHz, B Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

ADuM3151 IDD1 4.0 8.5 13.9 22 mA CL = 0 pF, low speed channels

IDD2 4.6 8 9.0 17 mA CL = 0 pF, low speed channels

ADuM3152 IDD1 4.8 8 14.0 21.5 mA CL = 0 pF, low speed channels

IDD2 5.0 8 10.0 16 mA CL = 0 pF, low speed channels

ADuM3153 IDD1 4.0 6.5 14.0 21.5 mA CL = 0 pF, low speed channels

IDD2 4.7 9 10.0 15 mA CL = 0 pF, low speed channels

ADuM3151/ADuM3152/ADuM3153 Data Sheet

Rev. B | Page 8 of 22

Table 9. For All Models1, 2, 3

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

MCLK, MSS, MO, SO, VIA, VIB, VIC

Logic High Input Threshold VIH 0.7 × VDDx V

Logic Low Input Threshold VIL 0.3 × VDDx V

Input Hysteresis VIHYST 500 mV

Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VINPUT ≤ VDDx

SCLK, SSS, MI, SI, VOA, VOB, VOC

Logic High Output Voltages VOH VDDX − 0.1 VDDX V IOUTPUT = −20 µA, VINPUT = VIH

DDX

− 0.4

DDX

− 0.2

OUTPUT

= −4 mA, V

INPUT

= V

Logic Low Output Voltages

0.0

0.1

OUTPUT

= 20 µA, V

INPUT

= V

0.2 0.4 V IOUTPUT = 4 mA, VINPUT = VIL

VDD1, VDD2 Undervoltage Lockout UVLO 2.6 V

Supply Current for All Low Speed Channels

Quiescent Side 1 Current IDD1(Q) 4.3 mA

Quiescent Side 2 Current IDD2(Q) 4.7 mA

AC SPECIFICATIONS

Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%

Common-Mode Transient Immunity4 |CM| 25 35 kV/µs VINPUT = VDDX, VCM = 1000 V,

transient magnitude = 800 V

1 VDDx = VDD1 or VDD2.

2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, VIB, or VIC pins.

3 IOUTPUT is the output current of any of the SCLK, SSS, MI, SI, VOA, VOB, VOC pins.

4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges.

Data Sheet ADuM3151/ADuM3152/ADuM3153

Rev. B | Page 9 of 22

ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION

All typical specifications are at TA = 25°C, VDD1 = 3.3 V, and VDD2 = 5 V. Minimum and maximum specifications apply over the entire

recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching

specifications are tested with CL =15 pF and CMOS signal levels, unless otherwise noted.

Table 10. Switching Specifications

Parameter Symbol

A Grade B Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

MCLK, MO, SO

SPI Clock Rate SPIMCLK 1 15.6 MHz

Data Rate Fast (MO, SO) DRFAS T 2 34 Mbps Within PWD limit

Propagation Delay tPHL, tPLH 27 16 ns 50% input to 50% output

Pulse Width PW 100 12.5 ns Within PWD limit

Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|

Codirectional Channel Matching1 tPSKCD 5 2 ns

Jitter, High Speed

MSS

Data Rate Fast DRFAS T 2 34 Mbps Within PWD limit

Propagation Delay tPHL, tPLH 27 27 ns 50% input to 50% output

Pulse Width PW 100 12.5 ns Within PWD limit

Pulse Width Distortion PWD 2 3 ns |tPLH − tPHL|

Setup Time2 MSSSETUP 1.5 10 ns

Jitter, High Speed JHS 1 1 ns

VIA, VIB, VIC

Data Rate DRSLOW 250 250 kbps Within PWD limit

Propagation Delay tPHL, tPLH 0.1 2.6 0.1 2.6 µs 50% input to 50% output

Pulse Width PW 4 4 µs Within PWD limit

Jitter, Low Speed JLS 2.5 2.5 µs |tPLH − tPHL|

VIx3 Minimum Input Skew4 tVIx SKEW3 10 10 ns

1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output

ahead of another fast signal, it must be set up prior to the competing signal by different times depending on speed grade.

3 VIx = VIA, VIB, or VIC.

4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the

leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.

Table 11. Supply Current

Device Number Symbol

1 MHz, A Grade/B Grade 17 MHz, B Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

ADuM3151 IDD1 2.8 6.5 10.5 18 mA CL = 0 pF, low speed channels

IDD2 6.0 10.5 13.0 23 mA CL = 0 pF, low speed channels

ADuM3152 IDD1 3.5 6 11.7 18 mA CL = 0 pF, low speed channels

IDD2 6.5 10.5 13.4 22.5 mA CL = 0 pF, low speed channels

ADuM3153 IDD1 2.8 5.5 11.7 18 mA CL = 0 pF, low speed channels

IDD2 6.0 12 13.4 21 mA CL = 0 pF, low speed channels

ADuM3151/ADuM3152/ADuM3153 Data Sheet

Rev. B | Page 10 of 22

Table 12. For All Models1, 2, 3

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DC SPECIFICATIONS

MCLK, MSS, MO, SO, VIA, VIB, VIC

Logic High Input Threshold VIH 0.7 × VDDx V

Logic Low Input Threshold VIL 0.3 ×

VDDx

Input Hysteresis VIHYST 500 mV

Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VINPUT ≤ VDDx

SCLK, SSS, MI, SI, VOA, VOB, VOC

Logic High Output Voltages VOH VDDx − 0.1 VDDX V IOUTPUT = −20 µA, VINPUT = VIH

VDDx − 0.4 VDDX − 0.2 V IOUTPUT = −4 mA, VINPUT = VIH

Logic Low Output Voltages VOL 0.0 0.1 V IOUTPUT = 20 µA, VINPUT = VIL

0.2 0.4 V IOUTPUT = 4 mA, VINPUT = VIL

VDD1, VDD2 Undervoltage Lockout UVLO 2.6 V

Supply Current for All Low Speed Channels

Quiescent Side 1 Current IDD1(Q) 2.9 mA

Quiescent Side 2 Current

DD2(Q)

6.1

AC SPECIFICATIONS

Output Rise/Fall Time

2.5

10% to 90%

Common-Mode Transient Immunity4 |CM| 25 35 kV/µs VINPUT = VDDX, VCM = 1000 V,

transient magnitude = 800 V

1 VDDx = VDD1 or VDD2.

2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, VIB, VIC pins.

3 IOUTPUT is the output current of any of the SCLK, SSS, MI, SI, VOA, VOB, VOC pins.

4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges.

PACKAGE CHARACTERISTICS

Table 13.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

Resistance (Input to Output)1 RI-O 1012 Ω

Capacitance (Input to Output)1 CI-O 1.0 pF f = 1 MHz

Input Capacitance2 CI 4.0 pF

IC Junction to Case Thermal Resistance θJC 75 °C/W Thermocouple located at center of package underside

1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

2 Input capacitance is from any input data pin to ground.

Data Sheet ADuM3151/ADuM3152/ADuM3153

Rev. B | Page 11 of 22

REGULATORY INFORMATION

The ADuM3151/ADuM3152/ADuM3153 are approved by the organizations listed in Table 14. See Table 19 and the Insulation Lifetime

section for the recommended maximum working voltages for specific cross isolation waveforms and insulation levels.

Table 14.

UL CSA VDE

Recognized under 1577 Component

Recognition Program1

Approved under CSA Component Acceptance

Notice #5A

Certified according to DIN V VDE V 0884-10

(VDE V 0884-10):2006-122

3750 V rms Single Protection Basic insulation per CSA 60950-1-07+A1+A2

and IEC 60950-1 2nd Ed.+A1+A2, 510 V rms

(721 V peak) maximum working voltage3

Reinforced insulation, 565 V peak

File E214100 File 205078 File 2471900-4880-0001

1 In accordance with UL 1577, each model is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (current leakage detection limit = 10 µA).

2 In accordance with DIN V VDE V 0884-10, each model is proof tested by applying an insulation test voltage ≥ 525 V peak for 1 second (partial discharge detection limit = 5 pC).

The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.

3 See Table 19 for recommended maximum working voltages under various operating conditions.

INSULATION AND SAFETY RELATED SPECIFICATIONS

Table 15.

Parameter Symbol Value Unit Test Conditions/Comments

Rated Dielectric Insulation Voltage 3750 V rms 1-minute duration

Minimum External Air Gap (Clearance) L(I01) 5.1 mm min Measured from input terminals to output terminals,

shortest distance through air

Minimum External Tracking (Creepage) L(I02) 5.1 mm min Measured from input terminals to output terminals,

shortest distance path along body

Minimum Internal Gap (Internal Clearance) 0.017 mm min Insulation distance through insulation

Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303, Part 1

Material Group II Material group (DIN VDE 0110, 1/89, Table 1)

ADuM3151/ADuM3152/ADuM3153 Data Sheet

Rev. B | Page 12 of 22

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by

protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.

Table 16.

Description Test Conditions/Comments Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV

For Rated Mains Voltage ≤ 300 V rms I to III

For Rated Mains Voltage ≤ 400 V rms I to II

Climatic Classification 40/105/21

Pollution Degree per DIN VDE 0110, Table 1 2

Maximum Working Insulation Voltage VIORM 565 V peak

Input-to-Output Test Voltage, Method b1 VIORM × 1.875 = Vpd(m), 100% production test,

tini = tm = 1 sec, partial discharge < 5 pC

Vpd(m) 1059 V peak

Input-to-Output Test Voltage, Method a

After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,

partial discharge < 5 pC

Vpd(m) 848 V peak

After Input and/or Safety Test Subgroup 2

and Subgroup 3

VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,

partial discharge < 5 pC

Vpd(m) 678 V peak

Highest Allowable Overvoltage VIOTM 5000 V peak

Surge Isolation Voltage VIOSM(TEST) = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 6250 V peak

Safety Limiting Values Maximum value allowed in the event of a

failure (see Figure 4)

Case Temperature TS 150 °C

Safety Total Dissipated Power IS1 1.4 W

Insulation Resistance at TS VIO = 500 V RS >109 Ω

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0020015010050

12368-004

SAFE LIMITING POWER (W)

AMBI E NT T EMPERATURE ( °C)

Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values

with Case Temperature per DIN V VDE V 0884-10

RECOMMENDED OPERATING CONDITIONS

Table 17.

Parameter Symbol Min Max Unit

Operating Temperature Range TA −40°C +125 °C

Supply Voltage Range1 VDD1,

VDD2

3.0 5.5 V

Input Signal Rise and Fall Times 1.0 ms

1 See the DC Correctness and Magnetic Field Immunity section for information

on the immunity to the external magnetic fields.

Data Sheet ADuM3151/ADuM3152/ADuM3153

Rev. B | Page 13 of 22

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 18.

Parameter Rating

Storage Temperature (TST) Range −65°C to +150°C

Ambient Operating Temperature (TA)

Range

−40°C to +125°C

Supply Voltages (VDD1, VDD2) −0.5 V to +7.0 V

Input Voltages (VIA, VIB, VIC, MCLK,

MO, MSS)

−0.5 V to VDDx + 0.5 V

Output Voltages (SCLK,

SSS

, MI, SI,

VOA, VOB, VOC)

−0.5 V to V

DDx

+ 0.5 V

Average Current per Output Pin1 −10 mA to +10 mA

Common-Mode Transients2 −100 kV/µs to +100 kV/µs

1 See Figure 4 for maximum safety rated current values across temperature.

2 Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause latch-up

or permanent damage.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 19. Maximum Continuous Working Voltage1

Parameter Max Unit Constraint

AC 60 Hz RMS

Voltage

400 V rms 20-year lifetime at 0.1%

failure rate, zero average

voltage

DC Voltage 722 V peak Limited by the creepage of

the package,

Pollution Degree 2,

Material Group II2, 3

1 See the Insulation Lifetime section for more details.

2 Other pollution degree and material group requirements yield a different limit.

3 Some system level standards allow components to use the printed wiring

board (PWB) creepage values. The supported dc voltage may be higher for

those standards.

ESD CAUTION

ADuM3151/ADuM3152/ADuM3153 Data Sheet

Rev. B | Page 14 of 22

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DD1 1

GND

MCLK

MSS

IA7

IB 813

OC 912

GND

DD2

GND

SCLK

SSS

GND

10 11

12368-005

ADuM3151

(No t t o Scale)

TOP VIEW

Figure 5. ADuM3151 Pin Configuration

Table 20. ADuM3151 Pin Function Descriptions

Pin No. Mnemonic Direction Description

1 VDD1 Power Input Power Supply for Side 1. A bypass capacitor from VDD1 to GND1 to local ground is required.

2, 10

GND

Return

Ground 1. Ground reference for Isolator Side 1.

3 MCLK Input SPI Clock from the Master Controller.

4 MO Input SPI Data from the Master MO/SI Line.

5 MI Output SPI Data from the Slave to the Master MI/SO Line.

6 MSS Input Slave Select from the Master. This signal uses an active low logic. The slave select pin requires a 10 ns

setup time from the next clock or data edge.

7 VIA Input Low Speed Data Input A.

8 VIB Input Low Speed Data Input B.

9 VOC Output Low Speed Data Output C.

11, 19 GND2 Return Ground 2. Ground reference for Isolator Side 2.

12 VIC Input Low Speed Data Input C.

Output

Low Speed Data Output B.

14 VOA Output Low Speed Data Output A.

15 SSS Output Slave Select to the Slave. This signal uses an active low logic.

16 SO Input SPI Data from the Slave to the Master MI/SO Line.

17 SI Output SPI Data from the Master to the Slave MO/SI Line.

18 SCLK Output SPI Clock from the Master Controller.

20 VDD2 Power Input Power Supply for Side 2. A bypass capacitor from VDD2 to GND2 to local ground is required.

Data Sheet ADuM3151/ADuM3152/ADuM3153

Rev. B | Page 15 of 22

DD1 1

GND

MCLK

MSS

IA 7

OB 813

OC 912

GND

DD2

GND

SCLK

SSS

GND

10 11

12368-006

ADuM3152

(No t t o Scale)

TOP VIEW

Figure 6. ADuM3152 Pin Configuration

Table 21. ADuM3152 Pin Function Descriptions

Pin No. Mnemonic

Direction Description

1 VDD1 Power Input Power Supply for Side 1. A bypass capacitor from VDD1 to GND1 to local ground is required.

2, 10 GND1 Return Ground 1. Ground reference for Isolator Side 1.

3 MCLK Input SPI Clock from the Master Controller.

4 MO Input SPI Data from the Master MO/SI Line.

Output

SPI Data from the Slave to the Master MI/SO Line.

6 MSS Input Slave Select from the Master. This signal uses an active low logic. The slave select pin requires a 10 ns

setup time from the next clock or data edge.

7 VIA Input Low Speed Data Input A.

8 VOB Output Low Speed Data Output B.

9 VOC Output Low Speed Data Output C.

11, 19 GND2 Return Ground 2. Ground reference for Isolator Side 2.

12 VIC Input Low Speed Data Input C.

13 VIB Input Low Speed Data Input B.

14 VOA Output Low Speed Data Output A.

15 SSS Output Slave Select to the Slave. This signal uses an active low logic.

16 SO Input SPI Data from the Slave to the Master MI/SO Line.

17 SI Output SPI Data from the Master to the Slave MO/SI Line.

18 SCLK Output SPI Clock from the Master Controller.

20 VDD2 Power Input Power Supply for Side 2. A bypass capacitor from VDD2 to GND2 to local ground is required.

ADuM3151/ADuM3152/ADuM3153 Data Sheet

Rev. B | Page 16 of 22

DD1 1

GND

MCLK

MSS

OA7

OB 813

OC 912

GND

DD2

GND

SCLK

SSS

GND

10 11

12368-007

ADuM3153

(No t t o Scale)

TOP VIEW

Figure 7. ADuM3153 Pin Configuration

Table 22. ADuM3153 Pin Function Descriptions

Pin No. Mnemonic

Direction Description

1 VDD1 Power Input Power Supply for Side 1. A bypass capacitor from VDD1 to GND1 to local ground is required.

2, 10 GND1 Return Ground 1. Ground reference for Isolator Side 1.

3 MCLK Input SPI Clock from the Master Controller.

4 MO Input SPI Data from the Master MOSI Line

Output

SPI Data from the Slave to the Master MI/SO Line.

6 MSS Input Slave Select from the Master. This signal uses an active low logic. The slave select pin requires a 10 ns

setup time from the next clock or data edge.

7 VOA Output Low Speed Data Output A.

8 VOB Output Low Speed Data Output B.

9 VOC Output Low Speed Data Output C.

11, 19 GND2 Return Ground 1. Ground reference for Isolator Side 2.

12 VIC Input Low Speed Data Input C.

13 VIB Input Low Speed Data Input B.

14 VIA Input Low Speed Data Input A.

15 SSS Output Slave Select to the Slave. This signal uses an active low logic.

16 SO Input SPI Data from the Slave to the Master MI/SO Line.

17 SI Output SPI Data from the Master to the Slave MO/SI Line.

18 SCLK Output SPI Clock from the Master Controller.

20 VDD2 Power Input Power Supply for Side 2. A bypass capacitor from VDD2 to GND2 to local ground is required.

Table 23. ADuM3151/ADuM3152/ADuM3153 Power-Off Default State Truth Table (Positive Logic)1

DD1

State

DD2

State

Side 1 Outputs

Side 2 Outputs

SSS

Comments

Unpowered Powered Z Z Z Outputs on an unpowered side are high impedance within

one diode drop of ground

Powered Unpowered Z Z Z Outputs on an unpowered side are high impedance within one

diode drop of ground

1 Z is high impedance.

Data Sheet ADuM3151/ADuM3152/ADuM3153

Rev. B | Page 17 of 22

TYPICAL PERFORMANCE CHARACTERISTICS

020 40 60 80

DATA RAT E (Mb p s)

3.3V

5.0V

12368-100

DYNAMIC SUPPLY CURRENT

PER I NP UT CHANNEL (mA)

Figure 8. Typical Dynamic Supply Current per Input Channel vs. Data Rate

for 5.0 V and 3.3 V Operation

020 40 60 80

DD1

SUPPLY CURRENT ( mA)

DATA RAT E (Mb p s)

3.3V

5.0V

12368-102

Figure 9. Typical IDD1 Supply Current vs. Data Rate for

5.0 V and 3.3 V Operation

–40 10 60 110

PROPAGATION DELAY (ns)

AMBIENT TEMPERATURE ( °C)

3.3V

5.0V

12368-012

Figure 10. Typical Propagation Delay vs. Ambient Temperature for High

Speed Channels Without Glitch Filter (See the High Speed Channels Section)

12368-101

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

020 40 60 80

DATA RAT E (Mb p s)

3.3V

5.0V

DYNAMIC SUPPLY CURRENT

PER O UTPUT CHANNEL (mA)

Figure 11. Typical Dynamic Supply Current per Output Channel vs. Data Rate

for 5.0 V and 3.3 V Operation

020 40 60 80

IDD2 SUPPLY CURRENT ( mA)

DATA RAT E (Mb p s)

3.3V

5.0V

12368-103

Figure 12. Typical IDD2 Supply Current vs. Data Rate for

5.0 V and 3.3 V Operation

–40 10 60 110

AMBIENT TEMPERATURE ( °C)

3.3V

5.0V

PROPAGATION DELAY (ns)

12368-013

Figure 13. Typical Propagation Delay vs. Ambient Temperature for High

Speed Channels with Glitch Filter (See the High Speed Channels Section)

ADuM3151/ADuM3152/ADuM3153 Data Sheet

Rev. B | Page 18 of 22

APPLICATIONS INFORMATION

INTRODUCTION

The ADuM3151/ADuM3152/ADuM3153 are a family of devices

created to optimize isolation of SPI for speed and provide

additional low speed channels for control and status monitoring

functions. The isolators are based on differential signaling

iCoupler technology for enhanced speed and noise immunity.

High Speed Channels

The ADuM3151/ADuM3152/ADuM3153 have four high speed

channels. The first three channels, CLK, MI/SO, and MO/SI

(the slash indicates the connection of the particular input and

output channel across the isolator), are optimized for either low

propagation delay in the B grade or high noise immunity in the

A grade. The difference between the grades is the addition of a

glitch filter to these three channels in the A grade version,

which increases the propagation delay. The B grade version,

with a maximum propagation delay of 14 ns, supports a

maximum clock rate of 17 MHz in the standard 4-wire SPI.

However, because the glitch filter is not present in the B grade

version, ensure that spurious glitches of less than 10 ns are not

present.

Glitches of less than 10 ns in the B grade devices can cause the

missing of the second edge of the glitch. This pulse condition is

then seen as a spurious data transition on the output that is

corrected by a refresh or the next valid data edge. It is recommended

to use the A grade devices in noisy environments.

The relationship between the SPI signal paths and the pin

mnemonics of the ADuM3151/ADuM3152/ADuM3153 and

the data directions is detailed in Table 24.

Table 24. Pin Mnemonics Correspondence to the SPI Signal

Path Names

SPI Signal Path Master Side 1 Data Direction Slave Side 2

CLK MCLK

→

SCLK

MO/SI MO

→

MI/SO MI

←

SS MSS

→

SSS

The datapaths are SPI mode agnostic. The CLK and MOSI, SPI

data paths are optimized for propagation delay and channel to

channel matching. The MISO SPI datapath is optimized for

propagation delay. The devices do not synchronize to the clock

channels so there are no constraints on the clock polarity or the

timing with respect to the data lines. To allow compatibility

with nonstandard SPI interfaces, the MI pin is always active,

and does not tristate when the slave select is not asserted. This

precludes tying several MI lines together without adding a

tristate buffer or multiplexor.

The SS (slave select bar) is typically an active low signal. It can

have many different functions in SPI and SPI-like busses. Many

of these functions are edge triggered, so the SS path contains a

glitch filter in both the A grade and the B grade.

The glitch filter prevents short pulses from propagating to the

output or causing other errors in operation. The MSS signal

requires a 10 ns setup time in the B grade devices prior to the

first active clock edge to allow the added propagation time of

the glitch filter.

Low Speed Data Channels

The low speed data channels are provided as economical

isolated datapaths where timing is not critical. The dc value of

all high and low speed inputs on a given side of the devices are

sampled simultaneously, packetized and shifted across an

isolation coil. The high speed channels are compared for dc

accuracy, and the low speed data is transferred to the appropriate

low speed outputs. The process is then reversed by reading the

inputs on the opposite side of the devices, packetizing them and

sending them back for similar processing. The dc correctness data

for the high speed channels is handled internally, and the low

speed data is clocked to the outputs simultaneously.

A free running internal clock regulates this bidirectional data

shuttling. Because data is sampled at discrete times based on

this clock, the propagation delay for a low speed channel is

between 0.1 µs and 2.6 µs, depending on where the input data

edge changes with respect to the internal sample clock.

Figure 14 illustrates the behavior of the low speed channels and

the relationship between the codirectional channels.

• Point A: When data is sampled between the input edges of

two low speed data inputs, a very narrow gap between

edges is increased to the width of the output clock.

• Point B: Data edges that occur on codirectional channels

between samples are sampled and simultaneously sent to

the outputs, which synchronizes the data edges between

the two channels at the outputs.

• Point C: Data pulses that are less than the minimum low

speed pulse width may not be transmitted because they

may not be sampled.

INPUT A

OUTPUT A

SAMPLE CLOCK

OUTPUT CLOCK

INPUT B

OUTPUT B

12368-014

Figure 14. Slow Channel Timing

Data Sheet ADuM3151/ADuM3152/ADuM3153

Rev. B | Page 19 of 22

A low speed data system that is carefully designed so that

staggered data transitions at the inputs become either

synchronized or pushed apart when they are presented at the

output. Edge order is always preserved for as long as the edges

are separated by at least VIx SKEW. In other words, if one edge is

leading another at the input, the order of the edges is not

reversed by the isolator.

PRINTED CIRCUIT BOARD (PCB) LAYOUT

The ADuM3151/ADuM3152/ADuM3153 digital isolators

require no external interface circuitry for the logic interfaces.

Power supply bypassing is strongly recommended at both input

and output supply pins: VDD1 and VDD2 (see Figure 15). The

capacitor value must be between 0.01 µF and 0.1 µF. The total

lead length between both ends of the capacitor and the input

power supply pin must not exceed 20 mm.

BYPASS < 2mm

12368-015

DD1

GND

MCLK

MSS

DD2

GND

SCLK

SSS

GND

ADuM3151/

ADuM3152/

ADuM3153

Figure 15. Recommended PCB Layout

In applications involving high common-mode transients, it is

important to minimize board coupling across the isolation

barrier. Furthermore, design the board layout so that any

coupling that does occur affects all pins equally on a given

component side. Failure to ensure this can cause voltage

differentials between pins exceeding the absolute maximum

ratings of the device, thereby leading to latch-up or permanent

damage.

PROPAGATION DELAY RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes

a logic signal to propagate through a component. The input to

output propagation delay time for a high to low transition may

differ from the propagation delay time of a low to high

transition.

INPUT

OUTPUT

PLH

PHL

50%

12368-016

Figure 16. Propagation Delay Parameters

Pulse width distortion is the maximum difference between

these two propagation delay values and an indication of how

accurately the timing of the input signal is preserved.

Channel to channel matching refers to the maximum amount

the propagation delay differs between channels within a single

ADuM3151/ADuM3152/ADuM3153 component.

DC CORRECTNESS AND MAGNETIC FIELD

IMMUNITY

Positive and negative logic transitions at the isolator input cause

narrow (~1 ns) pulses to be sent via the transformer to the decoder.

The decoder is bistable and is, therefore, either set or reset by

the pulses indicating input logic transitions. In the absence of

logic transitions at the input for more than ~1.2 µs, a periodic

set of refresh pulses indicative of the correct input state are sent

via the low speed channel to ensure dc correctness at the output.

If the low speed decoder receives no pulses for more than about

5 µs, the input side is assumed to be unpowered or nonfunctional,

in which case, the isolator output is forced to a high-Z state by

the watchdog timer circuit.

The limitation on the magnetic field immunity of the device is

set by the condition in which induced voltage in the transformer

receiving coil is sufficiently large to either falsely set or reset the

decoder. The following analysis defines such conditions. The

ADuM3151/ADuM3152/ADuM3153 were examined in a 3 V

operating condition because it represents the most susceptible

mode of operation for this product.

The pulses at the transformer output have an amplitude greater

than 1.5 V. The decoder has a sensing threshold of about 1.0 V;

thereby, establishing a 0.5 V margin in which induced voltages

can be tolerated. The voltage induced across the receiving coil is

given by

V = (−dβ/dt)∑πrn2; n = 1, 2, …, N

where:

β is the magnetic flux density.

rn is the radius of the nth turn in the receiving coil.

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM3151/

ADuM3152/ADuM3153 and an imposed requirement that the

induced voltage be, at most, 50% of the 0.5 V margin at the

decoder, a maximum allowable magnetic field is calculated as

shown in Figure 17.

MAGNE TI C FI E LD F RE QUENCY ( Hz )

MAXIMUM ALLOWABLE MAGNETIC FLUX

DENSI TY ( kgau ss)

0.001

100

100M

0.1

0.01

10k 100k 1M 10M

12368-017

Figure 17. Maximum Allowable External Magnetic Flux Density

ADuM3151/ADuM3152/ADuM3153 Data Sheet

Rev. B | Page 20 of 22

For example, at a magnetic field frequency of 1 MHz, the

maximum allowable magnetic field of 0.5 kgauss, induces a

voltage of 0.25 V at the receiving coil. This is about 50% of the

sensing threshold and does not cause a faulty output transition.

If such an event occurs, with the worst-case polarity, during a

transmitted pulse, it reduces the received pulse from >1.0 V to

0.75 V, which is still well above the 0.5 V sensing threshold of

the decoder.

The preceding magnetic flux density values correspond to

specific current magnitudes at given distances away from the

ADuM3151/ADuM3152/ADuM3153 transformers. Figure 18

expresses these allowable current magnitudes as a function of

frequency for selected distances. The ADuM3151/ADuM3152/

ADuM3153 are insensitive to external fields. Only extremely

large, high frequency currents, very close to the component are

a concern. For the 1 MHz example noted, a user would have to

place a 1.2 kA current 5mm away from the ADuM3151/

ADuM3152/ADuM3153 to affect component operation.

MAGNE TI C FI E LD F RE QUENCY ( Hz )

MAXI MUM AL LO WABL E CURRE NT (kA)

1000

100

0.1

0.011k 10k 100M

100k 1M 10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

12368-018

Figure 18. Maximum Allowable Current for Various Current to

ADuM3151/ADuM3152/ADuM3153 Spacings

At combinations of strong magnetic field and high frequency,

any loops formed by the PCB traces may induce sufficiently

large error voltages to trigger the thresholds of succeeding

circuitry. Take care to avoid PCB structures that form loops.

POWER CONSUMPTION

The supply current at a given channel of the ADuM3151/

ADuM3152/ADuM3153 isolators is a function of the supply

voltage, the data rate of the channel, and the output load of the

channel and whether it is a high or low speed channel.

The low speed channels draw a constant quiescent current

caused by the internal ping-pong datapath. The operating

frequency is low enough that the capacitive losses caused by

the recommended capacitive load are negligible compared to

the quiescent current. The explicit calculation for the data rate

is eliminated for simplicity, and the quiescent current for each

side of the isolator due to the low speed channels can be found

in Table 3, Table 6, Table 9, and Table 12 for the particular

operating voltages.

These quiescent currents add to the high speed current as is

shown in the following equations for the total current for each

side of the isolator. Dynamic currents are taken from Table 3

and Table 6 for the respective voltages.

For Side 1, the supply current is given by

IDD1 = IDDI(D) × (fMCLK + fMO + fMSS) +

fMI × (IDDO(D) + ((0.5 × 10−3) × CL(MI) × VDD1)) + IDD1(Q)

For Side 2, the supply current is given by

IDD2 = IDDI(D) × fSO +

fSCLK × (IDDO(D) + ((0.5 × 10−3) × CL(SCLK) × VDD2)) +

fSI × (IDDO(D) + ((0.5 × 10−3) × CL(SI) × VDD2)) +

fSSS × (IDDO(D) + ((0.5 × 10−3) × CL(SSS) × VDD2)) + IDD2(Q)

where:

IDDI(D), IDDO(D) are the input and output dynamic supply currents

per channel (mA/Mbps).

fx is the logic signal data rate for the specified channel (Mbps).

CL(x) is the load capacitance of the specified output (pF).

VDDx is the supply voltage of the side being evaluated (V).

IDD1(Q), IDD2(Q) are the specified Side 1 and Side 2 quiescent

supply currents (mA).

Figure 8 and Figure 11 show the supply current per channel as a

function of data rate for an input and unloaded output. Figure 9

and Figure 12 show the total IDD1 and IDD2 supply currents as a

function of data rate for the ADuM3151/ADuM3152/ADuM3153

channel configurations with all high speed channels running at

the same speed and the low speed channels at idle.

INSULATION LIFETIME

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period. The rate of

insulation degradation is dependent on the characteristics of the

voltage waveform applied across the insulation as well as the

materials and material interfaces.

There are two types of insulation degradation of primary interest:

breakdown along surfaces exposed to the air and insulation

wear out. Surface breakdown is the phenomenon of surface

tracking and the primary determinant of surface creepage

requirements in system level standards. Insulation wear out is

the phenomenon where charge injection or displacement

currents inside the insulation material cause long-term

insulation degradation.

Surface Tracking

Surface tracking is addressed in electrical safety standards by

setting a minimum surface creepage based on the working

voltage, the environmental conditions, and the properties of the

insulation material. Safety agencies perform characterization

testing on the surface insulation of components that allow the

components to be categorized into different material groups.

Lower material group ratings are more resistant to surface

tracking and, therefore, can provide adequate lifetime with

smaller creepage.

Data Sheet ADuM3151/ADuM3152/ADuM3153

Rev. B | Page 21 of 22

The minimum creepage for a given working voltage and

material group is in each system level standard and is based on

the total rms voltage across the isolation, pollution degree, and

material group. The material group and creepage for the

ADuM3151/ADuM3152/ADuM3153 isolators are detailed in

Table 15.

Insulation Wear Out

The lifetime of insulation due to wear out is determined by its

thickness, the material properties, and the voltage stress applied.

It is important to verify that the product lifetime is adequate at

the application working voltage. The working voltage supported

by an isolator for wear out may not be the same as the working

voltage supported for tracking. It is the working voltage

applicable to tracking that is specified in most standards.

Testing and modeling have shown that the primary driver of

long-term degradation is displacement current in the polyimide

insulation causing incremental damage. The stress on the

insulation can be broken down into broad categories, such as

dc stress, which causes very little wear out because there is no

displacement current, and an ac component time varying

voltage stress, which causes wear out.

The ratings in certification documents are usually based on

60 Hz sinusoidal stress because this reflects isolation from line

voltage. However, many practical applications have combinations

of 60 Hz ac and dc across the barrier, as shown in Equation 1.

Because only the ac portion of the stress causes wear out, the

equation can be rearranged to solve for the ac rms voltage, as

shown in Equation 2. For insulation wear out with the

polyimide materials used in this product, the ac rms voltage

determines the product lifetime.

DCRMSACRMS

VVV +=

(1)

DCRMSRMS

VVV −=

(2)

where:

VAC RMS is the time varying portion of the working voltage.

VDC is the dc offset of the working voltage.

VRMS is the total rms working voltage.

Calculation and Use of Parameters Example

The following is an example that frequently arises in power

conversion applications. Assume that the line voltage on one

side of the isolation is 240 V ac rms, and a 400 V dc bus voltage

is present on the other side of the isolation barrier. The isolator

material is polyimide.

To establish the critical voltages in determining the creepage

clearance and lifetime of a device, see Figure 19 and the

following equations.

ISOLATION VOLTAGE

TIME

AC RMS

RMS

12368-019

PEAK

Figure 19. Critical Voltage Example

The working voltage across the barrier from Equation 1 is

DCRMSACRMS

VVV +=

400240 +=

RMS

VRMS = 466 V

This is the working voltage used together with the material

group and pollution degree when looking up the creepage

required by a system standard.

To determine if the lifetime is adequate, obtain the time varying

portion of the working voltage. The ac rms voltage can be

obtained from Equation 2.

DCRMSRMSAC

VVV −=

400466 −=

RMSAC

VAC RMS = 240 V rms

In this case, the ac rms voltage is simply the line voltage of

240 V rms. This calculation is more relevant when the

waveform is not sinusoidal. The value is compared to the limits

for the working voltage listed in Table 19 for the expected

lifetime, under a 60 Hz sine wave, and it is well within the limit

for a 50-year service life.

Note that the dc working voltage limit in Table 19 is set by the

creepage of the package as specified in IEC 60664-1. This value

may differ for specific system level standards.

ADuM3151/ADuM3152/ADuM3153 Data Sheet

Rev. B | Page 22 of 22

OUTLINE DIMENSIONS

COM PLI ANT TO JEDE C S TANDARDS MO-150-AE

20 11

7.50

7.20

6.90

8.20

7.80

7.40

5.60

5.30

5.00

0.05 MI N

0.65 BSC

2.00 M A X

0.38

0.22

1.85

1.75

1.65

0.25

0.09

0.95

0.75

0.55

8°

4°

0°

COPLANARITY

0.10

PKG-004600

06-01-2006-A

TOP VIEW

SIDE VIEW END VIEW

PIN 1

INDICATOR

SEATING

PLANE

Figure 20. 20-Lead Shrink Small Outline Package [SSOP]

(RS-20)

Dimensions shown in millimeters

ORDERING GUIDE

Model1

No. of

Inputs,

VDD1 Side

No. of

Inputs,

VDD2 Side

Maximum

Data Rate

(MHz)

Maximum

Propagation

Delay, 5 V (ns)

Isolation

Rating

(V ac)

Temperature

Range

Package

Description

Package

Option

ADuM3151ARSZ 5 2 1 25 3750 −40°C to +125°C 20-Lead SSOP RS-20

ADuM3151ARSZ-RL7 5 2 1 25 3750 −40°C to +125°C

20-Lead SSOP,

7” Tape and Reel

RS-20

ADuM3151BRSZ 5 2 17 14 3750 −40°C to +125°C 20-Lead SSOP RS-20

ADuM3151BRSZ-RL7 5 2 17 14 3750 −40°C to +125°C

20-Lead SSOP,

7” Tape and Reel

RS-20

EVAL-ADuM3151Z Evaluation Board

ADuM3152ARSZ 4 3 1 25 3750 −40°C to +125°C 20-Lead SSOP RS-20

ADuM3152ARSZ-RL7 4 3 1 25 3750 −40°C to +125°C

20-Lead SSOP,

7” Tape and Reel

RS-20

ADuM3152BRSZ 4 3 17 14 3750 −40°C to +125°C 20-Lead SSOP RS-20

ADuM3152BRSZ-RL7 4 3 17 14 3750 −40°C to +125°C

20-Lead SSOP,

7” Tape and Reel

RS-20

ADuM3153ARSZ 3 4 1 25 3750 −40°C to +125°C 20-Lead SSOP RS-20

ADuM3153ARSZ-RL7 3 4 1 25 3750 −40°C to +125°C

20-Lead SSOP,

7” Tape and Reel

RS-20

ADuM3153BRSZ 3 4 17 14 3750 −40°C to +125°C 20-Lead SSOP RS-20

ADuM3153BRSZ-RL7 3 4 17 14 3750 −40°C to +125°C

20-Lead SSOP,

7” Tape and Reel

RS-20

1 Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D12368-0-6/17(B)