OKI Semiconductor FEDL9261A-01
Issue Date: Mar. 28, 2002
ML9261A
60-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver
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GENERAL DESCRIPTION
The ML9261A is a monolithic IC designed for directly driving the grid and anode of the vacuum fluorescent
display (VFD) tube. The device contains a 60-bit shift register, a 60-bit register circuit, and 60 VFD tube driving
circuits on a single chip.
Display data is serially stored in the shift register at the rising edge of a clock pulse.
Setting the CL pin low allows all the VFD tube driving circuits to be driven low, which makes it possible to set the
display blanking.
Also, setting both of the CL and CHG pins high allows all the VFD tube driving circuits to be driven high, which
provides the easy testing of all lights after final assembly of a VFD tube panel.
FEATURES
• Logic Supply Voltage (VDD) : +3.3 V ± 10% or +5.0 V ± 10%
• Driver Supply Voltage (VDISP) : +20 to +60 V
• Driver Output Current
I
OHVH1 (Only one driver output: “H”) : –40 mA (VDISP = 40 V)
I
OHVH2 (All the driver outputs: “H”) : –120 mA (VDISP = 40 V)
I
OHVL
: 1 mA
• Directly connected to VFD tube by using push-pull output (Pull-down resistors are not needed)
• Data Transfer Speed : 4 MHz
• Package: 70-pin plastic SSOP (SSOP70-P-500-0.80-K) : ML9261AMB
FEDL9261A-01
OKI Semiconductor ML9261A
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BLOCK DIAGRAM
VDISP
VDD
CL
CHG
LS
DIN
CLK
HVO 1
HVO 2
HVO60
DOUT
L-GND
D-GND
CSI
PO-
PO-2
60-Bit
Shift
Register
60-Bit
Register
P0-60
SO
D-60 O-60
D-2
D-1
O-2
O-1
RESET
RRC
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OKI Semiconductor ML9261A
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PIN CONFIGURATION (TOP VIEW)
ML9261A
70-Pin Plastic SSOP
(SSOP70-P-500-0.80-K)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
HVO 25
HVO 24
HVO 23
HVO 22
HVO 21
HVO 20
HVO 19
HVO 18
HVO 17
HVO 16
HVO 15
HVO 14
HVO 13
HVO 12
HVO 11
HVO 10
HVO 26
HVO 27
HVO 28
HVO 29
HVO 30
HVO 31
HVO 32
HVO 33
HVO 34
HVO 35
HVO 36
HVO 37
HVO 38
HVO 39
HVO 40
HVO 41
17
18
19
20
54
53
52
51
HVO 9
HVO 8
HVO 7
HVO 6
HVO 42
HVO 43
HVO 44
HVO 45
21
22
23
24
25
26
50
49
48
47
46
45
HVO 5
HVO 4
HVO 3
HVO 2
HVO 1
VDISP
HVO 46
HVO 47
HVO 48
HVO 49
HVO 50
HVO 51
27
28
29
30
44
43
42
41
VDD
DIN
DOUT
CLK
HVO 52
HVO 53
HVO 54
HVO 55
31 40
LS HVO 56
32
33
34
35
39
38
37
36
CL
CHG
L-GND
D-GND
HVO 57
HVO 58
HVO 59
HVO 60
FEDL9261A-01
OKI Semiconductor ML9261A
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PIN DESCRIPTION
Symbol Type Description
CLK l Shift register clock input pin.
Shift register reads data from DIN while the CLK pin is low and the data in the shift
register is shifted from one stage to the next stage at the rising edge of the clock.
DIN I Serial data input pin of the shift register.
Display data (positive logic) is input in the DIN pin in synchronization with clock.
DOUT O Serial data output pin of the shift register.
Data is output from the DOUT pin in synchronization with the CLK signal.
LS I
Latch strobe input pin.
The contents of the parallel outputs (PO1 to PO60) of the shift register are read at the
rising edge of LS (edge-triggered). When the CLK rises while LS is high, the parallel
outputs (PO1 to PO60) and latch outputs (O1 to O60) go low.
CL I
Clear input pin with a built-in pull-down resistor.
The CL pin is normally set high.
If the CL pin is high and the CHG pin is low, the driver outputs (HVO1 to HVO60) are in
phase with the corresponding register outputs (O1 to O60).
If the CL pin is high and the CHG pin is high, the driver outputs (HVO1 to HVO60) are
high irrespective of the states of the register outputs.
If the CL pin is set low, the driver outputs are driven low irrespective of the states of the
CHG pin and register outputs.
This allows display blanking to be set.
CHG I
Input for testing (with a pull-down resistor).
The CL pin is normally set low.
If the CHG pin is low and the CL pin is high, the driver outputs (HVO1 to HVO60) are in
phase with the corresponding register outputs (O1 to O60).
If the CHG pin is low and the CL pin is low, the driver outputs (HVO1 to HVO60) are low
irrespective of the states of the register outputs.
If the CHG pin is set high, the driver outputs are driven high irrespective of the states of
the register outputs.
This provides the easy testing of all lights after final assembly.
VHO1-60 O
High voltage driver outputs for driving a VFD tube.
If the CL pin is high and the CHG pin is low, the driver outputs are in phase with the
corresponding register outputs (O1 to O60).
The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors.
VDISP Power supply pin for VFD tube driver circuits
VDD Power supply pin for logic
D-GND GND pin for VFD tube driver circuits.
Since the D-GND pin is not connected internally to the L-GND pin, connect these pins
outside of the IC.
L-GND GND pin for the logic circuits.
Since the L-GND pin is not connected internally to the D-GND pin, connect thiese pins
outside of the IC.
FEDL9261A-01
OKI Semiconductor ML9261A
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ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Rating Unit
Supply Voltage (1) *1 VDD Applicable to logic supply pin –0.3 to +6.5 V
Supply Voltage (2) *1, *2 VDISP Applicable to driver supply pin –0.3 to +70 V
Input Voltage *1 VIN Applicable to all input pins –0.3 to VDD +0.3 V
Output Voltage *1 VO Applicable to DOUT –0.3 to VDD +0.3 V
Output Current lO Applicable to HVO1 to HVO60 –50 to 0.0 mA
Withstand Output Voltage *1, *2 VHVO Applicable to HVO1 to HVO60 –0.3 to VDISP +0.3 V
Power Dissipation PD Ta ≤ 25°C 1.47 W
Package Thermal Resistance *3 Rj-a Ta > 25°C 68 °C/W
Storage Temperature TSTG — –55 to +150 °C
Notes: *1 Supply Voltage for L-GND and D-GND
*2 Permanent damage may be caused if the voltage is supplied over the rating value.
*3 Package Thermal Resistance (between junction and ambient)
The junction temperature (Tj) expressed by the equation indicated belo w should not exceed
125°C under the operating conditions.
T
j = P × Rj–a + Ta (P: Maximum power consumption)
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OKI Semiconductor ML9261A
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RECOMMENDED OPERATING CONDITIONS-1
Unit Power Supply: 5.0 V (Typ.)
Parameter Symbol Condition Min. Typ. Max. Unit
Power Supply (1) VDD — 4.5 5.0 5.5 V
Power Supply (2) VDISP — 20 — 60 V
“H” Input Voltage VIH Applicable to all inputs 0.7 VDD — — V
“L” Input Voltage VIL Applicable to all inputs — — 0.3 VDD V
lOHVH1 Only 1 output is ON. — — –40 mA
Driver Output Current lOHVH2 All outputs are ON. — — –120 mA
CLK Frequency fCLK — — — 4.0 MHz
Operating Temperature TOP — –40 — +85 °C
RECOMMENDED OPERATING CONDITIONS-2
Unit Power Supply: 3.3 V (Typ.)
Parameter Symbol Condition Min. Typ. Max. Unit
Power Supply (1) VDD — 3.0 3.3 3.6 V
Power Supply (2) VDISP — 20 — 60 V
“H” Input Voltage VIH Applicable to all inputs 0.8 VDD — — V
“L” Input Voltage VIL Applicable to all inputs — — 0.2 VDD V
lOHVH1 Only 1 output is ON. — — –40 mA
Driver Output Current lOHVH2 All outputs are ON. — — –120 mA
CLK Frequency fCLK — — — 4.0 MHz
Operating Temperature TOP — –40 — +85 °C
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ELECTRICAL CHARACTERISTICS
DC Characteristics-1
(VDD = 4.5 to 5.5 V, VDISP = 20 to 60 V, Ta = –40 to +85°C)
Parameter Symbol Applicable pin Condition Min. Typ. Max. Unit
“H” Input Voltage VIH All inputs — 0.7 VDD — — V
“L” Input Voltage VIL All inputs — — — 0.3 VDD V
lIH1 DIN, CLK, LS VDD = VIN = 5.5 V –1.0 — +1.0 µA
“H” Input Current IIH2 CL, CHG VDD = VIN = 5.5 V 5.0 — 80 µA
“L” Input Current IIL All inputs VDD = 5.5 V, VIN = 0 V –1.0 — +1.0 µA
Input Capacitance CIN All inputs Ta = 25°C — 15 — pF
VOH1 DOUT IOH = –0.1 mA VDD–1 — — V
“H” Output Voltage VOH2 HVO1 to 60 VDISP = 40 V
IOH = –40 mA VDISP–4 — — V
VOL1 DOUT IOL = 0.1 mA — — 1.1 V
“L” Output Voltage VOL2 HVO1 to 60 VDISP = 40 V
IOL = 1 mA — — 3.0 V
IDD1 V
DD All inputs: “L” — — 10.0 µA
IDD2 V
DD All inputs: “H” — — 10.0 µA
IDISP1 V
DISP All inputs: “L” — — 70.0 µA
Supply Current
IDISP2 V
DISP
No load
All inputs: “H” — — 70.0 µA
DC Characteristics-2
(VDD = 3.0 to 3.6 V, VDISP = 20 to 60 V, Ta = –40 to +85°C)
Parameter Symbol Applicable pin Condition Min. Typ. Max. Unit
“H” Input Voltage VIH All inputs — 0.8 VDD — — V
“L” Input Voltage VIL All inputs — — — 0.2 VDD V
lIH1 DIN, CLK, LS VDD = VIN = 3.3 V –1.0 — +1.0 µA
“H” Input Current IIH2 CL, CHG VDD = VIN = 3.3 V 2.0 — 50 µA
“L” Input Current IIL All inputs VDD = 3.3 V, VIN = 0 V –1.0 — +1.0 µA
Input Capacitance CIN All inputs Ta = 25°C — 15 — pF
VOH1 DOUT IOH = –0.1 mA VDD–1 — — V
“H” Output Voltage VOH2 HVO1 to 60 VDISP = 40 V
IOH = –40 mA VDISP–4 — — V
VOL1 DOUT IOL = 0.1 mA — — 1.1 V
“L” Output Voltage VOL2 HVO1 to 60 VDISP = 40 V
IOL = 1 mA — — 3.0 V
IDD1 V
DD All inputs: “L” — — 10.0 µA
IDD2 V
DD All inputs: “H” — — 10.0 µA
IDISP1 V
DISP All inputs: “L” — — 70.0 µA
Supply Current
IDISP2 V
DISP
No load
All inputs: “H” — — 70.0 µA
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OKI Semiconductor ML9261A
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AC Characteristics-1 (VDD = 4.5 to 5.5 V, VDISP = 20 to 60 V, Ta = –40 to +85°C)
Parameter Symbol Condition Min. Max. Unit
CLK Pulse Width tW (CLK) — 80 150 ns
DIN Setup Time tSU (D-CLK) — 50 — ns
DIN Hold Time tH (CLK-D) — 50 — ns
CLK-LS Setup Time tSU (CLK-LS) — 50 — ns
tSU (LS-CLK) During normal operation 50 — ns
LS-CLK Setup Time tSU (L-CLK) At display data reset 50 — ns
CLK-LS Hold Time tH (CLK-L) At display data reset 50 — ns
LS-CHG Setup Time tSU (LS-CHG) — 50 — ns
LS-CL Setup Time tSU (LS-CL) — 50 — ns
LS Pulse Width tW (LS) — 80 — ns
CHG Pulse Width tW (CHG) — 10 — µs
CL Pulse Width tW (CL) — 10 — µs
DOUT Delay time tPD, tPRD Load: 30 pF — 50 ns
tDLH — 2.0 µs
tDHL — 2.0 µs
Driver Output Delay Time tDRHL
VDISP = 40 V
Load: 1.0 kΩ resistance in
parallel with 20 pF capacitance — 2.0 µs
tTLH — 5.0 µs
Driver Output Slew Rate tTHL
VDISP = 40 V
Load: 1.0 kΩ resistance in
parallel with 20 pF capacitance — 5.0 µs
AC Characteristics-2 (VDD = 3.0 to 3.6 V, VDISP = 20 to 60 V, Ta = –40 to +85°C)
Parameter Symbol Condition Min. Max. Unit
CLK Pulse Width tW (CLK) — 80 150 ns
DIN Setup Time tSU (D-CLK) — 50 — ns
DIN Hold Time tH (CLK-D) — 50 — ns
CLK-LS Setup Time tSU (CLK-LS) — 50 — ns
tSU (LS-CLK) During normal operation 50 — ns
LS-CLK Setup Time tSU (L-CLK) At display data reset 50 — ns
CLK-LS Hold Time tH (CLK-L) At display data reset 50 — ns
LS-CHG Setup Time tSU (LS-CHG) — 50 — ns
LS-CL Setup Time tSU (LS-CL) — 50 — ns
LS Pulse Width tW (LS) — 80 — ns
CHG Pulse Width tW (CHG) — 10 — µs
CL Pulse Width tW (CL) — 10 — µs
DOUT Delay time tPD, tPRD Load: 30 pF — 50 ns
tDLH — 3.0 µs
tDHL — 3.0 µs
Driver Output Delay Time tDRHL
VDISP = 40 V
Load: 1.0 kΩ resistance in
parallel with 20 pF capacitance — 3.0 µs
tTLH — 5.0 µs
Driver Output Slew Rate tTHL
VDISP = 40 V
Load: 1.0 kΩ resistance in
parallel with 20 pF capacitance — 5.0 µs
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OKI Semiconductor ML9261A
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TIMING DIAGRAMS
Normal Display Operation
CLK
DIN
LS
HVO (OTHERS)
CL
HVO (1, 2, 59, 60)
CHG
DOUT
T1/2 T3/4 T59/60 T1/2 T3/4
tSU(D-CLK)
tPD
tSU(CLK-LS) tSU(LS-CLK)
tSU(LS-CHG)
tW(CHG)
tSU(LS-C
L
) tW(C
L
) tW(C
L
)
tDLH tDLH tDHL tDHL
tTLH tTLH tTHL tTHL
tH(CLK-D)
tW(CHG)
1/fCLK tW(CLK)
tPD
tW(LS)
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OKI Semiconductor ML9261A
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Display Data Reset Operation
CLK
DIN
LS
HVO (OTHERS)
CL
HVO (1, 2, 59, 60)
CHG
DOUT
T1/2 T3/4 T59/60 T1/2
tPRD
tDRHL
tSU(L-CLK) tH(CLK-L)
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OKI Semiconductor ML9261A
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FUNCTIONAL DESCRIPTION
Display Data Reset
When the power is turned on, the shift register outputs (PO1 to PO60) and register outputs (O1 to O60) are
indeterminate. Consequently the display of a VFD tube may flicker because unnecessary driver outputs go high.
To prevent such flicker, it is required to perform the following operations.
1. Turn on the logic power supply while the CL input is kept low.
2. Set the LS input high.
3. Switch the CLK input from a low level to a high level at least once.
By performing the above operations, all of the shift register outputs (PO1 to PO60) and register outputs (O1 to
O60) are set low.
4. Enter display data.
5. Set the CL input high.
Data Transfer
Write display data by using a serial transfer.
Serial data is input in the shift register at the rising edge of a CLK input pulse.
When the LS input rises, display data is written in the latch.
Driver Output Control
1. To turn on or off driver outputs by using display data transferred into the shift register, set the CL input high
and set the CHG input low.
2. To set all the driv er outputs low, set the CL input low.
3. To set all the driver outputs high, set the CL input and CHG input high at a time.
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OKI Semiconductor ML9261A
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Function Table
Shift register
Input Shift Register Parallel Out Output
CLK DIN LS PO1 PO2 • • • • PO59 PO60 DOUT
H L H PO1n • • • • PO58n PO59n PO59n
L L L PO1n • • • • PO58n PO59n PO59n
X L PO1n PO2n • • • • PO59n PO60n PO60n
X H L L • • • • L L L
X: Don’t Care
PO1n to PO59n: PO1 to PO59 data just before CLOCK rises.
Register
Input Shift Register Parallel Out Latch Output
CLK LS POm Om
X H H
X L L
X X No Change
H L L
X: Don’t Care, m: 1 to 60
Driver output
Input Latch Output Output
CL CHG CLK LS Om HVOm
H L X X H H
H L X X L L
H H X X X H
L X X X X L
X X H L L
X: Don’t Care, m: 1 to 60
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OKI Semiconductor ML9261A
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TEST CIRCUIT
NOTES ON POWER APPLICATION
Connect L-GND and G-GND pins externally to provide the equal potential.
To prevent IC err oneous oper ation, turn on VDD be fore tur ning on VDISP, and turn off VDISP before turning off VDD.
DOUT
HVO60
HVO1
HVO2
20 pF
1.0 k
Ω
VDISP
DIN CLK LS
CL
CHG
VDD
D-GND
L-GND
20 pF
20 pF
1.0 kΩ
1.0 kΩ
30 pF
Voltage
Time
VDD voltage
VDISP voltage
FEDL9261A-01
OKI Semiconductor ML9261A
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PACKAGE DIMENSIONS
SSOP70-P-500-0.80-K
Mirror finish
Package material Epoxy resin
Lead frame materi al 42 alloy
Pin treatment Solder plating (≥5µm)
Package weight (g) 2.15 TYP.
5Rev. No./Last Revised 3/Dec. 5, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
(Unit: mm)
FEDL9261A-01
OKI Semiconductor ML9261A
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REVISION HISTORY
Page
Document
No. Date Previous
Edition Current
Edition Description
PEDL9261A-01 Jan. 22, 2002 – – Preliminary first edition
Removed Preliminary classification.
1 1
The following contents of “FEATURES” have
been revised:
• “Logic Supply Voltage (VCC)” to “Logic Suppl y
Voltage (VDD)”.
• “Drive Supply Voltage (VHV): +60 V” to “Drive
Supply Voltage (VDISP): +20 to +60 V”.
Rating and Unit of Parameter “Power
Dissipation” in the table have been revised from
1.9 and mW to 1.47 and W, respectively.
5 5
Partially changed the content of Note *3.
7 7
Removed (Design Goal) from Parameter
“Supply Current” in the two tables.
12 12
Symbol “PO2n” has been changed to Symbol
“PO1n” in Column “PO2” of Column “Shift
Register Parallel Out”.
The test circuit has been partially changed.
“The logic power supply” and “the driver p ower
supply” have been chang ed to VDD and VDISP in
the sentence of “NOTES ON POWER
APPLICATIONS”.
FEDL9261A-01 Mar. 28, 2002
13 13
Changed “VDISP pin voltage” and “VDD pin
voltage” to “VDISP voltage” and VDD voltage” in
the bottom figure.
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NOTICE
1. The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is
up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard a ction a nd perf ormance of the pr oduct. When pla nning t o use t he product , please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximu m ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual phy sical or electri cal stress includin g, but not l imited to, ex posure to pa rameters beyond t he specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or applicatio n where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safet y devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2002 Oki Electric Industry Co., Ltd.
