Rev. 4665D–SIGE–08/04
Features
•Gain Control in 20-dB Steps
•Very Low I/Q Amplitude and Phase Errors
•High Input P1dB
•Small and Optimized Package for High Reliability and Performance
Applications
•Infrastructure Digital Communication Systems
•GSM/Cellular Transceivers
•ISM Band Transceivers
Benefits
•Fully Integrated Device with Reduced External Component Count
Electrostatic sensitive device.
Observe precautions for handling.
Description
The ATR0797 is a multi-purpose demodulator RFIC. The silicon monolithic integrated
circuit is designed with Atmel’s advanced SiGe technology. This demodulator is capa-
ble of both quadrature demodulation or direct IF output. Features include switchable
gain control on a frequency range from 65 MHz to 300 MHz. The device performs a
very low amplitude as well as phase error and allows high input P1dB. The ATR0797
targets a variety of system applications for communications including 3G wireless.
Figure 1. Block Diagram
ϕ
IFP
IFN
GC1 GC2
BBIP
BBIN
BBQP
BBQN
LOP
LON
1
2
16
15
1213
45
8
9
65 - 300 MHz
SiGe IF
Receiver/
Demodulator
ATR0797
2ATR0797
4665D–SIGE–08/04
Pin Configuration
Figure 2. Pinning
BBQP
BBQN
VCC
LOP
LON
GND
VCC
IFN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BBIN
BBIP
VCC
GC2
GC1
GND
VCC
IFP
Pin Description
Pin Symbol Function
1 BBIN Baseband I-axis negative output, self biasing
2 BBIP Baseband I-axis positive output, self biasing
3 VCC 5 V power supply
4 GC2 Gain control input, stage 2, 5 V CMOS levels
5 GC1 Gain control input, stage 1, 5 V CMOS levels
6 GND Ground
7 VCC 5 V power supply
8 IFP IF positive input, self biasing, AC-coupled
9 IFN IF negative input, self biasing, AC-coupled
10 VCC 5 V power supply
11 GND Ground
12 LON Local oscillator, negative input, self biasing, AC-coupled
13 LOP Local oscillator, positive input, self biasing, AC-coupled
14 VCC 5 V power supply
15 BBQN Baseband Q-axis negative output, self biasing
16 BBQP Baseband Q-axis positive output, self biasing
3
ATR0797
4665D–SIGE–08/04
Product Description Atmel’s ATR0797 is a variable gain I-Q demodulator designed for use in receiver IF sec-
tions, that are typically existing in superheterodyne RF architectures.
The ATR0797 has two gain stages that are independent of each other. These gain
stages are broadband differential amplifiers each with a digital control pin to set the
gain. Since the amplifiers have approximately the same gain, setting GC1 high and GC2
low results in approximately the same gain as setting GC1 low and GC2 high. Former
setting offers better noise figures.
The IF input is a differential input that has internal bias circuitry to set the common mode
voltage. The use of blocking capacitors to facilitate AC coupling is highly recommended
to avoid changing the common mode voltage. Either input may be driven single ended if
the other input is connected to ground through an AC short such as a 1000 pF capacitor.
This typically results in slightly lower input P1dB.
The two matched mixers are configured with the quadrature LO generator to provide in-
phase and quadrature baseband outputs.
The LO and IF ports offer a differential 50 Ω impedance. The passives at these ports
(parallel L-R network) and the package itself adds inductance that tends to degrade
return loss.
The ATR0797 features immunity from changes in LO power. The gain features change
by less than 0.6 dB over a 6 dB range of LO power. Also note the excellent I/Q balance,
which typically falls within 0.1 dB and 1 degree from 65 MHz to 300 MHz, and varies
less than 0.05 dB and 0.5 degree over temperature (-40°C to +85°C).
The frequency response of the IF and LO ports is dominated by the L-R network on the
input. When de-embedded, the gain and P1dB response is within 0.5 dB from 65 MHz to
300 MHz.
The figures in the datasheet illustrate a typical ATR0797’s performance with respect to
temperature. Note that these numbers include the effect of the R-L network in the IF
port.
Evaluation board design and equipment constraints:
Please take into account that the evaluation board uses baluns on the I/Q outputs, and
these baluns limit the low frequency response of the device. For true baseband opera-
tion, the baluns should be removed, and the differential signals used directly.
The 27 pF capacitor on the evaluation board is appropriate for lower frequencies.
4ATR0797
4665D–SIGE–08/04
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages are referred to GND.
Parameters Symbol Value Unit
Supply voltage VCC 5.5 V
LO input LOP, LON 10 dBm
IF input IFN, IFP 10 V
Operating temperature TOP -40 to +85 °C
Storage temperature Tstg -65 to +150 °C
Note: The device may not survive all maximums applied simultaneously.
Thermal Resistance
Parameters Symbol Value Unit
Junction ambient RthJA 35 K/W
Electrical Characteristics
Test conditions: VCC = 5 V, Tamb = 25°C, LO input: 0 dBm at 200 MHz
IF input: at 200.1 MHz, GC1 = 0, GC2 = 0; 0 dBm
IF input: at 200.1 MHz, GC1 = 1, GC2 = 0; -20 dBm
IF input: at 200.1 MHz, GC1 = 1, GC2 = 1; -40 dBm
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type(1)
1 IF Input (I/Q Mixing to Baseband)
1.1 Frequency range 8-9 f 65 120 -
220 300 MHz B
1.2 IF input return loss 50 Ω nominal
differential input(2) 8-9 RL 20 dB D
1.3 IF input common
mode voltage Internally generated 8, 9 VCH 2V
1.4 Gain
Gain set = high;
GC1 = GC2 = 1
2-1,
16-15
G323538dBA
1.5 Input P1dB 1, 2,
15, 16
P1dB -29 -27 dBm C
1.6 DSB Noise figure 2-1,
16-15
NF 11 dB D
1.7 Gain
Gain set = medium;
GC1 = 1; GC2 = 0 or
GC1 = 0; GC2 = 1
2-1,
16-15
G121517dBA
1.8 Input P1dB 1, 2,
15, 16
P1dB -8 -6 dBm C
1.9 DSB Noise figure 2-1,
16-15
NF 14.5 dB D
Notes: 1. Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
2. The parasitic inductance of the package, the board, and L5, L6 must be matched out at the center frequency with a series
capacitor to achieve 20 dB of port match.
3. The parasitic inductance of the package must be matched out to reach 20 dB port match above 100 MHz.
5
ATR0797
4665D–SIGE–08/04
1.10 Gain
Gain set = low;
GC1 = GC2 = 0
2-1,
16-15
G-7-4-2dBA
1.11 Input P1dB 1, 2,
15, 16
P1dB 12 14 dBm C
1.12 DSB Noise figure 2-1,
16-15
NF 31 dB D
2 I/Q Output
2.1 I/Q output frequency
range
1, 2,
15, 16 fI/Q DC 500 MHz D
2.2 I/Q output amplitude
error
2-1,
16-15 -0.2 +0.2 dB A
2.3 I/Q phase error 2-1,
16-15 -2 +2 deg A
2.4 I/Q output common
mode voltage
1, 2,
15, 16 2.5 V A
2.5 I/Q output differential
offset voltage
2-1,
16-15 Voffset -100 +100 mV A
2.6 I/Q output return loss 50 Ω nominal
differential output(3) 1, 2,
15, 16 RLI/Q 20 dB D
3 LO input
3.1 LO input level 13-12 PLO -3 0 +3 dBm D
3.2 Return loss 13-12 RLLO 20 dB D
3.3 LO frequency range 13-12 RLLO 65 300 MHz D
4 Miscellaneous
4.1 Supply voltage 3, 7,
10, 14 VCC 4.75 5 5.25 V A
4.2 Supply current 3, 7,
10, 14 ICC 195 mA A
4.3 GC1, GC2 logic level
low 4, 5 VIL 00.3 ×
VCC VD
4.4 GC1, GC2 logic level
high 4, 5 VIH 0.7 ×
VCC VCC VD
4.5 GC1, GC2 input
impedance 4, 5 Z 40 kΩD
Electrical Characteristics (Continued)
Test conditions: VCC = 5 V, Tamb = 25°C, LO input: 0 dBm at 200 MHz
IF input: at 200.1 MHz, GC1 = 0, GC2 = 0; 0 dBm
IF input: at 200.1 MHz, GC1 = 1, GC2 = 0; -20 dBm
IF input: at 200.1 MHz, GC1 = 1, GC2 = 1; -40 dBm
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type(1)
Notes: 1. Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
2. The parasitic inductance of the package, the board, and L5, L6 must be matched out at the center frequency with a series
capacitor to achieve 20 dB of port match.
3. The parasitic inductance of the package must be matched out to reach 20 dB port match above 100 MHz.
6ATR0797
4665D–SIGE–08/04
Figure 3. Gain versus Temperature
Figure 4. Noise Figure versus Temperature
Figure 5. Amplitude Difference versus LO Frequency
-10
-5
0
5
10
15
20
25
30
35
-40-200 20406080100
Temperature (°C)
Gain (dB)
Low Gain
Med Gain
High Gain
0
5
10
15
20
25
30
35
-40-20 0 20406080100
Temperature (°C)
Noise Figure (dB)
Low Gain
Med Gain
High Gain
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0 100 200 300 400 500 600 700 800
LO Frequency (MHz)
Amplitude Difference (dB)
7
ATR0797
4665D–SIGE–08/04
Figure 6. Output P1dB versus Temperature
Figure 7. Output P1dB versus LO Power
Figure 8. Phase Difference versus LO Frequency
5
6
7
8
9
10
-40-20 0 20 406080100
Temperature (°C)
Output P1dB (dBm)
Low Gain
High Gain
Med Gain
5
6
7
8
9
10
-4-3-2-10 1234
Temperature (°C)
Output P1dB (dBm)
Low Gain
High Gain
Med Gain
89.0
89.5
90.0
90.5
91.0
91.5
92.0
0 100 200 300 400 500 600 700 800
LO Frequency (MHz)
Phase Difference (degrees)
8ATR0797
4665D–SIGE–08/04
Figure 9. Demo Test Board Schematic
IFin
T4
GC1
GC2
T3
LOin
R4
L2
C4
BBIN
BBIP
BBQP
BBQN
VCC
5 V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ATR0797
J2
H2
D1
R9
J1
J6
J5
J4
J3
L1
L7
L5L6
L3
L4
C8
C3C7
C12
C15
C19
C17 C18
C16
C14
C13
C11
C5
C9
C10 C6
R3
R7R8
R10
R5
R6
VCC
VCC
VCC VCC
VCC
VCC
Table 1. Bill of Materials
Component Reference Vendor Part Number Value Size/Package
IF Demodulator D1Atmel ATR0797 PSSO16
SMA end launch
connector J1, J2, J3, J4, J5, J6Johnson
Components™742-0711-841
Transformer T3, T4Mini-Circuits®TC1-1
Supply bypass
capacitor C19 1 µF 1206
Resistor R7, R81 kΩ0402
Capacitor C11, C12, C16 22 pF 0402
Inductor L1, L2, L3, L4, L7Würth Elektronik®74476401 1 µH 1210
Capacitor C13, C14, C17, C18 68 pF 0402
Resistor R3, R4, R5, R60 Ω0402
Capacitor C3, C4, C5, C6, C7, C8,
C9, C10 820 pF 0402
Resistor R9, R10 51 Ω0402
Inductor L5, L610 nH 0402
Capacitor C15 100 pF 0402
9
ATR0797
4665D–SIGE–08/04
Figure 10. Demo Test Board (Fully Assembled PCB)
Figure 11. Recommended Package Footprint
Remark: Heatslug must be soldered to GND.
In order to avoid soldering problems, plugging of the vias under the heatslug is recom-
mended. Only ground signal traces are allowed directly under the package.
3.0
0.25
1.25
0.74
0.4
φ0.33 via
- Indicates metalization - vias connect pad to underlying ground plane
all units are in mm
3.0
0.9
0.7
6.9
0.74
10 ATR0797
4665D–SIGE–08/04
Package Information
Ordering Information
Extended Type Number Package Remarks
ATR0797-6CPH PSSO16 Lead free
Printed on recycled paper.
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
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4665D–SIGE–08/04
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Atmel® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Johnson Components™ is a trademark
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