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Rev. A
02/02/2018
Copyright © 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS43/46LD16128B
IS43/46LD32640B
DESCRIPTION
The IS43/46LD16128B/32640B is 2Gbit CMOS
LPDDR2 DRAM. The device is organized as 8 banks
of 16Meg words of 16bits or 8Meg words of 32bits.
This product uses a double-data-rate architecture to
achieve high-speed operation. The double data rate
architecture is essentially a 4N prefetch architecture
with an interface designed to transfer two data words
per clock cycle at the I/O pins. This product offers fully
synchronous operations referenced to both rising and
falling edges of the clock. The data paths are internally
pipelined and 4n bits prefetched to achieve very high
bandwidth.
2Gb (x16, x32) Mobile LPDDR2 S4 SDRAM FEBRUARY 2018
FEATURES
• Low-voltage Core and I/O Power Supplies
VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V,
VDD1 = 1.70-1.95V
• High Speed Un-terminated Logic(HSUL_12) I/O
Interface
• Clock Frequency Range : 10MHz to 533MHz
(data rate range : 20Mbps to 1066Mbps per I/O)
• Four-bit Pre-fetch DDR Architecture
• Multiplexed, double data rate, command/ad-
dress inputs
• Eight internal banks for concurrent operation
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable Read/Write latencies(RL/WL)
and burst lengths(4,8 or 16)
• ZQ Calibration
• On-chip temperature sensor to control self re-
fresh rate
• Partial –array self refresh(PASR)
• Deep power-down mode(DPD)
• Operation Temperature
Commercial (TC = 0°C to 85°C)
Industrial (TC = -40°C to 85°C)
Automotive, A1 (TC = -40°C to 85°C)
Automotive, A2 (TC = -40°C to 105°C)
Automotive, A25 (TC = -40°C to 115°C)(3)
OPTIONS
• Configuration:
− 128Mx16 (16M x 16 x 8 banks)
− 64Mx32 (8M x 32 x 8 banks)
Package:
− 134-ball BGA for x16 / x32
− 168-ball PoP BGA for x32
KEY TIMING PARAMETERS(1)
ADDRESS TABLE
Speed
Grade
Data
Rate
(Mb/s)
Write
Latency
Read
Latency
tRCD/
tRP(2)
-18 1066 4 8 Typical
-25 800 3 6 Typical
-3 667 2 5 Typical
Parameter 64Mx32 128Mx16
Row Addresses R0-R13 R0-R13
Column Addresses C0-C8 C0-C9
Bank Addresses BA0-BA2 BA0-BA2
Refresh Count 8192 8192
Notes:
1. Other clock frequencies/data rates supported; please
refer to AC timing tables.
2. Please contact ISSI for Fast trcd/trp.
3. When Tc > 105°C, Self-Refresh mode is not supported
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
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IS43/46LD16128B
IS43/46LD32640B
BALL ASSIGNMENTS AND DESCRIPTIONS
134-ball FBGA (x32), 0.65mm pitch
Top View (ball down)
1 2 3 4 5 6 7 8 9 10
ADNU DNU DNU DNU A
BDNU NC NC VDD2 VDD1 DQ31 DQ29 DQ26 DNU B
CVDD1 VSS RFU VSS VSSQ VDDQ DQ25 VSSQ VDDQ C
DVSS VDD2 ZQ VDDQ DQ30 DQ27 DQS3 DQS3# VSSQDDQ
EVSSCACA9CA8 DQ28 DQ24 DM3 DQ15 VDDQ VSSQECA
FVDDCA CA6CA7 VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ FPower
G
VDD2 CA5 Vref(CA) DQS1# DQS1 DQ10 DQ9 DQ8 VSSQ
G
Ground
HVDDCA VSS CK# DM1 VDDQ HNo ball
JVSSCA NC CK VSSQ VDDQ VDD2 VSS Vref(DQ) JZQ
KCKE RFU RFU DM0 VDDQ KClock
L
CS# RFU RFU DQS0# DQS0 DQ5 DQ6 DQ7 VSSQ
L
NC, DNU, RFU
MCA4CA3CA2 VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ M
NVSSCA VDDCA CA1 DQ19 DQ23 DM2 DQ0 VDDQ VSSQN
PVSS VDD2 CA0 VDDQ DQ17 DQ20 DQS2 DQS2# VSSQP
RVDD1 VSS NC VSS VSSQ VDDQ DQ22 VSSQ VDDQ R
T
DNU NC NC VDD2 VDD1 DQ16 DQ18 DQ21 DNU
T
UDNU DNU DNU DNU U
1 2 3 4 5 6 7 8 9 10
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IS43/46LD16128B
IS43/46LD32640B
BALL ASSIGNMENTS AND DESCRIPTIONS
134-ball FBGA (x16), 0.65mm pitch
Top View (ball down)
1 2 3 4 5 6 7 8 9 10
ADNU DNU DNU DNU A
BDNU NC NC VDD2 VDD1 NC NC NC DNU B
C
VDD1 VSS RFU VSS VSSQ VDDQ NC VSSQ VDDQ
C
DVSS VDD2 ZQ VDDQ NC NC NC NC VSSQDDQ
E
VSSCACA9CA8 NC NC NC DQ15 VDDQ VSSQ
E
CA
FVDDCA CA6CA7 VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ FPower
GVDD2 CA5 Vref(CA) DQS1# DQS1 DQ10 DQ9 DQ8 VSSQGGround
HVDDCA VSS CK# DM1 VDDQ HNo ball
J
VSSCA NC CK VSSQ VDDQ VDD2 VSS Vref(DQ)
J
ZQ
KCKE RFU RFU DM0 VDDQ KClock
L
CS# RFU RFU DQS0# DQS0 DQ5 DQ6 DQ7 VSSQ
L
NC, DNU, RFU
MCA4CA3CA2 VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ M
NVSSCA VDDCA CA1 NC NC NC DQ0 VDDQ VSSQN
PVSS VDD2 CA0 VDDQ NC NC NC NC VSSQP
RVDD1 VSS NC VSS VSSQ VDDQ NC VSSQ VDDQ R
T
DNU NC NC VDD2 VDD1 NC NC NC DNU
T
U
DNU DNU DNU DNU
U
1 2 3 4 5 6 7 8 9 10
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IS43/46LD16128B
IS43/46LD32640B
168-ball FBGA - 12mm x 12mm (x32), 0.5mm pitch
Note:
1. Balls labeled Vss1 (at coordinates B5, B8, F2, J2, AC9) may be connected to Vss or left unconnected.
2. Balls indicated as (NC) are no connects.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
Top View (ball down)
1
DNU
DNU
VSS
NC
NC
NC 1
NC
NC
NC 1
NC
NC
NC
NC
ZQ
VSS
CA9
CA7
VSSCA
CA5
CK#
VSS
DNU
DNU
1
2
DNU
DNU
VDD2
NC
NC
VSS
NC
NC
VSS
NC
NC
VSS
VDD1
VREFCA
VDD2
CA8
VDDCA
CA6
VDDCA
CK
VDD2
DNU
DNU
2
4
NC
NC
NC
NC
4
3
NC
VDD1
CS#
CKE
3
5
NC
VSS
VDD1
VSS
5
6
NC
NC
CA1
CA0
6
7
NC
NC
VSSCA
CA2
7
8
NC
VSS
CA3
VDDCA
8
9
NC
1NC
CA4
VSS
9
11
VDD1
VDD2
VSS
NC
11
13
DQ30
VDDQ
VDDQ
DQ17
13
14
DQ29
DQ28
DQ18
DQ19
14
15
VSSQ
DQ27
DQ20
VSSQ
15
16
DQ26
VDDQ
VDDQ
DQ21
16
22
DNU
DNU
DQ15
VDDQ
DQ12
DQ11
VDDQ
DQ8
DQS1
VDDQ
VDD2
VREFDQ
VDD1
DQS#0
VDDQ
DQ6
DQ5
VDDQ
DQ2
DQ1
VDDQ
DNU
DNU
22
23
DNU
DNU
VSSQ
DQ14
DQ13
VSSQ
DQ10
DQ9
VSSQ
DQS#1
DM1
VSS
DM0
VSSQ
DQS0
DQ7
VSSQ
DQ4
DQ3
VSSQ
DQ0
DNU
DNU
23
10
NC
VSS
VDD2
NC
1
10
12
VSSQ
DQ31
DQ16
VSSQ
12
18
VSSQ
DQS3
DQS2
VSSQ
18
19
DQS#3
VDDQ
VDDQ
DQS#2
19
20
VDD1
DM3
DM2
VDD1
20
21
VSS
VDD2
VDD2
VSS
21
17
DQ25
DQ24
DQ22
DQ23
17
1
Integrated Silicon Solution, Inc. — www.issi.com 5
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IS43/46LD16128B
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INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Pad Definition and Description
Name Type Description
CK, CK#Input Clock: CK and CK# are differential clock inputs. All Double Data Rate (DDR) CA
inputs are sampled on both positive and negative edge of CK. Single Data Rate (SDR)
inputs, CS# and CKE, are sampled at the positive Clock edge.
Clock is defined as the differential pair, CK and CK#. The positive Clock edge is
defined by the crosspoint of a rising CK and a falling CK#. The negative Clock edge is
defined by the crosspoint of a falling CK and a rising CK#.
CKE InputClock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and
therefore device input buffers and output drivers. Power savings modes are entered and
exited through CKE transitions.
CKE is considered part of the command code. See Command Truth Ta ble for command
code descriptions.
CKE is sampled at the positive Clock edge.
CS# Input Chip Select: CS# is considered part of the command code. See Command Truth Ta ble
for command code descriptions.
CS# is sampled at the positive Clock edge.
CA0 - CA9Input DDR Command/Address Inputs:Uni-directional command/address bus inputs.
CA is considered part of the command code. See Command Truth Ta ble for command
code descriptions.
DQ0 - DQ15
(x16)
DQ0 - DQ31
(x32)
I/OData Inputs/Output: Bi-directional data bus
DQS0,
DQS0#,
DQS1,
DQS1#
(x16)
DQS0 -
DQS3,
DQS0# -
DQS3#
(x32)
I/O Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for
read and write data) and differential (DQS and DQS#). It is output with read data and
input with write data. DQS is edge-aligned to read data and centered with write data.
For x16, DQS0 and DQS0# correspond to the data on DQ0 - DQ7; DQS1 and
DQS1# to the data on DQ8 - DQ15.
For x32 DQS0 and DQS0# correspond to the data on DQ0 - DQ7, DQS1 and
DQS1# to the data on DQ8 - DQ15, DQS2 and DQS2# to the data on DQ16 - DQ23,
DQS3 and DQS3# to the data on DQ24 - DQ31.
DM0-DM1
(x16)
DM0 - DM3
(x32)
Input Input Data Mask: For LPDDR2 devices that do not support the DNV feature, DM is the
input mask signal for write data. Input data is masked when DM is sampled HIGH
coincident with that input data during a Write access. DM is sampled on both edges of
DQS. Although DM is for input only, the DM loading shall match the DQ and DQS (or
DQS#).
DM0 is the input data mask signal for the data on DQ0-7.
For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15.
For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is
the input data mask signal for the data on DQ24-31.
6 Integrated Silicon Solution, Inc. — www.issi.com
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IS43/46LD16128B
IS43/46LD32640B
NOTE 1 Data includes DQ and DM.
VDD1SupplyCore Power Supply 1
VDD2SupplyCore Power Supply 2
VDDCA SupplyInput Receiver Power Supply: Power supply for CA0-9, CKE, CS#, CK, and CK#
input buffers.
VDDQSupply I/O Power Supply: Power supply for Data input/output buffers.
VREF(CA)SupplyReference Voltage for CA Command and Control Input Receiver: Reference voltage
for all CA0-9, CKE, CS#, CK, and CK# input buffers.
VREF(DQ)SupplyReference Voltage for DQ Input Receiver: Reference voltage for all Data input buffers.
VSS SupplyGround
VSSCA SupplyGround for Input Receivers
VSSQ Supply I/O Ground
ZQ I/O Reference Pin for Output Drive Strength Calibration
Name Type Description
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FUNCTIONAL BLOCK DIAGRAM
Bank 5
Bank 6
Bank 7
Bank 4
Bank 7
Bank 4
Bank 5
Bank 6
xRow-
address
MUX
Control
logic
Column-
address
counter/
latch
Mode
registers
Column
decoder
Bank 0
Memory array
Bank 0
row-
address
latch
and
decoder
Sense amplier
Bank
control
logic
Bank 1
Bank 2
Bank 3
x
y - 1
3
3
Refresh
counter
n
nn
4n
4n
4n
CK out
DATA
DQS, DQS#
CK, CK#
COL0
COL0
CK in
MUX
DQS
generator
n
n
n
n
n
DQS, DQS#
Read
latch
WRITE
FIFO
and
drivers
Data
n
n
n
n
4n
4
4
4
4
Mask
4
4
4
4
4
8
n
n
1
Bank 1
Bank 2
Bank 3
Input
registers
DM
DQ0–DQn-1
CA0
CA1
CK
CS#
CA2
CK#
Command / Address
Multiplex and Decode
CKE
CA3
CA4
CA5
CA6
CA7
CA8
CA9
I/O gating
DM mask logic
DRVRS
RCVRS
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IS43/46LD32640B
SIMPLIFIED STATE DIAGRAM
Power
applied
Resetting Self
refreshing
Refreshing
Power-on
Resetting
MR reading
Idle
MR reading
Active
MR reading
Active
power-down
Idle
power-down
Deep
power-down
Idle 1
Active BST
BST
PR
Precharging
MR writing
Writing Reading
Reading
with
auto precharge
Writing
with
auto precharge
Resetting
power-down
RESET
MRR
RESET
MRR
MRW
MRRWR
RD
PD
PDX
PDX
PD
PDX
PD
DPDX
DPD
SREF
REF
WRA
WRA
RDA
RDA
SREFX
RDWR
Automatic sequence
Command sequence
PR, PRA
ACT
Abbreviation Function Abbreviation Function Abbreviation Function
ACT Active PD Enter Power Down REF Refresh
RD(A) Read (w/ Autopre-
charge)
PDX Exit Power Down SREF Enter self refresh
WR(A) Write (w/ Autopre-
charge)
DPD Enter Deep Power Down SREFX Exit self refresh
PR(A) Precharge (All) DPDX Exit Deep Power Down
MRW Mode Register Write BST Burst Terminate
MRR Mode Register Read RESET Reset is achieved through MRW command
Note: For LPDDR2-S4 SDRAM in the idle state, all banks are precharged.
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LPDDR2-S4 is a high-speed SDRAM device internally congured as an 8-Bank memory. This device contains
2,147,483,648 bits (2 Gigabit)
All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number
of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each
command uses one clock cycle, during which command information is transferred on both the positive and negative
edge of the clock.
This LPDDR2-S4 device also uses a double data rate architecture on the DQ pins to achieve high speed operation.
The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two
data bits per DQ every clock cycle at the I/O pins. A single read or write access for the memory device effectively
consists of a single 4n-bit wide, one clock cycle data transfer at the internal SDRAM core and four corresponding n-
bit wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the LPDDR2 are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an Activate command, which is then followed by a Read or Write command.
The address and BA bits registered coincident with the Activate command are used to select the row and the Bank
to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank
and the starting column location for the burst access.
Prior to normal operation, the LPDDR2 must be initialized. The following section provides detailed information cover-
ing device initialization, register denition, command description and device operation.
FUNCTIONAL DESCRIPTION
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IS43/46LD32640B
POWER-UP AND INITIALIZATION
DDR2 SDRAMs must be powered up and initialized in a predened manner. Operational procedures other than those
specied may result in undened operation.
The following sequence is required for Power-up and Initialization.
1. Voltage ramp up sequence is required :
A. While applying power, attempt to maintain CKE below 0.2 x VDDCA and all other inputs must be between VILmin
and VIHmax. The device outputs remain at High-Z while CKE is held LOW. The voltage ramp time tINIT0 ( Tb-Ta)
must be no greater than 20 ms from Tb which is point for all supply and reference voltage are within their dened
operating ranges , to Ta which is point for any power supply rst reaches 300mV.
B. The following conditions apply for voltage ramp after Ta is reached,
− VDD1 must be greater than VDD2-200mV AND
− VDD1 and VDD2 must be greater than VDDCA-200mV AND
− VDD1 and VDD2 must be greater than VDDQ-200mV AND
− VREF must always be less than all other supply voltages
− The voltage difference between any of VSS, VSSQ, and VSSCA pins must not exceed 100mV
2. Start clock and maintain stable condition.
Beginning at Tb, CKE must remain LOW for at least tINIT1 = 100 ns, after which CKE can be asserted HIGH. The
clock must be stable at least tINIT2 = 5 × tCK prior to the rst CKE LOW-to-HIGH transition (Tc). CKE, /CS, and CA
inputs must observe setup and hold requirements (tIS, tIH) with respect to the rst rising clock edge (and to subse-
quent falling and rising edges).
Once the ramping of the supply voltages is complete ( Tb), CKE must be maintained LOW. DQ, DM, DQS and DQS#
voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latchup. CK, /CK, /CS, and CA input
levels must be between VSSCA and VDDCA during voltage ramp to avoid latch-up
If any Mode Register Read ( MRRs ) are issued, the clock period must be within the range dened for tCKb (18ns to
100ns). Mode Register Write (MRWs) can be issued at normal clock frequencies as long as all AC timings are met.
Some AC parameters could have relaxed timings before the system is appropriately congured. While keeping CKE
HIGH, NOP commands must be issued for at least tINIT3 = 200μs (Td).
3. RESET Command
After tINIT3 is satised, the MRW RESET command must be issued (Td).
An optional PRECHARGE ALL command can be issued prior to the MRW RESET command. Wait at least tINIT4
while keeping CKE asserted and issuing NOP commands
4. Mode Register Reads and Device Auto Initialization (DAI) Polling:
After tINIT4 is satised (Te), only MRR commands and power-down entry/exit commands are supported. After Te,
CKE can go LOW in alignment with power-down entry and exit specications.
Use the MRR command to poll the DAI bit and report when device auto initialization is complete; otherwise, the con-
troller must wait a minimum of tINIT5, or until the DAI bit is set before proceeding.
As the memory output buffers are not properly congured by Te, some AC parameters must have relaxed timings
before the system is appropriately congured. After the DAI bit (MR0, DAI) is set to zero by the memory device (DAI
complete), the device is in the idle state (Tf ). DAI status can be determined by issuing the MRR command to MR0.
The device sets the DAI bit no later than tINIT5 after the RESET command. The controller must wait at least tINIT5 or
until the DAI bit is set before proceeding
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5. ZQ Calibration
After tINIT5 (Tf ), the MRR initialization calibration (ZQ_CAL) command can be issued to the memory (MR10).
This command is used to calibrate output impedance over process, voltage, and temperature. In systems where more
than one LPDDR2 device exists on the same bus, the controller must not overlap MRR ZQ_CAL commands. The
device is ready for normal operation after tZQINIT.
6. Normal Operation
After tZQINIT (Tg), MRW commands must be used to properly congure the memory . Specically, MR1, MR2, and
MR3 must be set to congure the memory for the target frequency and memory conguration
After the initialization sequence is complete, the device is ready for any valid command. After Tg, the clock frequency
can be changed using the procedure described in Input Clock Frequency Changes and Clock Stop Events‖.
INITIALIZATION TIMING
Symbol Parameter Value Unit
min max
tINIT0 Maximum Power Ramp Time - 20 ms
tINIT1 Minimum CKE low time after completion of power ramp 100 - ns
tINIT2 Minimum stable clock before rst CKE high 5 - tCK
tINIT3 Minimum idle time after rst CKE assertion 200 - us
tINIT4 Minimum idle time after Reset command, this time will be about 2 x
tRFCab + tRPab
1 - us
tINIT5 Maximum duration of Device Auto-Initialization - 10 us
tCKb Clock cycle time during boot 18 100 ns
tZQINIT ZQ initial calibration 1 - us
Figure - Power Ramp and Initialization Sequence
Ta Tb Tc Td Te Tf Tg
RESET MRR MRW
ZQ_CALValid
CK/CK#
Supplies
CKE
CA
RTT
DQ
tINIT0
tINIT1 tINIT3
tINIT4 tZQINIT
tINIT5
tISCKE
tINIT2
Initialization After RESET (without voltage ramp):
If the RESET command is issued before or after the power-up initialization sequence, the re-initialization procedure
must begin at Td
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Power-Off Sequence
Use the following sequence to power off the device. Unless specied otherwise, this procedure is mandatory and
applies to S4 devices.
While powering off, CKE must be held LOW (≤ 0.2 × VDDCA); all other inputs must be between VILmin and VIHmax.
The device outputs remain at High-Z while CKE is held LOW.
DQ, DM, DQS, and /DQS voltage levels must be between VSSQ and VDDQ during the power-off sequence to avoid
latch-up. CK, /CK, /CS, and CA input levels must be between VSSCA and VDDCA during the power-off sequence to
avoid latch-up.
Tx is the point where any power supply drops below the minimum value specied in the DC operating condition table.
Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off
Required Power Supply Conditions Between Tx and Tz:
• VDD1 must be greater than VDD2 - 200mV
• VDD1 must be greater than VDDCA - 200mV
• VDD1 must be greater than VDDQ - 200mV
• VREF must always be less than all other supply voltages
The voltage difference between VSS, VSSQ, and VSSCA must not exceed 100mV.
For supply and reference voltage operating conditions, see Recommended DC Operating Conditions table.
Uncontrolled Power-Off Sequence
When an uncontrolled power-off occurs, the following conditions must be met:
1. At Tx, when the power supply drops below the minimum values specied, all power supplies must be turned off and
all power-supply current capacity must be at zero, except for any static charge remaining in the system.
2. After Tz , the device must power off. The time between Tx and Tz must not exceed 20ms. During this period, the
relative voltage between power supplies is uncontrolled. VDD1 and VDD2 must decrease with a slope lower than 0.5
V/μs between Tx and Tz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device
Mode Register Denition
LPDDR2 devices contain a set of mode registers used for programming device operating parameters, reading device
information and status, and for initiating special operations such as DQ calibration, ZQ calibration, and device reset.
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Mode Register Assignment
The MRR command is used to read from a register. The MRW command is used to write to a register.
Mode Register Assignment
MR# MA <7:0> Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
0 00H Device Info. R (RFU) DI DAI
1 01H Device Feature1 W nWR (for AP) WC BT BL
2 02H Device Feature2 W (RFU) RL & WL
3 03H I/O Config-1 W (RFU) DS
4 04H Refresh Rate R TUF (RFU) Refresh Rate
5 05H Basic Config-1 R LPDDR2 Manufacturer ID
6 06H Basic Config-2 R Revision ID1
7 07H Basic Config-3 R Revision ID2
8 08H Basic Config-4 R I/O width Density Type
9 09H Test Mode W Vendor-Specific Test Mode
10 0AH IO Calibration W Calibration Code
11~15 0BH~0FH (reserved) (RFU)
Mode Register Assignment
MR# MA <7:0> Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
16 10H PASR_BANK W Bank Mask
17 11H PASR_Seg W Segment Mask
18-19 12H-13H (Reserved) (RFU)
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Mode Register Assignment
MR# MA <7:0> Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
20-31 18H-1FH Reserved
Mode Register Assignment (Reset Command & RFU part)
MR# MA <7:0> Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
32 20H DQ calibration pattern A R See “Data Calibration Pattern Description”
33-39 21H-27H (Do Not Use)
40 28H DQ calibration pattern B R See “Data Calibration Pattern Description”
41-47 29H-2FH (Do Not Use)
48-62 30H-3EH (Reserved) (RFU)
63 3FH Reset W X
64-126 40H-7EH (Reserved) (RFU)
127 7FH (Do Not Use)
128-190 80H-BEH (Reserved for Vendor Use) (RFU)
191 BFH (Do Not Use)
192-254 C0H-FEH (Reserved for Vendor Use) (RFU)
255 FFH (Do Not Use)
Notes:
1. RFU bits shall be set to ‘0’ during Mode Register writes.
2.RFU bits shall be read as ‘0’ during Mode Register reads.
3.All Mode Registers that are specied as RFU or write-only shall return undened data when read and DQS shall be toggled.
4.All Mode Registers that are specied as RFU shall not be written.
5.See Vendor Device Datasheets for details on Vendor Specic Mode Registers.
6.Writes to read-only registers shall have no impact on the functionality of the device.
MR0_Device Information (MA<7:0> = 00H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
(RFU) DI DAI
OP1 DI (Device Information) Read-only
0B: SDRAM
1B: Do Not Use
OP0
DAI (Device Auto-Initialization
Status)
Read-only
0B: DAI complete
1B: DAI still in progress
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MR1_Device Feature 1 (MA<7:0> = 01H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
nWR (for AP) WC BT BL
OP<2:0> BL (Burst Length) Write-only
010B: BL4 (default)
011B: BL8
100B: BL16
All others: reserved
OP3 BT*1 (Burst Type) Write-only
0B: Sequential (default)
1B: Interleaved
OP4 WC (Wrap) Write-only
0B: Wrap (default)
1B: No wrap (allowed for SDRAM BL4 only)
OP<7:5> nWR*2 Write-only
001B: nWR=3 (default)
010B: nWR=4
011B: nWR=5
100B: nWR=6
101B: nWR=7
110B: nWR=8
All others: reserved
Burst Sequence by BL, BT, and WC
C3 C2 C1 C0 WC BT BL
Burst Cycle Number and Burst Address Sequence
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
x x 0B 0B
wrap any
4
0 1 2 3
x x 1B 0B 2 3 0 1
x x x 0B
nw any
y y+1 y+2 y+3
Notes:
1. BL16, interleaved is not an ofcial combination to be supported.
2. Programmed value in nWR register is the number of clock cycles which determines when to start internal
precharge operation for a write burst with AP enabled. It is determined by RU(tWR/tCK)
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C3 C2 C1 C0 WC BT BL
Burst Cycle Number and Burst Address Sequence
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
x 0B 0B 0B
wrap
seq
8
0 1 2 3 4 5 6 7
x 0B 1B 0B 2 3 4 5 6 7 0 1
x 1B 0B 0B 4 5 6 7 0 1 2 3
x 1B 1B 0B 6 7 0 1 2 3 4 5
x 0B 0B 0B
int
0 1 2 3 4 5 6 7
x 0B 1B 0B 2 3 0 1 6 7 4 5
x 1B 0B 0B 4 5 6 7 0 1 2 3
x 1B 1B 0B 6 7 4 5 2 3 0 1
x x x 0B nw any illegal (not allowed)
0B 0B 0B 0B
wrap
seq
16
0 1 2 3 4 5 6 7 8 9 A B C D E F
0B 0B 1B 0B 2 3 4 5 6 7 8 9 A B C D E F 0 1
0B 1B 0B 0B 4 5 6 7 8 9 A B C D E F 0 1 2 3
0B 1B 1B 0B 6 7 8 9 A B C D E F 0 1 2 3 4 5
1B 0B 0B 0B 8 9 A B C D E F 0 1 2 3 4 5 6 7
1B 0B 1B 0B A B C D E F 0 1 2 3 4 5 6 7 8 9
1B 1B 0B 0B C D E F 0 1 2 3 4 5 6 7 8 9 A B
1B 1B 1B 0B E F 0 1 2 3 4 5 6 7 8 9 A B C D
x x x 0B int illegal (not allowed)
x x x 0B nw any illegal (not allowed)
Non-Wrap Restrictions
Width 64Mb 128Mb/256Mb 512Mb/1Gb/2Gb 4Gb/8Gb
Cannot cross full page boundary
X16 FE, FF, 00, 01 1FE, 1FF, 000, 001 3FE, 3FF, 000, 001 7FE, 7FF, 000, 001
X32 7E, 7F, 00, 01 FE, FF, 00, 01 1FE, 1FF, 000, 001 3FE, 3FF, 000, 001
Cannot cross sub-page boundary
X16 7E, 7F, 80, 81 0FE, 0FF, 100, 101 1FE, 1FF, 200, 201 3FE, 3FF, 400, 401
X32 none none None none
.
Notes:
1. C0 input is not present on CA bus. It is implied zero.
2. For BL=4, the burst address represents C1~C0.
3. For BL=8, the burst address represents C2~C0.
4. For BL=16, the burst address represents C3~C0.
5. For no-wrap, BL4, the burst must not cross the page boundary or the sub-page boundary.The variabley can start at any ad-
dress with C0 equal to 0, but must not start at any address shown below
Note: Non-wrap BL=4 data orders shown are prohibited.
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MR2_Device Feature 2 (MA<7:0> = 02H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
(RFU) RL & WL
OP<3:0>
RL & WL (Read Latency & Write
Latency)
Write-only
0001B: RL3 / WL1 (default)
0010B: RL4 / WL2
0011B: RL5 / WL2
0100B: RL6 / WL3
0101B: RL7 / WL4
0110B: RL8 / WL4
All others: reserved
MR3_I/O Configuration 1 (MA<7:0> = 03H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
(RFU) DS
OP<3:0> DS (Drive Strength) Write-only
0000B: reserved
0001B: 34.3 ohm typical
0010B: 40.0 ohm typical (default)
0011B: 48.0 ohm typical
0100B: 60.0 ohm typical
0101B: reserved
0110B
B
: 80.0 ohm typical
All others: reserved
0111 : 120.0 ohm typical
MR4_Device Temperature (MA<7:0> = 04H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
TUF (RFU) SDRAM Refresh Rate
OP<2:0> SDRAM Refresh Rate Read-only
000B: Reserved
001B: Reserved
010B: 2 x tREFI
011B: 1 x tREFI
100B: Reserved
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Notes:
1. A Mode Register Read from MR4 will reset OP7 to “0”.
2. OP7 is reset to “0” at power-up.
3. If OP2 equals “1”, the device temperature is greater than 85C.
4. OP7 is set to “1”, if OP2~OP0 has changed at any time since the last read of MR4.
5. LPDDR2 might not operate properly when OP<2:0> = 000B or 111B.
6. For specied operating temperature range and maximum operating temperature.
7. LPDDR2 devices must be derated by adding 1.875ns to the following core timing parameters: tRCD, tRC, tRAS, tRP,
and tRRD. The tDQSCK parameter must be derated Prevailing clock frequency specications and related setup and
hold timings remain unchanged.
8. The recommended frequency for reading MR4 is provided in “Temperature Sensor”
OP7 TUF (Temperature Update Flag) Read-only
MR5_Basic Configuration 1 (MA<7:0> = 05H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
LPDDR2 Manufacturer ID
OP<7:0>
Manufacturer ID
Read-only
1111 1101B: ISSI
All Others : Reserved
MR6_Basic Configuration 2 (MA<7:0> = 06H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Revision ID1
OP<7:0> Revision ID1 Read-only 00000000B: A-version
MR7_Basic Configuration 3 (MA<7:0> = 07H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Revision ID2
OP<7:0> Revision ID2 Read-only 00000000B: A-version
101B: 0.25 x tREFI, set to 85°C, do not derate
SDRAM timing
110B: 0.25 x tREFI, set to 95°C, derate SDRAM
AC timing
111B: temp > 105C, set to 105°C, stall
0B: OP <2:0> value has not changed since last read of MR4.
1B: OP <2:0> value has changed since last read of MR4.
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OP7 OP6 OP5 OP4O OP3 OP2 OP1 OP0
I/O width Density Type
OP7 OP6 OP5 OP4O OP3 OP2 OP1 OP0
Vendor-specic Test Mode
OP<1:0> Type Read-only
00B:S4 SDRAM
01B: Reserved
10B: Reserved
11B: Reserved
OP<5:0> Density Read-only
0000B: 64Mb (Reserved)
0001B: 128Mb (Reserved)
0010B: 256Mb (Reserved)
0011B: 512Mb (Reserved)
0100B: 1Gb (Reserved)
0101B: 2Gb
0110 B: 4Gb (Reserved)
0111B: 8Gb (Reserved)
1000B: 16Gb (Reserved)
1001B: 32Gb (Reserved)
All others: Reserved
OP<7:6> I/O width Read-only
00B: x32
01B: x16
10B: x8 (Reserved)
11B: not used
MR8_Basic Conguration 4 (MA<7:0> =08H):
MR9_Test Mode (MA<7:0> =09H):
OP7 TUF (Temperature Update Flag) Read-only
MR5_Basic Configuration 1 (MA<7:0> = 05H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
LPDDR2 Manufacturer ID
OP<7:0>
Manufacturer ID
Read-only
1111 1101B: ISSI
All Others : Reserved
MR6_Basic Configuration 2 (MA<7:0> = 06H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Revision ID1
OP<7:0> Revision ID1 Read-only 00000000B: A-version
MR7_Basic Configuration 3 (MA<7:0> = 07H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Revision ID2
OP<7:0> Revision ID2 Read-only 00000000B: A-version
101B: 0.25 x tREFI, set to 85°C, do not derate
SDRAM timing
110B: 0.25 x tREFI, set to 95°C, derate SDRAM
AC timing
111B: temp > 105C, set to 105°C, stall
0B: OP <2:0> value has not changed since last read of MR4.
1B: OP <2:0> value has changed since last read of MR4.
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MR10_Calibration (MA<7:0> = 0AH):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Calibration Code
OP<7:0> Calibration Code Write-only
0xFF: Calibration command after initialization
0xAB: Long calibration
0x56: Short calibration
0xC3: ZQ Reset
All others: Reserved
MR11:15_(Reserved) (MA<7:0> = 0BH- 0FH):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU
Notes:
1. Host processor shall not write MR10 with “Reserved” values.
2. LPDDR2 devices shall ignore calibration command, when a “Reserved” values is written into MR10.
3. See AC timing table for the calibration latency.
4. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see “MRW ZQ Calibration Command”) or
default calibration (through the ZQ RESET command) is supported. If ZQ is connected to VDDCA, the device operates
with default calibration,and ZQ calibration commands are ignored. In both cases, the ZQ connection must not change after
power is supplied to the device.
5. Devices that do not support calibration ignore the ZQ calibration command.
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MR16_PASR_Bank Mask (MA<7:0> = 010H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Bank Mask (8-Bank)-
OP<7:0> Bank Mask Code Write-only
0B: refresh enable to the bank (=unmasked, default)
1B: refresh blocked (=masked)
OP Bank Mask 8 Bank
0 XXXXXXX1 Bank 0
1 XXXXXX1X Bank 1
2 XXXXX1XX Bank 2
3 XXXX1XXX Bank 3
4 XXX1XXXX Bank 4
5 XX1XXXXX Bank 5
6 X1XXXXXX Bank 6
7 1XXXXXXX Bank 7
MR17_PASR_Segment Mask (MA<7:0> = 011H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Segment Mask
OP<7:0> Segment Mask Code Write-only
0B: refresh enable to the segment(=unmasked, default)
1B: refresh blocked (=masked)
Segment OP Bank Mask
2Gb, 4Gb
R13:11
0 0 XXXXXXX1 000B
1 1 XXXXXX1X 001B
2 2 XXXXX1XX 010B
3 3 XXXX1XXX 011B
4 4 XXX1XXXX 100B
5 5 XX1XXXXX 101B
6 6 X1XXXXXX 110B
7 7 1XXXXXXX 111B
Note: This table indicates the range of row addresses in each masked segment. X is don’t care for a particular segment.
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MR18:19_(Reserved) (MA<7:0> = 012H- 013H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU
MR20:31_(Do Not Use) (MA<7:0> = 014H- 01FH):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Do Not Use
MR32_(Calibration Pattern “A”) (MA<7:0> = 020H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Calibration Pattern “A”
MR33:39_(Do Not Use) (MA<7:0> = 021H- 027H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Do Not Use
MR40_(Calibration Pattern “B”) (MA<7:0> = 028H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Calibration Pattern “B”
MR41:47_(Do Not Use) (MA<7:0> = 029H- 02FH):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Do Not Use
DQ outputs pattern A1001
Bit Time 0 Bit Time 1 Bit Time 2 Bit Time 3
DQ outputs pattern B100 1
Bit Time 0 Bit Time 1 Bit Time 2 Bit Time 3
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MR48:62_(Reserved) (MA<7:0> = 030H- 03EH):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU
MR63_Reset (MA<7:0> = 03FH): MRW only
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
X
MR64:126_(Reserved) (MA<7:0> = 040H- 07EH):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU
MR127_(Do Not Use) (MA<7:0> = 07FH):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Do Not Use
MR128:190_(Reserved for Vendor Use) (MA<7:0> = 080H- 0BEH):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU
MR191_(Do Not Use) (MA<7:0> = 0BFH):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Do Not Use
Note: For additional information on MRW RESET, see “Mode Register Write Command” on Timing Spec.
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MR192:254_(Reserved for Vendor Use) (MA<7:0> = 0C0H- 0FEH):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU
MR255_(Do Not Use) (MA<7:0> = 0FFH):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Do Not Use
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Table 49: Command Truth Table
Notes 1–11 apply to all parameters conditions
Command
Command Pins CA Pins
CK
Edge
CKE
CS# CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9CK( n-1) CK( n)
MRW HHLL LLLMA0 MA1 MA2 MA3 MA4 MA5
HHX MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7
MRR HHLL LLH MA0 MA1 MA2 MA3 MA4 MA5
HHX MA6 MA7 X
REFRESH
(per bank)
HHLL LHL X
HHX X
REFRESH
(all banks)
HHLL LHH X
HHX X
Enter self
refresh
HLLL LH X
XLX X
ACTIVATE
(bank)
HHLL HR8R9 R10 R11 R12 BA0 BA1 BA2
HHXR0R1R2R3R4R5R6R7 R13 R14
WRITE (bank) HHLH LLRFU RFU C1 C2 BA0 BA1 BA2
HHXAPC3C4C5C6C7C8C9 C10 C11
READ (bank) HHLH LHRFU RFU C1 C2 BA0 BA1 BA2
HHXAPC3C4C5C6C7C8C9 C10 C11
PRECHARGE
(bank)
HHLH HLHAB X X BA0 BA1 BA2
HHX X
BST HHLH HLL X
HHX X
Enter DPD HLLH HL X
XLX X
NOP HHLH HH X
HHX X
Maintain PD,
SREF, DPD,
(NOP)
LLLH HH X
LLX X
Truth Tables
Truth tables provide complementary information to the state diagram. They also clarify device
behavior and applicable restrictions when considering the actual state of the banks.
Unspecied operations and timings are illegal. To ensure proper operation after an illegal event,
the device must be powered down and then restarted using the specied initialization sequence
before normal operation can continue.
Command Truth Table
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Command
Command Pins CA Pins
CK
Edge
CKE
CS# CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9CK( n-1) CK( n)
NOP HHHX
HHX X
Maintain PD,
SREF, DPD,
(NOP)
LLHX
LLX X
Enter power-
down
HLH X
XLX X
Exit PD, SREF,
DPD
LHH X
XHX X
Note:
1. All commands are dened by the current state of CS#, CA0, CA1, CA2, CA3, and CKE at
the rising edge of the clock.
2. Bank addresses (BA) determine which bank will be operated upon.
3.AP HIGH during a READ or WRITE command indicates that an auto precharge will occur
to the bank associated with the READ or WRITE command.
4. X indicates a “Don’t Care” state, with a dened logic level, either HIGH (H) or LOW (L).
5. Self refresh exit and DPD exit are asynchronous.
6. VREF must be between 0 and VDDQ during self refresh and DPD operation.
7. CAxr refers to command/address bit “x” on the rising edge of clock.
8. CAxf refers to command/address bit “x” on the falling edge of clock.
9. CS# and CKE are sampled on the rising edge of the clock.
10. Per-bank refresh is only supported in devices with eight banks.
11. The least-signicant column address C0 is not transmitted on the CA bus, and is inferred
to be zero
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CKE Truth Table
Device
Current State
*3
CKE
n-1
*1
CKE
n
*1
CS_n
*
2
Notes
LLx
LHH6,9
LLx
LHH6,9
LLx
LHH6,9,12
LLx
LHH 8
LLx
LHH7,10
Bank(s) Active HLH
HLH
HLL
HLL
Resetting HLH
Other states HH
Device Next State
Idle
Power Down
x
NOP
Maintain Active Power Down
Exit Active Power Down
Active Power Down
Active
Idle Power Down
Idle
Resetting
Power Down
Active
Power Down
Command n
*4
Operation n
*4
xMaintain Idle Power Down
xMaintain Resertting Power Down
Maintain Deep Power Down Deep Power Down
xMaintain Self Refresh Self Refresh
Self Refresh NOPExit Self Refresh Idle
NOPEnter Resetting Power Down Resetting Power Down
Refer to the Command Truth Table
Deep
Power Down NOPExit Deep Power Down Power On
x
Resetting Power Down
NOPExit Idle Power Down
NOPExit Resetting Power Down Idle or Resetting
NOPEnter Active Power Down Active Power Down
Enter
Self-Refresh Enter Deep Power Down Deep Power Down
All Banks Idle
NOPEnter Idle Power Down Idle Power Down
Enter
Self-Refresh Enter Self Refresh Self Refresh
Notes:
1.“CKEn” is the logic state of CKE at clock edge n; “CKEn-1” was the logic state of CKE at previous clock edge.
2. “CS_n” is the logic state of CS_n at the clock rising edge n;
3. “Current state” is the state of the LPDDR2 device immediately prior to clock edge n.
4. “Command n” is the command registered at clock edge N, and “Operation n” is a result of “Command n”.
5. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
6. Power Down exit time (tXP) should elapse before a command other than NOP is issued.
7. Self-Refresh exit time (tXSR) should elapse before a command other than NOP is issued.
8. The Deep Power- Down exit procedure must be followed as discussed in the DPD section of the Functional Description.
9. The clock must toggle at least once during the tXP period.
10. The clock must toggle at least once during the tXSR period.
11. “x” means “Don’t care”.
12. Upon exiting Resetting Power Down, the device will return to the idle state if tINIT5 has expired.
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Current State Bank n – Command to Bank n Truth Table
Notes:
1. Values in this table apply when both CKEn -1 and CKEn are HIGH, and after tXSR or tXP has been met, if the previous state
was power-down.
2. All states and sequences not shown are illegal or reserved.
3. Current state denitions:
Idle: The bank or banks have been precharged, and tRP has been met.
Active: A row in the bank has been activated, and tRCD has been met. No data bursts or accesses and no register acesses are in
progress.
Reading: A READ burst has been initiated with auto precharge disabled and has not yet terminated or been terminated.
Writing: A WRITE burst has been initiated with auto precharge disabled and has not yet terminated or been terminated.
4. The states listed below must not be interrupted by a command issued to the same bank.
NOP commands or supported commands to the other bank must be issued on any clock edge occurring during these states. Sup-
ported commands to the other banks are determined by that bank’s current state, and the denitions given in Current State Bank
n to Command to Bank m Truth Table.
Precharge: Starts with registration of a PRECHARGE command and ends when tRP is met. After tRP is met, the bank is in the
idle state.
Row activate: Starts with registration of an ACTIVATE command and ends when tRCD is met. After tRCD is met, the bank is in
the active state.
READ with AP enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP is met.
After tRP is met, the bank is in the idle state.
WRITE with AP enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP is met.
After tRP is met, the bank is in the idle state.
5. The states listed below must not be interrupted by any executable command. NOP commands must be applied to each rising
clock edge during these states.
Current State Bank n – Command to Bank n
Current State Notes
Any
6
7
7
7,8
9,15
9
10,11
10,11,12
13
10,11
10,11,14
13
Power On 7,9
ResettingMRRRead value from Mode Register Resetting MR Reading
Active
ResetBegin Device Auto-initializationResetting
Reading
Idle
Row Active
Reading
Writing
WriteSelect column, and start new write burstWriting
BST Write burst terminate
MRW
MRR
Reset
Precharge
ACTIVATE
Refresh (Per Bank
)R
efreshing (Per Bank)
Refresh (All Bank)
Read value from Mode Register Active / MR Reading
Deactivate row in bank or banksPrecharging
MRR
Precharge
Read
Select column, and start write burstWriting
Select column, and start new read burstReading
Refreshing (AllBank)
Begin to refresh
Load value from Mode Register MR Writing
Select column, and start write burstWriting
Active
Write
BST Read burst terminate
Read Select column, and start read burst
Begin Device Auto-initializationResetting
Read value from Mode Register Idle / MR Reading
Deactivate row in bank or banksPrecharging
Select column, and start read burstReadingRead
Write
Operation
Select and activate row
Begin to refresh
Command
NOP
Next State
Continue previous operationCurrent State
Active
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Refresh (per bank): Starts with registration of a REFRESH (per bank) command and ends when tRFCpb is met. After tRFCpb is
met, the bank is in the idle state.
Refresh (all banks): Starts with registration of a REFRESH (all banks) command and ends when tRFCab is met. After tRFCab is
met,
the device is in the all banks idle state.
Idle MR reading: Starts with registration of the MRR command and ends when tMRR is met. After tMRR is met, the device is in
the all
banks idle state.
Resetting MR reading: Starts with registration of the MRR command and ends when tMRR is met. After tMRR is met, the device
is in
the all banks idle state.
Active MR reading: Starts with registration of the MRR command and ends when tMRR is met. After tMRR is met, the bank is in
the active state.
MR writing: Starts with registration of the MRW command and ends when tMRW is met. After tMRW is met, the device is in the all
banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. After tRP is met, the device is in the all banks idle state.
6. Bank-specic; requires that the bank is idle and no bursts are in progress.
7. Not bank-specic; requires that all banks are idle and no bursts are in progress.
8. Not bank-specic.
9. This command may or may not be bank specic. If all banks are being precharged, they must be in a valid state for precharg-
ing.
10. If a PRECHARGE command is issued to a bank in the idle state, tRP still applies.
11. A command other than NOP should not be issued to the same bank while a burst READ or burst WRITE with auto precharge
is enabled.
12. The new READ or WRITE command could be auto precharge enabled or auto precharge disabled.
13. A WRITE command can be issued after the completion of the READ burst; otherwise, a BST must be issued to end the
READ prior to asserting a WRITE command.
14. Not bank-specic. The BST command affects the most recent READ/WRITE burst started by the most recent READ/WRITE
command, regardless of bank.
15. A READ command can be issued after completion of the WRITE burst; otherwise, a BST must be used to end the WRITE
prior to asserting another READ command.
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Current State Bank n to Command to Bank m Truth Table
Current State
of Bank nCommand to Bank mOperation Next State for Bank mNotes
Any NOP Continue previous operation Current state of bank m
Idle Any Any command supported to bank m
–7
Current State
of Bank nCommand to Bank mOperation Next State for Bank mNotes
Row activating,
active, or pre-
charging
ACTIVATE Select and activate row in bank mActive 8
READ Select column and start READ burst
from bank m
Reading 9
WRITE Select column and start WRITE burst to
bank m
Writing 9
PRECHARGE Deactivate row(s) in bank or banks Precharging 10
MRR READ value from mode register Idle MR reading or active
MR reading
11, 12, 13
BST READ or WRITE burst terminates an on-
going READ/WRITE from/to bank m
Active 7
Reading
(auto precharge
disabled)
READ Select column and start READ burst
from bank m
Reading 9
WRITE Select column and start WRITE burst to
bank m
Writing 9, 14
ACTIVATE Select and activate row in bank mActive
PRECHARGE Deactivate row(s) in bank or banks Precharging 10
Writing
(auto precharge
disabled)
READ Select column and start READ burst
from bank m
Reading 9, 15
WRITE Select column and start WRITE burst to
bank m
Writing 9
ACTIVATE Select and activate row in bank mActive
PRECHARGE Deactivate row(s) in bank or banks Precharging 10
Reading with
auto precharge
READ Select column and start READ burst
from bank m
Reading 9, 16
WRITE Select column and start WRITE burst to
bank m
Writing 9, 14, 16
ACTIVATE Select and activate row in bank mActive
PRECHARGE Deactivate row(s) in bank or banks Precharging 10
Writing with
auto precharge
READ Select column and start READ burst
from bank m
Reading 9, 15, 16
WRITE Select column and start WRITE burst to
bank m
Writing 9, 16
ACTIVATE Select and activate row in bank mActive
PRECHARGE Deactivate row(s) in bank or banks Precharging 10
Power-on MRW RESET Begin device auto initialization Resetting 17, 18
Resetting MRR Read value from mode register Resetting MR reading
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Notes:
1. This table applies when: the previous state was self refresh or power-down; after tXSR z or tXP has been met; and both
CKEn -1 and CKEn are HIGH.
2. All states and sequences not shown are illegal or reserved.
3. Current state denitions:
Idle: The bank has been precharged and tRP has been met.
Active: A row in the bank has been activated, tRCD has been met, no data bursts or accesses and no register accesses are in
progress.
Read: A READ burst has been initiated with auto precharge disabled and the READ has not yet terminated or been terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and the WRITE has not yet terminated or been termi-
nated.
4. Refresh, self refresh, and MRW commands can only be issued when all banks are idle.
5. A BST command cannot be issued to another bank; it applies only to the bank represented by the current state.
6. The states listed below must not be interrupted by any executable command. NOP commands must be applied during
each clock cycle while in these states:
Idle MRR: Starts with registration of the MRR command and ends when tMRR has been met. After tMRR is met, the device is
in the all banks idle state.
Reset MRR: Starts with registration of the MRR command and ends when tMRR has been met. After tMRR is met, the device
is in the all banks idle state.
Active MRR: Starts with registration of the MRR command and ends when tMRR has been met. After tMRR is met, the bank is
in the active state.
MRW: Starts with registration of the MRW command and ends when tMRW has been met. After tMRW is met, the device is in
the all banks idle state.
7. BST is supported only if a READ or WRITE burst is ongoing.
8. tRRD must be met between the ACTIVATE command to bank n and any subsequent ACTIVATE command to bank m.
9. READs or WRITEs listed in the command column include READs and WRITEs with or without auto precharge enabled.
10. This command may or may not be bank-specic. If all banks are being precharged, they must be in a valid state for pre-
charging.
11. MRR is supported in the row-activating state.
12. MRR is supported in the precharging state.
13. The next state for bank m depends on the current state of bank m (idle, row-activating,precharging, or active).
14. A WRITE command can be issued after the completion of the READ burst; otherwise a BST must be issued to end the
READ prior to asserting a WRITE command.
15. A READ command can be issued after the completion of the WRITE burst; otherwise, a BST must be issued to end the
WRITE prior to asserting another READ command.
16. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be followed by any valid command
to other banks provided that the timing restrictions in the PRECHARGE and Auto Precharge Clarication table are met.
17. Not bank-specic; requires that all banks are idle and no bursts are in progress.
18. RESET command is achieved through MODE REGISTER WRITE command
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DM Operation Truth Table
Note: Used to mask write data, and is provided simultaneously with the corresponding input data.
Command
Activate
The ACTIVATE command is issued by holding CS# LOW, CA0 LOW, and CA1 HIGH at the rising
edge of the clock. The bank addresses BA[1:0] are used to select the desired bank.
Row addresses are used to determine which row to activate in the selected bank. The ACTIVATE
command must be applied before any READ or WRITE operation can be executed.
The device can accept a READ or WRITE command at tRCD after the ACTIVATE command is
issued. After a bank has been activated, it must be precharged before another ACTIVATE com-
mand can be applied to the same bank. The bank active and precharge times are dened as tRAS
and tRP, respectively. The minimum time interval between successive ACTIVATE commands to
the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval
between ACTIVATE commands to different banks is tRRD.
ACTIVATE Command
DM Operation Truth Table
Function DM DQ Notes
Write Enable LValid 1
Write InhibitHX1
Activate command cycle: tRCD=3, tRP=3, tRRD=2
Notes:
1. tRCD = 3, tRP = 3, tRRD = 2.
2. A PRECHARGE ALL command uses tRPab timing, and a single-bank PRECHARGE command uses tRPpb timing. In
this gure, tRP is used to denote either an all-bank PRECHARGE or a single-bank PRECHARGE
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Note: Exclusively for 8-bank devices.
Certain restriction on operation of 8 bank devices must be observed, One rule restricts the number
of sequential ACTIVATE commands that can be issued; the second provides additional RAS pre-
charge time for a PRECHARGE ALL command.
• The 8-Bank Device Sequential Bank Activation Restriction:No more than four banks can be ac-
tivated (or refreshed, in the case of REFpb) in a rolling tFAW window. To convert to clocks, divide
tFAW[ns] by tCK[ns], and round up to the next integer value. For example, if RU(tFAW/tCK) is 10
clocks, and an ACTIVATE command is issued in clock n, no more than three further ACTIVATE
commands can be issued at or between clock n + 1 and n + 9. REFpb also counts as bank activa-
tion for purposes of tFAW.
• The 8-Bank Device PRECHARGE ALL Provision: tRP for a PRECHARGE ALL command must
equal tRPab, which is greater than tRPpb
tFAW Timing (8-Bank Devices)
t
FAW timing
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Read and Write Access Modes
After a bank is activated, a READ or WRITE command can be issued with CS# LOW, CA0 HIGH,
and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine
whether the access cycle is a READ operation (CA2 HIGH) or a WRITE operation (CA2 LOW).
The LPDDR2 provide a fast column access operation .A single READ or WRITE command initiates
a burst READ or burst WRITE operation on successive clock cycles.
For LPDDR2 –S4 devices, a new burst access must not interrupt the previous 4-bit burst operation
when BL = 4.
In case of BL = 8 or BL = 16, READs can be interrupted by READs and WRITEs can be interrupted
by WRITEs, provided that the interrupt occurs on a 4-bit boundary and that tCCD is met.
Burst READ
The burst READ command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2 HIGH at the
rising edge of the clock. The command address bus inputs, CA5r–CA6r and CA1f–CA9f, determine
the starting column address for the burst. The read latency (RL) is defined from the rising edge of
the clock on which the READ command is issued to the rising edge of the clock from which the
tDQSCK delay is measured. The first valid data is available RL × tCK + tDQSCK + tDQSQ after the
rising edge of the clock when the READ command is issued. The data strobe output is driven LOW
tRPRE before the first valid rising strobe edge. The first bit of the burst is synchronized with the first
rising edge of the data strobe. Each subsequent data-out appears on each DQ pin, edge aligned
with the data strobe. The RL is programmed in the mode registers.
Pin input timings for the data strobe are measured relative to the crosspoint of DQS and its com-
plement, DQS#.
Data Output (Read) Timing – tDQSCK (MAX)
Data output (Read) timing (tDQSCKmax)
Notes:
1. tDQSCK can span multiple clock periods.
2. An effective burst length of 4 is shown
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Data Output (Read) Timing– tDQSCK (MIN)
Data output (Read) timing (tDQSCKmin), BL=4
Note: An effective BL=4 is shown.
Burst READ – RL = 5, BL = 4, tDQSCK > tCK
Burst Read: RL=5, BL=4, tDQSCK > tCK
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Burst READ – RL = 3, BL = 8, tDQSCK < tCK
Burst Read: RL=3, BL=8, tDQSCK < tCK
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tDQSCKDL Timing
Notes:
1. tDQSCKDL = (tDQSCKn - tDQSCKm).
2. tDQSCKDL (MAX) is dened as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm)
pair within any 32ms rolling window.
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tDQSCKDM Timing
Notes:
1. tDQSCKDM = (tDQSCKn - tDQSCKm).
2. tDQSCKDM (MAX) is dened as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm)
pair within any 1.6μs rolling window.
tDQSCKDM timing
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tDQSCKDS Timing
tDQSCKDS timing
Notes:
1. tDQSCKDS = (tDQSCKn - tDQSCKm).
2. tDQSCKDS (MAX) is dened as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm) pair for
READs within a consecutive burst, within any 160ns rolling window.
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Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4
The minimum time from the burst READ command to the burst WRITE command is defined
by the read latency (RL) and the burst length (BL). Minimum READ-to-WRITE latency is RL +
RU(tDQSCK(MAX)/tCK) + BL/2 + 1 - WL clock cycles. Note that if a READ burst is truncated
with a burst TERMINATE (BST) command, the effective burst length of the truncated READ burst
should be used for BL when calculating the minimum READ-to-WRITE delay.
Seamless Burst READ – RL = 3, BL = 4, tCCD = 2
A seamless burst READ operation is supported by enabling a READ command at every other
clock cycle for BL = 4 operation, every fourth clock cycle for BL = 8 operation, and every eighth
clock cycle for BL = 16 operation. This operation is supported as long as the banks are activated,
whether the accesses read the same or different banks.
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READs Interrupted by a READ
For LP-DDR2-S4 devices, burst READ can be interrupted by another READ with a 4-bit burst
boundary, provided that tCCD is met.
A burst READ can be interrupted by other READs on any subsequent clock, provided that tCCD is
met.
READ Burst Interrupt Example – RL = 3, BL = 8, tCCD = 2
Note: READs can only be interrupted by other READs or the BST command.
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Burst WRITE
The burst WRITE command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2 LOW at
the rising edge of the clock. The command address bus inputs, CA5r–CA6r and CA1f–CA9f, deter-
mine the starting column address for the burst. Write latency (WL) is defined from the rising edge
of the clock on which the WRITE command is issued to the rising edge of the clock from which the
tDQSS delay is measured. The first valid data must be driven WL × tCK + tDQSS from the rising
edge of the clock from which the WRITE command is issued. The data strobe signal (DQS) must
be driven LOW tWPRE prior to data input. The burst cycle data bits must be applied to the DQ pins
tDS prior to
the associated edge of the DQS and held valid until tDH after that edge. Burst data is sampled on
successive edges of the DQS until the 4-, 8-, or 16-bit burst length is completed.
After a burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the
same bank can be issued.
Pin input timings are measured relative to the crosspoint of DQS and its complement, DQS#.
Data Input (WRITE) Timing
Data input (Write) timing
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NT6TL64M32AQ
Burst write: WL=1, BL=4
Burst write followed by burst read: RL=3, WL=1, BL=4
Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4
Burst WRITE – WL = 1, BL = 4
Notes:
1. The minimum number of clock cycles from the burst WRITE command to the burst READ command for any bank is
[WL + 1 + BL/2 + RU(tWTR/tCK)].
2. tWTR starts at the rising edge of the clock after the last valid input data.
3. If a WRITE burst is truncated with a BST command, the effective burst length of the truncated WRITE burst should
be used as BL to calculate the minimum WRITE-to-READ delay.
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Seamless Burst WRITE – WL = 1, BL = 4, tCCD = 2
WRITEs Interrupted by a WRITE
For LPDDR2-S4 devices, a burst WRITE can only be interrupted by another WRITE with a 4-bit
burst boundary, provided that tCCD (MIN) is met.
A WRITE burst interrupt can occur on any clock after the initial WRITE command, provided that
tCCD (MIN) is met.
WRITE Burst Interrupt Timing – WL = 1, BL = 8, tCCD = 2
Note: The seamless burst WRITE operation is supported by enabling a WRITE command every other clock for BL = 4 operation,
every four clocks for BL = 8 operation, or every eight clocks for BL = 16 operation. This operation is supported for any activated
bank.
Notes:
1. WRITEs can only be interrupted by other WRITEs or the BST command.
2. The effective burst length of the rst WRITE equals two times the number of clock cycles between the rst WRITE
and the interrupting WRITE
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BURST TERMINATE (BST)
The BURST TERMINATE (BST) command is initiated with CS# LOW, CA0 HIGH, CA1 HIGH, CA2
LOW, and CA3 LOW at the rising edge of the clock. A BST command can only be issued to termi-
nate an active READ or WRITE burst. Therefore, a BST command can only be issued up to and
including BL/2 - 1 clock cycles after a READ or WRITE command.
The effective burst length of a READ or WRITE command truncated by a BST command is as fol-
lows:
•Effectiveburstlength=2×(numberofclockcyclesfromtheREADorWRITEcommandtothe
BST command).
•IfaREADorWRITEburstistruncatedwithaBSTcommand,theeffectiveburstlengthofthe
truncated burst should be used for BL when calculating the minimum READ to-WRITE or WRITE-
to-READ delay.
•TheBSTcommandonlyaffectsthemostrecentREADorWRITEcommand.TheBSTcommand
truncates an ongoing READ burst RL × tCK + tDQSCK + tDQSQ after the rising edge of the clock
where the BST command is issued. The BST command truncates an ongoing WRITE burst WL ×
tCK + tDQSS after the rising edge of the clock where the BST command is issued.
•The4-bitprefetcharchitectureenablesBSTcommandassertiononevenclockcyclesfollowinga
WRITE or READ command. The effective burst length of a READ or WRITE command truncated by
a BST command is thus an integer multiple of four.
Burst WRITE Truncated by BST – WL = 1, BL = 16
Burst Write truncated by BST: WL=1, BL=16
Notes:
1. The BST command truncates an ongoing WRITE burst WL × tCK + tDQSS after the rising edge of the clock
where the BST command is issued.
2. BST can only be issued an even number of clock cycles after the WRITE command.
3. Additional BST commands are not supported after T4 and must not be issued until after the next READ or
WRITE command.
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Burst READ Truncated by BST – RL = 3, BL = 16
Write Data Mask
On LPDDR2 devices, one write data mask (DM) pin for each data byte (DQ) is supported, con-
sistent with the implementation on LPDDR SDRAM. Each DM can mask its respective DQ for any
given cycle of the burst. Data mask timings match data bit timing,
but are inputs only. Internal data mask loading is identical to data bit loading to ensure matched
system timing.
Data Mask Timing
Notes:
1. The BST command truncates an ongoing READ burst (RL × tCK + tDQSCK + tDQSQ) after the rising edge of the clock where
the BST command is issued.
2. BST can only be issued an even number of clock cycles after the READ command.
3. Additional BST commands are not supported after T4 and must not be issued until after the next READ or WRITE command
Data Mask Timing
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Write Data Mask – Second Data Bit Masked
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PRECHARGE
The PRECHARGE command is used to precharge or close a bank that has been activated.
The PRECHARGE command is initiated with CS# LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and
CA3 HIGH at the rising edge of the clock. The PRECHARGE command can be used to precharge
each bank independently or all banks simultaneously.
This is an 8-bank device, such that the AB flag and the bank address bits BA0, BA1, and BA2 are
used to determine which bank(s) to precharge. The precharged bank(s) will be available for sub-
sequent row access tRPab after an all bank PRECHARGE command is issued, or tRPpb after a
single-bank PRECHARGE command is issued.
In order to ensure that 8-bank devices can meet the instantaneous current demand required to
operate, the row precharge time (tRP) for an all bank PRECHARGE in 8-bank devices (tRPab) will
be longer than the row precharge time for a single-bank PRECHARGE (tRPpb).
Bank Selection for PRECHARGE by Address Bits
AB (CA4r) BA2 (CA9r)BA1 (CA8r)BA0 (CA7r)Precharged Bank(s)
8-bank device
0000Bank 0 only
0001Bank 1 only
0010Bank 2 only
0011Bank 3 only
0100Bank 4 only
0101Bank 5 only
0110Bank 6 only
0111Bank 7 only
1Don't care Don't care Don't care All Banks
Bank selection for Precharge by address bits
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READ Burst operation Followed by PRECHARGE
For the earliest possible precharge, the PRECHARGE command can be issued BL/2 clock cycles
after a READ command. A new bank ACTIVATE command can be issued to the same bank after
the row precharge time (tRP) has elapsed. A PRECHARGE command
cannot be issued until after tRAS is satisfied.
The minimum READ-to-PRECHARGE time (tRTP) must also satisfy a minimum analog time from
the rising clock edge that initiates the last 4-bit prefetch of a READ command. tRTP begins BL/2 -
2 clock cycles after the READ command.
If the burst is truncated by a BST command, the effective BL value is used to calculate when tRTP
begins.
READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(tRTP(MIN)/tCK) = 2
Burst Read followed by Precharge: RL=3, BL=8, RU(tRTP(min)/tCK)=2
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READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 3
Burst Read followed by Precharge: RL=3, BL=4, RU( tRTP(min)/tCK) = 3
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WRITE Burst operation Followed by PRECHARGE
For WRITE cycles, a WRITE recovery time ( tWR) must be provided before a PRECHARGE com-
mand can be issued. This delay is referenced from the last valid burst input data to the completion
of the burst WRITE. The PRECHARGE command must not be issued prior to the tWR delay.
These devices write data to the array in prefetch quadruples (prefetch = 4). An internal WRITE
operation can only begin after a prefetch group has been completely latched.
The minimum WRITE-to-PRECHARGE time for commands to the same bank is WL + BL/2 + 1 +
RU(tWR/tCK) clock cycles. For untruncated bursts, BL is the value set in the mode register. For
truncated bursts, BL is the effective burst length.
WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4
Burst Write followed by Precharge: WL=1, BL=4
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Auto Precharge
Before a new row can be opened in an active bank, the active bank must be precharged using
either the PRECHARGE command or the auto precharge function. When a READ or WRITE com-
mand is issued to the device, the auto precharge bit (AP) can be set to enable the active bank to
automatically begin precharge at the earliest possible moment during the burst READ or WRITE
cycle.
If AP is LOW when the READ or WRITE command is issued, then normal READ or WRITE burst
operation is executed and the bank remains active at the completion of the burst.
If AP is HIGH when the READ or WRITE command is issued, the auto precharge function is en-
gaged. This feature enables the PRECHARGE operation to be partially or completely hidden dur-
ing burst READ cycles (dependent upon READ or WRITE latency), thus improving system perfor-
mance for random data access.
READ Burst with Auto Precharge
If AP (CA0f) is HIGH when a READ command is issued, the READ with auto precharge function is
engaged.
These devices start an auto precharge on the rising edge of the clock BL/2 or BL/2 - 2 + RU(tRTP/
tCK) clock cycles later than the READ with auto precharge command, whichever is greater. For
auto precharge calculations see following table.
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From
CommandTo CommandMinimum Delay between "From Command" to
"To Command" Unit Note
s
Precharge (to same Bank as Read) BL/2 + max(2, RU(
t
RTP/
t
CK)) - 2 clks 1
Precharge AllBL/2 + max(2, RU(
t
RTP/
t
CK)) - 2 clks 1
Precharge (to same Bank as Read)
1c
lks1
Precharge All1clks 1
Precharge (to same Bank as Read w/AP) BL/2 + max(2, RU(
t
RTP/
t
CK)) - 2 clks 1,2
Precharge AllBL/2 + max(2, RU(
t
RTP/
t
CK)) - 2 clks 1
Activate (to same Bank as Read w/AP)
BL/2 + max(2, RU( RTP/ CK)) - 2 +
RU
(
t
RP /
t
CK
)
clks 1
Write or Write w/AP (same bank) illegal clks 3
Write or Write w/AP (different bank)RL + BL/2 + RU(
t
DQSCKmax/
t
CK) - WL + 1clks 3
Read or Read w/AP (same bank) illegal clks 3
Read or Read w/AP (different bank)BL/
2c
lks3
Precharge (to same Bank as Write) WL + BL/2 + RU
(
t
WR/
t
CK
)
+ 1 clks 1
Precharge AllWL + BL/2 + RU
(
t
WR/
t
CK
)
+ 1 clks 1
Precharge (to same Bank as Write) WL + RU
(
t
WR/
t
CK
)
+ 1 clks 1
Precharge AllWL + RU
(
t
WR/
t
CK
)
+ 1 clks 1
Precharge (to same Bank as Write w/AP) WL + BL/2 + RU(
t
WR/
t
CK) + 1 clks 1
Precharge AllWL + BL/2 + RU(
t
WR/
t
CK) + 1 clks 1
Activate (to same Bank as Write w/AP) WL + BL/2 + RU(
t
WR/
t
CK) + 1 + RU(
t
RP
p
b
/
t
CK) clks 1
Write or Write w/AP (same bank) illegal clks 3
Write or Write w/AP (different bank)BL/
2c
lks3
Read or Read w/AP (same bank) illegal clks 3
Read or Read w/AP (different bank)WL + BL/2 + RU
(
t
WTR/
t
CK
)
+ 1 clks 3
Precharge (to same Bank as Precharge)
1c
lks1
Precharge All1clks 1
Precharge
1c
lks1
Precharge All1clks 1
Precharge
Precharge
All
LPDDR2-S4: Precharge & Auto Precharge clarification
Read
BST
(for Reads)
Read w/AP
Write
BST
(for Writes)
Write w/AP
LPDDR2-S4: PRECHARGE and Auto Precharge Clarification
Notes:
1. For a given bank, the PRECHARGE period should be counted from the latest PRECHARGE command—either a one-bank
PRECHARGE or PRECHARGE ALL—issued to that bank.
The PRECHARGE period is satised after tRP, depending on the latest PRECHARGE command issued to that bank.
2. Any command issued during the specied minimum delay time is illegal.
3. After READ with auto precharge, seamless READ operations to different banks are supported.
After WRITE with auto precharge, seamless WRITE operations to different banks are supported. READ with auto precharge and
WRITE with auto precharge must not be interrupted or truncated.
Following an auto precharge operation, an ACTIVATE command can be issued to the same bank if the following two conditions
are satised simultaneously:
• The RAS precharge time (tRP) has been satised from the clock at which the auto precharge begins.
• The RAS cycle time (tRC) from the previous bank activation has been satised.
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READ Burst with Auto Precharge – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 2
-
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WRITE Burst operation Followed by PRECHARGE
For WRITE cycles, a WRITE recovery time ( tWR) must be provided before a PRECHARGE com-
mand can be issued. This delay is referenced from the last valid burst input data to the completion
of the burst WRITE. The PRECHARGE command must not be issued prior to the tWR delay.
These devices write data to the array in prefetch quadruples (prefetch = 4). An internal WRITE
operation can only begin after a prefetch group has been completely latched.
The minimum WRITE-to-PRECHARGE time for commands to the same bank is WL + BL/2 + 1 +
RU(tWR/tCK) clock cycles. For untruncated bursts, BL is the value set in the mode register. For
truncated bursts, BL is the effective burst length.
WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4
Bank m
col addr a Col addr a
READ w/AP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
RL = 3
Transitioning data
NOP NOP NOP ACTIVATE
tRTP
BL/2
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
Bank m
row addr Row addr
≥tRPpb
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REFRESH
The REFRESH command is initiated with CS# LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the
rising edge of the clock. Per-bank REFRESH is initiated with CA3 LOW at the rising edge of the
clock. All-bank REFRESH is initiated with CA3 HIGH at the rising edge of
the clock. Per-bank REFRESH is only supported in devices with eight banks.
A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to the bank
scheduled by the bank counter in the memory device. The bank sequence for per-bank REFRESH
is fixed to be a sequential round-robin: 0-1-2-3-4-5-6-7-0-1-.... The bank count is synchronized
between the controller and the SDRAM by resetting the bank count to zero. Synchronization can
occur upon issuing a RESET command or at every exit from self refresh. Bank addressing for the
per-bank REFRESH count is the same as established for the single-bank PRECHARGE com-
mand.
A bank must be idle before it can be refreshed. The controller must track the bank being refreshed
by the per-bank REFRESH command.
The REFpb command must not be issued to the device until the following conditions have been
met:
•tRFCabhasbeensatisedafterthepriorREFabcommand
•tRFCpbhasbeensatisedafterthepriorREFpbcommand
•tRPhasbeensatisedafterthepriorPRECHARGEcommandtothatbank
•tRRDhasbeensatisedafterthepriorACTIVATEcommand(ifapplicable,forexampleafteracti-
vating a row in a different bank than the one affected by the REFpb command)
The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb), however, other
banks within the device are accessible and can be addressed during the cycle.
During the REFpb operation, any of the banks other than the one being refreshed can be main-
tained in an active state or accessed by a READ or WRITE command.
When the per-bank REFRESH cycle has completed, the affected bank will be in the idle state.
After issuing REFpb, the following conditions must be met:
•tRFCpbmustbesatisedbeforeissuingaREFabcommand
•tRFCpbmustbesatisedbeforeissuinganACTIVATEcommandtothesamebank
•tRRDmustbesatisedbeforeissuinganACTIVATEcommandtoadifferentbank
•tRFCpbmustbesatisedbeforeissuinganotherREFpbcommand
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An all-bank REFRESH command (REFab) issues a REFRESH command to all banks. All banks
must be idle when REFab is issued (for instance, by issuing a PRECHARGE ALL command prior
to issuing an all-bank REFRESH command). REFab also synchronizes the bank count between
the controller and the SDRAM to zero. The REFab command must not be issued to the device until
the following conditions have been met:
•tRFCabhasbeensatisedfollowingthepriorREFabcommand
•tRFCpbhasbeensatisedfollowingthepriorREFpbcommand
•tRPhasbeensatisedfollowingthepriorPRECHARGEcommands
After an all-bank REFRESH cycle has completed, all banks will be idle. After issuing REFab:
•tRFCablatencymustbesatisedbeforeissuinganACTIVATEcommand
•tRFCablatencymustbesatisedbeforeissuingaREFaborREFpbcommand
REFRESH Command Scheduling Separation Requirements
Command Scheduling Separations related to Refresh
Symbol minimum delay fromt
oN
otes
REF
ab
Activate cmd to any bank .
REF
pb
REF
ab
Activate cmd to same bank as REF
pb
REF
pb
REF
pb
Activate cmd to different bank than REF
pb
REF
pb
affecting an idle bank (different bank than Activate)1
Activate cmd to different bank than prior Activate
REF
ab
t
RFC
ab
t
RFC
pb
REF
pb
t
RRDActivate
Note: A bank must be in the idle state before it is refreshed, so REFab is prohibited following an ACTIVATE command. REFpb is
supported only if it affects a bank that is in the idle state.
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The LPDDR2 devices provide significant flexibility in scheduling REFRESH commands as long as
the required boundary conditions are met (see figure of tSRF Definition).
In the most straightforward implementations, a REFRESH command should be scheduled every
tREFI. In this case, self refresh can be entered at any time.
Users may choose to deviate from this regular refresh pattern, for instance, to enable a period in
which no refresh is required. As an example, using a 2Gb LPDDR2 device, the user can choose
to issue a refresh burst of 8192 REFRESH commands at the maximum supported rate (limited by
tREFBW), followed by an extended period without issuing any REFRESH commands, until the
refresh window is complete. The maximum supported time without REFRESH commands is calcu-
lated as follows: tREFW - (R/8) × tREFBW= tREFW - R × 4 × tRFCab.
For example, a 2Gb device at TC ≤ 85˚C can be operated without a refresh for up to 32ms - 8192 ×
4 × 130ns ≈ 27ms.
Both the regular and the burst/pause patterns can satisfy refresh requirements if they are repeated
in every 32ms window. It is critical to satisfy the refresh requirement in every rolling refresh window
during refresh pattern transitions. The supported transition from a burst pattern to a regular distrib-
uted pattern is shown in figure of Supported Transition from Repetitive REFRESH Burst .
If this transition occurs immediately after the burst refresh phase, all rolling tREFW intervals will
meet the minimum required number of REFRESH commands.
A nonsupported transition is shown in Figure of Nonsupported Transition from Repetitive RE-
FRESH Burst . In this example, the regular refresh pattern starts after the completion of the pause
phase of the burst/pause refresh pattern. For several rolling tREFW intervals, the minimum number
of REFRESH commands is not satisfied.
Understanding this pattern transition is extremely important, even when only one pattern is em-
ployed. In self refresh mode, a regular distributed refresh pattern must be assumed.
ISSI recommends entering self refresh mode immediately following the burst phase of a burst/
pause refresh pattern; upon exiting self refresh, begin with the burst phase (see Figure of Recom-
mended Self Refresh Entry and Exit ).
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Regular Distributed Refresh Pattern
Notes:
1. Compared to repetitive burst REFRESH with subsequent REFRESH pause.
2. As an example, in a 512Mb LPDDR2 device at TC ≤ 85˚C, the distributed refresh pattern has one REFRESH command per
7.8μs; the burst refresh pattern has one REFRESH command per 0.52μs, followed by ≈ 30ms without any REFRESH command.
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Supported Transition from Repetitive REFRESH Burst
Notes:
1. Shown with subsequent REFRESH pause to regular distributed refresh pattern.
2. As an example, in a 512Mb LPDDR2 device at TC ≤ 85˚C, the distributed refresh pattern has one REFRESH command per
7.8μs; the burst refresh pattern has one REFRESH command per 0.52μs, followed by ≈ 30ms without any REFRESH command
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Nonsupported Transition from Repetitive REFRESH Burst
Notes:
1. Shown with subsequent REFRESH pause to regular distributed refresh pattern.
2. There are only ≈ 2048 REFRESH commands in the indicated tREFW window. This does not provide the required minimum
number of REFRESH commands (R).
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Recommended Self Refresh Entry and Exit
REFRESH Requirements
1. Minimum Number of REFRESH Commands
Mobile LPDDR2 requires a minimum number, R, of REFRESH (REFab) commands within any roll-
ing refresh window (tREFW = 32 ms @ MR4[2:0] = 011 or TC ≤ 85˚C). For actual values per den-
sity and the resulting average refresh interval (tREFI).
For tREFW and tREFI refresh multipliers at different MR4 settings, see the MR4 Device Tempera-
ture (MA[7:0] = 04h) table.
For devices supporting per-bank REFRESH, a REFab command can be replaced by a full cycle of
eight REFpb commands.
2. Burst REFRESH Limitation
To limit current consumption, a maximum of eight REFab commands can be issued in any roll-
ing tREFBW (tREFBW = 4 × 8 × tRFCab). This condition does not apply if REFpb commands are
used.
3. REFRESH Requirements and Self Refresh
If any time within a refresh window is spent in self refresh mode, the number of required REFRESH
commands in that window is reduced to the following:
R’ = RU〔tSRF / tREFI〔= R - RU ×〔R x tSRF / tREFW〔
Where RU represents the round-up function.
Note: In conjunction with a burst/pause refresh pattern
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tSRF Definition
Notes:
1. Time in self refresh mode is fully enclosed in the refresh window (tREFW).
2. At self refresh entry.
3. At self refresh exit.
4. Several intervals in self refresh during one tREFW interval. In this example, tSRF = tSRF1 +tSRF2.
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All-Bank REFRESH Operation
Per-Bank REFRESH Operation
Notes:
1. Prior to T0, the REFpb bank counter points to bank 0.
2. Operations to banks other than the bank being refreshed are supported during the tRFCpb period
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SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the array, even if the rest of the
system is powered down. When in the self refresh mode, the device retains data without external
clocking. The device has a built-in timer to accommodate SELF REFRESH operation. The SELF
REFRESH command is executed by taking CKE LOW, CS# LOW, CA0 LOW, CA1 LOW, and CA2
HIGH at the rising edge of the clock.
CKE must be HIGH during the clock cycle preceding a SELF REFRESH command. A NOP com-
mand must be driven in the clock cycle following the SELF REFRESH command.
After the power-down command is registered, CKE must be held LOW to keep the device in self
refresh mode. LPDDR2-S4 devices can operate in self refresh mode in both the standard and ex-
tended temperature ranges. These devices also manage self refresh power consumption
when the operating temperature changes, resulting in the lowest possible power consumption
across the operating temperature range.
After the device has entered self refresh mode, all external signals other than CKE are“Don’t Care.”
For proper self refresh operation, power supply pins (VDD1, VDD2, VDDQ, and VDDCA) must
be at valid levels. VDDQ can be turned off during self refresh. If VDDQ is turned off, VREFDQ
must also be turned off. Prior to exiting self refresh, both VDDQ and VREFDQ must be within their
respective minimum/maximum operating ranges . VREFDQ can be at any level between 0 and
VDDQ; VREFCA can be at any level between 0 and VDDCA during self refresh.
Before exiting self refresh, VREFDQ and VREFCA must be within specified limits (see AC and DC
Logic Input Measurement Levels for Single-Ended Signals . After entering self refresh mode, the
device initiates at least one all-bank REFRESH command internally during tCKESR. The clock is
internally disabled during SELF REFRESH operation to save power. The device must remain in self
refresh mode for at least tCKESR. The user can change the external clock frequency or halt the
external clock one clock after self refresh entry is registered; however, the clock must be restarted
and stable before the device can exit SELF REFRESH operation.
Exiting self refresh requires a series of commands. First, the clock must be stable prior to CKE
returning HIGH. After the self refresh exit is registered, a minimum delay, at least equal to the self
refresh exit interval (tXSR), must be satisfied before a valid command can be issued to the device.
This provides completion time for any internal refresh in progress. For proper operation, CKE must
remain HIGH throughout tXSR, except during self refresh re-entry. NOP commands must be regis-
tered on each rising clock edge during tXSR.
Using self refresh mode introduces the possibility that an internally timed refresh event could be
missed when CKE is driven HIGH for exit from self refresh mode. Upon exiting self refresh, at least
one REFRESH command (one all-bank command or eight per-bank commands) must be issued
before issuing a subsequent SELF REFRESH command.
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SELF REFRESH Operation
Notes:
1. Input clock frequency can be changed or stopped during self refresh, provided that upon exiting self-refresh, a minimum of two
cycles of stable clocks (tINIT2) are provided, and the clock frequency is between the minimum and maximum
frequencies for the particular speed grade.
2. The device must be in the all banks idle state prior to entering self refresh mode.
3. tXSR begins at the rising edge of the clock after CKE is driven HIGH.
4. A valid command can be issued only after tXSR is satised. NOPs must be issued during tXSR.
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Partial-Array Self Refresh – Bank Masking
Devices in densities of 64Mb–512Mb are comprised of four banks; densities of 1Gb and higher are
comprised of eight banks. Each bank can be configured independently whether or not a SELF RE-
FRESH operation will occur in that bank. One 8-bit mode register (accessible via the MRW com-
mand) is assigned to program the bank-masking status of each bank up to eight banks. For bank
masking bit assignments, see the MR16 PASR Bank Mask (MA[7:0] = 010h) and MR16 Op-Code
Bit Definitions tables.
The mask bit to the bank enables or disables a refresh operation of the entire memory space
within the bank. If a bank is masked using the bank mask register, a REFRESH operation to the
entire bank is blocked and bank data retention is not guaranteed in self refresh mode. To enable a
REFRESH operation to a bank, the corresponding bank mask bit must be programmed as “un-
masked.” When a bank mask bit is unmasked, the array space being refreshed within that bank is
determined by the programmed status of the
segment mask bits.
Partial-Array Self Refresh – Segment Masking
Programming segment mask bits is similar to programming bank mask bits. For densities 1Gb
and higher, eight segments are used for masking (see the MR17 PASR Segment Mask (MA[7:0]
= 011h) and MR17 PASR Segment Mask Definitions tables). A mode register is used for program-
ming segment mask bits up to eight bits. For densities less than 1Gb, segment masking is not
supported.
When the mask bit to an address range (represented as a segment) is programmed as“masked,”
a REFRESH operation to that segment is blocked. Conversely, when a segment mask bit to an ad-
dress range is unmasked, refresh to that segment is enabled.
A segment masking scheme can be used in place of or in combination with a bank masking
scheme. Each segment mask bit setting is applied across all banks. For segment masking bit as-
signments, see the tables noted above.
Bank and Segment Masking Example
Note: This table provides values for an 8-bank device with REFRESH operations masked to banks 1 and 7, and segments 2 and 7.
Segment Mask (MR17) Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Bank Mask (MR16) 01000001
Segment 0 0–M–––––M
Segment 1 0–M–––––M
Segment 21
M M M M M M M M
Segment 3 0–M–––––M
Segment 4 0–M–––––M
Segment 5 0–M–––––M
Segment 6 0–M–––––M
Segment 71
M M M M M M M M
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MODE REGISTER READ
The MODE REGISTER READ (MRR) command is used to read configuration and status data from
SDRAM mode registers. The MRR command is initiated with CS# LOW, CA0 LOW, CA1 LOW,
CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode register
is selected by CA1f–CA0f and CA9r–CA4r. The mode register contents are available on the first
data beat of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ and following the rising edge of the clock
where MRR is issued. Subsequent data beats contain valid but undefined
content, except in the case of the DQ calibration function, where subsequent data beats contain
valid content as described in Data Calibration Pattern Description. All DQS are toggled for the
duration of the mode register READ burst. The MRR command has a burst length of four. MRR
operation (consisting of the MRR command and the corresponding data traffic) must not be inter-
rupted. The MRR command period (tMRR) is two clock cycles.
MRR Timing – RL = 3, tMRR = 2
Notes:
1. MRRs to DQ calibration registers MR32 and MR40 are described in DQ Calibration .
2. Only the NOP command is supported during tMRR.
3. Mode register data is valid only on DQ[7:0] on the rst beat. Subsequent beats contain valid but undened data. DQ[MAX:8]
contain valid but undened data for the duration of the MRR burst.
4. Minimum MRR to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 - WL clock cycles.
5. Minimum MRR to MRW latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 clock cycles.
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READ bursts and WRITE bursts cannot be truncated by MRR. Following a READ command, the
MRR command must not be issued before BL/2 clock cycles have completed.
Following a WRITE command, the MRR command must not be issued before WL + 1 + BL/2 +
RU(tWTR/tCK) clock cycles have completed. If a READ or WRITE burst is truncated with a BST
command, the effective burst length of the truncated burst should be used for the BL value.
READ to MRR Timing – RL = 3, tMRR = 2
Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4
Notes:
1. The minimum number of clock cycles from the burst READ command to the MRR command is BL/2.
2. Only the NOP command is supported during tMRR.
Notes:
1. The minimum number of clock cycles from the burst WRITE command to the MRR command is [WL + 1 + BL/2 + RU(tWTR/
tCK)].
2. Only the NOP command is supported during tMRR.
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Temperature Sensor
LPDDR2 devices feature a temperature sensor whose status can be read from MR4. This sen-
sor can be used to determine an appropriate refresh rate, determine whether AC timing derating is
required in the extended temperature range, and/or monitor the operating temperature. Either the
temperature sensor or the device operating temperature can be used to determine whether operat-
ing temperature requirements
are being met (see Operating Temperature Range table). Temperature sensor data can be read
from MR4 using the mode register read protocol.
Upon exiting self-refresh or power-down, the device temperature status bits will be no older than
tTSI.
When using the temperature sensor, the actual device case temperature may be higher than the
operating temperature specification that applies for the standard or extended temperature ranges
(see table noted above). For example, TCASE could be above 85˚C when MR4[2:0] equals 011b.
To ensure proper operation using the temperature sensor, applications must accommodate the
parameters in the temperature sensor definitions table.
Temperature Sensor Definitions and Operating Conditions
LPDDR2 devices accommodate the temperature margin between the point at which the device
temperature enters the extended temperature range and the point at which the controller reconfig-
ures the system accordingly. To determine the required MR4 polling frequency, the system must
use the maximum TempGradient and the maximum response time of the system according to the
following equation:
TempGradient × (ReadInterval + tTSI + SysRespDelay) ≤ 2°C
For example, if TempGradient is 10˚C/s and the SysRespDelay is 1ms:
10°C / s × (ReadInterval + 32ms + 1ms) ≤ 2°C
In this case, ReadInterval must not exceed 167ms
ParameterSymbolMax/Min ValueUnitNotes
System Temperature Gradien
t
TempGradient MaxSystem DependentC/s
Maximum temperature gradient
experienced by the memory device at the
temperature of interest over a range of 2°C.
MR4 Read Interval ReadInterval MaxSystem DependentmsTime period between MR4 READs from the
system.
Temperature Sensor Interval
t
TSIMax16msMaximum delay between internal updates
of MR4.
System Response Delay
SysRespDelay
MaxSystem DependentmsMaximum response time from an MR4
READ to the system response.
Device Temperature Margin TempMargin Max2C Margin above maximum temperature to
support controller response.
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Temperature Sensor Timing
DQ Calibration
Mobile LPDDR2 devices feature a DQ calibration function that outputs one of two predefined sys-
tem timing calibration patterns. For x16 devices, pattern A (MRR to MRR32), and pattern B (MRR
to MRR40), will return the specified pattern on DQ0 and DQ8; x32 devices return the specified pat-
tern on DQ0, DQ8, DQ16, and DQ24.
For x16 devices, DQ[7:1] and DQ[15:9] drive the same information as DQ0 during the MRR burst.
For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] drive the same information as DQ0
during the MRR burst. MRR DQ calibration commands can occur only in the idle state.
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MR32 and MR40 DQ Calibration Timing – RL = 3, tMRR = 2
Note: Only the NOP command is supported during Tmrr
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Notes:
1. At time Ty, the device is in the idle state.
2. Only the NOP command is supported during tMRW.
Data Calibration Pattern Description
Truth Table for MRR and MRW
MODE REGISTER WRITE Command
The MODE REGISTER WRITE (MRW) command is used to write configuration data to the mode
registers. The MRW command is initiated with CS# LOW, CA0 LOW, CA1 LOW, CA2 LOW, and
CA3 LOW at the rising edge of the clock. The mode register is selected by
CA1f–CA0f, CA9r–CA4r. The data to be written to the mode register is contained in CA9f–CA2f.
The MRW command period is defined by tMRW. MRWs to read-only registers have no impact on
the functionality of the device. MRW can only be issued when all banks are in the idle precharge
state. One method of ensuring that the banks are in this state is to issue a PRECHARGE ALL com-
mand.
MODE REGISTER WRITE Timing – RL = 3, tMRW = 5
Pattern MR#Bit Time 0Bit Time 1Bit Time 2Bit Time 3Notes
Pattern AMR321 010Reads to MR32 return DQ callibration pattern A
Pattern BMR400 011Reads to MR32 return DQ callibration pattern B
Current State CommandIntermediate StateNext State
MRRMode Register Reading (All Banks idle)All Banks idle
MRWMode Register Writing (All Banks idle)All Banks idle
MRW (Reset) Restting (Device Auto-Init) All Banks idle
MRRMode Register Reading (Bank(s) idle)Bank(s) Active
MRWNot AllowedNot Allowed
MRW (Reset) Not AllowedNot Allowed
All Banks idle
Bank(s) Active
MR dataMR addr
MRWNOP 2MRW
T0 T1 T2 Tx Tx + 1 Tx + 2Ty1Ty + 1Ty + 2
CK#
CK
CA[9:0]
CMD Valid
tMRW tMRW
MR dataMR addr
NOP 2NOP 2NOP 2
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MRW RESET Command
The MRW RESET command brings the device to the device auto initialization (resetting) state in
the power-on initialization sequence (see RESET Command under Power-Up ). The MRW RESET
command can be issued from the idle state. This command resets all mode registers to their de-
fault values. Only the NOP command is supported during tINIT4. After MRW RESET, boot timings
must be observed until the
device initialization sequence is complete and the device is in the idle state. Array data is unde-
fined after the MRW RESET command has completed.
For MRW RESET timing, see Figure of Voltage Ramp and Initialization Sequence.
MRW ZQ Calibration Commands
The MRW command is used to initiate a ZQ calibration command that calibrates output driver
impedance across process, temperature, and voltage. LPDDR2-S4 devices support ZQ calibration.
To achieve tighter tolerances, proper ZQ calibration must be performed.
There are four ZQ calibration commands and related timings: tZQINIT, tZQRESET, tZQCL, and
tZQCS. tZQINIT is used for initialization calibration; tZQRESET is used for resetting ZQ to the
default output impedance; tZQCL is used for long calibration(s); and tZQCS is used for short
calibration(s). See the MR10 Calibration (MA[7:0] = 0Ah) table for ZQ calibration command code
definitions.
ZQINIT must be performed for LPDDR2 devices. ZQINIT provides an output impedance accuracy
of ±15%. After initialization, the ZQ calibration long (ZQCL) can be used to recalibrate the system
to an output impedance accuracy of ±15%. A ZQ calibration short (ZQCS) can be used periodi-
cally to compensate for temperature and voltage drift in the system.
ZQRESET resets the output impedance calibration to a default accuracy of ±30% across process,
voltage, and temperature. This command is used to ensure output impedance accuracy to ±30%
when ZQCS and ZQCL commands are not used.
One ZQCS command can effectively correct at least 1.5% (ZQ correction) of output impedance
errors within tZQCS for all speed bins, assuming the maximum sensitivities specified in the tables
"output Driver Sensitivity Definition" and "Output Driver Temperature and Voltage Sensitivity" (page
133) are met. The appropriate interval between ZQCS commands can be determined using these
tables and system-specific parameters.
LPDDR2 devices are subject to temperature drift rate (Tdriftrate) and voltage drift rate (Vdriftrate)
in various applications. To accommodate drift rates and calculate the necessary interval between
ZQCS commands, apply the following formula.
ZQcorrection / 〔(Tsens × Tdriftrate) + (Vsens × Vdriftrate)〔
Where Tsens = MAX (dRONdT) and Vsens = MAX (dRONdV) define temperature and voltage
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sensitivities.
For example, if Tsens = 0.75%/˚C, Vsens = 0.20%/mV, Tdriftrate = 1˚C/sec, and Vdriftrate =15 mV/
sec, then the interval between ZQCS commands is calculated as:
1.5 / 〔(0.75 × 1) + (0.20 × 15)〔= 0.4s
A ZQ calibration command can only be issued when the device is in the idle state with all banks
precharged.
No other activities can be performed on the data bus during calibration periods (tZQINIT, tZQCL,
or tZQCS). The quiet time on the data bus helps to accurately calibrate output impedance. There is
no required quiet time after the ZQRESET command. If multiple devices share a single ZQ resis-
tor, only one device can be calibrating at any given time. After calibration is complete, the ZQ ball
circuitry is disabled to reduce power consumption.
In systems sharing a ZQ resistor between devices, the controller must prevent tZQINIT, tZQCS,
and tZQCL overlap between the devices. ZQRESET overlap is acceptable. If the ZQ resistor is ab-
sent from the system, ZQ must be connected to VDDCA. In this situation, the device must ignore
ZQ calibration commands and the device will use the default calibration settings.
ZQ Timings
Notes:
1. Only the NOP command is supported during ZQ calibrations.
2. CKE must be registered HIGH continuously during the calibration period.
3. All devices connected to the DQ bus should be High-Z during the calibration process.
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ZQ External Resistor Value, Tolerance, and Capacitive Loading
To use the ZQ calibration function, a 240 ohm (±1% tolerance) external resistor must be connected
between the ZQ pin and ground. A single resistor can be used for each device or one resistor can
be shared between multiple devices if the ZQ calibration timings for each device do not overlap.
The total capacitive loading on the ZQ pin must be limited.
Power-Down
Power-down is entered synchronously when CKE is registered LOW and CS# is HIGH at the ris-
ing edge of clock. A NOP command must be driven in the clock cycle following power-down entry.
CKE must not go LOW while MRR, MRW, READ, or WRITE operations are in progress. CKE can
go LOW while any other operations such as ACTIVATE, PRECHARGE, auto precharge, or RE-
FRESH are in progress, but the power-down IDD specification will not be applied until such opera-
tions are complete.
If power-down occurs when all banks are idle, this mode is referred to as idle power-down;
if power-down occurs when there is a row active in any bank, this mode is referred to as active
power-down.
Entering power-down deactivates the input and output buffers, excluding CK, CK#, and CKE. In
power-down mode, CKE must be held LOW; all other input signals are “Don’t Care.” CKE LOW
must be maintained until tCKE is satisfied. VREFCA must be maintained at a valid level during
power-down.
VDDQ can be turned off during power-down. If VDDQ is turned off, VREFDQ must also be turned
off. Prior to exiting power-down, both VDDQ and VREFDQ must be within their respective mini-
mum/maximum operating ranges (see AC and DC Operating Conditions).
No refresh operations are performed in power-down mode. The maximum duration in power-down
mode is only limited by the refresh requirements outlined in REFRESH Command.
The power-down state is exited when CKE is registered HIGH. The controller must drive CS# HIGH
in conjunction with CKE HIGH when exiting the power-down state. CKE HIGH must be maintained
until tCKE is satisfied. A valid, executable command can be applied with power-down exit latency
tXP after CKE goes HIGH. Power-down exit latency is defined in the AC Timing section.
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Power-Down Entry and Exit Timing
CKE Intensive Environment
REFRESH-to-REFRESH Timing in CKE Intensive Environments
Note: Input clock frequency can be changed or the input clock stopped during power-down, provided that the clock frequency is
between the minimum and maximum specied frequencies for the speed grade in use, and that prior to power-down exit, a mini-
mum of two stable clocks complete.
Note: The pattern shown can repeat over an extended period of time. With this pattern, all AC and DC timing and voltage speci-
cations with temperature and voltage drift are ensured.
CK#
CK
CKE
CMD
tCKE
tCKE tCKE tCKE
REFRESH REFRESH
tXP tREFI
tXP
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Read to Power-Down entry
Notes:
1. CKE must be held HIGH until the end of the burst operation.
2. CKE can be registered LOW at (RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1) clock cycles after the clock on which the
READ command is registered
READ to Power-Down Entry
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READ with Auto Precharge to Power-Down Entry
Notes:
1. CKE must be held HIGH until the end of the burst operation.
2. CKE can be registered LOW at (RL + RU(tDQSCK/tCK)+ BL/2 + 1) clock cycles after the clock on which the READ
command is registered.
3. BL/2 with tRTP = 7.5ns and tRAS (MIN) is satised.
4. Start internal PRECHARGE
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WRITE to Power-Down Entry
Note: CKE can be registered LOW at (WL + 1 + BL/2 + RU(tWR/tCK)) clock cycles after the clock on which the WRITE com-
mand is registered.
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WRITE with Auto Precharge to Power-Down Entry
Notes:
1. CKE can be registered LOW at (WL + 1 + BL/2 + RU(tWR/tCK + 1) clock cycles after the WRITE command is registered.
2. Start internal PRECHARGE
Write with Auto-precharge to Power-Down entry
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REFRESH Command to Power-Down Entry
ACTIVATE Command to Power-Down Entry
PRECHARGE Command to Power-Down Entry
Note: CKE can go LOW tIHCKE after the clock on which the REFRESH command is registered.
Note: CKE can go LOW at tIHCKE after the clock on which the ACTIVATE command is registered
Note: CKE can go LOW tIHCKE after the clock on which the PRECHARGE command is registered.
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MRR Command to Power-Down Entry
MRW Command to Power-Down Entry
Note: CKE can be registered LOW at (RL + RU(tDQSCK/tCK)+ BL/2 + 1) clock cycles after the clock on which the MRR com-
mand is registered.
Note: CKE can be registered LOW tMRW after the clock on which the MRW command is registered
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Deep Power-Down
Deep power-down (DPD) is entered when CKE is registered LOW with CS# LOW, CA0 HIGH, CA1
HIGH, and CA2 LOW at the rising edge of the clock. The NOP command must be driven in the
clock cycle following power-down entry. CKE must not go LOW while MRR or MRW operations are
in progress. CKE can go LOW while other operations such as ACTIVATE, auto precharge, PRE-
CHARGE, or REFRESH are in progress, however, deep power-down IDD specifications will not be
applied until those operations complete. The contents of the array will be lost upon entering DPD
mode.
In DPD mode, all input buffers except CKE, all output buffers, and the power supply to internal
circuitry are disabled within the device. VREFDQ can be at any level between 0 and VDDQ, and
VREFCA can be at any level between 0 and VDDCA during DPD. All power supplies (including
VREF) must be within the specified limits prior to exiting DPD (see AC and DC Operating Condi-
tions).
To exit DPD, CKE must be HIGH, tISCKE must be complete, and the clock must be stable. To re-
sume operation, the device must be fully reinitialized using the power-up initialization sequence.
Deep Power-Down Entry and Exit Timing
Notes:
1. The initialization sequence can start at any time after Tx + 1.
2. tINIT3 and Tx + 1 refer to timings in the initialization sequence. For details, see Mode Register Denition
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Input Clock Frequency Changes and Stop Events
LPDDR2 support Clock frequency changes and clock stop under the conditions detailed in this
section
Input Clock Frequency Changes and Clock Stop with CKE LOW
During CKE LOW, Mobile LPDDR2 devices support input clock frequency changes and clock stop
under the following conditions:
•Refreshrequirementsaremet
•OnlyREFaborREFpbcommandscanbeinprocess
•AnyACTIVATEorPRECHARGEcommandshavecompletedpriortochangingthefrequency
•Relatedtimingconditions,tRCDandtRP,havebeenmetpriortochangingthefrequency
•TheinitialclockfrequencymustbemaintainedforaminimumoftwoclockcyclesafterCKEgoes
LOW
•TheclocksatisestCH(abs)andtCL(abs)foraminimumoftwoclockcyclespriortoCKEgoing
HIGH
For input clock frequency changes, tCK(MIN) and tCK(MAX) must be met for each clock cycle.
After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may
be required to set the WR, RL, etc. These settings may require adjustment to meet minimum timing
requirements at the target clock frequency.
For clock stop, CK is held LOW and CK# is held HIGH.
NO OPERATION Command
The NO OPERATION (NOP) command prevents the device from registering any unwanted com-
mands issued between operations. A NOP command can only be issued at clock cycle N when the
CKE level is constant for clock cycle N-1 and clock cycle N. The NOP command has two possible
encodings: CS# HIGH at the clock rising edge N; and CS# LOW with CA0, CA1, CA2 HIGH at the
clock rising edge N.
The NOP command will not terminate a previous operation that is still in process, such as a READ
burst or WRITE burst cycle
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Electrical Specifications
Absolute Maximum DC Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability
2. See “Power-Ramp” section in “Power-up, Initialization, and Power-Off” for relationships between power supplies.
3. VREFDQ 0.6 x VDDQ; however, VREFDQ may be VDDQ provided that VREFDQ 300mV.
4. VREFCA 0.6 x VDDCA; however, VREFCA may be VDDCA provided that VREFCA 300mV.
5. Storage Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement
conditions, please refer to JESD51-2 standard.
Parameter Symbol Min Max Units Notes
VDD1 supply voltage relative to VSS VDD1 -0.4 2.3V 2
VDD2 supply voltage relative to VSS VDD2 -0.4 1.6V 2
VDDCA supply voltage relative to VSSCA VDDCA -0.4 1.6V 2,4
VDDQ supply voltage relative to VSSQVDDQ -0.41.6
V2
,3
Voltage on any ball relative to VSS VIN, VOUT -0.4 1.6V
Storage Te mperature TSTG -55 125 °C 5
Package Theta-ja
(Airow = 0m/s)
Theta-jc Units
134-ball 42.8 5.3 °C/W
168-ball 45.4 2.8
Thermal Resistance
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Input/Output Capacitance
Parameter Symbol
LPDDR2 1066-466 LPDDR2 400-200
Unit NotesMIN MAX MIN MAX
Input capacitance, CK and CK# CCK 1.0 2.0 1.0 2.0 pF 2, 3
Input capacitance delta, CK and CK# CDCK 0 0.20 0 0.25 pF 2, 3, 4
Input capacitance, all other input-
only pins
CI1.0 2.0 1.0 2.0 pF 2, 3, 5
Input capacitance delta, all other input-
only pins
CDI –0.40 +0.40 –0.50 +0.50 pF 2, 3, 6
Input/output capacitance, DQ, DM, DQS,
DQS#
CIO 1.25 2.5 1.25 2.5 pF 2, 3, 7, 8
Input/output capacitance delta, DQS,
DQS#
CDDQS 0 0.25 0 0.30 pF 2, 3, 8, 9
Input/output capacitance delta, DQ, DM CDIO –0.5 +0.5 –0.6 +0.6 pF 2, 3, 8, 10
Notes:
1. TC –25˚C to +105˚C; VDDQ = 1.14–1.3V; VDDCA = 1.14–1.3V; VDD1 = 1.7–1.95V; VDD2 = 1.14–1.3V).
2. This parameter applies to die devices only (does not include package capacitance).
3. This parameter is not subject to production testing. It is veried by design and characterization. The capacitance is measured
according to
JEP147 (procedure for measuring input capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ, VSS, VSSCA,
and
VSSQ applied; all other pins are left oating.
4. Absolute value of CCK - CCK#.
5. CI applies to CS#, CKE, and CA[9:0].
6. CDI = CI - 0.5 × (CCK + CCK#).
7. DM loading matches DQ and DQS.
8. MR3 I/O conguration drive strength OP[3:0] = 0001b (34.3 ohm typical).
9. Absolute value of CDQS and CDQS#.
10. CDIO = CIO - 0.5 × (CDQS + CDQS#) in byte-lane.
11. Maximum external load capacitance on ZQ pin: 5pF.
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Operation or timing that is not specied is illegal, and after such an event, in order to guarantee proper operation, the
LPDDR2 Device must be powered down and then restarted through the specialized initialization sequence before
normal operation can continue.
Recommended DC Operating Conditions
Recommended LPDDR2-S4 DC Operating Conditions
NOTE 1VDD1 uses significantly less power than VDD2
Symbol
LPDDR2-S4B
DRAM Unit
Min Typ Max
VDD1 1.70 1.80 1.95 Core Power1 V
VDD2 1.14 1.20 1.3 Core Power2 V
VDDCA1.141.201.3 Input Buffer Power V
VDDQ 1.14 1.20 1.3 I/O Buffer Powe
rV
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Input Leakage Current
Parameter/Condition Symbol Min Max Unit Notes
Input Leakage current
For CA, CKE, CS_n, CK_t, CK_c
Any input 0V ≤ VIN ≤ VDDCA
(All other pins not under test = 0V)
IL-2 2u
A2
VREF supply leakage current
VREFDQ = VDDQ/2 or VREFCA = VDDCA/2
(All other pins not under test = 0V)
IVREF-1 1u
A1
Notes:
1. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be minimal.
2. Although DM is for input only, the DM leakage shall match the DQ and DQS_t/DQS_c output leakage specication.
Notes:
1. Operating Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement
conditions, please refer to JESD51-2 standard. Operation outside the range is not permitted.
2. Some applications require operation of LPDDR2 in the maximum temperature conditions in the Extended Temperature Range
between 85°C and 105°C case temperature. For LPDDR2 devices, some derating is necessary to operate in this range. See
MR4 and section on Temperature Sensor.
3. Either the device case temperature rating or the temperature sensor (See “Temperature Sensor”) may be used to set an ap-
propriate refresh rate, determine the need for AC timing de-rating and/or monitor the operating temperature.
4. Operation below 85°C is in the Standard Temperature Range.
Parameter/Condition Symbol Min Max Unit
Commercial
Toper
0 85 °C
Industrial -40 85
Automotive, A1 -40 85
Automotive, A2 -40 105
Automotive, A25 -40 115
Operating Temperature Range
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AC and DC Input Levels for Single-Ended CA and CS_n Signals
AC and DC Input Levels for CKE
Single-Ended AC and DC Input Levels for CKE
AC and DC Input Levels for Single-Ended Data Signals
Single-Ended AC and DC Input Levels for CA and CS_n Inputs
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit Notes
MinMaxMinMax
VIHCA(AC)AC input logic high Vref + 0.220Note 2Vref + 0.300Note 2V1, 2
VILCA(AC)AC input logic lowNote 2Vref - 0.220 Note 2Vref - 0.300V1, 2
VIHCA(DC) DC input logic high Vref + 0.130 VDDCAVref + 0.200VDDCA
V1
VILCA(DC)DC input logic low VSSCAVref - 0.130 VSSCAVref - 0.200V 1
VRefCA(DC) Reference Voltage for CA and
CS_n inputs
0.49 * VDDCA0.51 * VDDCA0.49 * VDDCA0.51 * VDDCAV 3, 4
Symbol Parameter MinMax Unit Notes
VIHCKECKE Input High Level 0.8 * VDDCA Note 1V1
VILCKECKE Input Low LevelNote 10.2 * VDDCAV 1
Single-Ended AC and DC Input Levels for DQ and DM
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Unit Notes
MinMaxMinMax
VIHDQ(AC)AC input logic high Vref + 0.220Note 2Vref + 0.300 Note 2V1, 2, 5
VILDQ(AC)AC input logic lowNote 2Vref - 0.220 Note 2Vref - 0.300 V1, 2, 5
VIHDQ(DC) DC input logic high Vref + 0.130 VDDQ Vref + 0.200VDDQV1
VILDQ(DC) DC input logic low VSSQVref - 0.130 VSSQVref - 0.200 V1
VRefDQ(DC)Reference Voltage for
DQ, DM inputs
0.49 * VDDQ 0.51 * VDDQ 0.49 * VDDQ0.51 * VDDQ V3, 4
Notes:
1. For CA and CS_n input only pins. Vref = VrefCA(DC).
2. See “Overshoot and Undershoot Specications”
3. The ac peak noise on VRefCA may not allow VRefCA to deviate from VRefCA(DC) by more than +/-1%
VDDCA (for reference: approx. +/- 12 mV).
4. For reference: approx. VDDCA/2 +/- 12 mV.
AC and DC Input Levels for CKE
Single-Ended AC and DC Input Levels for CKE
AC and DC Input Levels for Single-Ended Data Signals
Single-Ended AC and DC Input Levels for CA and CS_n Inputs
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit Notes
MinMaxMinMax
VIHCA(AC)AC input logic high Vref + 0.220Note 2Vref + 0.300Note 2V1, 2
VILCA(AC)AC input logic lowNote 2Vref - 0.220 Note 2Vref - 0.300V1, 2
VIHCA(DC) DC input logic high Vref + 0.130 VDDCAVref + 0.200VDDCA V1
VILCA(DC)DC input logic low VSSCAVref - 0.130 VSSCAVref - 0.200V 1
VRefCA(DC) Reference Voltage for CA and
CS_n inputs
0.49 * VDDCA0.51 * VDDCA0.49 * VDDCA0.51 * VDDCAV 3, 4
Symbol Parameter MinMax Unit Notes
VIHCKECKE Input High Level 0.8 * VDDCA Note 1V1
VILCKECKE Input Low LevelNote 10.2 * VDDCAV 1
Single-Ended AC and DC Input Levels for DQ and DM
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Unit Notes
MinMaxMinMax
VIHDQ(AC)AC input logic high Vref + 0.220Note 2Vref + 0.300 Note 2V1, 2, 5
VILDQ(AC)AC input logic lowNote 2Vref - 0.220 Note 2Vref - 0.300 V1, 2, 5
VIHDQ(DC) DC input logic high Vref + 0.130 VDDQ Vref + 0.200VDDQV1
VILDQ(DC) DC input logic low VSSQVref - 0.130 VSSQVref - 0.200 V1
VRefDQ(DC)Reference Voltage for
DQ, DM inputs
0.49 * VDDQ 0.51 * VDDQ 0.49 * VDDQ0.51 * VDDQ V3, 4
Note:
1. See “Overshoot and Undershoot Specications”
AC and DC Input Levels for CKE
Single-Ended AC and DC Input Levels for CKE
AC and DC Input Levels for Single-Ended Data Signals
Single-Ended AC and DC Input Levels for CA and CS_n Inputs
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit Notes
MinMaxMinMax
VIHCA(AC)AC input logic high Vref + 0.220Note 2Vref + 0.300Note 2V1, 2
VILCA(AC)AC input logic lowNote 2Vref - 0.220 Note 2Vref - 0.300V1, 2
VIHCA(DC) DC input logic high Vref + 0.130 VDDCAVref + 0.200VDDCA V1
VILCA(DC)DC input logic low VSSCAVref - 0.130 VSSCAVref - 0.200V 1
VRefCA(DC) Reference Voltage for CA and
CS_n inputs
0.49 * VDDCA0.51 * VDDCA0.49 * VDDCA0.51 * VDDCAV 3, 4
Symbol Parameter MinMax Unit Notes
VIHCKECKE Input High Level 0.8 * VDDCA Note 1V1
VILCKECKE Input Low LevelNote 10.2 * VDDCAV 1
Single-Ended AC and DC Input Levels for DQ and DM
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Unit Notes
MinMaxMinMax
VIHDQ(AC)AC input logic high Vref + 0.220Note 2Vref + 0.300 Note 2V1, 2, 5
VILDQ(AC)AC input logic lowNote 2Vref - 0.220 Note 2Vref - 0.300 V1, 2, 5
VIHDQ(DC) DC input logic high Vref + 0.130 VDDQ Vref + 0.200VDDQ
V1
VILDQ(DC) DC input logic low VSSQVref - 0.130 VSSQVref - 0.200
V1
VRefDQ(DC)Reference Voltage for
DQ, DM inputs
0.49 * VDDQ 0.51 * VDDQ 0.49 * VDDQ0.51 * VDDQ
V3
, 4
Notes:
1. For DQ input only pins. Vref = VrefDQ(DC).
2. See “Overshoot and Undershoot Specications”
3. The ac peak noise on VRefDQ may not allow VRefDQ to deviate from VRefDQ(DC) by more than +/-1%
VDDQ (for reference: approx. +/- 12 mV).
4. For reference: approx. VDDQ/2 +/- 12 mV.
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LPDDR2-S4 Refresh Requirement Parameters
Parameter Symbol 2Gb Unit
Number of Banks 8
Refresh Window Tcase ≤ 85°CtREFW 32 ms
Refresh Window
85°C < Tcase ≤ 115°CtREFW 8 ms
Required number of REFRESH
commands (min) R 8192
Average time between
REFRESH commands
(for reference only)
Tcase ≤ 85°C"
REFab tREFI 3.9
us
REFpb tREFIpb 0.4875
Average time between
REFRESH commands
(for reference only)
85°C < Tcase ≤ 115°C"
REFab tREFI 0.977
us
REFpb tREFIpb 0.122
Refresh Cycle time tRFCab 130 ns
Per Bank Refresh Cycle time tRFCpb 60 ns
Burst Refresh Window
= (4 x 8 x tRFCab) tREFBW 4.16 us
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AC TIMINGS
LPDDR2 AC Timing Table
(1,2)
Parameter Symbol min max min tCK
LPDDR2
Unit
8009331066 667533 466 400 333 266 200
400466533 333 266 233 200 166 133 100
min 2.5 33.75 4.3 567.5 10
-100-90 -95
90 95
180 190
-132 -140
132 140
-157 -166
157 166
-175 -185
175 185
-188 -199
188 199
-200 -211
200 211
-209 -221
209 221
-110 -120 -130 -140 -150 -180 -250
100 110 120 130 140 150 180 250
200 220 240 260 280 300 360 500
-147
147
-175
-194
-209
-222
-232
232
222
209
194
175
-162
162
-192
-214
-230
-244
-256
256
244
230
214
192
-177
177
-210
-233
-251
-266
-279
279
266
251
233
210
-191
191
-227
-253
-272
-288
-302
302
288
272
253
227
-206
206
-245
-272
-293
-311
-325
325
311
293
272
245
-221
221
-262
-291
-314
-333
-348
348
333
314
291
262
-265
265
-314
-350
-377
-399
-418
418
399
377
350
314
-368
368
-437
-486
-524
-555
-581
581
555
524
486
437
Max. Frequency ~
Clock Timing
Average Clock Period tCK(avg) ns
001xam
Average high pulse width tCH(avg)54.0nim tCK(avg)
55.0xam
Average low pulse widthtCL(avg)54.0nim tCK(avg)
55.0xam
Absolute Clock Period tCK(abs)min tCK(avg)min + tJIT(per),min ps
Absolute clock HIGH pulse width
(with allowed jitter)
tCH(abs),
allowed
min0.43 tCK(avg)
75.0xam tCK(avg)
Absolute clock LOW pulse width
(with allowed jitter)
tCL(abs),
allowed
min0.43 tCK(avg)
75.0xam tCK(avg)
Clock Period Jitter (with allowed jitter) tJIT(per),
allowed
min ps
max
Maximum Clock Jitter between two
consecutive clock cycles (with allowed jitter)
tJIT(cc),
allowed max ps
Duty cycle Jitter (with allowed jitter)tJIT(duty),
allowed
minmin((tCH(abs),min - tCH(avg),min), (tCL(abs),min - tCL(avg),min)) * tCK(avg)ps
max max((tCH(abs),max - tCH(avg),max), (tCL(abs),max - tCL(avg),max)) * tCK(avg)ps
Cumulative error across 2 cycles tERR(2per),
allowed
min ps
max
Cumulative error across 3 cycles tERR(3per),
allowed
min ps
max
Cumulative error across 4 cycles tERR(4per),
allowed
min ps
max
Cumulative error across 5 cycles tERR(5per),
allowed
min ps
max
Cumulative error across 6 cycles tERR(6per),
allowed
min ps
max
Cumulative error across 7 cycles tERR(7per),
allowed
min ps
max
MHz
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Cumulative error across 8 cycles tERR(8per),
allowed
min
ps
max
Cumulative error across 9 cycles tERR(9per),
allowed
min
ps
max
Cumulative error across 10 cycles tERR(10per),
allowed
min
ps
max
Cumulative error across 11 cycles tERR(11per),
allowed
min
ps
max
Cumulative error across 12 cycles tERR(12per),
allowed
min
ps
max
Cumulative error across n = 13, 14 . . .
49, 50 cycles
tERR(nper),
allowed
min
tERR(nper),allowed,min = (1 + 0.68ln(n)) * tJIT(per),allowed,min
ps
max
tERR(nper),allowed,max = (1 + 0.68ln(n)) * tJIT(per),allowed,max
LPDDR2 AC Timing Table (1,2)
Parameter Symbol min max min t CK
LPDDR2
Unit
8009331066 667533 466 400 333 266200
-214-229-217
229 217
-237-224
237 224
-244-231
244 231
-250-237
250 237
-256-242
256 242
-266 -290 -314 -338 -362 -435 -604
-249 -274 -299 -324 -349 -374 -449 -624
-257 -282 -308 -334 -359 -385 -462 -641
-263 -289 -316 -342 -368 -395 -474 -658
-269 -296 -323 -350 -377 -403 -484 -672
269 296 323 350 377 403 484 672
263 289 316 342 368 395 474 658
257 282 308 334 359 385 462 641
249 274 299 324 349 374 449 624
214 266 290 314 338 362 435 604
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ZQ Calibration Parameters
Initialization Calibration Time t
ZQINIT
min
1us
Long Calibration Time t
ZQCL
min6
360ns
Short Calibration Time t
ZQCS
min6
90 ns
Calibration Reset Time t
ZQRESET
min3
50 ns
Read Parameters
DQS output access time from
CK/CK# t
DQSCK
min
2500
5500 ps
ps
ps
ps
ps
ps
max
DQSCK Delta Short
(4)
t
DQSCKDS
max
DQSCK Delta Medium
(5)
t
DQSCKDM
max
DQSCK Delta Long
(6)
t
DQSCKDL
max
DQS - DQ skewt
DQSQ
max
Data hold skew factor t
QHS
max
DQS Output High Pulse Width t
QSH
min
t
CH
(abs) - 0.05 t
CK
(avg)
DQS Output Low Pulse Width t
QSL
min
t
CL
(abs) - 0.05 t
CK
(avg)
Data Half Period t
QHP
min
min(t
QSH
, t
QSL
)t
CK
(avg)
DQ / DQS output hold time from DQS t
QH
min
t
QHP
- t
QHS
ps
Read preamble
(8)
t
RPRE
min
0.9 t
CK
(avg)
Read postamble
(9)
t
RPST
min
t
CL
(abs) - 0.05 t
CK
(avg)
DQS low-Z from clock
(7)
t
LZ(DQS)
min
t
DQSCK(MIN)
- 300 ps
DQ low-Z from clock
(7)
t
LZ(DQ)
min
t
DQSCK(MIN)
- (1.4 * t
QHS(MAX)
)ps
DQS high-Z from clock
(7)
t
HZ(DQS)
max
t
DQSCK(MAX)
- 100 ps
DQ high-Z from clock
(7)
t
HZ(DQ)
max
t
DQSCK(MAX)
+ (1.4 * t
DQSQ(MAX)
)ps
LPDDR2 AC Timing Table(1,2)
Parameter Symbol min max min t
CK
LPDDR2
Unit
8009331066667 533466 400333 266 200
400 500 600
540 900450330 380
680 780
920 1050
200 220
230 260
670 77010801350 1800
1050 1800900 1350 1550 1900 2000 2100
1400 2400120018002100 - --
280240 340 370 700
480280 340 400 450 600 7501000
(3)
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Write Parameters
DQ and DM input hold time (Vref based) tDH min
ps
DQ and DM input setup time (Vref based) tDS min
ps
DQ and DM input pulse widthtDIPW min
0.35 tCK(avg)
Write command to 1st DQS
latching transition tDQSS
min
0.75 tCK(avg)
52.1
xam
DQS input high-level widthtDQSH min
0.4 tCK(avg)
DQS input low-level widthtDQSL min
0.4 tCK(avg)
DQS falling edge to CK setup time tDSSmin
0.2 tCK(avg)
DQS falling edge hold time from CK tDSHmin
0.2 tCK(avg)
Write postambletWPST min
0.4 tCK(avg)
Write preamble tWPRE min
0.35 tCK(avg)
LPDDR2 AC Timing Table
(1,2)
Parameter Symbol min max min tCK
LPDDR2
Unit
8009331066 667 533 466 400 333 266 200*5
270210 235
210 235
350 430 450 480 600 750 1000
270 350 430 450 480 600 750 1000
(3)
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CKE Input Parameters
CKE min. pulse width (high and low pulse width) tCKEmin3
3t
CK
(avg)
CKE input setup time tISCKE(10) 52.0 nim
t
CK
(avg)
CKE input hold time tIHCKE(11) 52.0nim
t
CK
(avg)
Command Address Input Parameters
Address and control input setup time (Vref based) tIS (12) min
520460370290220 250
220 250 290
600 740 900 1150
520460370 600 740 900 1150
ps
Address and control input hold time (Vref based) tIH min
ps
Address and control input pulse widthtIPWmin
0.40 t
CK
(avg)
Boot Parameters (10 MHz - 55 MHz)
Clock Cycle Time tCKb
max -
100ns
81nim
CKE Input Setup Time tISCKEb min-
2.5 ns
CKE Input Hold Time tIHCKEb min-
2.5ns
Address & Control Input Setup Time tISbmin-
1150 ps
Address & Control Input Hold Time tIHbmin-
1150 ps
DQS Output Data Access Time
from CK/CK# tDQSCKb
min-
2.0 ns
0.01xam
Data Strobe Edge to
Ouput Data Edge tDQSQb - 1.2 tDQSQbmax-
1.2ns
Data Hold Skew Factor tQHSb max-
1.2ns
Mode Register Parameters
MODE REGISTER Write command period tMRWmin5
5t
CK
(avg)
Mode Register Read command period tMRRmin2
2t
CK
(avg)
LPDDR2 AC Timing Table
(1,2)
Parameter Symbol min max min t CK
LPDDR2
Unit
8009331066 667533 466 400333 266200
(3)
(12)
(13,14,15)
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LPDDR2 SDRAM Core Parameters
Read Latency RL min3
33 t
CK
(avg)
223
45687
44
1nimLWycnetaL etirW
11 t
CK
(avg)
ACTIVE to ACTIVE command period t
RC
min
t
RAS
+ t
RPab
(with all-bank Precharge)
t
RAS
+ t
RPpb
(with per-bank Precharge) ns
CKE min. pulse width during Self-Refresh
(low pulse width during Self-Refresh)t
CKESR
min3
15 15 ns
Self refresh exit to next valid command delay t
XSR
min2
t
RFCab
+ 10 ns
Exit power down to next valid command delay t
XP
min2
7.5 7.5 ns
LPDDR2-S4 CAS to CAS delay t
CCD
min2
2 2 t
CK
(avg)
Internal Read to Precharge command delay t
RTP
min2
7.5 7.5 ns
RAS to CAS Delayt
RCD
Fast 3
15 15 ns
81
3pyT
18 ns
Row Precharge Time
(single bank) t
RPpb
Fast 3
15 15 ns
81
3pyT
18 ns
Row Precharge Time
(all banks)
t
RPab
8-bank
81
3tsaF
18 ns
12
3pyT
21 ns
Row Active Time t
RAS
min3
42 42 ns
max-
70 70 us
Write Recovery Time t
WR
min3
15 15 ns
Internal Write to Read
Command Delay t
WTR
min2
7.5 10 ns
Active bank A to Active bank Bt
RRD
min2
10 10 ns
Four Bank Activate Window t
FAW
min8
50 50 60 ns
Minimum Deep Power Down Time t
DPD
min
500 500 us
LPDDR2 AC Timing Table
(1,2)
Parameter Symbol min max min t
CK
LPDDR2
Unit
8009331066 667533 466 400 333 266 200
(16)
(18)
(19)
(19)
(19)
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LPDDR2 Temperature De-Rating(17)
tDQSCKDe-Rating tDQSCK
(Derated) sp00060265xam
Core Timings Te mperature De-Rating
tRCD
(Derated) mintRCD + 1.875 ns
tRC
(Derated) mintRC + 1.875 ns
tRAS
(Derated) mintRAS + 1.875 ns
tRP
(Derated) mintRP + 1.875 ns
tRRD
(Derated) mintRRD + 1.875 ns
Table 103 — LPDDR2 AC Timing Table
Parameter Symbol min
max
min
tCK
LPDDR2
Unit
1066 933 800667533466 400 333 266 200
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Notes:
1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine device capabilities.
2. All AC timings assume an input slew rate of 1 V/ns.
3. READ, WRITE, and input setup and hold values are referenced to VREF.
4. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a contigu-
ous sequence of bursts in a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the
system is < 10°C/s. Values do not include clock jitter.
5. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 1.6μs
rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is < 10 °C/s. Values do not
include clock jitter.
6. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 32ms
rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is < 10 °C/s. Values do not
include clock jitter.
7. For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point when the signal crosses the transition
threshold (VTT). tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These
parameters are not referenced to a specic voltage level but to the time when the device output is no longer driving (for tRPST,
tHZ(DQS) and tHZ(DQ)), or begins driving (for tRPRE, tLZ(DQS), tLZ(DQ)). Figure shows a method to calculate the point when
device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two differ-
ent voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters
tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are dened as single-ended. The timing parameters tRPRE and tRPST are deter-
mined from the differential signal DQS, /DQS.
VOL + 2x X mV
VOL + X mV
VOH - X mV
VOH - 2x X mV
2x X
X
2x Y
V
OH
VOL
Y
T1 T2
VTT - Y mV
VTT VTT
VTT - 2 x Y mV
VTT + 2 x Y mV
VTT + Y mV tLZ(DQS), tLZ(DQ)
tHZ(DQS), tHZ(DQ)
T1 T2
Start driving point = 2 × T1 - T2 End driving point = 2 × T1 - T2
a
c
t
u
a
l
w
a
v
e
f
o
r
m
8. Measured from the point when DQS, DQS# begins driving the signal to the point when DQS, DQS# begins driving the rst ris-
ing strobe edge.
9. Measured from the last falling strobe edge of DQS, DQS# to the point when DQS, DQS# nishes driving the signal.
10. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to CK, CK# crossing.
11. CKE input hold time is measured from CK, CK# crossing to CKE reaching a HIGH/LOW voltage level.
12. Input set-up/hold time for signal (CA[9:0], CS#).
13. To ensure device operation before the device is congured, a number of AC boot-timing parameters are dened in this table.
Boot parameter symbols have the letter b appended (for example, tCK during boot is tCKb).
14. The LPDDR device will set some mode register default values upon receiving a RESET (MRW) command as specied in ―
Mode Register Denition‖.
15. The output skew parameters are measured with default output impedance settings using the reference load.
16. The minimum tCK column applies only when tCK is greater than 6ns.
17. Timing derating applies for operation at 85°C to 105°C when the requirement to derate is indicated by mode register 4 op-
code.
18. Use even addressing whenever possible to optimize for long-life.
19. The parts support the parameter values corresponding to Typical. For parts that support Fast values, contact ISSI.
Output Transition Timing
(Note #7)
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Notes:
1. The setup and hold timing shown applies to all commands.
2. Setup and hold conditions also apply to the CKE pin. For timing diagrams related to the CKE pin, see Power-Down .
Command Input Setup and Hold Timing
t
IS
t
IH
CommandNOP Command
T0 T1 T2 T3
CK#
CK
CS#
CA
rise
CA[9:0]
CMD
Don’t Care
Transitioning data
CA
fall
CA
rise
CA
fall
CA
rise
CA
fall
CA
rise
CA
fall
NOP
t
IS
t
IH
t
IS
t
IH
t
IS
t
IH
V
IL(AC)
V
IH(DC)
V
IH(AC)
V
IL(DC)
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Note: AC/DC referenced for 1 V/ns CA and /CS slew rate and 2 V/ns differential CK, /CK slew rate.
CA and /CS Setup, Hold, and Derating
The For all input signals (CA and /CS), the total required setup time (tIS) and hold time (tIH) is
calculated by adding the data sheet tIS (base) and tIH (base) values to the 〔tIS and 〔tIH derating
values, respectively. Example: tIS (total setup time) = tIS(base) + 〔tIS.
Setup (tIS) typical slew rate for a rising signal is defined as the slew rate between the last cross-
ing of VREF(DC) and the first crossing of VIH(AC)min. The setup (tIS) typical slew rate for a falling
signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of
VIL(AC)max. If the actual signal is always earlier than the typical slew rate line between the shad-
ed VREF(DC)-to-(AC) region, use the typical slew rate for the derating value. If the actual signal
is later than the typical slew rate line anywhere between the shaded VREF(DC)-to-AC region, the
slew rate of a tangent line to the actual signal from the AC level to the DC level is used for the de-
rating value.
The hold (tIH) typical slew rate for a rising signal is defined as the slew rate between the last cross-
ing of VIL(DC)max and the first crossing of VREF(DC). The hold (tIH) typical slew rate for a falling
signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing
of VREF(DC). If the actual signal is always later than the typical slew rate line between the shaded
DC-to-VREF(DC) region, use the typical slew rate for the derating value. If the actual signal is
earlier than the typical slew rate line anywhere between the shaded DC-to-VREF(DC) region, the
slew rate of a tangent line to the actual signal from the DC level to VREF(DC) level is used for the
derating value.
For a valid transition, the input signal must remain above or below VIH/VIL(AC) for a specified time,
tVAC. For slow slew rates the total setup time could be a negative value (that is, a valid input signal
will not have reached VIH/VIL(AC) at the time of the rising clock transition). A valid input signal is
still required to complete the transition and reach VIH/VIL(AC).
For slew rates between the values listed, the derating values are obtained using linear interpola-
tion. Slew rate values are not typically subject to production testing. They are verified by design
and characterization.
CA and /CS Setup and Hold Base Values (> 400 MHz, 1 V/ns slew rate)
Parameter
Data Rate
Reference
tIS (base) VIH /VIL(AC) = V REF(DC) ±220mV
tIH (base)
800
70
160
933
30
120
1066
0
90
667
150
240
533
240
330
466
300
390 VIH /VIL(DC) = V REF(DC) ±130mV
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Derating Values for AC/DC-based tIS/tIH (AC220) - tIS, tIH derating in [ps], AC/DC-based
CK, CK# Dierential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
˂tIS ˂tIH ˂tIS ˂tIH ˂tIS ˂tIH ˂tIS ˂tIH ˂tIS ˂tIH ˂tIS ˂tIH ˂tIS ˂tIH ˂tIS ˂tIH
CA, CS# slew
rate V/ns
2.0 110 65 110 65 110 65
1.5 74 43 73 43 73 43 89 59
1.0 00000016 16 32 32
0.9 -3 -5 -3 -5 13 11 29 27 45 43
0.8 -8 -13 8324 19 40 35 56 55
0.7 2-61810342650466
67
8
0.6 10 -3 26 13 42 33 58 65
0.5 4-420163
64
8
0.4 -721
73
4
Note: Shaded cells are not supported.
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Required Time for Valid Transition with tVAC Above VIH(AC) and Below VIL(AC)
Typical Slew Rate and tVAC: tIS for CA and /CS Relative to Clock
Slew Rate (V/ns)
tVAC at 300mV (ps) tVAC at 220mV (ps)
Min Max Min Max
>2.0 75 – 175 –
2.0 57 – 170 –
1.5 50 – 167 –
1.0 38 – 163 –
0.9 34 – 162 –
0.8 29 – 161 –
0.7 22 – 159 –
0.6 13 – 155 –
0.5 0–150 –
<0.5 0–150 –
VREF to AC
region
VREF to AC
region
Setup slew rate
rising signal
Setup slew rate
falling signal
ΔTF ΔTR
VREF(DC) - VIL(AC)max
ΔTF
=
VIH(AC)min - V REF(DC)
ΔTR
=
Typical
slew rate
VSSQ
DQS#
DQS
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
Typical
slew rate
tVAC
tDH
tDS tDS
tDH
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Typical Slew Rate – tIH for CA and CS# Relative to Clock
Hold slew rate
falling signal
Hold slew rate
rising signal
VREF(DC) - VIL(DC)max
ΔTR
=
VIH(DC)min - V REF(DC)
ΔTF
=
ΔTR ΔTF
Typical
slew rate
DC to V REF
region
VSSQ
DQS#
DQS
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
DC to V REF
region
Typical
slew rate
tDH
tDS tDS
tDH
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Tangent Line: tIS for CA and /CS Relative to Clock
ΔTF ΔTR
Setup slew rate
rising signal
Setup slew rate
falling signal
tangent line [V
REF(DC)
- V
IL(AC)max
]
ΔTF
=
tangent line [V
IH(AC)min
- V
REF(DC)
]
ΔTR
=
VSSQ
DQS#
DQS
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
Typical line
Tangent line
Typical
line
Tangent line
VREF to AC
region
VREF to AC
region
tVAC
tDH
tDS tDS
tDH
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Tangent Line: tIH for CA and /CS Relative to Clock
Tangent
line
DC to V
REF
region
VSSQ
VDDQ
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(DC)max
VIH(AC)min
DC to V
REF
region Tangent
line
DQS
DQS#
Hold slew rate
falling signal
ΔTF
ΔTR
tangent line [VIH(DC)min - V REF(DC) ]
ΔTF
=
Typical line
Hold slew rate
rising signal
tangent lin e [V REF(DC) - VIL(DC)max ]
ΔTR
=
Nominal
line
tDH
tDS tDS
tDH
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Data Setup, Hold, and Slew Rate Derating
For all input signals (DQ, DM) calculate the total required setup time (tDS) and hold time (tDH) by
adding the data sheet tDS(base) and tDH(base) values to the tDS and tDH derating values, re-
spectively . Example: tDS = tDS(base) + tDS.
The typical tDS slew rate for a rising signal is defined as the slew rate between the last crossing
of VREF(DC) and the first crossing of VIH(AC)min. The typical tDS slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)
max .
If the actual signal is consistently earlier than the typical slew rate , the area shaded gray between
the VREF(DC) region and the AC region, use the typical slew rate for the derating value. If the ac-
tual signal is later than the typical slew rate line anywhere between the shaded VREF(DC) region
and the AC region, the slew rate of a tangent line to the actual signal from the AC level to the DC
level is used for the derating value .
The typical tDH slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(DC)max and the first crossing of VREF(DC). The typical tDH slew rate for a falling signal is de-
fined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC)
If the actual signal is consistently later than the typical slew rate line between the shaded DC-level-
to-VREF(DC) region, use the typical slew rate for the derating value. If the actual signal is earlier
than the typical slew rate line anywhere between shaded DC to- VREF(DC) region, the slew rate of
a tangent line to the actual signal from the DC level to the VREF(DC) level is used for the derating
value .
For a valid transition, the input signal must remain above or below VIH/VIL(AC) for the specified
time, tVAC . The total setup time for slow slew rates could be negative (that is, a valid input signal
may not have reached VIH/VIL(AC) at the time of the rising clock transition). A valid input
signal is still required to complete the transition and reach VIH/VIL(AC).
For slew rates between the values listed in the tables on the following page, the derating values
can be obtained using linear interpolation. Slew rate values are not typically subject to production
testing. They are verified by design and characterization.
Data Setup and Hold Base Values (>400 MHz, 1 V/ns slew rate)
Parameter
Data Rate
Reference
tDS (base) VIH /VIL(AC) = V REF(DC) ±220mV
tDH (base)
800
50
140
933
15
105
1066
-10
80
667
130
220
533
210
300
466
230
320 VIH /VIL(DC) = V REF(DC) ±130mV
Note: AC/DC referenced for 1 V/ns DQ, DM slew rate, and 2 V/ns differential DQS/DQS# slew rate.
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Derating Values for AC/DC-based tDS/tDH (AC220) - 〔tDS, 〔tDH derating in [ps], AC/DC-based
Derating Values for AC/DC-based tDS/tDH (AC300) - tDS, tDH derating in [ps], AC/DC-based
Note: Shaded cells are not supported.
Note: Shaded cells are not supported.
˂tDS, ˂tDH derating in ps
DQS, DQS# Dierential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH
DQ, DM
slew
rate
V/ns
2.0 110 65 110 65 110 65
1.5 74 43 73 43 73 43 89 59
1.0 0 0000016 16 32 32
0.9 -3 -5 -3 -5 13 11 29 27 45 43
0.8 -8 -13 8324 19 40 35 56 55
0.7 2-61810342650466
67
8
0.6 10 -3 26 13 42 33 58 65
0.5 4-420163
64
8
0.4 -721
73
4
DQS, DQS# Dierential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH ˂tDS ˂tDH
DQ, DM
slew
rate V/ns
2.0 150 100 150 100 150 100
1.5 100 67 100 67 100 67 116 83
1.0 00000016 16 32 32
0.9 -4 -8 -4 -8 12 828244440
0.8 -12 -20 4-4201236285248
0.7 -3 -18 13 -2 29 14 45 34 61 66
0.6 2 -21 18 -5 34 15 50 47
0.5 -12 -32 4 -12 20 20
0.4 4 -35 -40 -11 -8
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Required tVAC Above VIH(AC) or Below VIL(AC) for Valid Transition
Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe
Slew Rate (V/ns)
tVAC at 300mV (ps) tVAC at 220mV (ps)
Min Max Min Max
>2.0 75 – 175 –
2.0 57 – 170 –
1.5 50 – 167 –
1.0 38 – 163 –
0.9 34 – 162 –
0.8 29 – 161 –
0.7 22 – 159 –
0.6 13 – 155 –
0.5 0–150 –
<0.5 0–150 –
VREF to AC
region
VREF to AC
region
Setup slew rate
rising signal
Setup slew rate
falling signal
ΔTF ΔTR
VREF(DC) - VIL(AC)max
Δ
TF
=
VIH(AC)min - V REF(DC)
Δ
TR
=
Typical
slew rate
VSSQ
DQS#
DQS
VDDQ
VIH(DC)min
VREF(DC)
V
IL(AC)max
V
IL(DC)max
VIH(AC)min
Typical
slew rate
tVAC
tDH
tDS tDS
tDH
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Typical Slew Rate: tDH for DQ Relative to Strobe
Hold slew rate
falling signal
Hold slew rate
rising signal
VREF(DC) - VIL(DC)max
ΔTR
=
VIH(DC)min - V REF(DC)
ΔTF
=
ΔTR ΔTF
Typical
slew rate
DC to V REF
region
VSSQ
DQS#
DQS
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
DC to V REF
region
Typical
slew rate
tDH
tDS tDS
tDH
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Tangent Line: tDS for DQ with Respect to Strobe
ΔTF ΔTR
Setup slew rate
rising signal
Setup slew rate
falling signal
tangent line [V
REF(DC)
- V
IL(AC)max
]
ΔTF
=
tangent line [V
IH(AC)min
- V
REF(DC)
]
ΔTR
=
VSSQ
DQS#
DQS
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
Typical line
Tangent line
Typical
line
Tangent line
VREF to AC
region
VREF to AC
region
tVAC
tDH
tDS tDS
tDH
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Tangent Line: tDH for DQ with Respect to Strobe
Tangent
line
DC to V
REF
region
VSSQ
VDDQ
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(DC)max
VIH(AC)min
DC to V
REF
region Tangent
line
DQS
DQS#
Hold slew rate
falling signal
ΔTF
ΔTR
tangent line [VIH(DC)min - V REF(DC) ]
ΔTF
=
Typical line
Hold slew rate
rising signal
tangent lin e [V REF(DC) - VIL(DC)max ]
ΔTR
=
Nominal
line
tDH
tDS tDS
tDH
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IDD Specifications and Conditions
The following definitions and conditions are used in the IDD measurement tables unless stated
otherwise:
•LOW:VIN≤ VIL(DC)max
•HIGH:VIN≥ VIH(DC)min
•STABLE:InputsarestableataHIGHorLOWlevel
•SWITCHING:SeeTablesbellow
Switching for CA Input Signal
CK Rising/
CK#Falling
CK Falling/
CK# Rising
CK Rising/
CK#Falling
CK Falling/
CK# Rising
CK Rising/
CK#Falling
CK Falling/
CK# Rising
CK Rising/
CK#Falling
CK Falling/
CK# Rising
Cycle N N + 1 N + 2 N + 3
CS# HIGH HIGH HIGH HIGH
CA0 HLLLL
HHH
CA1 HHHLLL
LH
CA2 HLLLL
HHH
CA3 HHHLLL
LH
CA4 HLLLL
HHH
CA5 HHHLLL
LH
CA6 HLLLL
HHH
CA7 HHHLLL
LH
CA8 HLLLL
HHH
CA9 HHHLLL
LH
Notes:
1. /CS must always be driven HIGH.
2. For each clock cycle, 50% of the CA bus is changing between HIGH and LOW.
3. The noted pattern (N, N + 1, N + 2, N + 3...) is used continuously during IDD measurement for IDD values that require
switching on the CA bus
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Notes:
1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle.
2. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4R.
Notes:
1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle.
2. Data masking (DM) must always be driven LOW.
3. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4R.
Switching for IDD4R
Switching for IDD4W
Clock CKE CS#
Clock Cycle
Number Command CA[2:0] CA[9:3] All DQ
Rising HL N Read_Rising HLH LHLHLHL L
Falling HL N Read_Falling LLL LLLLLLL L
Rising HH N +1 NOP LLL LLLLLLL H
Falling HH N + 1 NOP HLH LHLLHLH L
Rising HL N + 2 Read_Rising HLH LHLLHLH H
Falling HL N + 2 Read_Falling LLL HHHHHHH H
Rising HH N + 3 NOP LLL HHHHHHH H
Falling HH N + 3 NOP HLH LHLHLHL L
Clock CKE CS#
Clock Cycle
Number Command CA[2:0] CA[9:3] All DQ
Rising HL NWrite_Rising LLH LHLHLHL L
Falling HL NWrite_Falling LLL LLLLLLL L
Rising HH N +1 NOP LLL LLLLLLL H
Falling HH N + 1 NOP HLH LHLLHLH L
Rising HL N + 2Write_Rising LLH LHLLHLH H
Falling HL N + 2Write_Falling LLL HHHHHHH H
Rising HH N + 3 NOP LLL HHHHHHH H
Falling HH N + 3 NOP HLH LHLHLHL L
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IDD Specification Parameters and Operating Conditions
Parameter/Condition Symbol Power Supply Notes
Operating one bank active-precharge current (SDRAM): tCK = tCKmin;
tRC = tRCmin; CKE is HIGH; CS# is HIGH between valid commands; CA bus in-
puts are switching; Data bus inputs are stable
IDD01 VDD1
IDD02 VDD2
IDD0,in VDDCA , V DDQ 4
Idle power-down standby current: tCK = tCKmin; CKE is LOW; CS# is HIGH;
All banks are idle; CA bus inputs are switching; Data bus inputs are stable
IDD2P1 VDD1
IDD2P2 VDD2
IDD2P,in VDDCA , V DDQ 4
Idle power-down standby current with clock stop: CK = LOW, CK# =
HIGH; CKE is LOW; CS# is HIGH; All banks are idle; CA bus inputs are stable;
Data bus inputs are stable
IDD2PS1 VDD1
IDD2PS2 VDD2
IDD2PS,in VDDCA , V DDQ 4
Idle non-power-down standby current: tCK = tCKmin; CKE is HIGH; CS# is
HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are sta-
ble
IDD2N1 VDD1
IDD2N2 VDD2
IDD2N,in VDDCA , V DDQ 4
Idle non-power-down standby current with clock stopped: CK = LOW;
CK# = HIGH; CKE is HIGH; CS# is HIGH; All banks are idle; CA bus inputs are
stable; Data bus inputs are stable
IDD2NS1 VDD1
IDD2NS2 VDD2
IDD2NS,in VDDCA , V DDQ 4
Active power-down standby current: tCK = tCKmin; CKE is LOW; CS# is
HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are
stable
IDD3P1 VDD1
IDD3P2 VDD2
IDD3P,in VDDCA , V DDQ 4
Active power-down standby current with clock stop: CK = LOW, CK# =
HIGH; CKE is LOW; CS# is HIGH; One bank is active; CA bus inputs are stable;
Data bus inputs are stable
IDD3PS1 VDD1
IDD3PS2 VDD2
IDD3PS,in VDDCA , V DDQ 4
Active non-power-down standby current: tCK = tCKmin; CKE is HIGH; CS#
is HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are
stable
IDD3N1 VDD1
IDD3N2 VDD2
IDD3N,in VDDCA , V DDQ 4
Active non-power-down standby current with clock stopped: CK =
LOW, CK# = HIGH CKE is HIGH; CS# is HIGH; One bank is active; CA bus inputs
are stable; Data bus inputs are stable
IDD3NS1 VDD1
IDD3NS2 VDD2
IDD3NS,in VDDCA , V DDQ 4
Operating burst READ current: tCK = tCKmin; CS# is HIGH between valid
commands; One bank is active; BL = 4; RL = RL (MIN); CA bus inputs are
switching; 50% data change each burst transfer
IDD4R1 VDD1
IDD4R2 VDD2
IDD4R,in VDDCA
IDD4RQ VDDQ 5
Operating burst WRITE current: tCK = tCKmin; CS# is HIGH between valid
commands; One bank is active; BL = 4; WL = WLmin; CA bus inputs are switch-
ing; 50% data change each burst transfer
IDD4W1 VDD1
IDD4W2 VDD2
IDD4W,in VDDCA , V DDQ 4
All-bank REFRESH burst current: tCK = tCKmin; CKE is HIGH between valid
commands; tRC = tRFCabmin; Burst refresh; CA bus inputs are switching; Data
bus inputs are stable
IDD51 VDD1
IDD52 VDD2
IDD5,in VDDCA , V DDQ 4
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Parameter/Condition Symbol Power Supply Notes
All-bank REFRESH average current: tCK = tCKmin; CKE is HIGH between
valid commands; tRC = tREFI; CA bus inputs are switching; Data bus inputs are
stable
IDD5AB1 VDD1
IDD5AB2 VDD2
IDD5AB,in VDDCA , V DDQ 4
Per-bank REFRESH average current: tCK = tCKmin; CKE is HIGH between
valid commands; tRC = tREFI/8; CA bus inputs are switching; Data bus inputs
are stable
IDD5PB1 VDD1
IDD5PB2 VDD2
IDD5PB,in VDDCA , V DDQ 4
Self refresh current (–25˚C to +85˚C): CK = LOW, CK# = HIGH; CKE is LOW;
CA bus inputs are stable; Data bus inputs are stable; Maximum 1x self refresh
rate
IDD61 VDD1 6
IDD62 VDD2 6
IDD6,in VDDCA , V DDQ 4, 6
Self refresh current (+85˚C to +105˚C): CK = LOW, CK# = HIGH; CKE is
LOW; CA bus inputs are stable; Data bus inputs are stable
IDD6ET1 VDD1 6, 7
IDD6ET2 VDD2 6, 7
IDD6ET,in VDDCA , V DDQ 4, 6, 7
Deep power-down current: CK = LOW, CK# = HIGH; CKE is LOW; CA bus in-
puts are stable; Data bus inputs are stable
IDD81 VDD1 7
IDD82 VDD2 7
IDD8,in VDDCA , V DDQ 4, 7
Notes:
1. Published IDD values are the maximum of the distribution of the arithmetic mean.
2. IDD current specications are tested after the device is properly initialized.
3. The 1x self refresh rate is the rate at which the device is refreshed internally during self refresh, before going into the extended
temperature range.
4. Measured currents are the summation of VDDQ and VDDCA.
5. Guaranteed by design with output reference load and RON = 40 ohm.
6. This is the general denition that applies to full-array SELF REFRESH).
7. IDD6ET and IDD8 are typical values, are sampled only, and are not tested.
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IDD SPECIFICATIONS
V
DD2
, V
DDQ
, V
DDCA
= 1.14–1.30V; V
DD1
= 1.70–1.95V
Parameter Supply
Speed Grade
Unit-25-18 -3
IDD01 VDD1 1010 10 mA
IDD02 VDD2 50 50
IDD0,in VDDCA + VDDQ 6.5 6.5
IDD2P1 VDD1 400 400 μA
IDD2P2 VDD2 1800 1800
IDD2P,in VDDCA + VDDQ 200 200
IDD2PS1 VDD1 400 400 μA
IDD2PS2 VDD2 1800 1800
IDD2PS,in VDDCA + VDDQ 200 200
IDD2N1 VDD1 0.6 0.6 mA
IDD2N2 VDD2 15 15
IDD2N,in VDDCA + VDDQ 6.5 6.5
IDD2NS1 VDD1 0.6 0.6 mA
IDD2NS2 VDD2 88
IDD2NS,in VDDCA + VDDQ 6.5 6.5
IDD3P1 VDD1 mA
IDD3P2 VDD2 10 10
IDD3P,in VDDCA + VDDQ 0.2 0.2
IDD3PS1 VDD1 mA
IDD3PS2 VDD2 10 10
IDD3PS,in VDDCA + VDDQ
IDD3N1 VDD1 1.5 1.5 mA
IDD3N2 VDD2 20 20
IDD3N,in VDDCA + VDDQ
IDD3NS1 VDD1 1.5 1.5 mA
IDD3NS2 VDD2 15 15
IDD3NS,in VDDCA + VDDQ
IDD4R1 VDD1 22mA
IDD4R2 VDD2 160 140
IDD4R,in VDDCA 6.5 6.5
IDD4W1 VDD1 22mA
IDD4W2 VDD2 170 150
IDD4W,in VDDCA + VDDQ 36.5 36.5
IDD51 VDD1 35
35
mA
IDD52 VDD2 143 143
IDD5,in VDDCA + VDDQ
50
6.5
400
1800
200
400
1800
200
0.6
15
6.5
6.5 6.56.5
6.5 6.56.5
6.5 6.56.5
0.6
8
6.5
11 1
10
0.2
0.2 0.20.2
10
1.5
20
1.5
15
2
210
6.5
2
220
36.5
35
143
11 1
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IDD SPECIFICATIONS (Continued)
IDD6 Partial-Array Self Refresh Current
V
DD2
, V
DDQ
, V
DDCA
= 1.14–1.30V; V
DD1
= 1.70–1.95V
Parameter Supply
Speed Grade
Unit-25 -3
IDD5PB1 VDD1 22mA
IDD5PB2 VDD2 18 18
IDD5PB,in VDDCA + VDDQ 6.5 6.5
IDD5AB1 VDD1 22mA
IDD5AB2 VDD2 18 18
IDD5AB,in VDDCA + VDDQ
IDD61 VDD1 850 850 μA
IDD62 VDD2 3500 3500
IDD6,in VDDCA + VDDQ 200 200
IDD81 VDD1 300 300 μA
IDD82 VDD2 600 600
IDD8,in VDDCA + VDDQ
-18
2
18
6.5
6.5 6.56.5
2
18
850
3500
200
200 200200
300
600
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
PASR Supply -40oC to +85oC Unit
Full array VDD1 850
μA
VDD2 3500
VDDi 200
1/2 array VDD1
750
VDD2 3000
VDDi
1/4 array VDD1 650
VDD2
2700
VDDi
1/8 array VDD1 600
VDD2 2500
VDDi
+85oC to +105oC
3000
10,000
300
200 300
200 300
200 300
2000
7000
1500
6000
1200
5000
VDD2
VDDCA + VDDQ
μA
400 400 400
3000 3000 3000
10,000 10,000 10,000
IDD6ET1
IDD6ET2
IDD6ET,in
VDD1
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VREF Tolerances
The DC tolerance limits and AC noise limits for the reference voltages VREFCA and VREFDQ are
illustrated below. This figure shows a valid reference voltage VREF(t) as a function of time. VDD is
used in place of VDDCA for VREFCA, and VDDQ for VREFDQ. VREF(DC) is the linear average of
VREF(t) over a very long period of time (for example, 1 second) and is specified as a fraction of the
linear average of VDDQ or VDDCA, also over a very long period of time (for example, 1 second).
This average must meet the MIN/MAX requirements in Table of Single-Ended AC and DC Input
Levels for CA and CS_n Inputs. Additionally, VREF(t) can temporarily deviate from VREF(DC)
by no more than ±1% VDD. VREF(t) cannot track noise on VDDQ or VDDCA if doing so would
force VREF outside these specifications.
VREF DC Tolerance and VREF AC Noise Limits
VREF(DC)
VREF(DC)max
VDD/2
VDD
VSS
VREF(DC)min
Voltage
Time
VREF(AC) noise VREF(t)
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and
VIL(DC) are dependent on VREF.
VREF DC variations affect the absolute voltage a signal must reach to achieve a valid HIGH or
LOW, as well as the time from which setup and hold times are measured. When VREF is outside
the specified levels, devices will function correctly with appropriate timing deratings as long as:
•VREFismaintainedbetween0.44xVDDQ(orVDDCA)and0.56xVDDQ(orVDDCA),and
•thecontrollerachievestherequiredsingle-endedACandDCinputlevelsfrominstantaneous
VREF .
System timing and voltage budgets must account for VREF deviations outside this range.
The setup/hold specification and derating values must include time and voltage associated with
VREF AC noise. Timing and voltage effects due to AC noise on VREF up to the specified limit
(±1% VDD) are included in LPDDR2 timings and their associated deratings.
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0.380V
0.000V
0.470V
0.576V
0.588V
0.600V
0.612V
0.624V
0.730V
0.820V
VIL(AC)
VIL(DC)
VREF - AC noise
VREF - DC error
VREF + DC error
VREF + AC noise
VIH(DC)
VIH(AC)
1.200V
1.550V
–0.350V
VDD
VDD + 0.35V
narrow pulse width
VSS - 0.35V
narrow pulse width
VSS
0.380V
0.470V
0.576V
0.588V
0.600V
0.612V
0.624V
0.730V
0.820V
Minimum V IL and V IH levels
VIH(DC)
VIH(AC)
VIL(AC)
VIL(DC)
VIL and V IH levels with ringback
Notes:
1. Numbers reect typical values.
2. For CA[9:0], CK, CK#, and CS# VDD stands for VDDCA. For DQ, DM, DQS, and DQS#, VDD stands for VDDQ.
3. For CA[9:0], CK, CK#, and CS# VSS stands for VSSCA. For DQ, DM, DQS, and DQS#, VSS stands for VSSQ.
Input Signal
LPDDR2 466-1066 Input Signal
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LPDDR2-200 to LPDDR2-400 Input Signal
0.300V
0.000V
0.400V
0.576V
0.588V
0.600V
0.612V
0.624V
0.800V
0.900V
VIL(AC)
VIL(DC)
VREF - AC noise
VREF - DC error
VREF + DC error
VREF + AC noise
VIH(DC)
VIH(AC)
1.200V
1.550V
–0.350V
VDD
VDD + 0.35V
narrow pulse width
VSS - 0.35V
narrow pulse width
VSS
0.300V
0.400V
0.576V
0.588V
0.600V
0.612V
0.624V
0.800V
0.900V
Minimum V IL and V IH levels
VIH(DC)
VIH(AC)
VIL(AC)
VIL(DC)
VIL and V IH levels with ringback
Notes:
1. Numbers reect typical values.
2. For CA[9:0], CK, CK#, and CS# VDD stands for VDDCA. For DQ, DM, DQS, and DQS#, VDD stands for VDDQ.
3. For CA[9:0], CK, CK#, and CS# VSS stands for VSSCA. For DQ, DM, DQS, and DQS#, VSS stands for VSSQ.
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AC and DC Logic Input Measurement Levels for Differential Signals
Differential AC Swing Time and tDVAC
Differential AC and DC Input Levels
Notes:
1. These values are not dened, however the single-ended signals CK, CK#, DQS, and DQS# must be within the respective limits
(VIH(DC)max, VIL(DC)min) for single-ended signals and must comply with the specied limitations for overshoot and undershoot.
2. For CK and CK#, use VIH/VIL(AC) of CA and VREFCA; for DQS and DQS#, use VIH/VIL(AC) of DQ and VREFDQ. If a re-
duced
AC HIGH or AC LOW is used for a signal group, the reduced voltage level also applies.
3. Used to dene a differential signal slew rate.
tDVAC
tDVAC
1/2 cycle
Time
VIH,diff(AC)min
VIH,diff(DC)min
0.0
VIH,diff(DC)max
VIH,diff(AC)max
CK, CK#
DQS, DQS#
Dierential Voltage
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit NotesMin Max Min Max
VIH,di(AC) Dierential input
HIGH AC
2 × (V IH(AC) - V REF ) Note 12 × (V IH(AC) - V REF ) Note 1V2
VIL,di(AC) Dierential input
LOW AC
Note 12 × (V REF - V IL(AC) ) Note 12 × (V REF - V IL(AC) )V 2
VIH,di(DC) Dierential input
HIGH
2 × (V IH(DC) - V REF ) Note 12 × (V IH(DC) - V REF ) Note 1V3
VIL,di(DC) Dierential input
LOW
Note 12 × (V REF - V IL(DC) ) Note 12 × (V REF - V IL(DC) )V 3
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Slew Rate (V/ns)
tDVAC (ps) at V IH /V ILdi(AC) =
440mV
tDVAC (ps) at V IH /V ILdi(AC) =
600mV
Min Min
> 4.0 175 75
4.0 170 57
3.0 167 50
2.0 163 38
1.8 162 34
1.6 161 29
1.4 159 22
1.2 155 13
1.0 150 0
< 1.0 150 0
CK/CK# and DQS/DQS# Time Requirements Before Ringback (tDVAC)
Single-Ended Requirements for Differential Signals
Each individual component of a differential signal (CK, CK#, DQS, and DQS#) must also comply
with certain requirements for single-ended signals.
CK and CK# must meet VSEH(AC)min/VSEL(AC)max in every half cycle. DQS, DQS# must meet
VSEH(AC)min/VSEL(AC)max in every half cycle preceding and following a valid transition.
The applicable AC levels for CA and DQ differ by speed bin.
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Note that while CA and DQ signal requirements are referenced to VREF, the single-ended compo-
nents of differential signals also have a requirement with respect to VDDQ/2 for DQS, and VD-
DCA/2 for CK.
The transition of single-ended signals through the AC levels is used to measure setup time.
For single-ended components of differential signals, the requirement to reach VSEL(AC)max or
VSEH(AC)min has no bearing on timing. This requirement does, however, add a restriction on the
common mode characteristics of these signals.
Single-Ended Levels for CK, CK#, DQS, DQS#
Single-Ended Requirements for Differential Signals
Time
VDDCA or V DDQ
VSSCA or V SSQ
VDDCA /2 or V DDQ /2
VSEH(AC)min
VSEH(AC)
VSEL(AC)max
VSEL(AC)
CK or DQS
Dierential Voltage
Symbol Parameter
LPDDR2-800 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit NotesMin Max Min Max
VSEH(AC) Single-ended HIGH
level for strobes
(V DDQ /2) + 0.220 Note 1(VDDQ /2) + 0.300 Note 1V2, 3
Single-ended HIGH
level for CK, CK#
(V DDCA /2) + 0.220 Note 1(VDDCA /2) + 0.300 Note 1V2, 3
VSEL(AC) Single-ended LOW
level for strobes
Note 1(VDDQ /2) - 0.220 Note 1(VDDQ /2) + 0.300 V 2, 3
Single-ended LOW
level for CK, CK#
Note 1(VDDCA /2) - 0.220 Note 1(VDDCA /2) + 0.300 V 2, 3
Notes:
1. These values are not dened, however the single-ended signals CK, CK#, DQS, and DQS# must be within the respective limits
(VIH(DC)max, VIL(DC)min) for single-ended signals and must comply with the specied limitations for overshoot and undershoot.
2. For CK and CK#, use VIH/VIL(AC) of CA and VREFCA; for DQS and DQS#, use VIH/VIL(AC) of DQ and VREFDQ. If a reduced
AC HIGH or AC LOW is used for a signal group, the reduced voltage level also applies.
3. Used to dene a differential signal slew rate.
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Differential Input Crosspoint Voltage
To ensure tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each crosspoint voltage of differential input signals (CK, CK#, DQS, and DQS#) must meet
the specifications in the table "Single-Ended Levels" (page 124). The differential input crosspoint
voltage (VIX) is measured from the actual crosspoint of the true signal and complement to the mid-
level between VDD and VSS.
VIX Definition
Notes:
1. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and it is expected to track variations
in VDD. VIX(AC) indicates the voltage at which differential input signals must cross.
2. For CK and CK#, VREF = VREFCA(DC). For DQS and DQS#, VREF = VREFDQ(DC).
Crosspoint Voltage for Differential Input Signals (CK, CK#, DQS, DQS#)
VDDCA , V DDQ
VSSCA , V SSQ
VDDCA /2,
VDDQ /2
VDDCA /2,
VDDQ /2
CK#, DQS#
VIX
CK, DQS
VDDCA , V DDQ
VSSCA , V SSQ
CK#, DQS#
VIX
VIX
CK, DQS
VIX
X
XX
X
Symbol Parameter
LPDDR2-1066 to LPDDR2-200
Unit NotesMin Max
VIXCA(AC) Dierential input crosspoint voltage rela-
tive to V DDCA /2 for CK and CK#
–120 120 mV 1, 2
VIXDQ(AC) Dierential input crosspoint voltage rela-
tive to V DDQ /2 for DQS and DQ#
–120 120 mV 1, 2
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Input Slew Rate
Differential Input Slew Rate Definition
Note: The differential signals (CK/CK# and DQS/DQS#) must be linear between these thresholds.
Differential Input Slew Rate Definition for CK, CK#, DQS, and DQS#
Output Characteristics and Operating Conditions
Single-Ended AC and DC Output Levels
Description
Measured 1
Dened byFrom To
Dierential input slew rate for rising
edge (CK/CK# and DQS/DQS#)
VIL,di,max VIH,di,min [V IH,di,min - V IL,di,max ] / ˂TR di
Dierential input slew rate for falling
edge (CK/CK# and DQS/DQS#)
VIH,di,min VIL,di,max [V IH,di,min - V IL,di,max ] / ˂TFdi
VIH,di ff,min
0
VIL,diff,max
Time
Dierential Input Voltage
ΔTFdiff ΔTR diff
Symbol Parameter Value Unit Notes
VOH(AC) AC output HIGH measurement level (for output slew rate) V REF + 0.12 V
VOL(AC) AC output LOW measurement level (for output slew rate) VREF - 0.12 V
VOH(DC) DC output HIGH measurement level (for I-V curve linearity) 0.9 x V DDQ
V1
VOL(DC) DC output LOW measurement level (for I-V curve linearity) 0.1 x V DDQ
V2
IOZ Output leakage current (DQ, DM, DQS, DQS#); DQ,
DQS, DQS# are disabled; 0V ื V OUT ื V DDQ
MIN –5 ˩A
MAX +5 ˩A
MMpupd Delta output impedance between pull-up and pull-
down for DQ/DM
MIN –15 %
MAX +15 %
Notes:
1. IOH = –0.1mA.
2. IOL = 0.1mA.
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Differential AC and DC Output Levels
Single-Ended Output Slew Rate
With the reference load for timing measurements, the output slew rate for falling and rising edges is
defined and measured between VOL(AC) and VOH(AC) for single-ended signals.
Differential Input Slew Rate Definition
Single-Ended Output Slew Rate Definition
Symbol Parameter Value Unit
VOHdi(AC) AC dierential output HIGH measurement level (for output SR) + 0.2 x V DDQ V
VOLdi(AC) AC dierential output LOW measurement level (for output SR) - 0.2 x V DDQ V
Description
Measured
Dened byFrom To
Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [V OH(AC) - V OL(AC) ] / ˂TR SE
Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [V OH(AC) - V OL(AC) ] / ˂TFSE
Note: Output slew rate is veried by design and characterization and may not be subject to production testing.
VOH(AC)
VREF
VOL(AC)
Time
Single-Ended Output Voltage (DQ)
ΔTFSE ΔTR SE
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Single-Ended Output Slew Rate
Differential Output Slew Rate Definition
Differential Output Slew Rate
With the reference load for timing measurements, the output slew rate for falling and rising edges is
defined and measured between VOL,diff(AC) and VOH,diff(AC) for differential signals.
Differential Output Slew Rate Definition
Notes:
1. Denitions: SR = slew rate; Q = output (similar to DQ = data-in, data-out); SE = singleended signals
2. Measured with output reference load.
3. The ratio of pull-up to pull-down slew rate is specied for the same temperature and voltage over the entire temperature and
voltage range. For a given output, the ratio represents the maximum difference between pull-up and pull-down drivers due to
process variation.
4. The output slew rate for falling and rising edges is dened and measured between VOL(AC) and VOH(AC).
5. Slew rates are measured under typical simultaneous switching output (SSO) conditions, with one-half of DQ signals per data
byte driving HIGH and one-half of DQ signals per data byte driving LOW.
Note: Output slew rate is veried by design and characterization and may not be subject to production testing.
Parameter Symbol
Value
UnitMin Max
Single-ended output slew rate (output impedance = 40 ˖±30%) SRQ SE 1.5 3.5 V/ns
Single-ended output slew rate (output impedance = 60 ˖±30%) SRQ SE 1.0 2.5 V/ns
Output slew-rate-matching ratio (pull-up to pull-down) 0.7 1.4 –
Parameter Symbol
Value
UnitMin Max
Dierential output slew rate (output impedance = 40 ˖±30%) SRQ di 3.0 7.0 V/ns
VOH,diff(AC)
0
VOL,diff(AC)
Time
Dierential Output Voltage (DQS, DQS#)
ΔTFdiff ΔTR diff
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Notes:
1. Denitions: SR = slew rate; Q = output (similar to DQ = data-in, data-out); SE = singleended signals.
2. Measured with output reference load.
3. The output slew rate for falling and rising edges is dened and measured between VOL(AC) and VOH(AC).
4. Slew rates are measured under typical simultaneous switching output (SSO) conditions, with one-half of DQ signals per data
byte driving HIGH and one-half of DQ signals per data byte driving LOW.
Parameter Symbol
Value
UnitMin Max
Dierential output slew rate (output impedance = 40 ˖±30%) SRQ di 3.0 7.0 V/ns
Parameter Symbol
Value
UnitMin Max
Dierential output slew rate (output impedance = 60 ˖±30%) SRQ di 2.0 5.0 V/ns
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AC Overshoot/Undershoot Specification
Applies for CA[9:0], CS#, CKE, CK, CK#, DQ, DQS, DQS#, DM
Notes:
1. VDD stands for VDDCA for CA[9:0], CK, CK#, CS#, and CKE. VDD stands for VDDQ for DQ, DM, DQS, and DQS#.
2. VSS stands for VSSCA for CA[9:0], CK, CK#, CS#, and CKE. VSS stands for VSSQ for DQ, DM, DQS, and DQS#.
Overshoot and Undershoot Definition
HSUL_12 Driver Output Timing Reference Load
The timing reference loads are not intended as a precise representation of any particular system
environment or a depiction of the actual load presented by a production tester. System designers
should use IBIS or other simulation tools to correlate the timing reference load to a system environ-
ment. Manufacturers correlate to their production test conditions, generally with one or more co-
axial transmission lines terminated at the tester electronics.
Notes:
1. VDD stands for VDDCA for CA[9:0], CK, CK#, CS#, and CKE. VDD stands for VDDQ for DQ, DM, DQS, and DQS#.
2. VSS stands for VSSCA for CA[9:0], CK, CK#, CS#, and CKE. VSS stands for VSSQ for DQ, DM, DQS, and DQS#.
Parameter Unit
Maximum peak amplitude provided for overshoot area V
Maximum peak amplitude provided for undershoot area V
Maximum area above VDD1V/ns
Maximum area below VSS2
800
0.35
0.35
0.20
0.20
933
0.35
0.35
0.17
0.17
1066
0.35
0.35
0.15
0.15
667
0.35
0.35
0.24
0.24
533
0.35
0.35
0.30
0.30
400
0.35
0.35
0.40
0.40
333
0.35
0.35
0.48
0.48 V/ns
Overshoot area
VDD
VSS
Volts (V)
Undershoot area
Maximum amplitude
Maximum amplitude
Time (ns)
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HSUL_12 Driver Output Reference Load for Timing and Slew Rate
Output Driver Impedance
The output driver impedance is selected by a mode register during initialization. The selected
value is able to maintain the tight tolerances specified if proper ZQ calibration is performed. Output
specifications refer to the default output driver unless specifically
stated otherwise. A functional representation of the output buffer is shown in bellow. The output
driver impedance RON is defined by the value of the external reference resistor RZQ as follows:
RONPU = (VDDQ – VOUT) / ABS(IOUT)
When RONPD is turned off.
RONPD = VOUT / ABS(IOUT)
When RONPU is turned off.
Output Driver
Chip in drive mode
Note: All output timing parameter values (tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc.) are reported with respect to this reference
load. This reference load is also used to report slew rate.
LPDDR2
VREF 0.5 × V DDQ
Output
CLOAD = 5pF
VTT = 0.5 × V DDQ
50Ω
To other
circuitry
(RCV, etc.)
Output Driver
Chip in Drive Mode
IPU
RONPU
RONPD
IPD
IOUT
VDDQ
VOUT
DQ
VSSQ
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Output Driver Impedance Characteristics with ZQ Calibration
Output driver impedance is defined by the value of the external reference resistor RZQ. Typical
RZQ is 240 ohms.
Output Driver DC Electrical Characteristics with ZQ Calibration
RONnom Resistor V OUT Min Typ Max Unit Notes
34.3˖RON34PD 0.5 × V DDQ 0.85 1.00 1.15 RZQ/7
RON34PU 0.5 × V DDQ 0.85 1.00 1.15 RZQ/7
40.0˖RON40PD 0.5 × V DDQ 0.85 1.00 1.15 RZQ/6
RON40PU 0.5 × V DDQ 0.85 1.00 1.15 RZQ/6
48.0˖RON48PD 0.5 × V DDQ 0.85 1.00 1.15 RZQ/5
RON48PU 0.5 × V DDQ 0.85 1.00 1.15 RZQ/5
60.0˖RON60PD 0.5 × V DDQ 0.85 1.00 1.15 RZQ/4
RON60PU 0.5 × V DDQ 0.85 1.00 1.15 RZQ/4
80.0˖RON80PD 0.5 × V DDQ 0.85 1.00 1.15 RZQ/3
RON80PU 0.5 × V DDQ 0.85 1.00 1.15 RZQ/3
120.0˖RON120PD 0.5 × V DDQ 0.85 1.00 1.15 RZQ/2
RON120PU 0.5 × V DDQ 0.85 1.00 1.15 RZQ /2
Mismatch between
pull-up and pull-down
MM PUPD –15.00 +15.00
%5
Notes:
1. Applies across entire operating temperature range after calibration.
2. RZQ = 240Ω.
3. The tolerance limits are specied after calibration, with xed voltage and temperature. For behavior of the tolerance limits if
temperature or voltage changes after calibration.
4. Pull-down and pull-up output driver impedances should be calibrated at 0.5 x VDDQ.
5. Measurement denition for mismatch between pull-up and pull-down, MMPUPD:
Measure RONPU and RONPD, both at 0.5 × VDDQ:
MMPUPD =( ( RONPU – RONPD ) / RON,nom ) × 100
For example, with MMPUPD (MAX) = 15% and RONPD = 0.85, RONPU must be less than 1.0.
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Output Driver Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen
Output Driver Sensitivity Definition
Output Driver Temperature and Voltage Sensitivity
Output Impedance Characteristics Without ZQ Calibration
Output driver impedance is defined by design and characterization as the default setting.
Output Driver DC Electrical Characteristics Without ZQ Calibration
Notes:
1. ΔT = T - T (at calibration). ΔV = V - V (at calibration).
2. dRONdT and dRONdV are not subject to production testing; they are veried by design and characterization.
Notes:
1. Applies across entire operating temperature range, without calibration.
2. RZQ = 240Ω
Symbol Parameter Min Max Unit
RONPD RON temperature sensitivity 0.00 0.75 %/˚C
RONPU RON voltage sensitivity 0.00 0.20 %/mV
Symbol Parameter Min Max Unit
RONPD RON temperature sensitivity 0.00 0.75 %/˚C
RONPU RON voltage sensitivity 0.00 0.20 %/mV
RON nom Resistor V OUT Min Typ Max Unit
34.3˖RON34PD 0.5 × V DDQ 0.70 1.00 1.30 RZQ/7
RON34PU 0.5 × V DDQ 0.70 1.00 1.30 RZQ/7
40.0˖RON40PD 0.5 × V DDQ 0.70 1.00 1.30 RZQ/6
RON40PU 0.5 × V DDQ 0.70 1.00 1.30 RZQ/6
48.0˖RON48PD 0.5 × V DDQ 0.70 1.00 1.30 RZQ/5
RON48PU 0.5 × V DDQ 0.70 1.00 1.30 RZQ/5
60.0˖RON60PD 0.5 × V DDQ 0.70 1.00 1.30 RZQ/4
RON60PU 0.5 × V DDQ 0.70 1.00 1.30 RZQ/4
80.0˖RON80PD 0.5 × V DDQ 0.70 1.00 1.30 RZQ/3
RON80PU 0.5 × V DDQ 0.70 1.00 1.30 RZQ/3
120.0˖RON120PD 0.5 × V DDQ 0.70 1.00 1.30 RZQ/2
RON120PU 0.5 × V DDQ 0.70 1.00 1.30 RZQ/2
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I-V Curves
Voltage (V)
RON = 240˖(R ZQ )
Pull-Down Pull-Up
Current (mA) / R ON (ohms) Current (mA) / R ON (ohms)
Default Value after
ZQRESET With Calibration
Default Value after
ZQRESET With Calibration
Min (mA) Max (mA) Min (mA) Max (mA) Min (mA) Max (mA) Min (mA) Max (mA)
0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
0.05 0.19 0.32 0.21 0.26 –0.19 –0.32 –0.21 –0.26
0.10 0.38 0.64 0.40 0.53 –0.38 –0.64 –0.40 –0.53
0.15 0.56 0.94 0.60 0.78 –0.56 –0.94 –0.60 –0.78
0.20 0.74 1.26 0.79 1.04 –0.74 –1.26 –0.79 –1.04
0.25 0.92 1.57 0.98 1.29 –0.92 –1.57 –0.98 –1.29
0.30 1.08 1.86 1.17 1.53 –1.08 –1.86 –1.17 –1.53
0.35 1.25 2.17 1.35 1.79 –1.25 –2.17 –1.35 –1.79
0.40 1.40 2.46 1.52 2.03 –1.40 –2.46 –1.52 –2.03
0.45 1.54 2.74 1.69 2.26 –1.54 –2.74 –1.69 –2.26
0.50 1.68 3.02 1.86 2.49 –1.68 –3.02 –1.86 –2.49
0.55 1.81 3.30 2.02 2.72 –1.81 –3.30 –2.02 –2.72
0.60 1.92 3.57 2.17 2.94 –1.92 –3.57 –2.17 –2.94
0.65 2.02 3.83 2.32 3.15 –2.02 –3.83 –2.32 –3.15
0.70 2.11 4.08 2.46 3.36 –2.11 –4.08 –2.46 –3.36
0.75 2.19 4.31 2.58 3.55 –2.19 –4.31 –2.58 –3.55
0.80 2.25 4.54 2.70 3.74 –2.25 –4.54 –2.70 –3.74
0.85 2.30 4.74 2.81 3.91 –2.30 –4.74 –2.81 –3.91
0.90 2.34 4.92 2.89 4.05 –2.34 –4.92 –2.89 –4.05
0.95 2.37 5.08 2.97 4.23 –2.37 –5.08 –2.97 –4.23
1.00 2.41 5.20 3.04 4.33 –2.41 –5.20 –3.04 –4.33
1.05 2.43 5.31 3.09 4.44 –2.43 –5.31 –3.09 –4.44
1.10 2.46 5.41 3.14 4.52 –2.46 –5.41 –3.14 –4.52
1.15 2.48 5.48 3.19 4.59 –2.48 –5.48 –3.19 –4.59
1.20 2.50 5.55 3.23 4.65 –2.50 –5.55 –3.23 –4.65
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Output Impedance = 240 Ohms, I-V Curves After ZQRESET
6
4
2
0
–2
–4
–6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
mA
Voltage
PD (MAX)
PD (MIN)
PU MAX)
PU (MIN)
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Output Impedance = 240 Ohms, I-V Curves After Calibration
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
6
4
2
0
–2
–4
–6
mA
Voltage
PD (MAX)
PD (MIN)
PU MAX)
PU (MIN)
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Clock Specification
The specified clock jitter is a random jitter with Gaussian distribution. Input clocks violating mini-
mum or maximum values may result in device malfunction.
Definitions and Calculations
Symbol Description Calculation Notes
tCK(avg) and
nCK
The average clock period across any consecutive
200-cycle window. Each clock period is calculated
from rising clock edge to rising clock edge.
Unit tCK(avg) represents the actual clock average
tCK(avg)of the input clock under operation. Unit
nCK represents one clock cycle of the input clock,
counting from actual clock edge to actual clock
edge.
tCK(avg)can change no more than ±1% within a
100-clock-cycle window, provided that all jitter
and timing specications are met.
tCK(avg) = Σ tCK j /N
Where N = 200
N
j = 1
tCK(abs) The absolute clock period, as measured from one
rising clock edge to the next consecutive rising
clock edge.
1
tCH(avg) The average HIGH pulse width, as calculated
across any 200 consecutive HIGH pulses. tCH(avg) = Σ tCHj /(N × tCK(avg))
Where N = 200
N
j = 1
tCL(avg) The average LOW pulse width, as calculated
across any 200 consecutive LOW pulses. tCL(avg) = Σ tCLj /(N × tCK(avg))
Where N = 200
N
j = 1
tJIT(per) The single-period jitter dened as the largest de-
viation of any signal tCK from tCK(avg). tJIT(per) = min/max of tCK i – tCK(avg)
Where i = 1 to 200
1
tJIT(per),act The actual clock jitter for a given system.
tJIT(per),
allowed
The specied clock period jitter allowance.
tJIT(cc) The absolute dierence in clock periods between
two consecutive clock cycles. tJIT(cc) denes the
cycle-to-cycle jitter.
tJIT(cc) = max of tCK i + 1 – tCK i
1
tERR(nper) The cumulative error across n multiple consecu-
tive cycles from tCK(avg). tERR(nper) = Σ tCK j – (n × tCK(avg))
i + n – 1
j = i
1
tERR(nper),act The actual cumulative error over n cycles for a
given system.
tERR(nper),
allowed
The specied cumulative error allowance over n
cycles.
tERR(nper),min The minimum tERR(nper). tERR(nper),min = (1 + 0.68LN(n)) × tJIT(per),min 2
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Notes:
1. Not subject to production testing.
2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value.
Notes:
1. tCK(avg),min is expressed in ps for this table.
2. tJIT(duty),min is a negative value
Symbol Description Calculation Notes
tERR(nper),max The maximum tERR(nper). tERR(nper),max = (1 + 0.68LN(n)) × tJIT(per),max 2
tJIT(duty) Dened with absolute and average specications
for tCH and tCL, respectively.
tJIT(duty),min =
MIN( (tCH(abs),min – tCH(avg),min),
( tCL(abs),min – tCL(avg),min)) × tCK(avg)
tJIT(duty),max =
MAX(( tCH(abs),max – tCH(avg),max),
( tCL(abs),max – tCL(avg),max)) × tCK(avg)
tCK(abs), tCH(abs), and tCL(abs)
These parameters are specified with their average values; however, the relationship between the
average timing and the absolute instantaneous timing (defined in the following table) is applicable
at all times.
tCK(abs), tCH(abs), and tCL(abs) Definitions
Parameter Symbol Minimum Unit
Absolute clock period tCK(abs) tCK(avg),min + tJIT(per),min ps1
Absolute clock HIGH pulse width tCH(abs) tCH(avg),min + tJIT(duty),min 2/tCK(avg)min tCK(avg)
Absolute clock LOW pulse width tCL(abs) tCL(avg),min + tJIT(duty),min 2/tCK(avg)min tCK(avg)
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Clock Period Jitter
LPDDR2 devices can tolerate some clock period jitter without core timing parameter derating. This
section describes device timing requirements with clock period jitter (tJIT(per)) in excess of the
values found in the AC Timing section. Calculating cycle time derating and clock cycle derating are
also described.
Clock Period Jitter Effects on Core Timing Parameters
Core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) extend
across multiple clock cycles. Clock period jitter impacts these parameters when measured in num-
bers of clock cycles. Within the specification limits, the device is characterized
and verified to support tnPARAM = RU[tPARAM/tCK(avg)]. During device operation where clock
jitter is outside specification limits, the number of clocks or tCK(avg), may need to be increased
based on the values for each core timing parameter.
Cycle Time Derating for Core Timing Parameters
For a given number of clocks (tnPARAM), when tCK(avg) and tERR(tnPARAM) exceed
tERR(tnPARAM),allowed, cycle time derating may be required for core timing parameters.
Conduct cycle time derating analysis for each core timing parameter. The amount of cycle time
derating required is the maximum of the cycle time deratings determined for each individual core
timing parameter.
Clock Cycle Derating for Core Timing Parameters
For each core timing parameter and a given number of clocks (tnPARAM), clock cycle derating
should be specified with tJIT(per). For a given number of clocks (tnPARAM), when tCK(avg) and
(tERR(tnPARAM),act) exceed the supported cumulative tERR(tnPARAM),allowed, if the equation
below results in a positive value for a core timing parameter (tCORE), the required clock cycle de-
rating (in clocks) will be that positive value.
Conduct cycle-time derating analysis for each core timing parameter.
CycleTimeDerating = max
t
PARAM +
t
ERR(
t
nPARAM),act –
t
ERR(
t
nPARAM),allowed – tCK(avg) , 0
tnPARAM
Clock
CycleDerating = RU
t
PARAM +
t
ERR(
t
nPARAM),act –
t
ERR(
t
nPARAM),allowed – tnPARAM
tCK(avg)
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Clock Jitter Effects on Command/Address Timing Parameters
Command/address timing parameters (tIS, tIH, tISCKE, tIHCKE, tISb, tIHb, tISCKEb, tIHCKEb) are
measured from a command/address signal (CKE, CS, or CA[9:0]) transition edge to its respective
clock signal (CK/CK#) crossing. The specification values are not affected by the tJIT(per) applied,
as the setup and hold times are relative to the clock signal crossing that latches the command/ad-
dress. Regardless of clock jitter values, these values must be met.
Clock Jitter Effects on READ Timing Parameters
tRPRE
When the device is operated with input clock jitter, tRPRE must be derated by the tJIT(per),act,max
of the input clock that exceeds tJIT(per),allowed,max. Output deratings are relative to the input
clock.
For example, if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500ps,
tJIT(per),act,min = –172ps, and JIT(per),act,max = +193ps, then tRPRE,min, derated = 0.9 -
(tJIT(per), act,max - tJIT(per), allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500 = 0.8628 tCK(avg).
tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)
These parameters are measured from a specific clock edge to a data signal transition (DMn or
DQm, where: n = 0, 1, 2, or 3; and m = DQ[31:0]), and specified timings must be met with respect
to that clock edge. Therefore, they are not affected by tJIT(per).
tQSH, tQSL
These parameters are affected by duty cycle jitter, represented by tCH(abs)min and tCL(abs)min.
Therefore tQSH(abs)min and tQSL(abs)min can be specified with tCH(abs)min and tCL(abs)min.
tQSH(abs)min = tCH(abs)min - 0.05 tQSL(abs)min = tCL(abs)min - 0.05. These parameters deter-
mine the absolute data-valid window at the device pin. The absolute minimum data-valid window
at the device pin = min [(tQSH(abs)min × tCK(avg)min - tDQSQmax - tQHSmax), (tQSL(abs)min
× tCK(avg)min - tDQSQmax - tQHSmax)]. This minimum data-valid window must be met at the
target frequency regardless of clock jitter.
tRPRE(min,derated) = 0.9 –
t
JIT(per),act,max –
t
JIT(per),allowed,max
tCK(avg)
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tRPST
tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min can be
specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min.
Clock Jitter Effects on WRITE Timing Parameters
tDS, tDH
These parameters are measured from a data signal (DMn or DQm, where n = 0, 1, 2, 3; and m =
DQ[31:0]) transition edge to its respective data strobe signal (DQSn, DQSn#: n = 0,1,2,3) cross-
ing. The specification values are not affected by the amount of tJIT(per) applied, because the
setup and hold times are relative to the clock signal crossing that latches the command/address.
Regardless of clock jitter values, these values must be met.
tDSS, tDSH
These parameters are measured from a data strobe signal crossing (DQSx, DQSx#) to its clock
signal crossing (CK/CK#). The specification values are not affected by the amount of tJIT(per))
applied, because the setup and hold times are relative to the clock signal crossing that latches the
command/address. Regardless of clock jitter values, these values must be met.
tDQSS
This parameter is measured from the clock signal (CK, /CK) crossing to the first latching
data strobe signal (DQSx, /DQSx) crossing. When the device is operated with input clock jit-
ter, this parameter must be derated by the actual tJIT(per),act of the input clock in excess of
tJIT(per),allowed.
For example, if the measured jitter into an LPDDR2-800 device has tCK(avg) = 2500ps,
tJIT(per),act,min = -172ps, and tJIT(per),act,max = +193ps, then:
tDQSS,(min,derated) = 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) = 0.75 - (-172 + 100)/2500 = 0.7788 tCK(avg), and
tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 1.25 - (193 - 100)/2500 = 1.2128 tCK(avg).
tDQSS(min,derated) = 0.75 -
t
JIT(per),act,min –
t
JIT(per),allowed, min
tCK(avg)
tDQSS(max,derated) = 1.25 – tJIT(per),act,max – tJIT(per),allowed, max
tCK(avg)
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ORDERING INFORMATION
Commercial Range: Tc = 0°C to +85°C
Industrial Range: Tc = -40°C to +85°C
Clock Speed Grade Order Part No. Organization Package
400 MHz -25 IS43LD16128B-25BL 128Mb x 16, LPDDR2-S4 134 ball BGA, lead free
IS43LD32640B-25BL 64Mb x 32, LPDDR2-S4 134 ball BGA, lead free
IS43LD32640B-25BPL 64Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free
533 MHz -18 IS43LD16128B-18BL 128Mb x 16, LPDDR2-S4 134 ball BGA, lead free
IS43LD32640B-18BL 64Mb x 32, LPDDR2-S4 134 ball BGA, lead free
IS43LD32640B-18BPL 64Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free
Clock Speed Grade Order Part No. Organization Package
400 MHz -25 IS43LD16128B-25BLI 128Mb x 16, LPDDR2-S4 134 ball BGA, lead free
IS43LD32640B-25BLI 64Mb x 32, LPDDR2-S4 134 ball BGA, lead free
IS43LD32640B-25BPLI 64Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free
533 MHz -18 IS43LD16128B-18BLI 128Mb x 16, LPDDR2-S4 134 ball BGA, lead free
IS43LD32640B-18BLI 64Mb x 32, LPDDR2-S4 134 ball BGA, lead free
IS43LD32640B-18BPLI 64Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free
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IS43/46LD32640B
Clock Speed Grade Order Part No. Organization Package
400 MHz -25 IS46LD16128B-25BLA1 128Mb x 16, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-25BLA1 64Mb x 32, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-25BPLA1 64Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free
533 MHz -18 IS46LD16128B-18BLA1 128Mb x 16, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-18BLA1 64Mb x 32, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-18BPLA1 64Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free
Automotive, A1 Range: Tc = -40°C to +85°C
Clock Speed Grade Order Part No. Organization Package
400 MHz -25 IS46LD16128B-25BLA2 128Mb x 16, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-25BLA2 64Mb x 32, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-25BPLA2 64Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free
533 MHz -18 IS46LD16128B-18BLA2 128Mb x 16, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-18BLA2 64Mb x 32, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-18BPLA2 64Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free
Automotive, A2 Range: Tc = -40°C to +105°C
Clock Speed Grade Order Part No. Organization Package
400 MHz -25 IS46LD16128B-25BLA25 128Mb x 16, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-25BLA25 64Mb x 32, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-25BPLA25 64Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free
533 MHz -18 IS46LD16128B-18BLA25 128Mb x 16, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-18BLA25 64Mb x 32, LPDDR2-S4 134 ball BGA, lead free
IS46LD32640B-18BPLA25 64Mb x 32, LPDDR2-S4 168 ball PoP BGA, lead free
Automotive, A25 Range: Tc = -40°C to +115°C
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IS43/46LD32640B
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IS43/46LD32640B
