DS04-27257-2Ea
FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©2006-2008 FUJITSU MICROELECTRONICS LIMITED Al l rights reserv ed
2007.3
ASSP For Power Supply Applications
6 ch DC/DC Converter IC with
Sync hronous Rectification
MB39A123
■DESCRIPTION
MB39A123 is a 6-channel DC/DC conver ter IC using pulse width modulation (PWM) , and it is suitable for up
conversion, down conversion, and up/down conversion. MB39A123 is built in 6 channels into BCC-48++/LQFP-
48P package and this IC ca n control and s oft-star t at each channel. MB39A123 is suitable for power supply of
high performance potable instruments such as a digital still camera (DSC).
■FEATURES
• Supports for step-down with synchronous rectification (ch.1)
• Supports for step-down and up/down Zeta conversion (ch.2 to ch.4)
• Supports for step-up and up/down Sepic conversion (ch.5, ch.6)
• Negative voltage output (Inverting amplifier) (ch.4)
• Low voltage start-up (ch.5, ch.6) : 1.7 V
• Power supp ly voltage range : 2.5 V to 11 V
• Reference voltage : 2.0 V ± 1%
• Error amplifier reference voltage : 1.0 V ± 1% (ch.1) , 1.23 V ± 1% (ch.2 to ch.6)
• Oscillation frequency range : 200 kHz to 2.0 MHz
• Standby current : 0 µA (Typ)
• Built-in soft-start circuit independent of loads
• Built-in totem-pole type output for MOS FET
• Short-circuit detection capability by external signal (−INS terminal)
• Two types of packages (BCC-48 pin : 1 type, LQFP-48 pin : 1 type)
■APPLICATIONS
• Digital still camera(DSC)
• Digital video camera(DVC)
• Surveillance camera etc.
MB39A123
2
■PIN ASSIGNMENTS
(Continued)
VCC
CS3
−INE3
FB3
DTC3
DTC2
FB2
−INE2
CS2
CS1
−INE1
FB1
CTL1 2 36 VCCO
CTL2 3 35 OUT1-1
CTL3 4 34 OUT1-2
CTL4 5 33 OUT2
CTL5 6 32 OUT3
CTL6 7 31 OUT4
−INS 8 30 OUT5
VREF 9 29 OUT6
GND 10 28 GNDO
RT 11 27 CS6
CT 12 26 −INE6
CSCP
DTC4
FB4
−INE4
CS4
OUTA
−INA
CS5
−INE5
FB5
DTC5
DTC6
CTL 46 45 44 40 3948 47
13 14 15
37
2522 23
431
16 17 18 19 FB6
42
20
41
21 24
38
(LCC-48P-M08)
(TOP VIEW)
MB39A123
3
(Continued)
VCC
CS3
−INE3
FB3
DTC3
DTC2
FB2
−INE2
CS2
CS1
−INE1
FB1
48 47 46 45 44 43 42 41 40 39 38 37
CTL 1 36 VCCO
CTL1 2 35 OUT1-1
CTL2 3 34 OUT1-2
CTL3 4 33 OUT2
CTL4 5 32 OUT3
CTL5 6 31 OUT4
CTL6 7 30 OUT5
−INS 8 29 OUT6
VREF 9 28 GNDO
GND 10 27 CS6
RT 11 26 −INE6
CT 12 25 FB6
13 14 15 16 17 18 19 20 21 22 23 24
CSCP
DTC4
FB4
−INE4
CS4
OUTA
−INA
CS5
−INE5
FB5
DTC5
DTC6
(TOP VIEW)
(FPT-48P-M26)
MB39A123
4
■PIN DESCRIPTIONS
(Continued)
Block
name Pin No. Pin name I/O Description
ch.1
37 FB1 O ch.1• Error amplifier output terminal
38 −INE1 I ch.1• Error amplifier inverted in pu t te rm ina l
39 CS1 ⎯ch.1• Soft-start setting capacitor connection terminal
35 OUT1-1 O ch.1• P-ch drive output terminal
(External main side FET gate driving)
34 OUT1-2 O ch.1• N-ch drive output terminal
(External synchronous rectification side FET gate driving)
ch.2
43 DTC2 I ch.2 • Dead time control terminal
42 FB2 O ch.2 • Error amplifier output terminal
41 −INE2 I ch.2 • Error amplifier inverted input terminal
40 CS2 ⎯ch.2 • Soft-start setting capacitor conn e ctio n te rm in al
33 OUT2 O ch.2 • P-ch driv e ou tp ut term in al
ch.3
44 DTC3 I ch.3 • Dead time control terminal
45 FB3 O ch.3 • Error amplifier output terminal
46 −INE3 I ch.3 • Error amplifier inverted input terminal
47 CS3 ⎯ch.3 • Soft-start setting capacitor conn e ctio n te rm in al
32 OUT3 O ch.3 • P-ch driv e ou tp ut term in al
ch.4
14 DTC4 I ch.4 • Dead time control terminal
15 FB4 O ch.4 • Error amplifier output terminal
16 −INE4 I ch.4 • Error amplifier inverted input terminal
17 CS4 ⎯ch.4 • Soft-start setting capacitor conn e ctio n te rm in al
31 OUT4 O ch.4 • P-ch driv e ou tp ut term in al
19 −INA I Inverting amplifier input terminal
18 OUTA O Inverting amplifier output terminal
ch.5
23 DTC5 I ch.5 • Dead time control terminal
22 FB5 O ch.5 • Error amplifier output terminal
21 −INE5 I ch.5 • Error amplifier inverted input terminal
20 CS5 ⎯ch.5 • Soft-start setting capacitor conn e ctio n te rm in al
30 OUT5 O ch.5 • N-ch drive output terminal
ch.6
24 DTC6 I ch.6 • Dead time control terminal
25 FB6 O ch.6 • Error amplifier output terminal
26 −INE6 I ch.6 • Error amplifier inverted input terminal
27 CS6 ⎯ch.6 • Soft-start setting capacitor conn e ctio n te rm in al
29 OUT6 O ch.6 • N-ch drive output terminal
MB39A123
5
(Continued)
Block
name Pin No. Pin name I/O Description
OSC 12 CT ⎯Triangular wave frequency setting capacitor connection terminal
11 RT ⎯Triangular wave frequency setting resistor connection terminal
Control
1 CTL I Power supply control terminal
2 CTL1 I ch.1 control terminal
3 CTL2 I ch.2 control terminal
4 CTL3 I ch.3 control terminal
5 CTL4 I ch.4 control terminal
6 CTL5 I ch.5 control terminal
7 CTL6 I ch.6 control terminal
13 CSCP ⎯Short-circuit detection circuit capacitor connection terminal
8−INS I Short-circuit detection comparator inverted input terminal
Power
36 VCCO ⎯Drive output block power supply terminal
48 VCC ⎯Power supply terminal
9 VREF O Reference voltage output terminal
28 GNDO ⎯Drive output block ground terminal
10 GND ⎯Ground terminal
MB39A123
6
■BLOCK DIAGRAM
−INE2
OUT2
VIN
(5 V-11 V)
OSC
0.9 V
0.4 V
Power
ON/OFF
CTL
VR
1.0 V/1.23 V
VREF
VCC
bias
2.0 V
CTL
GND
CS2
FB2
DTC2
−INE3
OUT3
CS3
FB3
DTC3
−INE5
OUT5
CS5
FB5
DTC5
1 V
−INE6
CS6
FB6
DTC6
GNDO
OUT6
VREF
SCP
Comp.
−INS
CSCP
RT CT VREF
Drive3
Error
Amp3
1.23 V
PWM
Comp.3
<<ch.3>>
VREF
UVLO2
Drive6
Error
Amp6 PWM
Comp.6
<<ch.6>>
N-ch
VREF
−INE1 VCCO
OUT1-1
Vo1
(1.2 V)
CS1
FB1
A
Error
Amp1
(1.0 V)
PWM
Comp.1
<<ch.1>>
P-ch
VREF
1.1 µA
Drive2
Error
Amp2
1.23 V
PWM
Comp.2
<<ch.2>>
VREF
Drive5
Error
Amp5
1.23 V
PWM
Comp.5
<<ch.5>>
VREF
N-ch
1.23 V
F
Vo6-2
(5.0 V)
Vo6-1
(15 V)
SCP
UVLO1
1.1 µA
1.1 µA
1.1 µA
1.1 µA
N-ch
Dead Time
OUT1-2
P-ch
P-ch
Vo2
(2.5 V)
B
Vo3
(3.3 V)
C
CHCTL
CTL1
CTL2
CTL3
41
40
42
43
33
46
47
45
32
21
20
22
30
26
27
25 28
29
48
1
10
8
13
9
1211
38
39
37
36
35
44
23
24
34
3
4
2
CTL4 5
CTL5 6
−INE4
OUT4
D
CS4
FB4
DTC4
Drive4
Error
Amp4
1.23 V
PWM
Comp.4
<<ch.4>>
VREF
1.1 µA
P-ch
Vo4
(−7.5 V)
D
16
17
15
31
14
<< 48 Pin >>
PKG:BCC-48++
:LQFP-48P
7
CTL6
19
18
−INA
OUTA INVAmp
E
Vo5
(15 V)
A
B
C
E
F
−
+
+
−
+
+
−
+
−
+
+
−
+
+
−
+
+
−
+
+
−
+
−
+
−
+
+
−
+
+
−
+
+
−
+
+
−
+
+
Reference voltage
1.0 V ±
1 %
Reference voltage
1.23 V ± 1 %
Reference voltage
1.23 V ± 1 %
Reference
voltage
1.23 V ± 1 %
Reference voltage
1.23 V ± 1 %
Reference voltage
1.23 V ± 1 %
Io = 300 mA
at VCCO = 7 V
Io = 300 mA
at VCCO = 7 V
Io = 300 mA
at VCCO = 7 V
Io = 300 mA
at VCCO = 7 V
Io = 300 mA
at VCCO = 7 V
H:ON (Power ON)
L:OFF(Standby mode)
VTH = 1.0 V
Transformer
Step-down
(Synchronous
Rectification)
Step-down
Step-up
Inverting
Step-down
Precision
±
1 %
Precision
±
0.8 %
Precision ± 0.5 %
(2.0 MHz)
Max Duty
92 %
±
5 %
Max Duty
92 %
±
5 %
Max Duty
92 %
±
5 %
H:UVLO release
H:at SCP
Dead Time
(td = 50 ns)
L priority
VREF
L priority
VREF
L priority
VREF
L priority
VREF
L priority
VREF
L priority
L priority
L priority
L priority
L priority
L priority
Charge current
1 µA
H:ON
L:OFF
VTH = 1.0 V
Io = 300 mA
at VCCO = 7 V
Io = 300 mA
at VCCO = 7 V
F
Error Amp power supply
SCP Comp. power supply
Error Amp
reference
Short-circuit
detection signal
(L: at short-circuit)
Drive1-1
Drive1-2
Max Duty
92 %
±
5 %
Max Duty
92 %
±
5 %
MB39A123
7
■ABSOLUTE MAXIMUM RATINGS
* : When mounted on a 117 mm × 84 mm × 0.8 mm FR-4 board s.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Conditions Rating Unit
Min Max
Power supply voltage VCC VCC, VCCO terminals ⎯12 V
Output current IOOUT1-1, OUT1-2, OUT2 to OUT6
terminals ⎯20 mA
Peak output curr e nt IOP OUT1-1, OUT1-2, OUT2 to OUT6
terminals
Duty ≤ 5% ⎯400 mA
Power dissipation PDTa ≤ +25 °C (BCC-48++) ⎯1670* mW
Ta ≤ +25 °C (LQFP-48P) ⎯2000* mW
Storage temperature TSTG ⎯−55 +125 °C
MB39A123
8
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended ope rating condition ranges. Oper ation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
Parameter Symbol Conditions Value Unit
Min Typ Max
Start power supply voltage VCC ch.5, ch.6, VCC, VCCO
terminals 1.7 ⎯11 V
Power supply voltage VCC VCC, VCCO terminals 2.5 4 11 V
Reference voltage output current IREF VREF terminal −1⎯0mA
Input voltage VINE
−INE1 to −INE6 terminals 0 ⎯VCC − 0.9 V
−INA terminal − 0.2 ⎯VCC − 1.8 V
−INS terminal 0 ⎯VREF V
VDTC DTC2 to DTC6 terminals 0 ⎯VREF V
Control input voltage VCTL CTL, CTL1 to CTL6
terminals 0⎯11 V
Output current IOOUT1-1, OUT1-2, OUT2 to
OUT6 terminals −15 ⎯+15 mA
Total gate charge of external FET Qg
OUT1-1, OUT1-2, OUT2 to
OUT6 terminals
connection FET
fosc = 2 MHz
⎯2.6 7.5 nC
Oscillation frequency fOSC ⎯0.2 1.0 2.0 MHz
Timing capacitor CT⎯27 100 680 pF
Timing resistor RT⎯3.0 6.8 39 kΩ
Soft-start capacitor CSCS1 to CS6 terminals ⎯0.1 1.0 µF
Short-circuit detection capacitor CSCP ⎯⎯0.1 1.0 µF
Reference voltage output
capacitor CREF ⎯⎯0.1 1.0 µF
Operating ambient temperature Ta ⎯−30 +25 +85 °C
MB39A123
9
■ELECTRICAL CHARACTERISTICS (VCC = VCCO = 4 V, Ta = +25 °C)
(Continued)
Parameter Symbol Pin No. Conditions Value Unit
Min Typ Max
Reference
Voltage Block
[VREF]
Output voltage VREF1 9VREF = 0 mA 1.98 2.00 2.02 V
VREF2 9VCC = 2.5 V to 11 V 1.975 2.000 2.025 V
VREF3 9VREF = 0 mA to −1 mA 1.975 2.000 2.025 V
Input stability Line 9 VCC = 2.5 V to 11 V* ⎯2⎯mV
Load stability Load 9 VREF = 0 mA to −1 mA* ⎯2⎯mV
Temperature
stability ∆VREF/
VREF 9Ta = 0 °C to +85 °C* ⎯0.20 ⎯%
Short-circuit
output current IOS 9VREF = 0 V* ⎯−130 ⎯mA
Under voltage
lockout
protection
circuit Block
(ch.1 to ch.4)
[UVLO1]
Threshold
voltage VTH1 35 VCC = 1.7 1.8 1.9 V
Hysteresis
width VH1 35 ⎯0.05 0.1 0.2 V
Reset voltage VRST1 35 VCC = 1.55 1.7 1.85 V
Under voltage
lockout
protection
circuit Block
(ch.5, ch.6)
[UVLO2]
Threshold
voltage VTH2 30 VCC = 1.35 1.5 1.65 V
Hysteresis
width VH2 30 ⎯0.02 0.05 0.1 V
Reset voltage VRST2 30 VCC = 1.27 1.45 1.63 V
Short-circuit
detection Block
[SCP]
Threshold
voltage VTH 13 ⎯0.65 0.70 0.75 V
Input source
current ICSCP 13 ⎯−1.4 −1.0 −0.6 µA
Triangular
Wave Oscilla-
tor Block
[OSC]
Oscillation
frequency
fosc129 to 35 CT = 10 0 pF ,
RT = 6.8 kΩ0.95 1.0 1.05 MHz
fosc229 to 35 CT = 10 0 pF , R T = 6.8 kΩ
VCC = 2.5 V to 11 V 0.945 1.0 1.055 MHz
Frequency
Input stability ∆fOSC/
fOSC 29 to 35 CT = 100 pF, RT = 6.8 kΩ
VCC = 2.5 V to 11 V* ⎯1.0 ⎯%
Frequency
temperature
stability
∆fOSC/
fOSC 29 to 35 CT = 100 pF, RT = 6.8 kΩ
Ta = 0 °C to +85 °C* ⎯1.0 ⎯%
Soft-Start Block
(ch.1 to ch.6)
[CS1 to CS6]
Charge
current ICS 17,20,27,
39,40,47 CS1 to CS6 = 0 V −1.45 −1.1 −0.75 µA
MB39A123
10
(VCC = VCCO = 4 V, Ta = +25 °C)
(Continued)
Parameter Symbol Pin No. Conditions Value Unit
Min Typ Max
Error Amp Block
(ch.1)
[Error Amp1]
Reference
voltage
VTH1 38 VCC = 2.5 V to 11 V
Ta = +25 °C0.990 1.000 1.010 V
VTH2 38 VCC = 2.5 V to 11 V
Ta = 0 °C to +85 °C* 0.988 1.000 1.012 V
Temperature
stability ∆VTH/
VTH 38 Ta = 0 °C to +85 °C* ⎯0.1 ⎯%
Input bias
current IB38 −INE1 = 0 V −120 −30 ⎯nA
Voltage gain AV37 DC* ⎯100 ⎯dB
Frequency
bandwidth BW 37 AV = 0 dB* ⎯1.4 ⎯MHz
Output
voltage VOH 37 ⎯1.7 1.9 ⎯V
VOL 37 ⎯⎯40 200 mV
Output source
current ISOURCE 37 FB1 = 0.65 V ⎯−2−1mA
Output sink
current ISINK 37 FB1 = 0.65 V 150 200 ⎯µA
Error Amp Block
(ch.2 to ch.6)
[Error Amp2 to
Error Amp6]
Reference
voltage
VTH3 16, 21,
26, 41,
46
VCC = 2.5 V to 11 V
Ta = +25 °C1.217 1.230 1.243 V
VTH4 16, 21,
26, 41,
46
VCC = 2.5 V to 11 V
Ta = 0 °C to +85 °C* 1.215 1.230 1.245 V
Temperature
stability ∆VTH/
VTH
16, 21,
26, 41,
46 Ta = 0 °C to +85 °C* ⎯0.1 ⎯%
Input bias
current IB16, 21,
26, 41,
46 −INE2 to −INE6 = 0 V −120 −30 ⎯nA
Voltage gain AV15 , 22 ,
25, 42,
45 DC* ⎯100 ⎯dB
Frequency
bandwidth BW 15, 22,
25, 42,
45 AV = 0 dB* ⎯1.4 ⎯MHz
Output
voltage
VOH 15, 22,
25, 42,
45 ⎯1.7 1.9 ⎯V
VOL 15, 22,
25, 42,
45 ⎯⎯40 200 mV
MB39A123
11
(VCC = VCCO = 4 V, Ta = +25 °C)
(Continued)
Parameter Symbol Pin No. Conditions Value Unit
Min Typ Max
Error Amp Block
(ch.2 to ch.6)
[Error Amp2 to
Error Amp6]
Output source
current ISOURCE 15, 22,
25, 42,
45 FB2 to FB6 = 0.65 V ⎯−2−1mA
Output sink
current ISINK 15, 22,
25, 42,
45 FB2 to FB6 = 0.65 V 150 200 ⎯µA
Inverting Amp
Block (ch.4)
[Inv Amp]
Input offset
voltage VIO 18 OUTA = 1.23V −10 0 + 10 mV
Input bias
current IB19 − INA = 0V −120 −30 ⎯nA
Voltage gain AV18 DC* ⎯100 ⎯dB
Frequency
bandwidth BW 18 AV = 0 dB* ⎯1.0 ⎯MHz
Output
voltage VOH 18 ⎯1.7 1.9 ⎯V
VOL 18 ⎯⎯40 200 mV
Output sour ce
current ISOURCE 18 OUTA = 1.23V ⎯−2−1mA
Output sink
current ISINK 18 OUTA = 1.23V 150 200 ⎯µA
PWM
Comparator
Block
(ch.1)
[PWM Comp.1]
Threshold
voltage
VT0 34, 35 Duty cycle = 0%0.35 0.4 0.45 V
VT100 34, 35 Duty cycle = 100%0.85 0.9 0.95 V
PWM
Comparator
Block
(ch.2 to ch.6)
[PWM Comp.2 to
PWM Comp.6]
Threshold
voltage VT0 29 to 33 Duty cycle = 0%0.35 0.4 0.45 V
VT100 29 to 33 Duty cycle = 100%0.85 0.9 0.95 V
Maximum duty
cycle Dtr 29 to 33 CT = 100 pF,
RT = 6.8 kΩ87 92 97 %
Output Block
(ch.1 to ch.6)
[Drive1 to Drive6]
Output source
current ISOURCE 29 to 35 Duty ≤ 5%
OUT = 0 V ⎯−130 −75 mA
Output sink
current ISINK 29 to 35 Duty ≤ 5%
OUT = 4 V 75 130 ⎯mA
Output on
resistor ROH 29 to 35 OUT = − 15 mA ⎯18 27 Ω
ROL 29 to 35 OUT = 15 mA ⎯18 27 Ω
Dead time tD1 34, 35 OUT2 − OUT1 * ⎯50 ⎯ns
tD2 34, 35 OUT1 − OUT2 * ⎯50 ⎯ns
MB39A123
12
(Continued) (VCC = VCCO = 4 V, Ta = +25 °C)
* : Standard design value
Parameter Symbol Pin No. Conditions Value Unit
Min Typ Max
Short-Circuit
Detection
Comparator
Block
[SCP Comp.]
Threshold
voltage VTH 35 ⎯0.97 1.00 1.03 V
Input bias
current IB8−INS = 0 V −25 −20 −17 µA
Control Block
(CTL,
CTL1 to CTL6)
[CTL, CHCTL]
Output on
condition VIH 1 to 7 CTL, CTL1 to CTL6 1.5 ⎯11 V
Output off
condition VIL 1 to 7 CTL, CTL1 to CTL6 0 ⎯0.5 V
Input current ICTLH 1 to 7 CTL, CTL1 to CTL6 = 3 V 5 30 60 µA
ICTLL 1 to 7 CTL, CTL1 to CTL6 = 0 V ⎯⎯ 1µA
General
Standby
current ICCS 48 CTL, CTL1 to CTL6 = 0 V ⎯02µA
ICCSO 36 CTL = 0 V ⎯01µA
Power supply
current ICC 48 CTL = 3 V ⎯4.5 6.8 mA
MB39A123
13
■TYPICAL CHARACTERISTICS
(Continued)
0
1
2
3
4
5
024681012
Ta = + 25 °C
CTL = 3 V
0 2 4 6 8 10 12
0
1
2
3
4
5Ta = + 25 °C
CTL = 3 V
VREF = 0 mA
1.95
1.96
1.97
1.98
1.99
2.00
2.01
2.02
2.03
2.04
2.05
−40 −20 0 +20 +40 +60 +80 +100
VCC = 4 V
CTL = 3 V
VREF = 0 mA
024681012
0.0
1.0
2.0
3.0
4.0
5.0 Ta = + 25 °C
VCC = 4 V
VREF = 0 mA
024681012
0
50
100
150
200 Ta = + 25 °C
VCC = 4 V
Power Supply Voltage VCC (V)
Power Supply Current vs.
Power Supply Voltage
Power Supply Current ICC (mA)
Power Supply Voltage VCC (V)
Reference Voltage vs.
Power Supply Voltage
Reference Voltage VREF (V)
Operating Ambient Temperature Ta ( °C)
Reference Voltage vs.
Operating Ambient Temperature
Reference Voltage VREF (V)
CTL Terminal Voltage VCTL (V)
Reference Voltage vs.
CTL Terminal Voltage
Reference Volt ag e V REF (V)
CTL Terminal Voltage VCTL (V)
CTL Terminal Curr ent vs.
CTL Terminal Voltage
CTL Terminal Current ICTL (µA)
MB39A123
14 (Continued)
10
100
1000
10000
1 10 100 1000
Ta = + 25 °C
VCC = 4 V
CTL = 3 V
CT = 680 pF CT = 220 pF
CT = 100 pF
CT = 27 pF
10
100
1000
10000
10 100 1000 10000
Ta = + 25 °C
VCC = 4 V
CTL = 3 V
RT = 3 kΩ
RT = 6.8 kΩ
RT = 13 kΩRT = 39 kΩ
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Ta = + 25 °C
VCC = 4 V
CTL = 3 V
RT = 6.8 kΩUpper limit
Lower limit
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
−40 −20 0 +20 +40 +60 +80 +100
VCC = 4 V
CTL = 3 V
R
T
= 6.8 kΩ
C
T
= 100 pF Upper limit
Lower limit
900
920
940
960
980
1000
1020
1040
1060
1080
1100
−40 −20 0 +20 +40 +60 +80 +100
VCC = 4 V
CTL = 3 V
RT = 6.8 kΩ
CT = 100 pF
Timing Resistor RT (kΩ)
Triangular Wave Oscillation Frequency vs.
Timing Resistor
Triangular Wave Oscillation
Frequency fOSC (kHz)
Timing Capacity CT (pF)
Triangular Wave Oscillation Frequency vs.
Timing Capacity
Triangular Wave Oscillation
Frequency fOSC (kHz)
Triangular Wave Oscillation Frequency fOSC (kHz)
Triangular Wave Upper and Lower Limit Voltage
vs. Triangular Wave Oscillation Frequency
Triangular Wav e Up pe r an d Lo we r
Limit Voltage VCT (V)
Operating Amb ient Temperat ur e Ta ( °C)
Triangular Wave Upper and Lower Limit Voltage
vs. Operating Ambient Tempe r atu r e
Triangular Wave Upper and Lower
Limit Voltage VCT (V)
Operating Amb ie nt Temperatur e Ta ( °C)
Triangular Wave Oscillation Frequency
vs. Operating Ambient Temperature
Triangular Wave Oscillation
Frequency fOSC (kHz)
MB39A123
15
(Continued)
50
55
60
65
70
75
80
85
90
95
100
0.6 0.65 0.7 0.75 0.8 0.85 0.9
Ta = + 25 °C
VCC = CTL = 4 V
FB = 2 V
CT = 100 pF
fosc = 200 kHz
fosc = 1 MHz
fosc = 2 MHz
70
75
80
85
90
95
100
0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Ta = + 25 °C
VCC = 4 V
CTL = 4 V
FB = 2 V
DTC = Open
RT = 3 kΩ
RT = 6.8 kΩ
RT = 39 kΩRT = 13 kΩ
70
75
80
85
90
95
100
024681012
Ta = + 25 °C
VCC = CTL
DTC pin open
FB = 2 V
CT = 100 pF
fosc = 2 MHz
fosc = 1 MHz
fosc = 200 kHz
70
75
80
85
90
95
100
−40 −20 0 +20 +40 +60 +80 +100
Ta = + 25 °C
VCC = CTL = 4 V
DTC pin open
FB = 2 V
C
T
= 100 pF
fosc = 2 MHz
fosc = 1 MHz
fosc = 200 kHz
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
1 10 100
Ta = + 25 °C
Ta = −30 °C
VCTL = VCC
CT = 100 pF
At evaluating Fujitsu EV board system
Start Power Supply Voltage VCC (V)
Timing Resistor RT (kΩ)
Start Power Supply Volt ag e vs. Timin g Resist or
Oscillation Frequency fOSC (kHz)
Maximum Duty Cycle vs. Oscillation Frequency
Maximum Duty Cycle Dtr (%)
DTC Termina l Voltage VDTC (V)
ON Duty Cycle vs. DTC Terminal Voltage
ON Duty Cycle Dtr (%)
Power Supply Voltage VCC (V)
Maximum Duty Cycle vs. Power Supply Voltage
Maximum Duty Cycle Dtr (%)
Maximum Duty Cycle Dtr (%)
Operating Ambi ent Temperature Ta ( °C)
Maximum Duty Cycle vs.
Operating Ambi ent Temperature
MB39A123
16
(Continued)
−50
−40
−30
−20
−10
0
10
20
30
40
50
1 k 10 k 100 k 1 M 10 M
−225
−180
−135
−90
−45
0
45
90
135
180
225
Av
φ
+−
+
+
37
38 36
2.0 V
OUT
10 kΩ
10 kΩ
1 µF
IN
240 kΩ
2.4 kΩ
1.0 V1.5 V
Ta = +25 °C
VCC = 7 V
0
200
400
600
800
1000
1200
1400
1600
1800
2000
−40 −20 0 +20 +40 +60 +80 +100
2250
−40 −20 0 +20 +40 +60 +80 +100
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2250
Maximum Power Dissipation PD (mW)
Operating Ambient Temperature Ta ( °C)
Maximum Power Dissipation vs.
Operating Ambie nt Temp er ature
(for BCC-48++)
Operating Ambi ent Temperature Ta ( °C)
Maximum Power Dissipation vs.
Operating Ambient Temperature
(for LQFP-48P)
Maximum Power Dissipation PD (mW)
Frequency f (Hz)
Error Amp Voltage Gain, Phase vs. Frequency
Error Amp Voltag e Gain AV (dB)
Phase φ (deg)
Error Amp1
the same as other
channels
MB39A123
17
■FUNCTIONAL DESCRIPTION
1. DC/DC Converter Function
(1) Reference voltage block (VREF)
The reference voltage circuit uses the voltage supplied from VCC terminal (pin 48) to generate a temperature
compensated r eference volt age ( 2. 0 V Typ) used as the reference voltage fo r th e inte rnal circuits of the I C. It is
also possible to supply the load current of up to 1 mA to external circuits as a reference voltage through the
VREF terminal (pin 9) .
(2) Triangular wave oscillator block (OSC)
The triangular wav e oscillator bloc k generates the triangular wav e oscillation wa vef orm width of 0.4 V lower limit
and 0.5 V amplit ude by the timing resistor (RT ) conn ected t o the RT terminal (pin 11) , and the tim ing ca pacitor
(CT) connected to the CT terminal (pin 12) . The triangular wave is input to the PWM comparator circuits on the IC.
(3) Error amplifier block (Error Amp1 to Error Amp6)
The error amplifier detects output voltage of the DC/DC con verter and outputs PWM control signals. An arbitrary
loop gain can be set by connecting a feedback resistor and capacit or fr om the o utput te rminal to inverted input
terminal of the error amplifier, enabling stable phase compensation for the system.
You can prev ent surge currents when the IC is turned on by co nnecting soft-sta rt capacitors to the CS1 terminal
(pin 39) to CS6 terminal (pin 27) which are the noninverting input terminals of the error amplifier. The IC is started
up at constant soft-start time intervals independent of the output load of the DC/DC converter.
(4) PWM comparator b lock (PWM Comp.1 to PWM Comp.6)
The PWM comparator block is a voltage-pulse width conver ter that controls the output duty depending on the
input/output voltage.
An output tr ansistor is turned on, during intervals when t he error amplifier outp ut v oltage and DTC v oltage (ch.2
to ch.6) are higher than the triangular wave voltage.
(5) Output block (Drive1 to Drive6)
The output circuit uses a totem-pole configuration and is capable of driving an external P-ch MOS FET (main
side of ch.1, ch.2, ch.3 and ch.4) and N-ch MOS FET (synchronous rectificat ion side of ch.1, ch.5 and ch.6).
MB39A123
18
2. Channel Control Function
Use the CTL terminal (pin 1), CTL1 terminal (pin 2), CTL2 terminal (pin 3), CTL3 terminal (pin 4), CTL4 terminal
(pin 5), CTL5 terminal (pin 6), and CTL6 terminal (pin 7) to set ON/OFF to the main and each channels.
ON/OFF setting conditions for each channel
Note : Note that current which is over standby current flows into VCC terminal when the CTL terminal is in “L” le vel
and one of the terminals between CTL1 to CTL6 terminals is set to “H” level.
(Refer to the following circuit)
CTL CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 Power ch.1 ch.2 ch.3 ch.4 ch.5 ch.6
L X X X X X X OFF OFF OFF OFF OFF OFF OFF
H L L L L L L ON OFF OFF OFF OFF OFF OFF
H H L L L L L ON ON OFF OFF OFF OFF OFF
H L H L L L L ON OFF ON OFF OFF OFF OFF
H L L H L L L ON OFF OFF ON OFF OFF OFF
H L L L H L L ON OFF OFF OFF ON OFF OFF
H L L L L H L ON OFF OFF OFF OFF ON OFF
H L L L L L H ON OFF OFF OFF OFF OFF ON
H H H H H H H ONONONONONONON
GND
VCC
86 kΩ
CTL1
∼
CTL6
223 kΩ
48
10
200 kΩ
ESD
protection
element
• CTL1 to CTL6 terminals equivalent circuit
MB39A123
19
3. Protection Function
(1) Timer-latch short-circuit pr otection circuit (SCP, SCP Comp.)
The short-circuit detection comparator (SCP) detects the output voltage level of each channel. If the output
voltage of any channel is lower than the short-circuit detection voltage, the timer circuit is actuated to start
charging to the capacitor (Cscp) externally connected to the CSCP terminal (pin 13).
When the capacitor (Cscp) voltage becomes about 0.7 V, the output transistor is turned off and the dead time
is set to 100%.
The short-circuit detection from external input is capable b y using −INS terminal (pin 8) on short-circuit detection
comparator (SCP Comp.) .
When the protection circuit is actuated, the power supply is rebooted or the CTL terminal (pin 1) is set to "L"
level, resetting the latch as the voltage at the VREF terminal (pin 9) becomes 1.27 V (Min) or less (Refer to
“■SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT”) .
(2) Under voltage lockout protect ion circuit block (UVLO)
The transient state or a momentary decrease in the power supply voltage, which occurs when the power supply
is turned on, ma y cause the cont rol IC to malfu nction, r esultin g in the brea kdo wn or deg r ada tion of the system.
To prevent such malfunctions, under voltage lockout protection circuit detects a decrease in internal reference
voltage level with respect to the power supply voltage, turns off the output transistor, and sets the dead time to
100% while holding the CSCP terminal (pin 13) at the "L" level.
The system returns to the normal state when the power supply voltage reaches the reference voltage of the
under voltage lockout protection circuit.
(3) Protection circuit operating function table
The following table shows the output state that the prot ection circuit is operating.
Operation circuit OUT1-1 OUT1-2 OUT2 OUT3 OUT4 OUT5 OUT6
Short-circui t pr ot ect i on circu i t H L H H H L L
Under voltage lockout protecti on circuit H L H H H L L
MB39A123
20
■SETTING THE OUTPUT VOLTAGE
Error
Amp
−INE1
CS1
Vo
R1
R2 1.00 V
−
+
+FB1
R3
38
39
37
•ch.1
VO =1.00 V (R1 + R2)
R2
(R1 + R3) ≥ VO
100 µA
Set R1 and R3 to prevent the error amp’s response from decreasing by using above formula.
Error
Amp
−INEX
CSX
Vo
R1
R2 1.23 V
−
+
+FBX
R3
• ch.2 to ch.6
X : Each channel number
VO =1.23 V (R1 + R2)
R2
(R1 + R3) ≥ VO
100 µA
Set R1 and R3 to prevent the error amp’s response from decreasing by using a bove formula.
MB39A123
21
Error
Amp
−INE4
CS4
Vo
R1
R2
1.23 V
Vo = R2
−1.23 V R1
R3 FB4
INVAmp
−INA
OUTA
R4
−
+
−
+
+
19
18
15
16
17
• ch.4 (Negative voltage output)
MB39A123
22
■SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY
The triangular wav e oscillation frequency can be set b y connecting a timing resistor (R T ) to the RT terminal (pin
11) and a timing capacit or (CT) to the CT terminal (pin 12).
Triangular wave oscillation frequency : fOSC
fOSC (kHz) :=680000
CT (pF) × RT (kΩ)
MB39A123
23
■SETTING THE SOFT-START TIME
To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors
(CS1 to CS6) to the CS1 terminal (pin 39) to CS6 terminal (pin 27) respectively.
As illustrated below, when each CTLX is set to “H” from “L”, the soft-start capacitors (CS1 to CS6) externally
connected to the CS1 to CS6 terminals are charged at about 1.1 µA.
The error amplif ier output (FB1 to FB6) is det ermined b y comparison between the lo wer v oltage of the two no n-
inverted input terminal voltage (1.23 V (ch.1 : 1.0 V) , CS terminal voltage) and the inverted input terminal voltage
(−INE1 to −INE6) . The FB terminal voltage is decided for the soft-start per iod (CS ter minal voltage < 1.23 V
(ch.1 : 1.0 V) ) by the comparison between −INE terminal voltage and CS terminal voltage. The DC/DC converter
output voltage rises in propor tion to the CS terminal voltage as the soft-start capacitor externally connected to
the CS terminal is charged. The soft-start time is obtained from t he following formula :
Soft-start time : ts (time until output voltage 100%)
ch.1 : ts (s) := 0.91 × CS1 (µF)
ch.2 to ch.6 : ts (s) := 1.12 × CSX (µF) X : Each channel numbe r
Vo
R1
R2
C
SX
−INEX
CSX
FBX
Error
AmpX
1.23 V (ch.1 : 1.0 V)
VREF
1.1 µA
CHCTL
CTLX
−
+
+
H : CSX can be charged when CTLX is set to "H" and
normal operation is selected
L : CSX is discharged when CTLX is set to "L" and
protective oper ation is selected
L priority
X : Each channel number
MB39A123
24
■PROCESSING WHEN NOT USING CS TERMINAL
When soft-start function is not used, leave the CS1 terminal (pin 39), the CS2 terminal (pin 40), the CS3 terminal
(pin 47), the CS4 terminal (pin 17) , th e CS5 te rmin al (p in 20 ) an d th e CS6 terminal (p in 27 ) op e n.
20
CS5
27
CS6
17
CS4
47 CS3
39 CS1
40 CS2
• When not setting soft-start time
“Open”
“Open”
“Open”“Open”
“Open”
“Open”
MB39A123
25
■SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION
CIRCUIT
Each channel uses the sho rt-circuit detection compar ato r (SCP) to always compare the error amplifier ’s output
level to the re ference voltage.
While DC/DC con verter load conditions are stab le on all channels, the short-circuit detection compa rator output
remains at “L” level, and the CSCP ter m inal (pin 13) is held at “L” level.
If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage
to drop, the output of the short-circuit detection comparator on that channel goes to “H” level.
This causes the exter n al short-circuit protection capacitor CSCP connected to the CSCP terminal (pin 13) to be
charged at 1 µA.
Short-circuit detection time : tCSCP
tCSCP (s) := 0.70 × CSCP (µF)
When the capacitor CSCP is charged to the threshold voltage (VTH := 0.70 V) , the latch is set to and the external
FET is turned off (dead time is set to 100%) . At this time, the latch input is closed and CSCP terminal (pin 13)
is held at “L” level.
The short-circuit detection from e xternal input is capab le b y using −INS terminal (pin 8) . In this case, the short-
circuit detection operates when the −INS terminal voltage becomes the level of the threshold voltage (V TH := IV)
or less.
Note that the latch is reset as the voltage at the VREF term inal (pin 9) is decreased to 1.27 V (Min) or less by
either recycling the power sup ply or setting the CTL terminal (pin 1) to “L” le vel.
MB39A123
26
1.1 V
1 µA
UVLO
CSCP
S
R
Latch
CTL
SCP
Comp.
13 VREF
Vo
R1
R2
Error
AmpX
1.23 V (ch.1 : 1.0 V)
−INEX
FBX
−
+
−
+
+
CTL
CSCP
To each
channel drive
• Timer-latch short-circuit protection circuit
X : Each channel
number
MB39A123
27
■PROCESSING WHEN NOT USING CSCP TERMINAL
To disable the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 13) to GND in the
shortest distance.
13
GND
10
CSCP
• Processing when not using the CSCP terminal
MB39A123
28
■SETTING THE DEAD TIME (ch.2 to ch.6)
When the device is set f or step-up or inv erted output based on the step-up, step-up/down Zeta method, step up/
down Sepic method, or flyback method, the FB terminal voltage may reach and exceed the triangular wave
voltage due to load fluctuation. If this is the case, the output transistor is fixed to a full-ON state (ON duty =
100%). To prevent this, set the maximum duty of the output transistor.
When the DTC terminal is opened, the maximum duty is 92% (Typ) because of this IC built-in resistor which
sets the DTC terminal voltage. This is based on the following setting: 1MHz (RT = 6.8kΩ/CT = 100pF).
To disable the DTC terminal, connect it to the VREF terminal (pin 9) as illustrated below (when dead time is not
set).
To change the maximum duty using e xternal resistors , set the DTC terminal volt age by dividing resistance using
the VREF voltage. Refer to “• When dead time is set : (Setting by external resistors)”.
It is possib le to set wi thout regard f or the b uilt-in resistance value (i ncluding tolerance) whe n setting the e xternal
resistance value to 1/10 of the built-in resistance or less.
Note that the VREF load current must be set such that the total current for all the channels does not exceed 1 mA.
When the DTC terminal voltage is higher than the triangular wave voltage, the output transistor is turned on.
The formula for calculating the maximum duty is as follows, assuming that the triangular wave amplitude and
triangular wave lower limit voltage are about 0.5 V and 0.4 V, respectively.
Note : DUTY ob tained by the above-men tioned formula is a calculated value. For setting, refer to “ON Duty cycle
vs. DTC terminal voltage”.
The maximum duty varies depending on the oscillation frequency, regardless of settings in built-in or exter nal
resistors.
(This is due to the dependency of the peak value of a triangular wave on the oscillation frequency and RT.
Therefore, if RT is greater, the maximum dut y decreases, even when the same frequency is used.)
• When dead time is set:
(Setting with built-in resistor:
1MHz [RT = 6.8kΩ/CT = 100pF] := 92%)
X : ch.2 to ch.6
• When dead time is not set:
X : ch.2 to ch.6
DUTY (ON) Max := Vdt − 0.4 V × 100 (%)
0.5 V
Vdt = Rb × VREF (V) (condition : Ra < R1 , Rb < R2 )
Ra + Rb 10 10
DTCX
“Open”
DTCX
VREF
9
MB39A123
29
Fur thermore, the maximum duty increases when the power supply voltage and the temperature are high. It is
therefore recommended to set the duty, based on the “■ TYPICAL CHARACTERISTICS” data, so that it does
not exceed 95% under the worst conditions.
50
55
60
65
70
75
80
85
90
95
100
0.6 0.65 0.7 0.75 0.8 0.85 0.9
fosc = 200 kHz
fosc = 1 MHz
fosc = 2 MHz
fosc = 1 MHz
Ta = + 25 °C
VCC = CTL = 4 V
FB = 2 V
C
T
= 100 pF
ON duty cycle vs. DTC termina l voltag e
Calculated value
ON duty cycle Dtr (%)
DTC terminal voltage VDTC (V)
DTCX
Ra
Rb
Vdt
R1 : 131.9 kΩ
R2 : 97.5 kΩ
GND
VREF
9
10
• When dead time is set
(Setting by exte rn al re sist or s)
To PWM Comp.X
X: ch.2 to ch.6
MB39A123
30
Setting example (for an aim maximum ON duty of 80% (Vdt = 0.8 V) with Ra = 13.7 kΩ and Rb = 9.1 k Ω)
• Calculation using external resistors Ra and Rb only
• Calculation taking account of the built-in resistor (tolerance ± 20%) also
Based on (1) and (2) above, selecting external resistances to 1/10th or less of the built-in resistance enables
the built-in resistance to be ignored.
As for the duty dispersion, please expect ± 5% at (fosc = 1 MHz) due to the dispersion of a triangular wave
amplitude.
■PROCESSING WHEN NOT USING ch.4 INV AMP
Short-circuit the - INA terminal (pin 19) and OUTA terminal (pin 18) in the shortest distance when not using ch.4
INV Amp.
Vdt = Rb × VREF := 0.80 V
Ra + Rb
DUTY (ON) Max := Vdt − 0.4 V × 100 (%) := 80% ⋅ ⋅ ⋅ ⋅ (1)
0.5 V
Vdt = (Rb, R2 Combined resistance) × VREF := 0.80 V ± 0.13%
(Ra, R1 Combined resistance) + (Rb, R2 Combined resistance)
DUTY (ON) Max := Vdt − 0.4 V × 100 (%) := 80% ± 0. 2% ⋅ ⋅ ⋅ ⋅ (2)
0.5 V
19
OUTA
18
−INA
• When not using ch.4 INV Amp
MB39A123
31
■OPERATION EXPLANATION WHEN CTL TURNING ON AND OFF
When CTL is turned on, internal reference voltage VR and VREF generate. When VREF exceeds each threshold
voltage (VTH) of UVLO (under voltage lock out protection circuit) , UVLO is released, and the operation of output
drive circuit of each channel beco mes possible.
When CTL is off, the CS and CSCP terminals are always set to "L" as soon as output drive circuit of each channel
is fix ed to full off even if UVLO is relea sed. When VR and VREF fall and VREF decreases the thresh old v oltage
(VRST) of UVLO (under voltage lockout protecti on circuit), output drive circuit becomes the UVLO state.
Power
ON/OFF
CTL
VR
Error Amp reference
1.0 V/1.23 V
VREF
bias
CTL
VREF
UVLO1
SCP
VCC
UVLO2
48
1
9
H : UVLO release
H : at SCP
H : UVLO release
ch.1 to ch.4
To output drive circuit
H : Possible to operate
L : Forced stop
CS1 to CS4
To charge/discharge circuit
H : Possible to charge
L : Forced discharge
ch.5, ch.6
To output drive circuit
H : Possible to operate
L : Forced stop
CS5, CS6
To charge/discharge circuit
H : Possible to charge
L : Forced discharge
To SCP circuit
: Possible to
operate SCP
: CSCP
terminal low
H
L
• CTL block equivalent circuit
MB39A123
32
*1 : As shown in the sequence on the above figure, when turning off CTL while each CHCTL is turned on, intermission
state may be generated due to noise around the CTL
threshold
voltage. To prevent this, it is recommended
to turn off CTL with a slope of - 1 V/50
µ
s or higher so that the CTL voltage does not remain in the specified
threshold
voltage range (0.5 V to 1.5 V) . If the above slope setting is difficult to achieve, it is recommended
to turn off CTL after turning off all CHCTLs.
Moreov er, a v oltage remains in the FB terminal, when VCC is turned off at the same time as CTL and CHCTL,
or when VCC is turned off at the same time as CTL while each CHCTL is still turned on. As this may lead to
an ov ershoot upon restart, it is recommended to tu rn off V
IN
and CTL after turning off all the CHCTLs to reduce
FB to 0V.
Likewise, it is recommended to turn off CHCTL with a slope of - 1 V/50
µ
s or higher.
*2 : When CTL and CHCTL are turned on at the same time, or when CTL is turned on while each CHCTL is turned
on, there e xists a period (appro x. 200 ns) when the error Amp output v oltage (FB) is higher tha n the triangular
wave voltage (CT) upon the startup of VREF. As a result, when UVLO is released and then the Output Drive
circuit of each channel becomes operable, the output transistor is turned on, generating a voltage at the DC/
DC converter output.
The voltage to be generated (Vop) depends on L, Co and V
IN
. (See
•
Vo characteristics (Vop) when turning on CTL
at CHCTL ON.)
It should be noted that the above event does not occur when CTL is turned on while CHCTL is turned off.
Therefore, it is recommended to turn on each CHCTL after turning on CTL.
UVLO2
CTL
VREF
L
H
L
H
0 V
2 V
ch.1 to ch.4
Output Drive
circuit control L
H
VTH1 VRST1
VR 0 V
1.23 V
UVLO1 L
H
ch.5, ch.6
Output Drive
circuit control L
H
VTH2 VRST2
∗1∗2
UVLO state
UVLO state
UVLO state
UVLO state
Fixed full off
Fixed full off
Fixed full off
Fixed full off
UVLO release
Possible operate
UVLO release
Possible operate
• Operatio n waveform when CTL turning on and off
MB39A123
33
3
2
1
10
0
5
CTL[V]
02 4 6 8 10 12 14 16 18 20 t[ms]
0
1
2
Vo[V]
3
4
50
1
CS[V]
2
CTL
CTL
CS
CS
Vo
Vo
Vo
VD
DCo
L
IL
0
100
200
300
400
500
600
1 10 100
L = 68 µH
L = 6.8 µH
Ta = + 25 °C
VCC = CTL = 7.2 V
VD
IL
Vo
Ip
VIN
TON
Ip = VIN / L × TON
Vop
Vop = Q / Co
Step-down operation
VIN = 7.2 V
Vo = 5 V
L = 15 µH
Co = 2.2 µF
Load = 50 Ω
CHCTL = ON
Generated voltage
Vop := 0.4 V
Generated output voltage - Output capacitor value
This energy Q
moves to Co
Output capacitor value Co (µF)
Generated ou tput voltage (mV)
At evaluating Fujitsu EV board system
At evaluating Fujitsu EV board system
When no load is
applied
• Vo characteristics (Vop) when turning on CTL at CHCTL ON
MB39A123
34
■ABOUT THE LOW VOLTAGE OPERATION
1.7 V or more is necessary for the VCC terminal (pin 48) and the VCCO terminal (pin 36) for the self-power
supply type to use the step-up circuit as the start voltage .
Ev en if t her eaft er VIN voltage decreases to 1 .5 V, op eration is possible if t he VCC terminal (pin 48) voltage and
the VCCO terminal (pin 36) voltage rise to 2.5 V or more after start-up. However, it is necessary not to exceed
the maximum dut y set value by the duty due t o the V IN decrease . In cludin g othe r cha nne ls, execute an enough
operation margin confirmation when using it.
Error
Amp5
−INE5
CS5
R1
R2 1.23 V
Drive5
<<ch.5>>
N-ch
A
Vo5
(5 V)
A
VCC
VCCO
VIN
PWM
Comp.5
0.9 V
0.4 V
DTC5
−
+
+
−
+
+OUT5
VREF
Max Duty
92% ± 5%
21
20
23
36
30
48
Step-up
MB39A123
35
■I/O EQUIVALENT CIRCUIT
(Continued)
1.23 V
VCC
9VREF
GND
124 kΩ
79 kΩ
48
10
+
−
GND
86 kΩ
CTLX
223 kΩ
VCC
CSX
GND
VREF
(2.0 V) VCC
13 CSCP
GND
VREF
(2.0 V)
2 kΩ
VCC VREF
(2.0 V)
VCC
GND
−INS 8
100 kΩ
(1 V)
0.64 V
11 RT
GND
VREF
(2.0 V)
+
−
VCC
GND
VREF
(2.0 V)
12
CT
VCC
VREF
(2.0 V)
VCC
GND
FBX
CSX
−INEX
1.0 V (ch.1)
1.23 V (ch.2 to ch.6)
X : Each channel number
• Reference voltage block • Control block (CTL, CTL1 to CTL6 )
ESD
protection
element
• Soft-start block • Short-circuit detection block • Short-circuit detection
comparator block
• Triangular wave oscillator block (RT) • Triangular wave oscillator block (CT)
• Error amplifier block (ch.1 to ch.6)
ESD
protection
element
ESD
protection
element
MB39A123
36
(Continued)
OUTX
GNDO
VCCO 36
28
VCC
GND
DTCX
FB2 to FB6 CT
VREF
(2.0 V) 131.9 kΩ
97.5 kΩ
18
VREF
(2.0 V)
VCC
GND
OUTA
19
−INA
X : Each channel number
• Output block• PWM comparator block
• Inverting amplifier block
MB39A123
37
■LAND MASK PATTERN (BCC-48++)
7.20
4- 0.55
49- 0.55
6.80
6.80
7.20
0.70
0.50
0.30
0.80
0.90
C0.20
Mounting Terminal Dimension
7.10
4- 0.50
49−∅0.52
6.75
6.75
7.10
0.70
0.24
0.23
0.70
0.80
C0.20
Mask Dimension (t = 0.15 mm)
Unit : mm
MB39A123
38
■USAGE PRECAUTIONS
• Printed circuit board ground lines should be set up with consideration for common impedance.
• Take appropriate static electricity measures.
• Containers f or se miconductor mate rials should have anti-static protection o r be made of co nduct ive mate rial.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be gr ounded with resistance of 250 kΩ to 1 MΩ between body and ground.
• Do not apply a negative voltages.
• The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause
abnormal operation.
■ORDERING IN FORMATION
■EV BOARD ORDERING INFORMATION
■RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION
The LSI products of Fujitsu Microelectronics with “E1” are compliant with RoHS Directive , and has obser ved
the standard of lead, cadmium, mercury, Hexa v alent chromium, polybrominated biphenyls (PBB) , and polybro-
minated diphenyl ethers (PBDE) .
The product that conforms to this standard is added “E1” at the end of the part number.
Part number Pac kage Remarks
MB39A123PMT-❏❏❏E1 48-pin plastic LQFP
(FPT-48P- M26) Lead Free version
MB39A123PVK-❏❏❏E1 48-pin plastic BCC
(LCC-48P-M08) Lead Free version
EV board part No. EV board version No. Remarks
MB39A123EVB-02 Board Rev.1.0 LQFP-48P
MB39A123
39
■MARKING FORMAT (LEAD FREE VERSION)
INDEX
M
XXXX E1
J
XXX
B39A123
APAN
INDEX
M
XXXX E1
B39A123
XXX
LQFP-48P
(FPT-48P-M26)
BCC-48++
(LCC-48P-M08)
Lead Free version
Lead Free version
MB39A123
40
■LABELING SAMPLE (LEAD FREE VERSION)
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
Lead-free mark
JEITA logo JEDEC logo
Lead Free version
MB39A123
41
■MB39A123PMT-❏❏❏E1, MB39A123PVK-❏❏❏E1
RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
[Temperature Profile for FJ Standard IR Reflow]
(1) IR (infrared reflow)
(2) Manual soldering (partial heating method)
Conditions : Temperature 400 °C Max
Times : 5 s max/pin
Item Condition
Mounting Method IR (infrared reflow) , Manual soldering (partial heating method)
Mounting times 2 times
Storage period
Before opening Please use it within two years after
Manufacture.
From opening to the 2nd
reflow Less than 8 days
When the storage period after
opening was exceeded Please processes within 8 days
after baking (125 °C, 24H)
Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
260 °C
(e)
(d')
(d)
255 °C
170 °C
190 °C
RT (b)
(a)
(c)
to
Note : Temperature : the top of th e package body
(a) Temperatu re Increase gradient : Average 1 °C/s to 4 °C/s
(b) Preliminary heating : Temperature 170 °C to 190 °C, 60 s to 180 s
(c) Temperatur e Increa se gradient : Average 1 °C/s to 4 °C/s
(d) Actual heating : Temperature 260 °C Max; 255 °C or more, 10 s or less
(d’) : Temperature 230 °C or more, 40 s or less
or
Temperature 225 °C or more, 60 s or less
or
Temperature 220 °C or more, 80 s or less
(e) Cooling : Natural cooling or forced cooling
H rank : 260 °C Max
MB39A123
42
■PACKAGE DIMENSIONS
(Continued)
48-pin plastic BCC Lead pitch 0.50 mm
Package width ×
package length 7.00 mm × 7.00 mm
Sealing method Plastic mold
Mounting height 0.80 mm Max
Weight 0.07 g
48-pin plastic BCC
(LCC-48P-M08)
(LCC-48P-M08)
C
2004 FUJITSU LIMITED C48061S-c-1-1
1
13
3725
5.00(.197)
REF
6.25(.246)
REF
"B" "C"
"A"
6.25(.246)REF
6.10(.240)
TYP
0.50±0.10
(.020±.004)
0.50(.020)
TYP
5.00(.197)REF
6.20(.244)TYP
0.075±0.025
(.003±.001)
13
2537
1
7.00±0.10(.276±.004)
(Stand off)
7.00±0.10
(.276±.004)
0.05(.002)
INDEX AREA
TYP
0.50(.020)
0.50±0.10
(.020±.004)
5.00±0.06
4.60(.181)
0.60±0.06
MIN
0.14(.006) 0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
Details of "C" part
C0.20(.008)
0.30±0.06
(.012±.002)
(.024±.002)
0.70±0.06
(.028±.002)
Details of "A" part
(.022±.002)
0.55±0.06
(.022±.002)
0.55±0.06
Details of "B" part
0.09(.004)
MIN
0.14(.006)
MIN
6.20(.244)
TYP
6.10(.240)TYP
(.197±.002)
5.00±0.06
(.197±.002)
4.60(.181)
0.80(.031)MAX
Mount height
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB39A123
43
(Continued)
48-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 7× 7 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Weight 0.17 g
Code
(Reference) P-LFQFP48-7×7-0.50
48-pin plastic LQFP
(FPT-48P-M26)
(FPT-48P-M26)
C
2003 FUJITSU LIMITED F48040S-c-2-2
24
13
3625
48
37
INDEX
SQ
9.00±0.20(.354±.008)SQ
0.145±0.055
(.006±.002)
0.08(.003)
"A" 0˚~8˚
.059 –.004
+.008
–0.10
+0.20
1.50
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
Details of "A" part
112
0.08(.003)M
(.008±.002)
0.20±0.05
0.50(.020)
LEAD No.
(Mounting height)
.276 –.004
+.016
–0.10
+0.40
7.00
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited Strategic Business Development Dept.
