IR5001S & (PbF)
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UNIVERSAL ACTIVE ORING CONTROLLER
Data Sheet No.PD60229 revB
F 1 - Typical application of the IR5001S in - 48V input, carrier class telecommunications equipment.
TYPICAL APPLICATIONAPPLICATIONS
+48V input
-48V in p ut B
-48V in p ut A
IR5001
Vline
Vcc
FETch
INP
INN
Gnd
Vout
FETst
IR5001
DC
DC
FET Check Pulse
FET A Status
Fet B Status
A
B
Vline
Vcc
FETch
FETst
Vout
Gnd
INN
INP
FEATURES
DESCRIPTION
The IR5001S is a universal high-speed controller and
N-channel power MOSFET driver for Active ORing and
reverse polarity protection applications. The output voltage
of the IR5001S is determined based on the polarity of the
voltage difference on its input terminals. In particular, if the
current flow through an N-channel ORing FET is from
source to drain, the output of the IR5001S will be pulled
high to Vcc, thus turning the Active ORing FET on. If the
current reverses direction and flows from drain to source
(due to a short-circuit failure of the source, for example),
the IC will quickly switch the Active ORing FET off. Typical
turn-off delay for the IR5001S is only 130nS, which helps
to minimize voltage sags on the redundant dc voltage.
Both inputs to the IC (INN and INP) as well as Vline
input contain integrated high voltage resistors and internal
clamps. This makes the IR5001S suitable for applications
at voltages up to 100V, and with a minimum number o
f
external components.
Controller / driver IC in an SO-8 package fo
r
implementation of Active ORing / reverse polarit
y
protection using N-channel Power MOSFETs
Suitable for both input ORing (for carrier class
telecom equipment) as well as output ORing fo
r
redundant DC-DC and AC-DC power supplies
130ns Typical Turn-Off delay time
3A Peak Turn-Off gate drive current
Asymmetrical offset voltage of the internal high-speed
comparato r preven ts pote ntia l o sc ill atio ns at light lo a d
Ability to withstand continuous gate short conditions
Integrated voltage clamps on both comparator inputs
allow continuous application of up to 100V
Option to be powered either directly from 36-75
V
universal telecom bus (100V max), or from an
external bias supply and bias resistor
Input/Output pins to determine the state of the Active
ORing circuit and power system redundancy
-48V/-24V Input Active OR ing for carrier
class com munication equipment
R e v e rs e in p ut p o la rity p r ot e c tion for
DC-DC power supplies
2 4 V /48 V o utp u t a c tiv e OR in g fo r
redundant AC-DC rectifiers
Low output voltage (12V, 5V, 3.3V...)
active ORing for redundant DC-DC
and AC-DC power supplies
A c tiv e ORing o f mu ltip le v o lta ge
regulators for re dundan t p rocessor
power
θJA=128°C/W
INP
Vout
Gnd
INN
Vline
4
3
2
1
5
6
7
8
FETst
Vcc
FETch
Top View PACKAGE / ORDERING INFORMATION
PKG PART LEADFREE PIN PARTS PARTS T & R
DESIG. NUMBER PART NUMBER COUNT PER TUBE PER REEL Oriantation
S IR5001S IR5001SPbF 8 95 ------
S IR5001STR IR5001STRPbF 8 ------- 2500 Fig A
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Unless otherwise specified, these specifications apply over Vline = 36V to 100V; Vcc is decoupled with 0.1uF to
Gnd, CL=10nF at V out; INP is connected to Gnd. T ypical values refer to TA=25°C. Minimum and maximum limits
apply to TA= 0°C to 85°C temperature range and are 100% production-tested at both temperature extremes. Low
duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.
ABSOLUTE MAXIMUM RATINGS
CAUTION:
1. Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress only rating and operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied.
2. This device is ESD sensitive. Use of standard ESD handling precautions is required.
.
ELECTRICAL SPECIFICATIONS
Vline Voltage -5.0V to 100V (continuous)
Vcc Voltage -0.5V to 15VDC
Icc Current 5mA
INN, INP Voltage -5.0V to 100V (continuous)
FETch, FETst -0.5V to 5.5V
FETst Sink Current 10mA
Junction Temperature -40°C to 125°C
Storage Temperature Range -65°C to 150°C
P ARAMETERS S YM BOL T ES T CO NDIT IO N M I N T YP M AX UNIT S
Vline=25V 0.14 0.3 0.5
Vline=36V 0.2 0.5 0.75
V li ne= 100V, Not e 1 1. 2 1. 7 2. 2
V CC out put volt age V c c(out ) V li ne= 25V 10. 2 12. 5 14. 1 V
UV L O S ecti o n
UV LO ON Thres hold V ol tage Vcc(ON)
Vli
ne=open,
VINP
=
0
;
VINN
= -
0.3V
V c c inc reas ed unt il V out s wit c hes
from LO to HI
,
Note 2
8.0 9.6 10.7
UV LO OF F Thres hold V olt age V c c (OFF ) V li ne= open, V INP= 0, VINN= -
0. 3V , V c c is dec reas ed unt il
V out s wit c hes from HI t o LO 5.6 7.2 8.8
UV LO Hy s t eres is 1. 6 2.3 2. 8 V
Input Com pa rator Se ction
Input Offset V olt age (V INP -
VINN) Vos V INP = 0V and V INN Ram ping up,
V O UT c hanges from HI t o LO ,
Fig.3 -7.9 -4.0 0
Input Hy s teres is V ol tage V hy s t V INP =0, VINN ram ping down,
F igures 3 and 4 13 31 44
(INN) Input Bias Current I(INN) V INP =0V , V INN= 36V 0. 2 0. 5 0. 9
(INP ) Input B ias Current I(INP ) VINN= 0V , V INP =36V 0. 2 0. 5 0. 9 mA
mV
Iline
Bia s Section
V li ne B i as Current
V
mA
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PIN DESCRIPTIONS
Note 1: Guaranteed by design but not tested in production.
Note 2: Low Vcc output voltage corresponds to low UVLO voltage
PIN# PIN SYMBOL PIN DESCRIPTION
1 Vline IC power supply pin for 36V to 75V input communications systems.
M inim um 25V has t o be applied at t his pin t o bi as th e IC.
2Vcc
O utput pin of t he int ernal s hunt regul ator, o r input pin for bias i ng the IC via
ex t ernal resis t or. Th is pin is int ernally regulat ed at 12.5 V typic al. A
m inim um 0. 1uF c apac it or m us t be c onnec t ed from t his pin t o G nd of IR5001.
3FETch
F E T c hec k input pin. Toget her wit h F E T s t at us out put pin, t he F E Tc h pin
c an be us ed to det erm ine the s tat e of the A c tive O Ring c irc uit and power
system redundancy.
4FETst
F E T s t atus out put pin. Together wit h F E Tc h input pin, t he FETs t pin can be
used to determine the state of the Active ORing circuit and power system
redundancy.
5INP
P os it ive input of int ernal c om parator. This pin s hould c onn ec t t o t he s ourc e
of N-c hannel A c t i ve O Ring M O S FET.
6INN
Negat ive input pin of int ernal c om parator. This pin s h ould c onnec t t o t he
drain of N-c hannel A c t ive O Ring MOS F E T.
7 G nd G round pin of the IR5001.
8 Vout O utput pin for t he IR5001. This pin is us ed t o direc t ly drive t he gat e of t he
A c t ive O ri ng N-Channel M OSF E T.
PARAM ETERS S YM BOL TEST CO NDITION M IN TYP M AX UNIT S
Output Section
High Level Output Voltage Vout HI Vline=25V, IO H= 50uA,
V(INN)= - 0.3V 10.2 11.5 14.1 V
Low Level Out put Volt age Vout LO IOL=10 0mA, V( I NN)= + 0 . 3V 0. 1 V
Turn-O n DelayTime t d( on) 5 27 45 us
Rise Time t r 0. 09 0. 7 1 ms
Turn-Off Delay Time td(off) 110 130 170
Fall Time t f 10 26 39
FET ch and FETst
F ETch Si nk Curre nt I(FETch) FETch=5V -0.5 -1.1 -2 uA
FETch O ut p ut Delay Time FETch_pd Note 1 0. 8 1. 8 us
FETch Threshold Vth(FETch) 0.9 1.2 1.5 V
FETst Threshold Voltage Vth(FETst) 5k r esist o r f r om FETst t o 5V logic bias.
V(I NP) = Gnd , V( I NN) r a mping dow n
from 0 until FETst switches to Low. -525 -300 -200 mV
FETst Low Level Out put
Voltage VO L I s ink= 1mA, V( INN)= - 0 . 5V 0 50 100 mV
Vout swit ching from LO to HI, Fig.5
Vout swit ching from HI to LO, Fig.5 ns
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Figure 2 - Simplified block diagram of the IR5001.
BLOCK DIAGRAM
50K
V
LINE
Vcc
V
OUT
9V
Gnd
INP
INN
5V
0.3V
28mV
3.5mV
5V
70K
70K
1.25V
FETst
FETch 2uA
Level
Shifter
12V
1
2
8
7
5
6
4
3
UVLO
12V Shunt
Regulator
5V, V
REF
Generator 1.25V
5V
clamp
clamp
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Figure 3 - Input Comparator Offset (Vos ) and Hysteresis
Voltage (Vhyst) Definition.
Figure 5 - Dynamic Parameters.
Figure 4 - Input Comparator Hysteresis Definition.
PARAMETER DEFINITION AND TIMING DIAGRAM
V
INP
- V
INN
V
OUT
(0,0)
VOS
VHYST
90mV
0
VIN
(VINP - VINN)
VINP - V INN = 200mV
tf
td(off)
90%
50%
10%
VOUT VOL
50mV
-50mV
-90mV
VOH
10ns
td(on)
10ns
tr
V
INN
(V
INP
=Gnd)
V
OUT
-Vos
V
HYST
Gnd
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TYPICAL OPERATING CHARACTERISTICS
5.1
5.2
5.3
5.4
5.5
5.6
5.7
-40 -10 20 50 80 110 140
Temperature (° C)
Vos value (mV)
8.4
8.8
9.2
9.6
10
10.4
10.8
-40 0 40 80 120
Temperature (° C)
UVLO_upper ( V)
16
18
20
22
24
26
28
-40 0 40 80 120
T em perat ure ( °C)
Fall time (ns)
-380
-360
-340
-320
-300
-280
-40-200 20406080100
Temperature (° C)
FETst t hreshold (mV
)
120
130
140
150
160
170
180
-40 -20 0 20 40 60 80 100
T em per ature (° C)
td(off) (ns)
15
17
19
21
23
25
27
29
31
-40 -10 20 50 80 110 140
Tem p erat ure (° C)
Hysteresis( mV)
Figure 6 - Turn Off Delay vs. Junction Temperature
Figure 8 - Vos vs. Junction Temperature Figure 9 - Fall Time vs. Junction Temperature
Figure 10 - INP, INN Input Hysteresis vs. Junction Temp. Figure 11 - FETst Threshold Voltage vs. Junction Temp.
Figure 7 - UVLO Upper Trip Point vs. Junction Temperature
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117.0
117.5
118.0
118.5
119.0
119.5
120.0
120.5
121.0
20 40 60 80 100
Vline (V)
Toff delay (nS
)
TYPICAL OPERATING CHARACTERISTICS
0
0.2
0.4
0.6
0.8
1
1.2
1.4
20 40 60 80 100
IN N (V)
I INN (mA
)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
20 40 60 80 100
Vline ( V)
I Vline ( m A)
Figure 13 - I(Vline) vs. Vline and Junction Temperature
Figure 15 - Turn Off Delay vs. Vline at Room Temperature
Figure 14 - Bias Current I(INN) vs. V(INN) at Vline=25V
11.6
11.8
12
12.2
12.4
12.6
12.8
13
20 40 60 80 100
Vline ( V)
Vcc (V)
Figure 12 - Vcc vs. Vline and Junction Temperature
Bottom:
Top: 25°C
85°C
125°C
-40°C Bottom:
Top: 125°C
85°C
25°C
-40°C
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DETAILED PIN DESCRIPTION
V
line and Vcc
Vline and Vcc are the input and output pins o
f
the internal shunt regulator. The internal shunt
regulator regulates the Vcc voltage at ~12V. The
Vcc pin should always be by-passed with a ceram ic
capacitor to the Gnd pin.
Both Vline a nd Vcc pins c an be used for bias ing
the IR5001S, as shown in Fig. 16. The Vline pin is
designed to bias the IR5001S directly when the
available bias voltage is above 25V and less than
100V (targeted at typical 36V – 75V telecom
applications). This connection is shown in Fig 16.a.
If the a vailable Vbias volta ge is l ower t han 25V, then
the IC m ust be biased using Vc c pin a nd an exter nal
bias resistor as shown in Fig. 16.b. If the available
bias vo ltage is abov e 100V, both Vline and Vcc pins
can be used with an external bias resistor. Fo
r
calculation of the proper bias resistor value, see
example below.
When the Vcc pin is used for biasing the
IR5001S, the Vbias must always be higher than the
maximum value of the Vcc UVLO threshold (10.7V).
The Rbias resistor should always be connected
between the Vbias voltage source and Vcc pin. The
Rbias resistor is selected to provide adequate Icc
current for the IC. The minimum required Icc to
guarantee pr o per IC o per ation un der al l conditions is
0.5mA. The maximum Icc is specified at 5mA.
Vbias
IR5001
Vcc
FETch
INP
INN
Gnd
OUT
FETst
Vline
+
a)
b)
Vbias
IR5001
Vcc
FETch
INP
INN
Gnd
OUT
FETst
Vline
Rbias
+
Figue 16 - Biasing options for IR5001
An example of Rbias calculation is given below.
Vbias voltages used in the example are referenced
to IR5001S Gnd:
Vbias min = 12V
Vbias max = 16V
Rbias = (Vbias min – Vcc UVLOmax) / Icc min =
= (12V – 10.7V) / 0.5mA = 2.6kOhm
Next, using a minimum Vcc (10.2V), verify that Icc
with the selected Rbias will be less than 5mA:
Icc max = (Vbias max – Vcc min)/Rbias =
= (16V - 10.2V) / 2.6kOhm = 2.23mA
Since 2. 23m A is below 5m A max Icc, the calculated
Rbias (2.6kOhm) can be used in this design.
INP and INN Inputs
INP and INN are the inputs of the internal high-
speed comparator. Both pins have integrated on-
board voltage clamps and high-voltage 70kOhm
resistors.
In a typical application, INP should be connected
to the source of the N-F ET and INN to the drai n. To
improve the noise immunity, the connections from
INN and INP pins to the source and drain terminals
of the N-FET should be as short as possible.
The (INP – INN) voltage difference determines
the state of the Vout pin of the IR5001S. When the
body diode of the Active ORing N-FET is forward-
biased and the current first starts flowing, the
voltage difference INP – INN will quickly rise toward
~700mV (typical body diode forward voltage drop).
A
s soon as this voltage exceeds Vhyst – Vos
(27mV typical), the Vout of the IR5001S will be
pulled high, turning the channel of the active ORing
FET on. As the channel of the N-F ET becomes fully
enhanced, the (INP – INN) will reduce and stabilize
at the value determined by the source-drain current,
Isd, and Rds(on) of the N-FET:
(INP – INN) steady state = Isd * RDS(on).
If for some reason (due to a short-circuit failure o
f
the source, for example), the current reverses
direction and tries to flow from drain to source, the
(INP – INN) will become negative; The IR5001S will
then quickly pull its output low, switching the ORing
FET off. For considerations regarding the selection
of the Active ORing N-FET and RDS(on), see
A
pplications Information Section.
The off set voltage of the internal high-spe ed
compar ator is c entered around neg ative 4m V, and is
always less than 0mV. This asymmetrical offset
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guarantees that once the ORing N-FET is
conducting and Vout of the IR5001S is high (FET
current flows from source to drain), the current must
reverse the direction before the IR5001S will switch
the FET off. The asymmetrical offset voltage
prevents po tential osci llations at ligh t load that coul d
otherwise occur if the offset voltage was centered
around 0mV (as is the case in standard
comparators).
V
out
Vout is t he outp ut pin of the IR5001S, and connects
directly to the gate of the external Active ORing N-
FET. The voltage level at the Vout pin is typically a
diode drop lower than the Vcc voltage.
FETst and FETch
FETch and FETst pins are diagnostic pins that can
be used to determ ine the status of the Active ORing
circuit.
FETst is an open-drain output pin. When the volta ge
difference between VINP - VINN is less than 0.3V,
the FETst pin will be logic high. This is normally the
case when Act ive ORing is operating pr operly (VINP
- VINN is less than ~100mV). If the Active ORing
FET is not turned on while the IR5001S is properly
biased, the output of the FETst pin will be logic low
(only the body diode of the N-FET is conducting, and
VINP - VINN is ~700mV).
FETch pin. In traditio nal s ystem s with diode ORing,
it is not possible to determine if the diode is
functioni ng pr operly unless externa l c ircuitry is used.
For example, the diode could be failed short, and the
system would not b e awar e of it until the s ource f ails
and the whole system gets powered down due to
lost redundancy (shorted diode failed to isolate the
source failure). With the FETch pin it is possible to
perform a periodic check of the status of the Active
ORing circuit to assure that system redundancy is
maintained.
In the IR50 01S , t he FETc h pi n is a n inp ut pi n t hat
can be used to turn off the output of the IR5001S:
logic h igh signal on FET ch will pull t he Vout pin lo w,
and turn-off the channel of the Act ive ORing N-FET .
This will force the current to flow through the body
diode, resulting in VINP – VINN voltage increase
from less than ~100mV, to ~700mV. This voltage
increase will be reported at FETst pin, which will
switch from logic high to logic low, and indicate that
the Active ORing circuit is working properly. Failure
of the FETst pin output to change from logic high to
logic low would indicate that the Active ORing circuit
may not be operating as designed, and the system
may no longer have power redundancy. For details
on how to use this feature consult IR5001S
Evaluati on Kit, P/N IRDC5001-LS48V.
If the FETch pin is not used, it should be tied to
ground (for noise immunity purposes). FETst pin
should be left open if unused.
Gnd
In typical targe t applic ations, the grou nd pin (Gnd) o
f
IR5001S is connected to the source of the Active
ORing N-FET.
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APPLICATION INFORMATION
The IR5001S is designed for multiple active ORing
and reverse polarity protection applications with
minimal number of external components. Examples
of typical circuit connections are shown below.
Negative Rail ORing/Reverse Polarity Protection
A typical connection of the IR5001S in negative
rail Active ORing or reverse polarity protection is
shown in Fig. 17 . In this exam ple, IR500 1S is b iased
directly from the positive rail. However, any of the
biasing schemes shown in Fig. 16 can be used.
For in put ORing in carrier-class communica tions
boards, one IR5001S is used per feed. This is
shown in Fig.1. An evaluation kit is available fo
r
typical system boards, with input voltages o
f
negative 36V to negative 75V, and for power levels
from 30W to about 300W . The p/n for the evaluat ion
kit is IRDC5001-LS48V. This ev aluation k it contains
detailed design considerations and in-circuit
performance data for the IR5001S.
Positive Rail ORing / Ground ORing in
Communications Boards
An example of a typical connection in positive
rail ORing is shown in Fig. 18. Typical applications
are inside redundant AC-DC and DC-DC power
supplies , or on-bo ard ORin g. For positi ve rail O Ring,
an additional Vbias voltage above the positive rail is
needed to bias the IR5001S.
An evaluation kit for high-current 12V positive
rail ORing is available under p/n IRAC5001-
HS100A, demonstrating performance of the
IR5001S at 100A output current.
Considerations for the Selection of the Active
ORing N-Channel MOSFET
Active ORing FET losses are all conduction
losses, and depend on the source-drain current and
RDS(on) of the FET. The conduction loss could be
virtually eliminated if a FET with very low RDS(on)
was used. However, using arbitrarily low RDS(on) is
not desirable for three reasons:
1. Turn off propagation delay. Higher RDS(on) will
provide more voltage information to the internal
comparator, and will result in faster FET turn of
f
protection in case of short-circuit of the source
(less voltage disturbance on the redundant bus).
2. Undetected reverse (drain to source) current
flow. W ith the asymm etrical offs et voltage, som e
small current can flow from the drain to source
of the ORing FET and be undetected by the
IR5001S. The amount of undetected drain-
source current depends on the RDS(on) of the
selected MOSFET and its RDS(on). To keep the
reverse (drain-source) current below 5 – 10% o
f
the nominal source-drain state, the RDS(on) o
f
the selected FET should produce 50mV to
100mV of the voltage drop during nominal
operation.
3. Cost. With properly selected RDS(on), Active
ORing using IR5001S can be very cost
competitive with traditional ORing while
providing huge power loss reduction. For
exam ple, a FET with 20m Ohm R DS(on) results in
60mV voltage drop at 3A; associated power
savings compared to the traditio nal diode ORing
(assuming typical 0.6V forward voltage drop) is
ten fold(0.18W vs. 1.8W)! Now assume that
FET RDS(on) was 10mOhm. The power loss
would be reduced by additional 90mW , which is
negligible compared to the power loss reduction
alread y achieved with 20mOhm FET. But to get
this negligible saving, the cost of the Active
ORing FET would increase significantly.
Vbias
IR5001
Vcc
FETch
INP
INN
Gnd
OUT
FETst
Vline
Rbias
+
Vin +
Vin -
Load
Redundant Vin -
Vbias
IR5001
Vcc
FETch
INP
INN
Gnd
OUT
FETst
Vline
Rbias
+
Vout +
Vout -
Redundant Vout +
Load
Figure. 18. Connection of INN,INP, and Gnd when the
MOSFET is placed in the path of positive rail.
Figure. 17 Connection of INN, INP, and Gnd for negative
rail Active ORing or reverse polarity protection.
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In a well - designed Active ORing circuit, the
Rds(on) of the Active ORing FET should generate
between 50mV to 100mV of (INP – INN) voltage
during normal, steady state operation. (The normal
operation refers to current flo wing from the source to
drain of the Active ORing FET, half of the full-load
system current flowing through each OR-ed source,
at nominal input voltage). Maximum powe
r
dissipation under worst-case conditions for the FET
should be calculated and verified against the data
sheet limits of the selected device.
IR5001S Thermal cons iderations
Maxim um junction temperature of the I R5001S in an
application should not exceed the maximum
operating junction temperature, specified at 12 5°C :
Tj = Pd iss * R t heta j-a + Ta mb <= T j (max),
where Rtheta j-a is the thermal resistance from
j
unction to ambient thermal resistance (specified at
128 °C/W), Pdiss is IC power dissipation, and Tamb
is operating ambient temperature.
The maximum power dissipation can be estimated
as follows:
Pdiss < (Tj max – Tamb max) / Rtheta j-a
Since T j max = 125 °C, T amb = 85 °C, and Rtheta j- a
= 128 °C/W, the maximum power dissipation allowed
is:
Pdiss max = (125 – 85) / 128 = 0.3W
With proper selection of Icc (as discussed in the
Detailed Pin Description), the maximum powe
r
dissipation will never be exceeded (Max Icc * Max
Vcc = 10mA * 13.9V = 0.14W).
Layout Considerations
INN and INP should be connected very close to
the drain and source terminal of the Active ORing
FET. PCB trace between the Vout pin and the gate
of the N-FET should also be minimized. A minimum
of 0.1uF decoupling capacitor must be connected
from Vcc to Gnd of the IR5001S and should be
placed as c lose to the IR5 001S as possible. Gr ound
should be connected to the source of N-FET
separately from the INP pin.
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the industrial market
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 12/15/2005
(S) SOIC Package
8-Pin Surface Mount, Narrow Body
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
PIN NO. 1
I
K
H
DETAIL-A
DETAIL-A
0.38 +/- 0.015 x 45°
T
G
F
D
A
B C
E
L
J
SYMBOL
A
B
C
D
E
F
G
H
I
J
K
L
T
MIN
4.80
0.36
3.81
1.52
0.10
0.19
5.80
0°
0.41
1.37
MAX
4.98
0.46
3.99
1.72
0.25
0.25
6.20
8°
1.27
1.57
1.27 BSC
0.53 REF
7° BSC
8-PIN
Feed Direction
Figure A
1 11
