CONNECTION DIAGRAM
8-Pin Plastic Mini-DIP (N), Cerdip (Q)
and SOIC (R) Packages
–IN
R
G
–V
S
+IN
R
G
+V
S
OUTPUT
REF
1
2
3
4
8
7
6
5
AD620
TOP VIEW
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Low Cost, Low Power
Instrumentation Amplifier
AD620
FEATURES
EASY TO USE
Gain Set with One External Resistor
(Gain Range 1 to 1000}
Wide Power Supply Range (62.3 V to 618 V)
Higher Performance than Three Op Amp IA Designs
Available in 8-Pin DIP and SOIC Packaging
Low Power, 1.3 mA max Supply Current
EXCELLENT DC PERFORMANCE (“A GRADE”)
125 mV max, Input Offset Voltage (50 mV max
“B” Grade)
1mV/8C max, Input Offset Drift
2.0 nA max, Input Bias Current
93 dB min Common-Mode Rejection Ratio (G = 10)
LOW NOISE
9 nV/√Hz, @ 1 kHz, Input Voltage Noise
0.28 mV p-p Noise (0.1 Hz to 10 Hz)
EXCELLENT AC SPECIFICATIONS
120 kHz Bandwidth (G = 100)
15 ms Settling Time to 0.01%
APPLICATIONS
Weigh Scales
ECG and Medical Instrumentation
Transducer Interface
Data Acquisition Systems
Industrial Process Controls
Battery Powered and Portable Equipment
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
PRODUCT DESCRIPTION
The AD620 is a low cost, high accuracy instrumentation ampli-
fier which requires only one external resistor to set gains of 1 to
1000. Furthermore, the AD620 features 8-pin SOIC and DIP
packaging that is smaller than discrete designs, and offers lower
0 5 10 15 20
30,000
5,000
10,000
15,000
20,000
25,000
0
TOTAL ERROR, PPM OF FULL SCALE
SUPPLY CURRENT – mA
AD620A
R
G
3 OP-AMP
IN-AMP
(3 OP-07s)
Three Op Amp IA Designs vs. AD620
SOURCE RESISTANCE – Ω100M10k1k 10M1M100k
10,000
0.1
100
1,000
10
1
TYPICAL STANDARD
BIPOLAR INPUT
IN-AMP
AD620 SUPERßETA
BIPOLAR INPUT
IN-AMP
RTI VOLTAGE NOISE
(0.1 –10Hz) – µV p-p
G = 100
Total Voltage Noise vs. Source Resistance
power (only 1.3 mA max supply current), making it a good fit
for battery powered, portable (or remote) applications.
The AD620, with its high accuracy of 40 ppm maximum
nonlinearity, low offset voltage of 50 µV max and offset drift of
0.6 µV/°C max, is ideal for use in precision data acquisition sys-
tems, such as weigh scales and transducer interfaces. Further-
more, the low noise, low input bias current, and low power of
the AD620 make it well suited for medical applications such as
ECG and noninvasive blood pressure monitors.
The low input bias current of 1.0 nA max is made possible with
the use of Superβeta processing in the input stage. The AD620
works well as a preamplifier due to its low input voltage noise of
9 nV/√Hz at 1 kHz, 0.28 µV p-p in the 0.1 Hz to 10 Hz band,
0.1 pA/√Hz input current noise. Also, the AD620 is well suited
for multiplexed applications with its settling time of 15 µs to
0.01% and its cost is low enough to enable designs with one in
amp per channel.
AD620–SPECIFICATIONS
(Typical @ +258C, V
S
=
6
15 V, and R
L
= 2 kV, unless otherwise noted)
AD620A AD620B AD620S
1
Model Conditions Min Typ Max Min Typ Max Min Typ Max Units
GAIN G = 1 + (49.4 k/R
G
)
Gain Range 1 10,000 1 10,000 1 10,000
Gain Error
2
V
OUT
= ±10 V
G = 1 0.03 0.10 0.01 0.02 0.03 0.10 %
G = 10 0.15 0.30 0.10 0.15 0.15 0.30 %
G = 100 0.15 0.30 0.10 0.15 0.15 0.30 %
G = 1000 0.40 0.70 0.35 0.50 0.40 0.70 %
Nonlinearity, V
OUT
= –10 V to +10 V,
G = 1–1000 R
L
= 10 kΩ10 40 10 40 10 40 ppm
G = 1–100 R
L
= 2 kΩ10 95 10 95 10 95 ppm
Gain vs. Temperature Gain <1000
2
–50 –50 –50 ppm/°C
VOLTAGE OFFSET (Total RTI Error = V
OSI
+ V
OSO
/G)
Input Offset, V
OSI
V
S
= ±5 V to ±15 V 30 125 15 50 30 125 µV
Over Temperature V
S
= ±5 V to ±15 V 185 85 225 µV
Average TC V
S
= ±5 V to ±15 V 0.3 1.0 0.1 0.6 0.3 1.0 µV/°C
Output Offset, V
OSO
V
S
= ±15 V 400 1000 200 500 400 1000 µV
V
S
= ±5 V 1500 750 1500 µV
Over Temperature V
S
= ±5 V to ±15 V 2000 1000 2000 µV
Average TC V
S
= ±5 V to ±15 V 5.0 15 2.5 7.0 5.0 15 µV/°C
Offset Referred to the
Input vs.
Supply (PSR) V
S
= ±2.3 V to ±18 V
G = 1 80 100 80 100 80 100 dB
G = 10 95 120 100 120 95 120 dB
G = 100 110 140 120 140 110 140 dB
G = 1000 110 140 120 140 110 140 dB
INPUT CURRENT
Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA
Over Temperature 2.5 1.5 4 nA
Average TC 3.0 3.0 8.0 pA/°C
Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA
Over Temperature 1.5 0.75 2.0 nA
Average TC 1.5 1.5 8.0 pA/°C
INPUT
Input Impedance
Differential 10i210i210i2GΩipF
Common-Mode 10i210i210i2GΩipF
Input Voltage Range
3
V
S
= ±2.3 V to ±5 V –V
S
+ 1.9 +V
S
– 1.2 –V
S
+ 1.9 +V
S
– 1.2 –V
S
+ 1.9 +V
S
– 1.2 V
Over Temperature –V
S
+ 2.1 +V
S
– 1.3 –V
S
+ 2.1 +V
S
– 1.3 –V
S
+ 2.1 +V
S
– 1.3 V
V
S
= ±5 V to ±18 V –V
S
+ 1.9 +V
S
– 1.4 –V
S
+ 1.9 +V
S
– 1.4 –V
S
+ 1.9 +V
S
– 1.4 V
Over Temperature –V
S
+ 2.1 +V
S
– 1.4 –V
S
+ 2.1 +V
S
– 1.4 –V
S
+ 2.3 +V
S
– 1.4 V
Common-Mode Rejection
Ratio DC to 60 Hz with
I kΩ Source Imbalance V
CM
= 0 V to ±10 V
G= 1 7390 8090 7390 dB
G = 10 93 110 100 110 93 110 dB
G= 100 110 130 120 130 110 130 dB
G= 1000 110 130 120 130 110 130 dB
OUTPUT
Output Swing R
L
= 10 kΩ,
V
S
= ±2.3 V to ±5 V –V
S
+ 1.1 +V
S
– 1.2 –V
S
+ 1.1 +V
S
– 1.2 –V
S
+ 1.1 +V
S
– 1.2 V
Over Temperature –V
S
+ 1.4 +V
S
– 1.3 –V
S
+ 1.4 +V
S
– 1.3 –V
S
+ 1.6 +V
S
– 1.3 V
V
S
= ±5 V to +18 V –V
S
+ 1.2 +V
S
– 1.4 –V
S
+ 1.2 +V
S
– 1.4 –V
S
+ 1.2 +V
S
– 1.4 V
Over Temperature –V
S
+ 1.6 +V
S
– 1.5 –V
S
+ 1.6 +V
S
– 1.5 –V
S
+ 2.3 +V
S
– 1.5 V
Short Current Circuit ±18 ±18 ±18 mA
REV. D
–2–
AD620
AD620A AD620B AD620S
1
Model Conditions Min Typ Max Min Typ Max Min Typ Max Units
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
G = 1 1000 1000 1000 kHz
G = 10 800 800 800 kHz
G = 100 120 120 120 kHz
G = 1000 12 12 12 kHz
Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs
Settling Time to 0.01% 10 V Step
G = 1–100 15 15 15 µs
G = 1000 150 150 150 µs
NOISE
Voltage Noise, 1 kHz
Total RTI Noise =(e
2ni
)+(e
no
/G)
2
Input, Voltage Noise, e
ni
913 913 913 nV/√Hz
Output, Voltage Noise, e
no
72 100 72 100 72 100 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G = 1 3.0 3.0 6.0 3.0 6.0 µV p-p
G = 10 0.55 0.55 0.8 0.55 0.8 µV p-p
G = 100–1000 0.28 0.28 0.4 0.28 0.4 µV p-p
Current Noise f = 1 kHz 100 100 100 fA/√Hz
0.1 Hz to 10 Hz 10 10 10 pA p-p
REFERENCE INPUT
R
IN
20 20 20 kΩ
I
IN
V
IN+
, V
REF
= 0 +50 +60 +50 +60 +50 +60 µA
Voltage Range –V
S
+ 1.6 +V
S
–1.6 V
S
+ 1.6 +V
S
– 1.6 –V
S
+ 1.6 +V
S
– 1.6 V
Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001
POWER SUPPLY
Operating Range
4
±2.3 ±18 ±2.3 ±18 ±2.3 ±18 V
Quiescent Current V
S
= ±2.3 V to ±18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA
Over Temperature 1.1 1.6 1.1 1.6 1.1 1.6 mA
TEMPERATURE RANGE
For Specified Performance –40 to +85 –40 to +85 –55 to +125 °C
NOTES
1
Does not include effects of external resistor R
G
.
2
One input grounded. G = 1.
3
This is defined as the same supply range which is used to specify PSR.
4
See Analog Devices military data sheet for 883B tested specifications.
Specifications subject to change without notice.
REV. D –3–
AD620
REV. D
–4–
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Pin Plastic Package: θ
JA
= 95°C/Watt
8-Pin Cerdip Package: θ
JA
= 110°C/Watt
8-Pin SOIC Package: θ
JA
= 155°C/Watt
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . . .650 mW
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range (Q) . . . . . . . . . .–65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . .–65°C to +125°C
Operating Temperature Range
AD620 (A, B) . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD620 (S) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300°C
ORDERING GUIDE
Model Temperature Range Package Option*
AD620AN –40°C to +85°C N-8
AD620BN –40°C to +85°C N-8
AD620AR –40°C to +85°C R-8
AD620BR –40°C to +85°C R-8
AD620A Chips –40°C to +85°C Die Form
AD620SQ/883B –55°C to +125°C Q-8
*N = Plastic DIP; Q = Cerdip; R = SOIC.
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without de-
tection. Although the AD620 features proprietary ESD protec-
tion circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis-
charges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
AD620
REV. D –5–
Typical Characteristics
(@ +258C, VS = 615 V, RL = 2 kV, unless otherwise noted)
INPUT OFFSET VOLTAGE – µV
20
30
40
50
–40 0 +40 +80
PERCENTAGE OF UNITS
–80
SAMPLE SIZE = 360
10
0
Figure 1. Typical Distribution of Input Offset Voltage
INPUT BIAS CURRENT – pA
0
10
20
30
40
50
–600 0 +600
PERCENTAGE OF UNITS
–1200 +1200
SAMPLE SIZE = 850
Figure 2. Typical Distribution of Input Bias Current
10
20
30
40
50
–200 0 +200 +400
INPUT OFFSET CURRENT – pA
PERCENTAGE OF UNITS
–400
SAMPLE SIZE = 850
0
Figure 3. Typical Distribution of Input Offset Current
TEMPERATURE – °C
INPUT CURRENT – nA
+I
B
–I
B
2.0
–2.0 175
–1.0
–1.5
–75
–0.5
0
0.5
1.0
1.5
1257525–25
Figure 4. Input Bias Current vs. Temperature
CHANGE IN OFFSET VOLTAGE – µV
1.5
0.5
WARM-UP TIME – Minutes
2
0051
1
432
Figure 5. Change in Input Offset Voltage vs.
Warm-Up Time
FREQUENCY – Hz
1000
11 100k
100
10
10 10k1k100
GAIN = 1
GAIN = 100, 1,000
GAIN = 10
GAIN = 1000
BW LIMIT
VOLTAGE NOISE – nV/ Hz
Figure 6. Voltage Noise Spectral Density vs. Frequency,
(G = 1–1000)
AD620–Typical Characteristics
FREQUENCY – Hz
1000
100
10 1 10 1000100
CURRENT NOISE – fA/ Hz
Figure 7. Current Noise Spectral Density vs. Frequency
RTI NOISE – 2.0 µV/div
TIME – 1 sec/div
Figure 8a. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
RTI NOISE – 0.1µV/div
TIME – 1 sec/div
Figure 8b. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
10
90
100
0%
100mV
1s
Figure 9. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div
100
1000
AD620A
FET INPUT
IN-AMP
SOURCE RESISTANCE – Ω
TOTAL DRIFT FROM 25°C TO 85°C, RTI – µV
100,000
10 1k 10M
10,000
10k 1M100k
Figure 10. Total Drift vs. Source Resistance
FREQUENCY – Hz
CMR – dB
+160
01M
+80
+40
1
+60
0.1
+140
+100
+120
100k10k1k10010
G = 1000
G = 100
G = 10
G = 1
+20
Figure 11. CMR vs. Frequency, RTI, Zero to 1 k
Ω
Source
Imbalance
REV. D
–6–
AD620
REV. D –7–
FREQUENCY – Hz
PSR – dB
160
1M
80
40
1
60
0.1
140
100
120
100k10k1k10010
20
G = 1000
G = 100
G = 10
G = 1
180
Figure 12. Positive PSR vs. Frequency, RTI (G = 1–1000)
FREQUENCY – Hz
PSR – dB
160
1M
80
40
1
60
0.1
140
100
120
100k10k1k10010
20
180
G = 10
G = 100
G = 1
G = 1000
Figure 13. Negative PSR vs. Frequency, RTI (G = 1–1000)
1000
100 10M
100
1
1k
10
100k 1M10k
FREQUENCY – Hz
GAIN – V/V
0.1
Figure 14. Gain vs. Frequency
OUTPUT VOLTAGE – Volts p-p
FREQUENCY – Hz
35
01M
15
5
10k
10
1k
30
20
25
100k
G = 10, 100, 1000
G = 1
G = 1000 G = 100
BW LIMIT
Figure 15. Large Signal Frequency Response
INPUT VOLTAGE LIMIT – Volts
(REFERRED TO SUPPLY VOLTAGES)
20
+1.0
+0.5
50
+1.5
–1.5
–1.0
–0.5
1510
SUPPLY VOLTAGE ± Volts
+Vs
–Vs
–0.0
+0.0
Figure 16. Input Voltage Range vs. Supply Voltage, G = 1
20
+1.0
+0.5
5
0
+1.5
–1.5
–1.0
–0.5
1510
SUPPLY VOLTAGE ± Volts
R = 10kΩ
L
R = 2kΩ
L
R = 10kΩ
L
+V
s
–V
s
OUTPUT VOLTAGE SWING – Volts
(REFERRED TO SUPPLY VOLTAGES)
–0.0
+0.0
R = 2kΩ
L
Figure 17. Output Voltage Swing vs. Supply Voltage,
G = 10
AD620
REV. D
–8–
OUTPUT VOLTAGE SWING – Volts p-p
LOAD RESISTANCE – Ω
30
0010k
20
10
100 1k
G = 10
V = ±15V
S
Figure 18. Output Voltage Swing vs. Load Resistance
10
90
100
0%
5V
1mV
10µs
Figure 19. Large Signal Pulse Response and Settling Time
G = 1 (0.5 mV = 0.01%)
10
90
100
0%
20mV
10µs
Figure 20. Small Signal Response, G = 1, R
L
= 2 k
Ω
,
C
L
= 100 pF
10
90
100
0%
5V
10µs
1mV
Figure 21. Large Signal Response and Settling Time,
G = 10 (0.5 mV = 001%)
10
90
100
0%
20mV
10µs
Figure 22. Small Signal Response, G = 10, R
L
= 2 k
Ω
,
C
L
= 100 pF
10
90
100
0%
5V
10µs
1mV
Figure 23. Large Signal Response and Settling Time,
G = 100 (0.5 mV = 0.01%)
AD620
REV. D –9–
10
90
100
0%
20mV
10µs
Figure 24. Small Signal Pulse Response, G = 100,
R
L
= 2 k
Ω
, CL = 100 pF
10
90
100
0%
5V
100 µs
5mV
Figure 25. Large Signal Response and Settling Time,
G = 1000 (0.5 mV = 0.01%)
10
90
100
0%
20mV
50µs
Figure 26. Small Signal Pulse Response, G = 1000,
R
L
= 2 k
Ω
, CL = 100 pF
OUTPUT STEP SIZE – Volts
SETTLING TIME – µs
TO 0.01%
TO 0.1%
20
0020
15
5
5
10
10 15
Figure 27. Settling Time vs. Step Size (G = 1)
GAIN
SETTLING TIME - µs
1000
11 1000
100
10
10 100
Figure 28. Settling Time to 0.01% vs. Gain, for a 10 V Step
10
90
100
0%
10µV2V
Figure 29a. Gain Nonlinearity, G = 1, R
L
= 10 k
Ω
(10
µ
V = 1 ppm)
AD620
REV. D
–10–
V
B
–V
S
A1 A2
A3
C2
R
G
Q1 Q2
R1 R2
GAIN
SENSE GAIN
SENSE
R3
400Ω
10kΩ
10kΩ
I2
I1
10kΩREF
10kΩ
+IN
– IN
20µA20µA
R4
400Ω
OUTPUT
C1
Figure 31. Simplified Schematic of AD620
THEORY OF OPERATION
The AD620 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp approach. Absolute
value trimming allows the user to program gain accurately (to
0.15% at G = 100) with only one resistor. Monolithic construc-
tion and laser wafer trimming allow the tight matching and
tracking of circuit components, thus insuring the high level of
performance inherent in this circuit.
The input transistors Q1 and Q2 provide a single differential-
pair bipolar input for high precision (Figure 31), yet offer 10×
lower Input Bias Current thanks to Superβeta processing. Feed-
back through the Q1-A1-R1 loop and the Q2-A2-R2 loop main-
tains constant collector current of the input devices Q1, Q2
thereby impressing the input voltage across the external gain
setting resistor R
G
. This creates a differential gain from the
inputs to the A1/A2 outputs given by G = (R1 + R2)/R
G
+ 1.
The unity-gain subtracter A3 removes any common-mode sig-
nal, yielding a single-ended output referred to the REF pin
potential.
The value of R
G
also determines the transconductance of the
preamp stage. As R
G
is reduced for larger gains, the transcon-
ductance increases asymptotically to that of the input transistors.
This has three important advantages: (a) Open-loop gain is
boosted for increasing programmed gain, thus reducing gain-
related errors. (b) The gain-bandwidth product (determined by
C1, C2 and the preamp transconductance) increases with pro-
grammed gain, thus optimizing frequency response. (c) The
input voltage noise is reduced to a value of 9 nV/√Hz, deter-
mined mainly by the collector current and base resistance of the
input devices.
The internal gain resistors, R1 and R2, are trimmed to an abso-
lute value of 24.7 kΩ, allowing the gain to be programmed accu-
rately with a single external resistor.
The gain equation is then
G=49.4 kΩ
RG+1
so that
R
G
=49.4 kΩ
G−1
10
90
100
0%
2V
100µV
Figure 29b. Gain Nonlinearity, G = 100, R
L
= 10 k
Ω
(100
µ
V = 10 ppm)
10
90
100
0%
1mV
2V
Figure 29c. Gain Nonlinearity, G = 1000, R
L
= 10 k
Ω
(1 mV = 100 ppm)
AD620
V
OUT
G=1
G=1000
49.9Ω
10kΩ * 1kΩ
10T 10kΩ
499Ω
G=10
G=100
5.49kΩ
+V
S
11kΩ1kΩ100Ω
100kΩ
INPUT
10V p-p
–V
S
* ALL RESISTORS 1% TOLERANCE
7
1
2
3
8
6
4
5
Figure 30. Settling Time Test Circuit
AD620
REV. D –11–
Make vs. Buy: A Typical Bridge Application Error Budget
The AD620 offers improved performance over “homebrew”
three op amp IA designs, along with smaller size, less compo-
nents and 10× lower supply current. In the typical application,
shown in Figure 32, a gain of 100 is required to amplify a bridge
output of 20 mV full scale over the industrial temperature range
of –40°C to +85°C. The error budget table below shows how to
calculate the effect various error sources have on circuit accuracy.
Regardless of the system it is being used in, the AD620 provides
greater accuracy, and at low power and price. In simple systems,
absolute accuracy and drift errors are by far the most significant
contributors to error. In more complex systems with an intelli-
gent processor, an auto-gain/auto-zero cycle will remove all
absolute accuracy and drift errors leaving only the resolution
errors of gain nonlinearity and noise, thus allowing full 14-bit
accuracy.
Note that for the homebrew circuit, the OP07 specifications for
input voltage offset and noise have been multiplied by √2. This
is because a three op amp type in amp has two op amps at its
inputs, both contributing to the overall input error.
R = 350Ω
+10V
PRECISION BRIDGE TRANSDUCER AD620A MONOLITHIC
INSTRUMENTATION
AMPLIFIER, G=100
"HOMEBREW" IN-AMP, G=100
*0.02% RESISTOR MATCH, 3PPM/°C TRACKING
**DISCRETE 1% RESISTOR, 100PPM/°C TRACKING
SUPPLY CURRENT = 15mA MAX
100Ω**
10kΩ*
10kΩ**
10kΩ*
10kΩ*
10kΩ**
10kΩ*
SUPPLY CURRENT = 1.3mA MAX
OP-07D
OP-07D
OP-07D
AD620A
R
G
499Ω
REFERENCE
R = 350ΩR = 350Ω
R = 350Ω
Figure 32. Make vs. Buy
Table I. Make vs. Buy Error Budget
AD620 Circuit “Homebrew” Circuit Error, ppm of Full Scale
Error Source Calculation Calculation AD620 Homebrew
ABSOLUTE ACCURACY at T
A
= +25°C
Input Offset Voltage, µV 125 µV/20 mV (150 µV × √2)/20 mV 16,250 10,607
Output Offset Voltage, µV 1000 µV/100/20 mV ((150 µV × 2)/100)/20 mV 14,500 10,150
Input Offset Current, nA 2 nA × 350 Ω/20 mV (6 nA × 350 Ω)/20 mV 14,118 14,153
CMR, dB 110 dB→3.16 ppm, × 5 V/20 mV (0.02% Match × 5 V)/20 mV/100 14,791 10,500
Total Absolute Error 17,558 11,310
DRIFT TO +85°C
Gain Drift, ppm/°C (50 ppm + 10 ppm) × 60°C 100 ppm/°C Track × 60°C13,600 16,000
Input Offset Voltage Drift, µV/°C1µV/°C × 60°C/20 mV (2.5 µV/°C × √2 × 60°C)/20 mV 13,000 10,607
Output Offset Voltage Drift, µV/°C 15 µV/°C × 60°C/100/20 mV (2.5 µV/°C × 2 × 60°C)/100/20 mV 14,450 10,150
Total Drift Error 17,050 16,757
RESOLUTION
Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 14,140 10,140
Typ 0.1 Hz–10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV (0.38 µV p-p × √2)/20 mV 141,14 13,127
Total Resolution Error 14,154 101,67
Grand Total Error 14,662 28,134
G = 100, V
S
= ±15 V.
(All errors are min/max and referred to input.)
AD620
REV. D
–12–
≈
3kΩ
+5V
DIGITAL
DATA
OUTPUT
ADC
REF
IN
AGND
20kΩ
10kΩ
20kΩ
AD620B
G=100
1.7mA 1.3mA
MAX 0.10mA 0.6mA
MAX
499Ω
3kΩ
3kΩ3kΩ
4
AD705
2
1
8
37
6
5
Figure 33. A Pressure Monitor Circuit which Operates on a +5 V Single Supply
Pressure Measurement
Although useful in many bridge applications such as weigh
scales, the AD620 is especially suited for higher resistance pres-
sure sensors powered at lower voltages where small size and low
power become more significant.
Figure 33 shows a 3 kΩ pressure transducer bridge powered
from +5 V. In such a circuit, the bridge consumes only 1.7 mA.
Adding the AD620 and a buffered voltage divider allows the sig-
nal to be conditioned for only 3.8 mA of total supply current.
Small size and low cost make the AD620 especially attractive for
voltage output pressure transducers. Since it delivers low noise
and drift, it will also serve applications such as diagnostic non-
invasive blood pressure measurement.
Medical ECG
The low current noise of the AD620 allows its use in ECG
monitors (Figure 34) where high source resistances of 1 MΩ or
higher are not uncommon. The AD620’s low power, low supply
voltage requirements, and space-saving 8-pin mini-DIP and
SOIC package offerings make it an excellent choice for battery
powered data recorders.
Furthermore, the low bias currents and low current noise
coupled with the low voltage noise of the AD620 improve the
dynamic range for better performance.
The value of capacitor C1 is chosen to maintain stability of the
right leg drive loop. Proper safeguards, such as isolation, must
be added to this circuit to protect the patient from possible
harm.
7
8
1
2
3
5
6
G = 7
AD620A
0.03Hz
HIGH
PASS
FILTER
OUTPUT
1V/mV
+3V
–3V
R
G
8.25kΩ
24.9kΩ
24.9kΩ
AD705J
G = 143
C1
1MΩ
R4
10kΩ
R1 R3
R2
4
OUTPUT
AMPLIFIER
PATIENT/CIRCUIT
PROTECTION/ISOLATION
Figure 34. A Medical ECG Monitor Circuit
AD620
REV. D –13–
Precision V-I Converter
The AD620 along with another op amp and two resistors make
a precision current source (Figure 35). The op amp buffers the
reference terminal to maintain good CMR. The output voltage
V
X
of the AD620 appears across R1 which converts it to a cur-
rent. This current less only the input bias current of the op amp
then flows out to the load.
AD620R
G
+V
s
–V
s
V
IN+
V
IN–
AD705
LOAD
R1
IL
V
x
I =
L
R1 =
IN+
[(V ) – (V )] G
IN–
R1
6
5
+ V -
x
4
2
1
8
37
Figure 35. Precision Voltage-to-Current Converter
(Operates on 1.8 mA,
±
3 V)
GAIN SELECTION
The AD620’s gain is resistor programmed by R
G
: or more pre-
cisely, by whatever impedance appears between Pins 1 and 8.
The AD620 is designed to offer accurate gains using 0.1%–1%
resistors. Table II shows required values of R
G
for various gains.
Note that for G = 1, the R
G
pins are unconnected (R
G
= ∞). For
any arbitrary gain R
G
can be calculated by using the formula:
R
G
=49.4 kΩ
G−1
To minimize gain error avoid high parasitic resistance in series
with R
G
, and to minimize gain drift R
G
should have a low TC—
less than 10 ppm/°C for the best performance.
Table II. Required Values of Gain Resistors
1% Std Table Calculated 0.1% Std Table Calculated
Value of R
G
, ΩGain Value of R
G
, ΩGain
49.9 k 1.990 49.3 k 2.002
12.4 k 4.984 12.4 k 4.984
5.49 k 9.998 5.49 k 9.998
2.61 k 19.93 2.61 k 19.93
1.00 k 50.40 1.01 k 49.91
499 100.0 499 100.0
249 199.4 249 199.4
100 495.0 98.8 501.0
49.9 991.0 49.3 1,003
INPUT AND OUTPUT OFFSET VOLTAGE
The low errors of the AD620 are attributed to two sources,
input and output errors. The output error is divided by G when
referred to the input. In practice, the input errors dominate at
high gains and the output errors dominate at low gains. The
total V
OS
for a given gain is calculated as:
Total Error RTI = input error + (output error/G)
Total Error RTO = (input error × G) + output error
REFERENCE TERMINAL
The reference terminal potential defines the zero output voltage,
and is especially useful when the load does not share a precise
ground with the rest of the system. It provides a direct means of
injecting a precise offset to the output, with an allowable range
of 2 V within the supply voltages. Parasitic resistance should be
kept to a minimum for optimum CMR.
INPUT PROTECTION
The AD620 features 400 Ω of series thin film resistance at its
inputs, and will safely withstand input overloads of up to ±15 V
or ±60 mA for several hours. This is true for all gains, and
power on and off, which is particularly important since the sig-
nal source and amplifier may be powered separately. For longer
time periods, the current should not exceed 6 mA (I
IN
≤
V
IN
/400 Ω). For input overloads beyond the supplies, clamping
the inputs to the supplies (using a low leakage diode such as an
FD333) will reduce the required resistance, yielding lower
noise.
RF INTERFERENCE
All instrumentation amplifiers can rectify out of band signals,
and when amplifying small signals, these rectified voltages act as
small dc offset errors. The AD620 allows direct access to the
input transistor bases and emitters enabling the user to apply
some first order filtering to unwanted RF signals (Figure 36),
where RC < 1/(2 πf) and where f ≥ the bandwidth of the
AD620; C ≤ 150 pF. Matching the extraneous capacitance at
Pins 1 and 8, and Pins 2 and 3 helps to maintain high CMR.
–IN
1
2
3
45
6
7
8
R
R
+IN
C
C
R
G
Figure 36. Circuit to Attenuate RF Interference
AD620
REV. D
–14–
COMMON-MODE REJECTION
Instrumentation amplifiers like the AD620 offer high CMR
which is a measure of the change in output voltage when both
inputs are changed by equal amounts. These specifications are
usually given for a full-range input voltage change and a speci-
fied source imbalance.
For optimal CMR the reference terminal should be tied to a low
impedance point, and differences in capacitance and resistance
should be kept to a minimum between the two inputs. In many
applications shielded cables are used to minimize noise, and for
best CMR over frequency the shield should be properly driven.
Figures 37 and 38 show active data guards which are configured
to improve ac common-mode rejections by “bootstrapping” the
capacitances of input cable shields, thus minimizing the capaci-
tance mismatch between the inputs.
REFERENCE
V
OUT
AD620
100Ω
100Ω
– INPUT
+ INPUT
AD648
R
G
1
2
3
7
85
6
4
–V
S
+V
S
–V
S
Figure 37. Differential Shield Driver
AD548
100Ω
– INPUT
+ INPUT
REFERENCE
V
OUT
AD620
4
–V
S
+V
S
8
3
1
27
5
6
2
R
G
2
R
G
Figure 38. Common-Mode Shield Driver
GROUNDING
Since the AD620 output voltage is developed with respect to the
potential on the reference terminal, it can solve many grounding
problems by simply tying the REF pin to the appropriate “local
ground.”
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground pins (Figure 39). It would be conve-
nient to use a single ground line, however, current through
ground wires and PC runs of the circuit card can cause hun-
dreds of millivolts of error. Therefore, separate ground returns
should be provided to minimize the current flow from the sensi-
tive points to the system ground. These ground returns must be
tied together at some point, usually best at the ADC package as
shown.
Figure 39. Basic Grounding Practice
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of an amplifier. There must be a direct return path
AD620
REV. D –15–
for these currents; therefore when amplifying “floating” input
V
OUT
7
AD620
– INPUT
R
G
LOAD
TO POWER
SUPPLY
GROUND
REFERENCE
2
1
8
3
4
5
6
+ INPUT
+V
S
–V
S
Figure 40a. Ground Returns for Bias Currents with
Transformer Coupled Inputs
sources such as transformers, or ac-coupled sources, there must
be a dc path from each input to ground as shown in Figure 40.
Refer to the Instrumentation Amplifier Application Guide (free
from Analog Devices) for more information regarding in amp
applications.
V
OUT
7
AD620
– INPUT
+ INPUT
R
G
LOAD
TO POWER
SUPPLY
GROUND
REFERENCE
2
1
8
3
4
5
6
+V
S
–V
S
Figure 40b. Ground Returns for Bias Currents with
Thermocouple Inputs
100kΩ
V
OUT
7
AD620
– INPUT
+ INPUT
R
G
LOAD
TO POWER
SUPPLY
GROUND
REFERENCE
2
1
8
3
4
5
6
100kΩ–V
S
+V
S
Figure 40c. Ground Returns for Bias Currents with AC Coupled Inputs
AD620
REV. D
–16–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8) Package
0.011±0.003
(0.28±0.08)
0.30 (7.62)
REF
15
°
0
°
PIN 1
4
58
1
0.25
(6.35) 0.31
(7.87)
0.10
(2.54)
BSC
SEATING
PLANE
0.035±0.01
(0.89±0.25)
0.18±0.03
(4.57±0.76)
0.033
(0.84)
NOM
0.018±0.003
(0.46±0.08)
0.125
(3.18)
MIN
0.165±0.01
(4.19±0.25)
0.39 (9.91) MAX
Cerdip (Q-8) Package
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
15
°
0
°
0.005 (0.13) MIN 0.055 (1.40) MAX
1
PIN 1
4
5
8
0.310 (7.87)
0.220 (5.59)
0.405 (10.29) MAX
0.200
(5.08)
MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
SOIC (R-8) Package
0.019 (0.48)
0.014 (0.36)
0.050
(1.27)
BSC
0.102 (2.59)
0.094 (2.39)
0.197 (5.01)
0.189 (4.80)
0.010 (0.25)
0.004 (0.10)
0.098 (0.2482)
0.075 (0.1905)
0.190 (4.82)
0.170 (4.32)
0.030 (0.76)
0.018 (0.46)
10
°
0
°
0.090
(2.29)
8
°
0
°
0.020 (0.051) x 45
°
CHAMF
1
85
4
PIN 1
0.157 (3.99)
0.150 (3.81)
0.244 (6.20)
0.228 (5.79)
0.150 (3.81)
C15499b–12–4/93
PRINTED IN U.S.A.
All brand or product names mentioned are trademarks or registered trademarks of their respective holders.