SST29VE010-200-4I-NHE - Silicon Storage Technology, Inc.

S71061-07-000 2/02 304

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

Small-Sector Flash and SSF are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

1 Mbit (128K x8) Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FEATURES:

• Single Voltage Read and Write Operations

– 4.5-5.5V for SST29EE010

– 3.0-3.6V for SST29LE010

– 2.7-3.6V for SST29VE010

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

– Active Current: 20 mA (typical) for 5V and 10 mA

(typical) for 3.0/2.7V

– Standby Current: 10 µA (typical)

• Fast Page-Write Operation

– 128 Bytes per Page, 1024 Pages

– Page-Write Cycle: 5 ms (typical)

– Complete Memory Rewrite: 5 sec (typical)

– Effective Byte-Write Cycle Time: 39 µs (typical)

• Fast Read Access Time

– 4.5-5.5V operation: 70 and 90 ns

– 3.0-3.6V operation: 150 and 200 ns

– 2.7-3.6V operation: 200 ns

• Latched Address and Data

• Automatic Write Timing

– Internal VPP Generation

• End of Write Detection

– Toggle Bit

– Data# Polling

• Hardware and Software Data Protection

• Product Identification can be accessed via

Software Operation

• TTL I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm, 8mm x 20mm)

– 32-pin PDIP

PRODUCT DESCRIPTION

The SST29EE/LE/VE010 are 128K x8 CMOS Page-Write

EEPROMs manufactured with SST’s proprietary, high per-

formance CMOS SuperFlash technology. The split-gate

cell design and thick oxide tunneling injector attain better

reliability and manufacturability compared with alternate

approaches. The SST29EE/LE/VE010 write with a single

power supply. Internal Erase/Program is transparent to the

user. The SST29EE/LE/VE010 conform to JEDEC stan-

dard pinouts for byte-wide memories.

Featuring high performance Page-Write, the SST29EE/LE/

VE010 provide a typical Byte-Write time of 39 µsec. The

entire memory, i.e., 128 Kbyte, can be written page-by-

page in as little as 5 seconds, when using interface features

such as Toggle Bit or Data# Polling to indicate the comple-

tion of a Write cycle. To protect against inadvertent write,

the SST29EE/LE/VE010 have on-chip hardware and Soft-

ware Data Protection schemes. Designed, manufactured,

and tested for a wide spectrum of applications, the

SST29EE/LE/VE010 are offered with a guaranteed Page-

Write endurance of 10,000 cycles. Data retention is rated at

greater than 100 years.

The SST29EE/LE/VE010 are suited for applications

that require convenient and economical updating of

program, configuration, or data memory. For all sys-

tem applications, the SST29EE/LE/VE010 significantly

improve performance and reliability, while lowering

power consumption. The SST29EE/LE/VE010

improve flexibility while lowering the cost for program,

data, and configuration storage applications.

To meet high density, surface mount requirements, the

SST29EE/LE/VE010 are offered in 32-lead PLCC and 32-

lead TSOP packages. A 600-mil, 32-pin PDIP package is

also available. See Figures 1, 2, and 3 for pinouts.

Device Operation

The SST Page-Write EEPROM offers in-circuit electrical

write capability. The SST29EE/LE/VE010 does not require

separate Erase and Program operations. The internally

timed Write cycle executes both erase and program trans-

parently to the user. The SST29EE/LE/VE010 have indus-

try standard optional Software Data Protection, which SST

recommends always to be enabled. The SST29EE/LE/

VE010 are compatible with industry standard EEPROM

pinouts and functionality.

SST29EE / LE / VE0101Mb Page-Write flash memories

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Read

The Read operations of the SST29EE/LE/VE010 are con-

trolled by CE# and OE#, both have to be low for the system

to obtain data from the outputs. CE# is used for device

selection. When CE# is high, the chip is deselected and

only standby power is consumed. OE# is the output control

and is used to gate data from the output pins. The data bus

is in high impedance state when either CE# or OE# is high.

Refer to the Read cycle timing diagram for further details

(Figure 4).

Write

The Page-Write to the SST29EE/LE/VE010 should always

use the JEDEC Standard Software Data Protection (SDP)

three-byte command sequence. The SST29EE/LE/VE010

contain the optional JEDEC approved Software Data Pro-

tection scheme. SST recommends that SDP always be

enabled, thus, the description of the Write operations will

be given using the SDP enabled format. The three-byte

SDP Enable and SDP Write commands are identical;

therefore, any time a SDP Write command is issued,

Software Data Protection is automatically assured. The

first time the three-byte SDP command is given, the device

becomes SDP enabled. Subsequent issuance of the same

command bypasses the data protection for the page being

written. At the end of the desired Page-Write, the entire

device remains protected. For additional descriptions,

please see the application notes, The Proper Use of

JEDEC Standard Software Data Protection and Protecting

Against Unintentional Writes When Using Single Power

Supply Flash Memories.

The Write operation consists of three steps. Step 1 is the

three-byte load sequence for Software Data Protection.

Step 2 is the byte-load cycle to a page buffer of the

SST29EE/LE/VE010. Steps 1 and 2 use the same timing

for both operations. Step 3 is an internally controlled Write

cycle for writing the data loaded in the page buffer into the

memory array for nonvolatile storage. During both the SDP

three-byte load sequence and the byte-load cycle, the

addresses are latched by the falling edge of either CE# or

WE#, whichever occurs last. The data is latched by the ris-

ing edge of either CE# or WE#, whichever occurs first. The

internal Write cycle is initiated by the TBLCO timer after the

rising edge of WE# or CE#, whichever occurs first. The

Write cycle, once initiated, will continue to completion, typi-

cally within 5 ms. See Figures 5 and 6 for WE# and CE#

controlled Page-Write cycle timing diagrams and Figures

15 and 17 for flowcharts.

The Write operation has three functional cycles: the Soft-

ware Data Protection load sequence, the page-load cycle,

and the internal Write cycle. The Software Data Protection

consists of a specific three-byte load sequence that allows

writing to the selected page and will leave the SST29EE/

LE/VE010 protected at the end of the Page-Write. The

page-load cycle consists of loading 1 to 128 bytes of data

into the page buffer. The internal Write cycle consists of the

TBLCO time-out and the write timer operation. During the

Write operation, the only valid reads are Data# Polling and

Tog g l e B it .

The Page-Write operation allows the loading of up to 128

bytes of data into the page buffer of the SST29EE/LE/

VE010 before the initiation of the internal Write cycle. Dur-

ing the internal Write cycle, all the data in the page buffer is

written simultaneously into the memory array. Hence, the

Page-Write feature of SST29EE/LE/VE010 allow the entire

memory to be written in as little as 5 seconds. During the

internal Write cycle, the host is free to perform additional

tasks, such as to fetch data from other locations in the sys-

tem to set up the write to the next page. In each Page-Write

operation, all the bytes that are loaded into the page buffer

must have the same page address, i.e. A7 through A16. Any

byte not loaded with user data will be written to FFH.

See Figures 5 and 6 for the Page-Write cycle timing dia-

grams. If after the completion of the three-byte SDP load

sequence or the initial byte-load cycle, the host loads a sec-

ond byte into the page buffer within a byte-load cycle time

(TBLC) of 100 µs, the SST29EE/LE/VE010 will stay in the

page-load cycle. Additional bytes are then loaded consecu-

tively. The page-load cycle will be terminated if no addi-

tional byte is loaded into the page buffer within 200 µs

(TBLCO) from the last byte-load cycle, i.e., no subsequent

WE# or CE# high-to-low transition after the last rising edge

of WE# or CE#. Data in the page buffer can be changed by

a subsequent byte-load cycle. The page-load period can

continue indefinitely, as long as the host continues to load

the device within the byte-load cycle time of 100 µs. The

page to be loaded is determined by the page address of

the last byte loaded.

Software Chip-Erase

The SST29EE/LE/VE010 provide a Chip-Erase operation,

which allows the user to simultaneously clear the entire

memory array to the “1” state. This is useful when the entire

device must be quickly erased.

The Software Chip-Erase operation is initiated by using a

specific six-byte load sequence. After the load sequence,

the device enters into an internally timed cycle similar to the

Write cycle. During the Erase operation, the only valid read

is Toggle Bit. See Table 4 for the load sequence, Figure 10

for timing diagram, and Figure 19 for the flowchart.

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Write Operation Status Detection

The SST29EE/LE/VE010 provide two software means to

detect the completion of a Write cycle, in order to optimize

the system Write cycle time. The software detection

includes two status bits: Data# Polling (DQ7) and Toggle Bit

(DQ6). The End-of-Write detection mode is enabled after

the rising WE# or CE# whichever occurs first, which ini-

tiates the internal Write cycle.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

Data# Polling (DQ7)

When the SST29EE/LE/VE010 are in the internal Write

cycle, any attempt to read DQ7 of the last byte loaded dur-

ing the byte-load cycle will receive the complement of the

true data. Once the Write cycle is completed, DQ7 will

show true data. Note that even though DQ7 may have valid

data immediately following the completion of an internal

Write operation, the remaining data outputs may still be

invalid: valid data on the entire data bus will appear in sub-

sequent successive Read cycles after an interval of 1 µs.

See Figure 7 for Data# Polling timing diagram and Figure

16 for a flowchart.

Toggle Bit (DQ6)

During the internal Write cycle, any consecutive attempts to

read DQ6 will produce alternating ‘0’s and ‘1’s, i.e. toggling

between 0 and 1. When the Write cycle is completed, the

toggling will stop. The device is then ready for the next

operation. See Figure 8 for Toggle Bit timing diagram and

Figure 16 for a flowchart. The initial read of the Toggle Bit

will typically be a “1”.

Data Protection

The SST29EE/LE/VE010 provide both hardware and soft-

ware features to protect nonvolatile data from inadvertent

writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 2.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST29EE/LE/VE010 provide the JEDEC approved

optional Software Data Protection scheme for all data alter-

ation operations, i.e., Write and Chip-Erase. With this

scheme, any Write operation requires the inclusion of a

series of three-byte load operations to precede the data

loading operation. The three-byte load sequence is used to

initiate the Write cycle, providing optimal protection from

inadvertent Write operations, e.g., during the system

power-up or power-down. The SST29EE/LE/VE010 are

shipped with the Software Data Protection disabled.

The software protection scheme can be enabled by apply-

ing a three-byte sequence to the device, during a page-

load cycle (Figures 5 and 6). The device will then be auto-

matically set into the data protect mode. Any subsequent

Write operation will require the preceding three-byte

sequence. See Table 4 for the specific software command

codes and Figures 5 and 6 for the timing diagrams. To set

the device into the unprotected mode, a six-byte sequence

is required. See Table 4 for the specific codes and Figure 9

for the timing diagram. If a write is attempted while SDP is

enabled the device will be in a non-accessible state for

~300 µs. SST recommends Software Data Protection

always be enabled. See Figure 17 for flowcharts.

The SST29EE/LE/VE010 Software Data Protection is a

global command, protecting all pages in the entire memory

array once enabled. Therefore using SDP for a single

Page-Write will enable SDP for the entire array. Single

pages by themselves cannot be SDP enabled.

Single power supply reprogrammable nonvolatile memo-

ries may be unintentionally altered. SST strongly recom-

mends that Software Data Protection (SDP) always be

enabled. The SST29EE/LE/VE010 should be programmed

using the SDP command sequence.

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Please refer to the following Application Notes for more

information on using SDP:

•Protecting Against Unintentional Writes When

Using Single Power Supply Flash Memories

•The Proper Use of JEDEC Standard Software

Data Protection

Product Identification

The Product Identification mode identifies the device

as the SST29EE/LE/VE010 and manufacturer as SST.

This mode is accessed via software. For details, see

Table 4, Figure 11 for the software ID entry and read

timing diagram and Figure 18, for the ID entry com-

mand sequence flowchart.

Product Identification Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exiting is

accomplished by issuing the Software ID Exit (reset) opera-

tion, which returns the device to the Read operation. The

Reset operation may also be used to reset the device to the

Read mode after an inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. See Table 4 for software command

codes, Figure 12 for timing waveform, and Figure 18 for a

flowchart.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST29EE010 0001H 07H

SST29LE010 0001H 08H

SST29VE010 0001H 08H

T1.3 304

Y-Decoder and Page Latches

I/O Buffers and Data Latches

304 ILL B1.1

Address Buffer & Latches

X-Decoder

DQ7 - DQ0

A16 - A0

WE#

OE#

CE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP

FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

A16

VDD

WE#

32-lead PLCC

Top View

304 ILL F02.3

14 15 16 17 18 19 20

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

A11

A13

A14

WE#

VDD

A16

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

304 ILL F01.2

Standard Pinout

Top View

Die Up

32-pin

PDIP

Top View

304 ILL F19.0

A16

A15

A12

DQ0

DQ1

DQ2

VSS

VDD

WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

A16-A7Row Address Inputs To provide memory addresses. Row addresses define a page for a Write cycle.

A6-A0Column Address Inputs Column Addresses are toggled to load page data

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide: 5.0V supply (4.5-5.5V) for SST29EE010

3.0V supply (3.0-3.6V) for SST29LE010

2.7V supply (2.7-3.6V) for SST29VE010

VSS Ground

NC No Connection Unconnected pins.

T2.2 304

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Page-Write VIL VIH VIL DIN AIN

Standby VIH X1

1. X can be VIL or VIH, but no other value.

XHigh Z X

Write Inhibit X VIL XHigh Z/ D

OUT X

XXV

IH High Z/ DOUT X

Software Chip-Erase VIL VIH VIL DIN AIN, See Table 4

Product Identification

Software Mode VIL VIH VIL Manufacturer’s ID (BFH)

Device ID2

2. Device ID = 07H for SST29EE010 and 08H for SST29LE/VE010

See Table 4

SDP Enable Mode VIL VIH VIL See Table 4

SDP Disable Mode VIL VIH VIL See Table 4

T3.3 304

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Note: This product supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code

sequence. For new designs, SST recommends that the three-byte command code sequence be used.

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Software

Data Protect Enable

& Page-Write

5555H AAH 2AAAH 55H 5555H A0H Addr2Data

Software Chip-Erase35555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H

Alternate

Software ID Entry6

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H

T4.3 304

1. Address format A14-A0 (Hex), Addresses A15 and A16 can be VIL or VIH, but no other value.

2. Page-Write consists of loading up to 128 Bytes (A6-A0)

3. The software Chip-Erase function is not supported by the industrial temperature part.

Please contact SST if you require this function for an industrial temperature part.

4. The device does not remain in Software Product ID mode if powered down.

5. With A14-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,

SST29EE010 Device ID = 07H, is read with A0 = 1

SST29LE/VE010 Device ID = 08H, is read with A0 = 1

6. Alternate six-byte Software Product ID command code

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST29EE010

Range Ambient Temp VDD

Commercial 0°C to +70°C 4.5-5.5V

Industrial -40°C to +85°C 4.5-5.5V

OPERATING RANGE FOR SST29LE010

Range Ambient Temp VDD

Commercial 0°C to +70°C 3.0-3.6V

Industrial -40°C to +85°C 3.0-3.6V

OPERATING RANGE FOR SST29VE010

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns

Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF

See Figures 13 and 14

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V FOR SST29EE010

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VIL/VIH, at f=1/TRC Min,

VDD=VDD Max

Read 30 mA CE#=OE#=VIL, WE#=VIH, all I/Os open

Write 50 mA CE#=WE#=VIL, OE#=VIH, VDD=VDD Max

ISB1 Standby VDD Current

(TTL input)

3 mA CE#=OE#=WE#=VIH, VDD=VDD Max

ISB2 Standby VDD Current

(CMOS input)

50 µA CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN =GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT =GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 2.0 V VDD=VDD Max

VOL Output Low Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min

VOH Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

T5.3 304

TABLE 6: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST29LE010 AND 2.7-3.0V FOR SST29VE010

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VIL/VIH, at f=1/TRC Min,

VDD=VDD Max

Read 12 mA CE#=OE#=VIL, WE#=VIH, all I/Os open

Write 15 mA CE#=WE#=VIL, OE#=VIH, VDD=VDD Max

ISB1 Standby VDD Current

(TTL input)

1 mA CE#=OE#=WE#=VIH, VDD=VDD Max

ISB2 Standby VDD Current

(CMOS input)

15 µA CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 2.0 V VDD=VDD Max

VOL Output Low Voltage 0.4 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage 2.4 V IOH=-100 µA, VDD=VDD Min

T6.3 304

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Write Operation 5 ms

T7.1 304

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T8.0 304

TABLE 9: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH 1Latch Up 100 mA JEDEC Standard 78

T9.5 304

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

AC CHARACTERISTICS

TABLE 10: READ CYCLE TIMING PARAMETERS FOR SST29EE010

Symbol Parameter

SST29EE010-70 SST29EE010-90

UnitsMinMaxMinMax

TRC Read Cycle Time 70 90 ns

TCE Chip Enable Access Time 70 90 ns

TAA Address Access Time 70 90 ns

TOE Output Enable Access Time 30 40 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 20 30 ns

TOHZ1OE# High to High-Z Output 20 30 ns

TOH1Output Hold from Address Change 0 0 ns

T10.2 304

TABLE 11: READ CYCLE TIMING PARAMETERS FOR SST29LE010

Symbol Parameter

SST29LE010-150 SST29LE010-200

UnitsMinMaxMinMax

TRC Read Cycle Time 150 200 ns

TCE Chip Enable Access Time 150 200 ns

TAA Address Access Time 150 200 ns

TOE Output Enable Access Time 60 100 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 30 50 ns

TOHZ1OE# High to High-Z Output 30 50 ns

TOH1Output Hold from Address Change 0 0 ns

T11.1 304

TABLE 12: READ CYCLE TIMING PARAMETERS FOR SST29VE010

Symbol Parameter

SST29VE010-200 SST29VE010-250

UnitsMinMaxMinMax

TRC Read Cycle Time 200 250 ns

TCE Chip Enable Access Time 200 250 ns

TAA Address Access Time 200 250 ns

TOE Output Enable Access Time 100 120 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 50 50 ns

TOHZ1OE# High to High-Z Output 50 50 ns

TOH1Output Hold from Address Change 0 0 ns

T12.1 304

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS

Symbol Parameter

SST29EE010 SST29LE/VE010

UnitsMin Max Min Max

TWC Write Cycle (Erase and Program) 10 10 ms

TAS Address Setup Time 0 0 ns

TAH Address Hold Time 50 70 ns

TCS WE# and CE# Setup Time 0 0 ns

TCH WE# and CE# Hold Time 0 0 ns

TOES OE# High Setup Time 0 0 ns

TOEH OE# High Hold Time 0 0 ns

TCP CE# Pulse Width 70 120 ns

TWP WE# Pulse Width 70 120 ns

TDS Data Setup Time 35 50 ns

TDH1Data Hold Time 0 0 ns

TBLC1Byte Load Cycle Time 0.05 100 0.05 100 µs

TBLCO1Byte Load Cycle Time 200 200 µs

TIDA1Software ID Access and Exit Time 10 10 µs

TSCE Software Chip-Erase 20 20 ms

T13.5 304

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 4: READ CYCLE TIMING DIAGRAM

FIGURE 5: WE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM

304 ILL F03.0

CE#

ADDRESS A16-0

OE#

WE#

DQ 7-0

VIH

TCLZ TOH

DATA VALID

TOLZ

TOE

HIGH-Z HIGH-Z

TCE

TCHZ

TOHZ

TRC TAA

304 ILL F04.1

CE#

OE#

WE#

ADDRESS A16-0

DQ 7-0

SW0

AA 55 A0

DATA VALID

SW1 SW2

BYTE 0 BYTE 1 BYTE 127

TDS

TDH

TBLC TBLCO

TWC

TWP

TOEH

TOES

TCH

TCS

TAH

TAS

5555

Three-Byte Sequence for

Enabling SDP

2AAA 5555

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 6: CE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM

FIGURE 7: DATA# POLLING TIMING DIAGRAM

304 ILL F05.1

CE#

OE#

WE#

ADDRESS A16-0

DQ 7-0

SW0

AA 55 A0

DATA VALID

SW1 SW2

BYTE 0 BYTE 1 BYTE 127

TDS

TDH

TBLC TBLCO

TWC

TCP

TOEH

TOES

TCH

TCS

TAH

TAS

5555

Three-Byte Sequence for

Enabling SDP

2AAA 5555

304 ILL F06.0

CE#

OE#

WE#

TWC + TBLCO

TOE

TOEH

TCE

TOES

D# D

ADDRESS A16-0

DQ 7D

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

FIGURE 9: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM

304 ILL F07.0

CE#

OE#

WE#

TWC + TBLCO

TWO READ CYCLES

WITH SAME OUTPUTS

TOEH

TOE

TOES

TCE

ADDRESS A16-0

DQ6

304 ILL F08.1

CE#

OE#

WE#

ADDRESS A14-0

DQ 7-0

SW0 SW1 SW2 SW3 SW4 SW5

TBLCO

TBLC

TWC

TWP

55555555

55AA 55 20AA80

Six-Byte Sequence for Disabling

Software Data Protection

2AAA2AAA 55555555

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 10: SOFTWARE CHIP-ERASE TIMING DIAGRAM

FIGURE 11: SOFTWARE ID ENTRY AND READ

304 ILL F09.1

CE#

OE#

WE#

ADDRESS A14-0

DQ 7-0

SW0 SW1 SW2 SW3 SW4 SW5

TBLCO

TBLC

TSCE

TWP

55555555

55AA 55 10AA80

Six-Byte Code for Software Chip-Erase

2AAA2AAA 55555555

304 ILL F10.2

CE#

OE#

WE#

ADDRESS A14-0

DQ 7-0

SW0 SW1 SW2 DEVICE ID = 07H for SST29EE010

= 08H for SST29LE010/29VE010

TIDA

TAA

TBLC

TWP

5555

55AA BF

DEVICE ID

Three-Byte Sequence

for Software ID Entry

00002AAA 00015555

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 12: SOFTWARE ID EXIT AND RESET

304 ILL F11.0

CE#

OE#

WE#

ADDRESS A14-0

DQ 7-0

SW0 SW1 SW2

TIDA

TBLC

TWP

5555

55AA F0

Three-Byte Sequence

for Software ID Exit and Reset

2AAA5555

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 14: A TEST LOAD EXAMPLE

304 ILL F12.1

REFERENCE POINTS OUTPUTINPUT

VHT

VLT

VHT

VLT

VIHT

VILT

AC test inputs are driven at VIHT (2.4V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for

inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns.

Note: VHT - VHIGH Te st

VLT - VLOW Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

304 ILL F13.1

TEST LOAD EXAMPLE

TO TESTER

TO DUT

CLRL LOW

RL HIGH

VDD

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 15: WRITE ALGORITHM

304 ILL F14.1

Load Byte

Data

Ye s

Byte

Address =

128?

Write

Completed

Increment

Byte Address

By 1

Wait TBLCO

Wait for end of

Write (TWC,

Data# Polling bit

or Toggle bit

operation)

Set Byte

Address = 0

Set Page

Address

Software Data

Protect Write

Command

Start

See Figure 17

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 16: WAIT OPTIONS

304 ILL F15.1

Read a byte

from page

Ye s

Does DQ6

match?

Write

Completed

Read same

byte

Page-Write

Initiated

Toggle Bit

Wait TWC

Write

Completed

Page-Write

Initiated

Internal Timer

Read DQ7

(Data for last

byte loaded)

Is DQ7 =

true data?

Write

Completed

Page-Write

Initiated

Data# Polling

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 17: SOFTWARE DATA PROTECTION FLOWCHARTS

304 ILL F16.1

Write data: AAH

Address: 5555H

Software Data Protect Enable

Command Sequence

Write data: 55H

Address: 2AAAH

Write data: A0H

Address: 5555H

Wait TWC

Wait TBLCO

SDP Enabled

Load 0 to

128 Bytes of

page data

Optional Page Load

Operation

Write data: AAH

Address: 5555H

Software Data Protect

Disable Command Sequence

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: AAH

Address: 5555H

Wait TWC

Wait TBLCO

SDP Disabled

Write data: 55H

Address: 2AAAH

Write data: 20H

Address: 5555H

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS

304 ILL F17.1

Write data: AAH

Address: 5555H

Software Product ID Entry

Command Sequence

Write data: 55H

Address: 2AAAH

Pause 10 µs

Write data: 90H

Address: 5555H

Read Software ID

Write data: AAH

Address: 5555H

Software Product ID Exit &

Reset Command Sequence

Write data: 55H

Address: 2AAAH

Pause 10 µs

Write data: F0H

Address: 5555H

Return to normal

operation

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

FIGURE 19: SOFTWARE CHIP-ERASE COMMAND CODES

304 ILL F18.2

Write data: AAH

Address: 5555H

Software Chip-Erase

Command Sequence

Write data: 55H

Address: 2AAAH

Write data: AAH

Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 10H

Address: 5555H

Wait TSCE

Chip-Erase

to FFH

Write data: 80H

Address: 5555H

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

PRODUCT ORDERING INFORMATION

Valid combinations for SST29EE010

SST29EE010-70-4C-NH SST29EE010-70-4C-WH SST29EE010-70-4C-EH SST29EE010-70-4C-PH

SST29EE010-90-4C-NH SST29EE010-90-4C-WH SST29EE010-90-4C-EH SST29EE010-90-4C-PH

SST29EE010-70-4I-NH SST29EE010-70-4I-WH SST29EE010-70-4I-EH

Valid combinations for SST29LE010

SST29LE010-150-4C-NH SST29LE010-150-4C-WH SST29LE010-150-4C-EH

SST29LE010-150-4I-NH SST29LE010-150-4I-WH SST29LE010-150-4I-EH

Valid combinations for SST29VE010

SST29VE010-200-4C-NH SST29VE010-200-4C-WH SST29VE010-200-4C-EH

SST29VE010-200-4I-NH SST29VE010-200-4I-WH SST29VE010-200-4I-EH

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Note: The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if you

require this function for an industrial temperature part.

Device Speed Suffix1 Suffix2

SST29xE010 - XXX -XX-XX

Package Modifier

H = 32 leads or pins

Package Type

N = PLCC

E = TSOP (type 1, die up, 8mm x 20mm)

P = PDIP

W = TSOP (type 1, die up, 8mm x 14mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

200 = 200 ns

150 = 150 ns

90 = 90 ns

70 = 70 ns

Function

E = Page-Write

Voltage

E = 4.5-5.5V

L = 3.0-3.6V

V = 2.7-3.6V

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

PACKAGING DIAGRAMS

32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)

SST PACKAGE CODE: NH

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

.040

.030

.021

.013

.530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

TOP VIEW SIDE VIEW BOTTOM VIEW

1232

.400

BSC

32-plcc-NH-3

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

Identifier .020 R.

MAX. R.

x 30˚

32-tsop-WH-7

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0˚- 5˚

DETAIL

Data Sheet

1 Mbit Page-Write EEPROM

SST29EE010 / SST29LE010 / SST29VE010

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM

SST PACKAGE CODE: EH

32-PIN PLASTIC DUAL IN-LINE PINS (PDIP)

SST PACKAGE CODE: PH

0.15

0.05

20.20

19.80

18.50

18.30

0.70

0.50

8.10

7.90 0.27

0.17

1.05

0.95

32-tsop-EH-7

Note: 1.Complies with JEDEC publication 95 MO-142 BD dimensions,

although some dimensions may be more stringent.

2.All linear dimensions are in millimeters (max/min).

3.Coplanarity: 0.1 mm

4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25mm between leads.

Pin # 1 Identifier

0.50

BSC

1mm

1.20

max.

DETAIL

0.70

0.50

0˚- 5˚

32-pdip-PH-3

Pin #1 Identifier

Base

Plane

Seating

Plane

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.200

.170

7˚

4 PLCS.

.600 BSC

.100 BSC

.150

.120

.022

.016

.065

.045

.080

.070

.050

.015

.075

.065

1.655

1.645

.012

.008

0˚

15˚

.625

.600

.550

.530

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036