This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publicati on# 21415 Rev: EAmendment/+1

Am29LV017D

DISTINCTIVE CHARACTERISTICS

— Access times as fast as 70 ns

— 200 nA standby mode current

— 9 mA read current

— 15 mA program/erase current

— Thirt y-two 64 Kbyte sectors

— Supports full chip erase

Temporary Sector Unprotec t featur e allows code

— Reduces ov erall prog ramming time when issuing

preprogr ams and erases the entire chip or any

— 40-pin TSOP

— Provides dev i ce-s pecific information to the

— Superior inadvertent write protection

— Suspends an er ase operation to read data from,

erased, then resumes the erase operation

— Hardware method to res et the device to reading

array data

— Specific address not requir ed for unlock cycles

read, program, and erase operat ions are accomplished

using only a single power supply. The device can also

be programmed in standard EPROM programmers.

The standard de vice offers access times of 70, 90, and

120 ns, allowing high speed microprocessors to

operate wit hout wait st ates. To eliminate bus contention

the device has separate chip enable (CE#), write

enable ( WE#) and output enable (OE#) controls.

The de vice requires only a single 3. 0 v o lt po wer sup-

of the device is similar to reading from other Flash or

Device programming occurs by executing the program

matically times the program pulse widths and verifies

bef ore ex ecuting the e rase operation. During er ase, the

device automatically times the erase pulse widths and

Family Part Number Am29LV017D

Speed Option VCC = 2.7–3.6 V -70 -90 -120

Am29LV017D -70 E C

TEMPERATURE RANGE

PACKAGE TYPE

DEVICE NU MB ER/ DE SCR IP TIO N

tion. The regi st er is composed of latches that store the

tion needed to execute the command. The contents of

Requirements for Reading Array Data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory con-

tent occurs during the pow er transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid addresses

on the device address inputs produc e valid data on the

altered.

See “Reading Array Data” for more information. Refer

0.3 V XX VCC ±

Sector Protect (See Note) L H L VID Sector Addresses,

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

During an erase or prog ram oper ation, th e system ma y

bits on DQ7–DQ0. St andard read cycle timings and I CC

read specifications apply. Refer to “Write Operation

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at VCC ± 0.3 V.

device is in either of these standby modes, before it is

The automatic sleep mode minimizes Flash device

energ y consumption. The dev ice automatically enables

ns. The automatic sleep mode is independent of the

resets the device to reading array data.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Charac teristics” section.

Reading Array Data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

After the device accepts an Erase Suspend command,

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

abl e the de vice f or reading arr ay data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” se ctio n , next.

See also “Requirements for Reading Arra y Dat a” in the

data. Once erasure begins, however, the device ig-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

sector boundaries. A bit cannot be programmed

The unlock bypass feature allows the system to pro-

gr am byte s to the de vice f ast er than using the standard

program command sequenc e. The unlock b ypass com-

mand sequence is initiated by first writing two unlock

the unloc k by pass command, 20h. The de vice then en-

command sequence, resulting in faster total program-

ming time . Table 8 shows t he requirements f or the com-

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

must issue the two-cycle unlock bypass reset com-

“Write Operation Status” for infor mation on these sta-

Characteristics” for parameters, and to Figure 16 for

writes of the Resume command are ignored. Another

vice has resumed erasing.

Data Poll

(Note 11) 2 XXX 90 XXX 00

DQ6 each offer a method for determining whether a

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-

completed, or whether t he device is in Erase Sus pend.

must provide the program address to read valid status

proximately 1 µs, then the device returns to reading

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When t he Embedded Erase al-

“0.” The system must provide an address within any of

formation on DQ7.

tors selected for erasing are protected, Data# Polling

on DQ7 is active f or approximately 100 µs , the n the de-

vice returns to reading array data. If not all selected

erases the unprotected sectors, and ignores the se-

sequence. Since RY/BY# is an open-drain output , sev-

eral RY/BY# pins can be tied together in parallel with a