• SCAN CONVERTER

• ISA MASTER/SLAVE

• DMA CONTROLLER

• INTERRUPT CONTROLLER

• TIMER / COUNTERS

device.

The device is based on a tightly coupled Unified

Memory Architecture (UMA), sharing the same

memory array between the CPU main memory

and the graphics and video frame buff ers.

Extra facilities are implemented to handle video

streams. Features include smooth scaling and

colour space conversion of the video input stream

and mixing of the video stream with non-video

data from the fram e buffer. The chip also i ncludes

DRAM

• Parallel processing integral floating point unit,

• Cl ock core speeds up to of 75 MH z.

• F ully static design for dynam ic clock control.

• O ptimi zed design for 3.3V operation.

• Integrated system memory and graphic frame

• 60, 70, 80 & 100ns DRAM speeds.

• M em ory hole size of 1 MByte to 8 MBy tes

• Hi dden refresh.

• Hardware acceleration for text, bitblts , trans-

• Up to 4MB long linear frame buffer.

• Int erla ced or non-inter laced out put.

• Ch ro ma and colou r keying allow ing video

• O ptional 2:1 dec imator

• St ores captured video in off setting area of

• Int egrated PCI arbitration interface able to

• Translation of PCI cycles to ISA bus.

• Tr a ns lation of ISA maste r initia te d cycle to

• Support for burst read/write from PCI master.

• Fast Gate A2 0 and Fast reset.

• Support s the single ROM that C, D, or E.

• Support s flash ROM.

• Supports RTC, interrupts and DMAs wake-up

The STPC Client has in addition to the 5ST86 a

Video subsystem and high quality digital Televi-

sion output.

The STMicroelectronics x86 processor core is em-

bedded wit h stan dard and appli catio n specif ic pe-

ripheral modules on the same silicon die. The core

has all the functionality of the ST Microele ctronics

standard x86 processor products, including the

System Management Mode (SMM) provides an

Further power management facilities include a

suspend mode that can be initiated from either

hardware or software. Because of the static nature

of the core, no internal data is lost.

The STPC Client makes use of a tightly coupled

ry and graphics frame-buffer. This significantly re-

ances equa l to th at o f a comparable sol ution with

tem w ith 320M B /s peak bandwidth, double that of

depth. The processor bus runs at the speed of the

vices).

The ‘standard’ PC chipset functions (DMA, inter-

rupt controller, timers, power management logic)

are integrated with the x86 processor core.

The PCI bus is the ma in data comm unication link

also implements the PCI mandatory header regis-

ters in Type 0 PCI configuration space for easy

porting of PCI aware system BIOS. The device

nal PCI devices.

The STPC Client integrates an ISA bus controller.

Peripheral modules such as parallel and serial

communications ports, keyboard controllers and

additional ISA devices can be accessed by the

STPC Client chip set through this bus.

This Graphics Engine is tuned to work with the

host CPU to provide a balanced graphics system

with a low silicon area cost. It performs limited

graphics drawing ope rations, which include hard-

ware acceleration of text, bitblts, transparent blts

and fills. These operations can operate on off-

screen or o n-screen areas. T he fram e buffer size

is up to 4 MBytes anywhere in the physical main

memory.

The graphics resolution supported is a maximum

to handle MPEG or similar video streams. The

Video Input Port accepts an enc oded dig ital video

factor of 2:1, and deposits it into an off screen area

of the frame buffer. An interrupt request can be

generated w hen an ent ire fiel d or f ram e has been

The video output pipeline incorporates a video-

scaler and colour space converter function and

our and Chroma key functions are also imple-

mented to allow mixing video stream with non-vid-

The video output passes directly to the RAMDAC

for monitor output or through another optional col-

our space converter (RGB to 4:2:2 YC rCb ) to the

programma ble anti-flicker filter. The flicke r filter is

configured as either a two line filter with gamma

correction (primarily designed for DOS type text)

(STV0119). It takes a 24 bit RGB non-interlaced

pixel stream and converts to a multiplexed 4:2:2

YCrCb 8 bit output stream, the logic includes a

progressive to interlaced scan converter and logic

to insert appropriate CCIR656 timing reference

codes into the output stream. It facilitates the high

quality display of VGA or full screen video streams

received via the Video input port to standard

The STPC Client core is compliant with the Ad-

power usage and supports compliance with the

United States Environmental Protection Agen cy's

Energy Star Computer Program. The PMU pro-

software in managing the power consumption by

th e syste m.

- System Activity Detection.

- 3 power-down timers detecting system inactivity:

by state.

- SUSP# modulation to adjust the system per-

formance in various power down states of the sys-

tem including full power on state.

- Power control outputs to disable power from dif-

Lack of system activity for progressively longer

period of times is detected by the three power

down timers. These timers can generate SMI in-

the system in decreasing states of power con-

sump ti o n. Alte rn atively, system acti vit y in a power

ODD_EVEN

PCI_CLKI

multiplexed address and data bus. This bus is

driven by the master during the address phase

and data phase of write transactions. It is driven

by the target during data phase of read transac-

tions. Signals AD[12:11] for internal use only. Not

they define the command and during the data

phase they carry the Byte enable information.

than the STPC Client owns the bus and outputs

FRAME#

TRDY#

This is t he t arget ready sig-

nal of the PCI bus. It is driven as an output when

current PCI master is ready to complete the cur-

Stop is used to imple-

the PCI bus. It is used as an input fo r the b us cy-

device has decoded itself to be the target of the

current transact ion. It is asserted as a n output ei-

ther when the STPC Client is the target of the cur-

rent PCI transaction o r when no other device as-

serts DEVSEL# prior to the subtractive decode

phase of the current PCI transaction.

and PAR. This signal is driven by the master dur-

ing the address phase and data phase of write

transactions. It is driven by the target during data

nal of the PCI bus. It may, if enabled , be a sserted

for one PCI clock cycle if the target aborts an

by either the STPC Client or by another PCI bus

agent will trigger the assertion of NMI to the host

This is the lock signal of the PCI

quire use of th e bus.

These pins indicate

that the PCI bus has been granted master, re-

This pin has two func-

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

to guarantee it is active only when ISA bus is idle.

This pin has two func-

tions, depending on whet her the I SA bus is ac t ive

When the IDE bus is active, this signal is used as

signal. This signal is to be externally ANDed with

to guarantee it is active only when ISA bus is idle.

This pin has two functions, de-

pending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus i s active, this pin is ISA B us un-

bus master owns the bus, this pin is in input mode.

When the IDE bus is active, this signas is used as

to guarantee it is active only when ISA bus is idle.

When the ISA bus i s active, this pin is ISA B us un-

the ISA bus is accessed by any cycle initiated from

PCI bus, th is pin is in output m ode. When an ISA

bus master owns the bus, this pin is in input mode.

When the IDE bus is active, this signals is used as

the active high primary slave IDE chip sele ct sig-

nal. This signal is to be externally NANDed with

these pins are tristat ed.

These are the

SYSRSTO#

Interrupt Controller Interrupt input lines. This is a

divided down version of either the PCICLK or

latch enable output of the ISA bus and is asserted

The STPC Cli-

ent generates SMEMR# signal of the ISA bus only

This is the I/O read command sig-

This signal is

active when an ISA device has been granted bus

nals. The STPC Client does not drive IOCS16#

(similar to PC-AT design). An ISA master access

to an internal register of the STPC Client is exe-

cuted as an extended 8-bit I/O cycle.

the ISA bus. It is used as an input when an ISA

master owns the bus and is used to trigger a re-

fresh cycle.

The STPC Client performs a pseudo hidden re-

fresh. It requests the h ost bus for two host clo cks

nal buffers. The host bus is then relinquished

while the refresh cycle continues on the ISA bus.

AEN

of the signal indicates to I /O devices to ig nore t he

IOR#/IOW# signal during DMA transfers.

IOCHCK#

GPIOCS#

This output signa l is used by the ex ternal latc h on

ISA b us t o l atch t he d ata on t he SD [7: 0] bus. T he

latch can be used by the PMU unit to control the

external peripheral devices to power down or any

other desired function.

This pin is also serves as a strap input during re-

PDACK#

SDACK#

read. Active low output.

real time clock.

is a multi-function pin. When ISAOE# is active,

this signal is used as KBCS#. This signal is assert-

ed if a keyboard access is decoded during a I/O

cycle.

and is then connected to t he key board. A n LS 244

or equivalent function can be used if OE# is con-

is a multi-function pin. When ISAOE# is active,

weak pull-up resistor.

alent function can be used if OE # is con nected to

pull-up resistor.

IRQ_MUX[3:0]

These are the ISA bus interrupt signals . They are

to be encoded before connection to the STPC Cli-

ent using ISACLK and ISACLKX2 as the input se-

lection strobes.

These are

the PCI bus interrupt signals. They are to be en-

coded before connection to the STPC Client using

ISACLKX2 as the control strobes.

TC

the TC line of the ISA bus. It is asserted during the

RED, GREEN, BLUE

the vertical synchronization signal from the VGA

controller.

HSYNC

Th is is

VGA controller.

VREF_DAC

An external

voltage reference is connected to this pin to bias

T his is the R A M D AC co m-

ST[6],

ST[3:0] The pins are for testing the STPC. The

default settings on these pins should be 1111 for

ST[3:0] to 0111, the STPC is tristated.

CLKDEL[2:0]

Table 2-3. Pinout.

AC4 VSS

AC8 VSS

AD3 VSS

AE1:2 VSS

and the TV output logic. Its va lue is dependen t on the selected display mode.

Its frequency can be as high as 135 MHz. This signal is either driven by the internal PLL to a minimum of

8MHz or by an external oscillator. The direction can be controlled by a strap option or an internal register