CYW20736
Single-Chip Bluetooth Low Energy System-On-Chip
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-14883 Rev. *I Revised June 30, 2017
The Cypress CYW20736 is a an advanced Bluetooth Low Energy SoC that supports wireless charging profile. The CYW20736 is
designed to support the entire spectrum of Bluetooth Low Energy use cases for the medical, home automation, accessory, sensor,
Internet Of Things, and wearable market segments.
The CYW20736 radio has been designed to provide low power, low cost, and robust communications for applications operating in
the globally available 2.4 GHz unlicensed Industrial, Scientific, and Medical (ISM) band.
The single-chip Bluetooth low energy SoC is a monolithic component implemented in a standard digital CMOS process and requires
minimal external components to make a fully compliant Bluetooth device. The CYW20736 is available in a 32-pin, 5 mm × 5 mm
32-QFN package as well as WLCSP. CYW20736 device is supported in WICED SDK 2.x
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Features
The following profiles are supported1 in ROM:
■Battery status
■Blood pressure monitor
■Find me
■Heart rate monitor
■Proximity
■Thermometer
■Weight scale
■Time
Additional profiles that can be supported1 from RAM include:
■Blood glucose monitor
■Temperature alarm
■Location
Applications
■AirFuel wireless charging
■Bluetooth Low Energy (BLE)-compliant
■Infrared modulator
■IR learning
■Supports Adaptive Frequency Hopping
■Excellent receiver sensitivity
■10-bit auxiliary ADC with nine analog channels
■On-chip support for serial peripheral interface (master and
slave modes)
■Broadcom Serial Communications interface (compatible with
NXP I2C slaves)
■Programmable output power control
■Integrated ARM Cortex-M3 based microprocessor core
■Automation Profile
■Support for secure OTA
■On-chip power-on reset (POR)
■Support for EEPROM and serial flash interfaces
■Integrated low-dropout regulator (LDO)
■On-chip software controlled power management unit
■Package type:
❐32-pin 32-QFN package (5 mm × 5 mm)
❐80-pin WLCSP package (2104 µm × 2085 µm)
■RoHS compliant
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number Cypress Part Number
BCM20736 CYW20736
BCM20736A1KML2G CYW20736A1KML2G
BCM20736A1KWBGT CYW20736A1KWBGT
1. Full qualification and use of these profiles may require FW updates from Cypress. Some of these profiles are under development/approval at the Cypress SIG and
conformity with the final approved version is pending. Contact your supplier for updates and the latest list of profiles.
Document Number: 002-14883 Rev. *I Page 2 of 47
CYW20736
Figure 1. Functional Block Diagram
IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website
(http://community.cypress.com/).
Processing
Unit
(ARM -CM3)
System Bus
Bluetooth
Baseband
Core
2.4 GHz
Radio
RF Control
and Data
T/R
Switch
RF I/O
GPIO
Control/
Status
Registers
Frequency
Synthesizer
24 MHz
Ref Xtal
PMU
I/O Ring Bus
I/O Ring
Control
Registers
Peripheral
Interface
Block
1.2V VDD_CORE
Domain
VDD_IO
Domain
WAKE
1.2V
LDO 1.425V to 3.6V
1.62V to 3.6V
1.2V
VDD_CORE
320K
ROM 60K
RAM
BSC/SPI
Master
Interface
(BSC is I
2
C-
compaƟble)
SDA/
MOSI
SCL/
SCK
High Current
Driver Controls
14 GPIOs
32 kHz
LPCLK
9 ADC
Inputs
24
MHz
hclk
(24 MHz to 1 MHz)
AutoCal
MISO
1.2V VDD_RF
Domain PWM
WDT
128 kHz
LPO
÷4
32 kHz
LPCLK
128 kHz
LPCLK
32 kHzyƚĂů;ŽƉƟŽŶĂůͿ
Power
1.62V to 3.6V
VDD_IO
1.2V
POR
1.2V
Test
UART
IR
I/O
IR
Mod.
and
Learning
SPI
M/S
3.6V
MIA POR
28 ADC
Inputs
CT ɇѐ
ADC
VSS,
VDDO,
VDDC
Periph
UART
UART_RXD
UART_TXD Tx
Rx
RTS_N
CTS_N
Muxed on GPIO
Volt. Trans
Document Number: 002-14883 Rev. *I Page 3 of 47
CYW20736
Contents
1. Functional Description ................................................. 4
1.1 Bluetooth Baseband Core ..................................... 4
1.2 Infrared Modulator .................................................5
1.3 Infrared Learning ................................................... 5
1.4 ADC Port ............................................................... 6
1.5 Serial Peripheral Interface ..................................... 7
1.6 Microprocessor Unit .............................................. 8
1.7 Integrated Radio Transceiver ................................9
1.8 Peripheral Transport Unit .................................... 10
1.9 Clock Frequencies ............................................... 11
1.10 GPIO Port .......................................................... 12
1.11 PWM .................................................................. 13
1.12 Power Management Unit ................................... 14
2. Pin Information ........................................................... 15
2.1 Pin Descriptions ..................................................15
2.2 Pin Maps .............................................................19
2.3 WLCSP Pin List and Coordinates ....................... 21
3. GPIO Information ........................................................ 24
4. Specifications ............................................................. 32
4.1 Electrical Characteristics ..................................... 32
4.2 RF Specifications ................................................ 34
4.3 Timing and AC Characteristics ............................ 36
4.4 ESD Test Models ................................................ 39
5. Mechanical Information ............................................. 40
5.1 QFN ..................................................................... 40
5.2 WLCSP ................................................................ 43
6. Ordering Information .................................................. 44
A. Appendix: Acronyms and Abbreviations ............... 45
Document History .......................................................... 46
Sales, Solutions, and Legal Information ...................... 47
Document Number: 002-14883 Rev. *I Page 4 of 47
CYW20736
1. Functional Description
1.1 Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high performance Bluetooth operation.
The BBC manages the buffering, segmentation, and data routing for all connections. It also buffers data that passes through it, han-
dles data flow control, schedules ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data
into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these func-
tions, it independently handles HCI event types and HCI command types.
The following transmit and receive functions are also implemented in the BBC hardware to increase TX/RX data reliability and secu-
rity before sending over the air:
■Receive Functions: symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic
redundancy check (CRC), data decryption, and data dewhitening.
■Transmit Functions: data framing, FEC generation, HEC generation, CRC generation, link key generation, data encryption, and data
whitening.
1.1.1 Frequency Hopping Generator
The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state,
Bluetooth clock, and device address.
1.1.2 E0 Encryption
The encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and pro-
vide minimal processor intervention.
1.1.3 Link Control Layer
The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the Link Control Unit
(LCU). This layer consists of the Command Controller, which takes software commands, and other controllers that are activated or
configured by the Command Controller to perform the link control tasks. Each task performs a different Bluetooth link controller state.
STANDBY and CONNECTION are the two major states. In addition, there are five substates: page, page scan, inquiry, and inquiry
scan.
1.1.4 Adaptive Frequency Hopping
The CYW20736 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map
selection. The link quality is determined by using both RF and baseband signal processing to provide a more accurate frequency
hop map.
1.1.5 Bluetooth Low Energy Profiles
The CYW20736 supports Bluetooth low energy, including the following profiles that are supported1 in ROM:
■Battery status
■Blood pressure monitor
■Find me
■Heart rate monitor
■Proximity
■Thermometer
■Weight scale
■Time
■AirFuel wireless charging
■Automation profile
■Support for secure OTA
1. Full qualification and use of these profiles may require FW updates from Cypress. Some of these profiles are under development/approval at the Bluetooth SIG and
conformity with the final approved version is pending. Contact your supplier for updates and the latest list of profiles.
Document Number: 002-14883 Rev. *I Page 5 of 47
CYW20736
The following additional profiles can be supported1 from RAM:
■Blood glucose monitor
■Temperature alarm
■Location
■Custom profile
1.1.6 Test Mode Support
The CYW20736 fully supports Bluetooth Test mode, as described in the Bluetooth low energy specification.
1.2 Infrared Modulator
The CYW20736 includes hardware support for infrared TX. The hardware can transmit both modulated and unmodulated wave-
forms. For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced
from firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter.
If descriptors are used, they include IR on/off state and the duration between 1–32767 µsec. The CYW20736 IR TX firmware driver
inserts this information in a hardware FIFO and makes sure that all descriptors are played out without a glitch due to underrun (see
Figure 2).
Figure 2. Infrared TX
1.3 Infrared Learning
The CYW20736 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated sig-
nals. For modulated signals, the CYW20736 can detect carrier frequencies between 10 kHz–500 kHz and the duration that the sig-
nal is present or absent. The CYW20736 firmware driver supports further analysis and compression of learned signal. The learned
signal can then be played back through the CYW20736 IR TX subsystem (see Figure 3).
Figure 3. Infrared RX
Document Number: 002-14883 Rev. *I Page 6 of 47
CYW20736
1.4 ADC Port
The CYW20736 contains a 16-bit ADC (effective number of bits is 10).
Additionally:
■There are 9 analog input channels in the 32-pin package
■The following GPIOs can be used as ADC inputs:
❐P0
❐P1
❐P8/P33 (select only one)
❐P11
❐P12
❐P13/P28 (select only one)
❐P14/P38 (select only one)
❐P15
❐P32
■The conversion time is 10 s.
■There is a built-in reference with supply- or bandgap-based reference modes.
■The maximum conversion rate is 187 kHz.
■There is a rail-to-rail input swing.
The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes
the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input mul-
tiplexers that select the ADC input signal Vinp and the ADC reference signals Vref.
The ADC input range is selectable by firmware control:
■When an input range of 0–3.6V is used, the input impedance is 3 M.
■When an input range of 0–2.4V is used, the input impedance is 1.84 M.
■When an input range of 0–1.2V is used, the input impedance is 680 k.
ADC modes are defined in Ta b l e 2 .
Table 2. ADC Modes
Mode ENOB (Typical) Maximum Sampling Rate (kHz) Latencya (μs)
a. Settling time after switching channels.
Mode
013 5.8591710
1 12.6 11.7 85 1
2 12 46.875 21 2
3 11.5 93.75 11 3
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CYW20736
1.5 Serial Peripheral Interface
The CYW20736 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or a slave.
Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the
CYW20736 has optional I/O ports that can be configured individually and separately for each functional pin as shown in Table 3,
Table 4, and Tab l e 5 . The CYW20736 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20736 can also
act as an SPI slave device that supports a 1.8V or 3.3V SPI master.
Table 3. CYW20736 First SPI Set (Master Mode)
Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Configured Pin Name
SCL SDA P24 –
––P26–
––P32–
Table 4. CYW20736 Second SPI Set (Master Mode)
Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Configured Pin Name
P3 P0 P1 –
–P4P25–
P24 P27 – –
Table 5. CYW20736 Second SPI Set (Slave Mode)
Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CS
Configured Pin Name
P3 P0 P1 P2
–P27– –
P24 P33 P25 P26
–––P32
Document Number: 002-14883 Rev. *I Page 8 of 47
CYW20736
1.6 Microprocessor Unit
The CYW20736 microprocessor unit (µPU) executes software from the link control (LC) layer up to the application layer compo-
nents. The microprocessor is based on an ARM Cortex-M3, 32-bit RISC processor with embedded ICE-RT debug and JTAG inter-
face units. The µPU has 320 KB of ROM for program storage and boot-up, 60 KB of RAM for scratch-pad data, and patch RAM
code. The SoC has a total storage of 380 KB, including RAM and ROM.
The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in different HID applications
with an external serial EEPROM or with an external serial flash memory. At power-up, the lowest layer of the protocol stack is exe-
cuted from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can
also support the integration of user applications.
1.6.1 EEPROM Interface
The CYW20736 provides a Broadcom Serial Control (BSC) master interface. BSC is programmed by the CPU to generate four types
of bus transfers: read-only, write-only, combined read/write, and combined write/read. BSC supports both low-speed and fast mode
devices. BSC is compatible with an NXP I2C slave device, except that master arbitration (multiple I2C masters contending for the
bus) is not supported.
The EEPROM can contain customer application configuration information including application code, configuration data, patches,
pairing information, BD_ADDR, baud rate, SDP service record, and file system information used for code.
Native support for the Microchip 24LC128, Microchip 24AA128, and ST Micro M24128-BR is included.
1.6.2 Serial Flash Interface
The CYW20736 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB
slave interface, transmit and receive FIFOs, and the SPI core PHY logic.
Devices natively supported include the following:
■Atmel AT25BCM512B
■MXIC MX25V512ZUI-20G
1.6.3 Internal Rese t
Figure 4. Internal Reset Timing
VDDO
VDDOPOR
VDDC
VDDOPORthreshold
VDDOPORdelay
~2ms
VDDCPOR
VDDCPORthreshold
VDDCPORdelay
~2ms
BasebandReset
Crystal
warm‐up
delay:
~5ms
CrystalEnable
StartreadingEEPROMand
firmwareboot
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CYW20736
1.6.4 External Reset
The CYW20736 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external
active low reset signal, RESET_N, can be used to put the CYW20736 in the reset state. The RESET_N pin has an internal pull-up
resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after the
VDDO supply voltage level has been stabilized.
Figure 5. External Reset Timing
1.7 Integrated Radio Transceiver
The CYW20736 has an integrated radio transceiver that is optimized for 2.4 GHz Bluetooth wireless systems. It has been designed
to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed
ISM band. It is fully compliant with Bluetooth Radio Specification 4.0 and meets or exceeds the requirements to provide the highest
communication link quality of service.
1.7.1 Transmitter Path
The CYW20736 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.
Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes
any frequency drift or anomalies in the modulation characteristics of the transmitted signal.
Power Amplifier
The CYW20736 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation.
1.7.2 Receiver Path
The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit syn-
chronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order, on-chip channel filter-
ing to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation,
enables the CYW20736 to be used in most applications without off-chip filtering.
Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit syn-
chronization algorithm.
Receiver Signal Strength Indicator
The radio portion of the CYW20736 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller
to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the
transmitter should increase or decrease its output power.
RESET_N
Pulsewidth
>20µs
CrystalEnable
BasebandReset
StartreadingEEPROMand
firmwareboot
Crystal
warm‐up
delay:
~5ms
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CYW20736
1.7.3 Local Oscillator
The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The
CYW20736 uses an internal loop filter.
1.7.4 Calibration
The CYW20736 radio transceiver features a self-contained automated calibration scheme. No user interaction is required during
normal operation or during manufacturing to provide optimal performance. Calibration compensates for filter, matching network, and
amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. Calibration takes process and tem-
perature variations into account, and it takes place transparently during normal operation and hop setting times.
1.7.5 Internal LDO Regulator
The CYW20736 has an integrated 1.2V LDO regulator that provides power to the digital and RF circuits. The 1.2V LDO regulator
operates from a 1.425V to 3.63V input supply with a 30 mA maximum load current.
Note: Always place the decoupling capacitors near the pins as closely together as possible.
1.8 Peripheral Transport Unit
1.8.1 Broadcom Serial Communications Interface
The CYW20736 provides a 2-pin master BSC interface, which can be used to retrieve configuration information from an external
EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse
devices. The BSC interface is compatible with I2C slave devices. The BSC does not support multimaster capability or flexible
wait-state insertion by either master or slave devices.
The following transfer clock rates are supported by the BSC:
■100 kHz
■400 kHz
■800 kHz (not a standard I2C-compatible speed.)
■1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.)
The following transfer types are supported by the BSC:
■Read (Up to 16 bytes can be read.)
■Write (Up to 16 bytes can be written.)
■Read-then-Write (Up to 16 bytes can be read and up to 16 bytes can be written.)
■Write-then-Read (Up to 16 bytes can be written and up to 16 bytes can be read.)
Hardware controls the transfers, requiring minimal firmware setup and supervision.
The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW20736 are required on
both the SCL and SDA pins for proper operation.
1.8.2 UART Interface
The UART is a standard 2-wire interface (RX and TX) and has adjustable baud rates from 9600 bps to 1.5 Mbps. The baud rate can
be selected via a vendor-specific UART HCI command. The interface supports the Bluetooth 3.0 UART HCI (H5) specification. The
default baud rate for H5 is 115.2 kbaud.
Both high and low baud rates can be supported by running the UART clock at 24 MHz.
The CYW20736 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within
±5%.
Document Number: 002-14883 Rev. *I Page 11 of 47
CYW20736
1.9 Clock Frequencies
The CYW20736 is set with crystal frequency of 24 MHz.
1.9.1 Crystal Oscillator
The crystal oscillator requires a crystal with an accuracy of ±20 ppm as defined by the Bluetooth specification. Two external load
capacitors in the range of 5 pF to 30 pF (see Figure 6) are required to work with the crystal oscillator. The selection of the load
capacitors is crystal-dependent. Table 6 shows the recommended crystal specifications.
Figure 6. Recommended Oscillator Configuration—12 pF Load Crystal
Table 6 shows the recommended crystal specifications.
Peripheral Block
The peripheral blocks of the CYW20736 all run from a single 128 kHz low-power RC oscillator. The oscillator can be turned on at the
request of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock request line.
The keyboard scanner is a special case, in that it may drop its clock request line even when enabled, and then reassert the clock
request line if a keypress is detected.
Table 6. Reference Crystal Electrical Specifications
Parameter Conditions Minimum Typical Maximum Unit
Nominal frequency – – 24.000 – MHz
Oscillation mode – Fundamental –
Frequency tolerance @25°C – ±10 – ppm
Tolerance stability over temp @0°C to +70°C – ±10 – ppm
Equivalent series resistance – – – 60
Load capacitance – – 12 – pF
Operating temperature range – 0 – +70 °C
Storage temperature range – –40 – +125 °C
Drive level – – – 200 
Aging – – – ±10 ppm/year
Shunt capacitance – – – 2 pF
22pF
20pF
Crystal
XIN
XOUT
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CYW20736
32 kHz Crystal Oscillator
Figure 7 shows the 32 kHz crystal (XTAL) oscillator with external components and Ta b le 7 lists the oscillator’s characteristics. It is a
standard Pierce oscillator using a comparator with hysteresis on the output to create a single-ended digital output. The hysteresis
was added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mV. This circuit can be
operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar frequency. The default component
values are: R1 = 10 M, C1 = C2 = ~10 pF. The values of C1 and C2 are used to fine-tune the oscillator.
Figure 7. 32 kHz Oscillator Block Diagram
1.10 GPIO Port
The CYW20736 has 14 general-purpose I/Os (GPIOs) in the 32-pin package. All GPIOs support programmable pull-up and
pull-down resistors, and all support a 2 mA drive strength except P26, P27, and P28, which provide a 16 mA drive strength at 3.3V
supply.
The following GPIOs are available:
■P0–P4
■P8/P33 (Dual bonded, only one of two is available.)
■P11/P27 (Dual bonded, only one of two is available.)
■P12/P26 (Dual bonded, only one of two is available.)
■P13/P28 (Dual bonded, only one of two is available.)
■P14/P38 (Dual bonded, only one of two is available.)
■P15
■P24
■P25
■P32
Table 7. XTAL Oscillator Characteristics
Parameter Symbol Conditions Minimum Typical Maximum Unit
Output frequency Foscout – – 32.768 – kHz
Frequency
tolerance
–Crystal dependent –100–ppm
Start-up time Tstartup –––500ms
XTAL drive level Pdrv For crystal selection 0.5 – – 
XTAL series
resistance Rseries For crystal selection ––70k
XTAL shunt
capacitance Cshunt For crystal selection ––1.3pF
C2
C1
R1 32.768kHz
XTAL
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CYW20736
For a description of all GPIOs, see Table 11 on page 24.
1.11 PWM
The CYW20736 has four internal PWM channels. The PWM module is described as follows:
■PWM0–3
■The following GPIOs can be mapped as PWMs:
❐P26
❐P27
❐P14/P28 (Dual bonded, only one of two is available.)
❐P13
■Each of the PWM channels, PWM0–3, contains the following registers:
❐10-bit initial value register (read/write)
❐10-bit toggle register (read/write)
❐10-bit PWM counter value register (read)
■The PWM configuration register is shared among PWM0–3 (read/write). This 12-bit register is used:
❐To configure each PWM channel.
❐To select the clock of each PWM channel.
❐To change the phase of each PWM channel.
Figure 8 shows the structure of one PWM channel.
Figure 8. PWM Channel Block Diagram
pwm_cfg_adrregister pwm#_init_val_adrregister pwm#_togg_val_adrregister
pwm#_cntr_adr
enable
cntrvalueisCM3readable
clk_sel
o_flip
10'H000
10'H3FF
10
10 10
Example:PWMcntrw/pwm#_init_val=0(dashedline)
PWMcntrw/pwm#_init_val=x(solidline)
10'Hx
pwm_out
pwm_togg_val_adr
pwm_out
Document Number: 002-14883 Rev. *I Page 14 of 47
CYW20736
1.12 Power Management Unit
The Power Management Unit (PMU) provides power management features that can be invoked by software through power manage-
ment registers or packet-handling in the baseband core.
1.12.1 RF Power Management
The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-
ceiver, which then processes the power-down functions accordingly.
1.12.2 Host Controller Power Management
Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the
disabling of the on-chip regulator when in deep sleep mode.
1.12.3 BBC Power Management
There are several low-power operations for the BBC:
■Physical layer packet handling turns RF on and off dynamically within packet TX and RX.
■Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYW20736 runs on the Low
Power Oscillator and wakes up after a predefined time period.
The CYW20736 automatically adjusts its power dissipation based on user activity. The following power modes are supported:
■Active mode
■Idle mode
■Sleep mode
■HIDOFF (Deep Sleep) mode
■Timed Deep Sleep mode
The CYW20736 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered
when user activity resumes.
In HIDOFF (Deep Sleep) mode, the CYW20736 baseband and core are powered off by disabling power to LDOOUT. The VDDO
domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power
consumption and is intended for long periods of inactivity.
Document Number: 002-14883 Rev. *I Page 15 of 47
CYW20736
2. Pin Information
2.1 Pin Descriptions
Table 8 provides pin descriptions for the QFN package.
Table 8. QFN Package Pin Descriptions
Pin Number Pin Name I/O Power Domain Description
Radio I/O
6 RF I/O VDD_RF RF antenna port
RF Power Supplies
4 VDDIF I VDD_RF IFPLL power supply
5 VDDFE I VDD_RF RF front-end supply
7 VDDVCO I VDD_RF VCO, LOGEN supply
8 VDDPLL I VDD_RF RFPLL and crystal oscillator supply
Power Supplies
11 VDDC I VDDC Baseband core supply
28 VDDO I VDDO I/O pad and core supply
14 VDDM I VDDM I/O pad supply
Clock Generator and Crystal Interface
9 XTALI I VDD_RF Crystal oscillator input. See page 11 for options.
10 XTALO O VDD_RF Crystal oscillator output.
1XTALI32KIVDDO
Low-power oscillator (LPO) input is used.
Alternative Function:
■P11
■P27
32 XTALO32K O VDDO
Low-power oscillator (LPO) output.
Alternative Function:
■P12
■P26
Core
18 RESET_N I/O PU VDDO Active-low system reset with open-drain output & internal
pull-up resistor
17 TMC I VDDO
Test mode control
High: test mode
Connect to GND if not used.
UART
12 UART_RXD I VDDM
UART serial input – Serial data input for the HCI UART
interface. Leave unconnected if not used.
Alternative function:
■GPIO3
13 UART_TXD O, PU VDDM
UART serial output – Serial data output for the HCI UART
interface. Leave unconnected if not used.
Alternative Function:
■GPIO2
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Table 9 provides pin descriptions for the WLCSP package. The table is ordered by pin name.
BSC
15 SDA I/O, PU VDDM
Data signal for an external I2C device.
Alternative function:
■SPI_1: MOSI (master only)
■GPIO0
■CTS
16 SCL I/O, PU VDDM
Clock signal for an external I2C device.
Alternative function:
■SPI_1: SPI_CLK (master only)
■GPIO1
■RTS
LDO Regulator Power Supplies
2 LDOIN I N/A Battery input supply for the LDO
3 LDOOUT O N/A LDO output
Table 9. WLCSP Package Pin Descriptions
Pin Numbers Pin Name Type Power Domain Description
57 AVSS I AVSS Analog ground
69 FEVDD I FEVDD RF front-end supply
70 FEVSS I VSS Ground
67 IFVDD I IFVDD IF PLL power supply
54, 68, 71, 72 IFVSS I VSS Ground
76 PLLVDD I PLLVDD RF PLL and crystal oscillator supply
79 PLLVSS I VSS Ground
Table 8. QFN Package Pin Descriptions (Cont.)
Pin Number Pin Name I/O Power Domain Description
Document Number: 002-14883 Rev. *I Page 17 of 47
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21 P0 I VDDO
General purpose I/O
(See Table 12: “WLCSP Package GPIO Pin Descrip-
tions,” on page 27.)
26 P1 I VDDO
22 P2 I VDDO
13 P3 I VDDO
31 P4 I VDDO
14 P5 I VDDO
27 P6 I VDDO
18 P7 I VDDO
36 P8 I VDDO
63 P9 I VDDO
53 P10 I VDDO
66 P11 I VDDO
55 P12 I VDDO
20 P13 I VDDO
35 P14 I VDDO
52 P15 I VDDO
32 P16 I VDDO
23 P17 I VDDO
41 P18 I VDDO
28 P19 I VDDO
33 P20 I VDDO
43 P21 I VDDO
15 P22 I VDDO
48 P23 I VDDO
47 P24 I VDDO
19 P25 I VDDO
30 P26 I VDDO
25 P27 I VDDO
49 P28 I VDDO
44 P29 I VDDO
50 P30 I VDDO
39 P31 I VDDO
38 P32 I VDDO
46 P33 I VDDO
34 P34 I VDDO
29 P35 I VDDO
62 P36 I VDDO
64 P37 I VDDO
24 P38 I VDDO
51 P39 I VDDO
Table 9. WLCSP Package Pin Descriptions (Cont.)
Pin Numbers Pin Name Type Power Domain Description
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73 RF I/O VDD_RF RF antenna port
16 RST_N I/O PU VDDO Active-low system reset with open-drain output & internal
pull-up resistor
2 SCL I/O, PU VDDM
Clock signal for an external I2C device.
Alternative function:
■SPI_1: SPI_CLK (master only)
■GPIO1
■RTS
7 SDA I/O, PU VDDM
Data signal for an external I2C device.
Alternative function:
■SPI_1: MOSI (master only)
■GPIO0
■CTS
11 TMC I VDDO
Test mode control
High: test mode
Connect to GND if not used.
10 UART_RXD I VDDM
UART serial input – Serial data input for the HCI UART
interface. Leave unconnected if not used.
Alternative function:
■GPIO3
9 UART_TXD O, PU VDDM
UART serial output – Serial data output for the HCI UART
interface. Leave unconnected if not used.
Alternative Function:
■GPIO2
77, 80 VCOVDD I VCOVDD VCO and LO generator supply
74 VCOVSS I N/A Ground
1, 4 VDDC I VDDC Baseband core supply
3 VDDM I VDDM I/O pad supply
17, 37, 45, 58 VDDO I VDDO I/O pad and core supply
65 VREG O VREG Internal LDO regulator output
60 VR3V I N/A Internal LDO regulator input
5, 6, 8 VSSC I N/A Ground
12, 40, 59 VSSO I N/A Ground
42 VSS0 I N/A Ground
75 XIN I VDD_RF Crystal oscillator input. See page 11 for options.
78 XOUT O VDD_RF Crystal oscillator output.
61 XTAL32KI I VDDO Low-power oscillator (LPO) input is used.
56 XTAL32KO O VDDO Low-power oscillator (LPO) output.
Table 9. WLCSP Package Pin Descriptions (Cont.)
Pin Numbers Pin Name Type Power Domain Description
Document Number: 002-14883 Rev. *I Page 19 of 47
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2.2 Pin Maps
Figure 9 shows the ball map of the QFN package.
Figure 9. 32-Pin QFN Ball Map
Document Number: 002-14883 Rev. *I Page 20 of 47
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Figure 10 shows the bump map of the WLCSP package.
Figure 10. 80-Pin WLCSP Bump Map—Top View of Package with Bumps Facing Down
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2.3 WLCSP Pin List and Coordinates
Table 10 provides the WLCSP pin list and coordinates.
Table 10. WLCSP Pin List and Coordinates
Bump # Net Name
Package Bottom View
(Bumps Facing Up)
Package Center (0,0)
Package Top View
(Bumps Facing Down)
Package Center (0,0)
X Coordinate Y Coordinate X Coordinate Y Coordinate
1 VDDC –895.5 –877.2587 –895.5 877.2587
2 SCL –895.5 –677.2587 –895.5 677.2587
3 VDDM –895.5 –477.2587 –895.5 477.2587
4 VDDC –895.5 –277.2587 –895.5 277.2587
5 VSSC –895.5 –77.2587 –895.5 77.2587
6 VSSC –695.5 –877.2587 –695.5 877.2587
7 SDA –695.5 –677.2587 –695.5 677.2587
8 VSSC –695.5 –477.2587 –695.5 477.2587
9 UART_TXD –695.5 –277.2587 –695.5 277.2587
10 UART_RXD –695.5 –77.2587 –695.5 77.2587
11 TMC –495.5 –877.2587 –495.5 877.2587
12 VSSO –495.5 –677.2587 –495.5 677.2587
13 P3 –495.5 –477.2587 –495.5 477.2587
14 P5 –495.5 –277.2587 –495.5 277.2587
15 P22 –495.5 –77.2587 –495.5 77.2587
16 RST_N –295.5 –877.2587 –295.5 877.2587
17 VDDO –295.5 –677.2587 –295.5 677.2587
18 P7 –295.5 –477.2587 –295.5 477.2587
19 P25 –295.5 –277.2587 –295.5 277.2587
20 P13 –295.5 –77.2587 –295.5 77.2587
21 P0 –95.5 –877.2587 –95.5 877.2587
22 P2 –95.5 –677.2587 –95.5 677.2587
23 P17 –95.5 –477.2587 –95.5 477.2587
24 P38 –95.5 –277.2587 –95.5 277.2587
25 P27 –95.5 –77.2587 –95.5 77.2587
26 P1 104.5 –877.2587 104.5 877.2587
27 P6 104.5 –677.2587 104.5 677.2587
28 P19 104.5 –477.2587 104.5 477.2587
29 P35 104.5 –277.2587 104.5 277.2587
30 P26 104.5 –77.2587 104.5 77.2587
31 P4 304.5 –877.2587 304.5 877.2587
32 P16 304.5 –677.2587 304.5 677.2587
33 P20 304.5 –477.2587 304.5 477.2587
34 P34 304.5 –277.2587 304.5 277.2587
35 P14 304.5 –77.2587 304.5 77.2587
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36 P8 504.5 –877.2587 504.5 877.2587
37 VDDO 504.5 –677.2587 504.5 677.2587
38 P32 504.5 –477.2587 504.5 477.2587
39 P31 504.5 –277.2587 504.5 277.2587
40 VSSO 504.5 –77.2587 504.5 77.2587
41 P18 704.5 –877.2587 704.5 877.2587
42 VSS0 704.5 –677.2587 704.5 677.2587
43 P21 704.5 –477.2587 704.5 477.2587
44 P29 704.5 –277.2587 704.5 277.2587
45 VDDO 704.5 –77.2587 704.5 77.2587
46 P33 904.5 –877.2587 904.5 877.2587
47 P24 904.5 –677.2587 904.5 677.2587
48 P23 904.5 –477.2587 904.5 477.2587
49 P28 904.5 –277.2587 904.5 277.2587
50 P30 904.5 –77.2587 904.5 77.2587
51 P39 794 322.7413 794 –322.7413
52 P15 594 322.7413 594 –322.7413
53 P10 394 322.7413 394 –322.7413
54 IFVSS 211.14 422.7413 211.14 –422.7413
55 P12 794 522.7413 794 –522.7413
56 XTAL32KO 594 522.7413 594 –522.7413
57 AVSS 394 522.7413 394 –522.7413
58 VDDO 794 922.7413 794 –922.7413
59 VSSO 594 922.7413 594 –922.7413
60 VR3V 394 922.7413 394 –922.7413
61 XTAL32KI 794 722.7413 794 –722.7413
62 P36 794 122.7413 794 –122.7413
63 P9 594 722.7413 594 –722.7413
64 P37 594 122.7413 594 –122.7413
65 VREG 394 722.7413 394 –722.7413
66 P11 394 122.7413 394 –122.7413
67 IFVDD 194 922.7413 194 –922.7413
68 IFVSS 194 722.7413 194 –722.7413
69 FEVDD –6 922.7413 –6 –922.7413
70 FEVSS –6 722.7413 –6 –722.7413
71 IFVSS –75.35 224.6363 –75.35 –224.6363
72 IFVSS –275.35 224.6363 –275.35 –224.6363
Table 10. WLCSP Pin List and Coordinates (Cont.)
Bump # Net Name
Package Bottom View
(Bumps Facing Up)
Package Center (0,0)
Package Top View
(Bumps Facing Down)
Package Center (0,0)
X Coordinate Y Coordinate X Coordinate Y Coordinate
Document Number: 002-14883 Rev. *I Page 23 of 47
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73 RF –330.025 822.7413 –330.025 –822.7413
74 VCOVSS –517.5 927.0313 –517.5 –927.0313
75 XIN –651.09 154.5313 –651.09 –154.5313
76 PLLVDD –651.09 354.5313 –651.09 –354.5313
77 VCOVDD –717.5 927.0313 –717.5 –927.0313
78 XOUT –851.09 154.5313 –851.09 –154.5313
79 PLLVSS –851.09 354.5313 –851.09 –354.5313
80 VCOVDD –917.5 927.0313 –917.5 –927.0313
Table 10. WLCSP Pin List and Coordinates (Cont.)
Bump # Net Name
Package Bottom View
(Bumps Facing Up)
Package Center (0,0)
Package Top View
(Bumps Facing Down)
Package Center (0,0)
X Coordinate Y Coordinate X Coordinate Y Coordinate
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3. GPIO Information
Table 11 provides the GPIO alternate function descriptions for the QFN package.
Table 11. QFN Package GPIO Pin Descriptionsa
Pin Number Pin Name Default
Direction
After
POR State
Power
Domain Alternate Function Description
19 P0 Input Input
floating VDDO
■GPIO: P0
■A/D converter input
■Peripheral UART: puart_tx
■SPI_2: MOSI (master and slave)
■IR_RX
■60Hz_main
■Not available during TMC=1
20 P1 Input Input
floating VDDO
■GPIO: P1
■A/D converter input
■Peripheral UART: puart_rts
■SPI_2: MISO (master and slave)
■IR_TX
21 P3 Input Input
floating VDDO
■GPIO: P3
■Peripheral UART: puart_cts
■SPI_2: SPI_CLK (master and slave)
22 P2 Input Input
floating VDDO
■GPIO: P2
■Peripheral UART: puart_rx
■SPI_2: SPI_CS (slave only)
■SPI_2: SPI_MOSI (master only)
23 P4 Input Input
floating VDDO
■GPIO: P4
■Peripheral UART: puart_rx
■SPI_2: MOSI (master and slave)
■IR_TX
24
P8 Input Input
floating VDDO
■GPIO: P8
■A/D converter input
■External T/R switch control: ~tx_pd
P33 Input Input
floating VDDO
■GPIO: P33
■A/D converter input
■SPI_2: MOSI (slave only)
■Auxiliary clock output: ACLK1
■Peripheral UART: puart_rx
1
P11 Input Input
floating VDDO
■GPIO: P11
■A/D converter input
■XTALI32K
P27
PWM1 Input Input
floating VDDO
■GPIO: P27
■SPI_2: MOSI (master and slave)
Current: 16 mA
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32
P12 Input Input
floating VDDO
■GPIO: P12
■A/D converter input
■XTALO32K
P26
PWM0 Input Input
floating VDDO
■GPIO: P26
■SPI_2: SPI_CS (slave only)
■SPI_1: MISO (master only)
Current: 16 mA
29
P13
PWM3 Input Input
floating VDDO
■GPIO: P13
■A/D converter input
P28
PWM2 Input Input
floating VDDO
■GPIO: P28
■A/D converter input
■LED1
■IR_TX
Current: 16 mA
30
P14
PWM2 Input Input
floating VDDO
■GPIO: P14
■A/D converter input
P38 Input Input
floating VDDO
■GPIO: P38
■A/D converter input
■SPI_2: MOSI (master and slave)
■IR_TX
31 P15 Input Input
floating VDDO
■GPIO: P15
■A/D converter input
■IR_RX
■60 Hz_main
27 P24 Input Input
floating VDDO
■GPIO: P24
■SPI_2: SPI_CLK (master and slave)
■SPI_1: MISO (master only)
■Peripheral UART: puart_tx
26 P25 Input Input
floating VDDO
■GPIO: P25
■SPI_2: MISO (master and slave)
■Peripheral UART: puart_rx
Table 11. QFN Package GPIO Pin Descriptionsa (Cont.)
Pin Number Pin Name Default
Direction
After
POR State
Power
Domain Alternate Function Description
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25 P32 Input Input
floating VDDO
■GPIO: P32
■A/D converter input
■SPI_2: SPI_CS (slave only)
■SPI_1: MISO (master only)
■Auxiliary clock output: ACLK0
■Peripheral UART: puart_tx
a. During a power-on reset, all inputs are disabled.
Table 11. QFN Package GPIO Pin Descriptionsa (Cont.)
Pin Number Pin Name Default
Direction
After
POR State
Power
Domain Alternate Function Description
Document Number: 002-14883 Rev. *I Page 27 of 47
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Table 12 provides the GPIO alternate function descriptions for the WLCSP package.
Table 12. WLCSP Package GPIO Pin Descriptionsa
Pin Number Pin Name Default
Direction After POR Power
Domain Alternate Function Description
21 P0 Input Floating VDDO
■GPIO: P0
■Keyboard scan input (row): KSI0
■A/D converter input
■Peripheral UART: puart_tx
■SPI_2: MOSI (master and slave)
■IR_RX
■60 Hz_main
■Not available during TMC=1
26 P1 Input Floating VDDO
■GPIO: P1
■Keyboard scan input (row): KSI1
■A/D converter input
■Peripheral UART: puart_rts
■SPI_2: MISO (master and slave)
■IR_TX
22 P2 Input Floating VDDO
■GPIO: P2
■Keyboard scan input (row): KSI2
■Quadrature: QDX0
■Peripheral UART: puart_rx
■SPI_2: SPI_CS (slave only)
■SPI_2: SPI_MOSI (master only)
13 P3 Input Floating VDDO
■GPIO: P3
■Keyboard scan input (row): KSI3
■Quadrature: QDX1
■Peripheral UART: puart_cts
■SPI_2: SPI_CLK (master and slave)
31 P4 Input Floating VDDO
■GPIO: P4
■Keyboard scan input (row): KSI4
■Quadrature: QDY0
■Peripheral UART: puart_rx
■SPI_2: MOSI (master and slave)
■IR_TX
14 P5 Input Floating VDDO
■GPIO: P5
■Keyboard scan input (row): KSI5
■Quadrature: QDY1
■Peripheral UART: puart_tx
■SPI_2: MISO (master and slave)
27 P6
PWM2 Input Floating VDDO
■GPIO: P6
■Keyboard scan input (row): KSI6
■Quadrature: QDZ0
■Peripheral UART: puart_rts
■SPI_2: SPI_CS (slave only)
■60Hz_main
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18 P7 Input Floating VDDO
■GPIO: P7
■Keyboard scan input (row): KSI7
■Quadrature: QDZ1
■Peripheral UART: puart_cts
■SPI_2: SPI_CLK (master and slave)
36 P8 Input Floating VDDO
■GPIO: P8
■Keyboard scan output (column): KSO0
■A/D converter input
■External T/R switch control: ~tx_pd
63 P9 Input Floating VDDO
■GPIO: P9
■Keyboard scan output (column): KSO1
■A/D converter input
■External T/R switch control: tx_pd
53 P10
PWM3 Input Floating VDDO
■GPIO: P10
■Keyboard scan output (column): KSO2
■A/D converter input
66 P11 Input Floating VDDO
■GPIO: P11
■Keyboard scan output (column): KSO3
■A/D converter input
■XTALI32K (40-QFN only)
55 P12 Input Floating VDDO
■GPIO: P12
■Keyboard scan output (column): KSO4
■A/D converter input
■XTALO32K (40-QFN only)
20 P13
PWM3 Input Floating VDDO
■GPIO: P13
■Keyboard scan output (column): KSO5
■A/D converter input
■Alternative Function: P28
35 P14
PWM2 Input Floating VDDO
■GPIO: P14
■Keyboard scan output (column): KSO6
■A/D converter input
52 P15 Input Floating VDDO
■GPIO: P15
■Keyboard scan output (column): KSO7
■A/D converter input
■IR_RX
■60Hz_main
■Alternative Function: P26
32 P16 Input Floating VDDO
■GPIO: P16
■Keyboard scan output (column): KSO8
Table 12. WLCSP Package GPIO Pin Descriptionsa (Cont.)
Pin Number Pin Name Default
Direction After POR Power
Domain Alternate Function Description
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23 P17 Input Floating VDDO
■GPIO: P17
■Keyboard scan output (column): KSO9
■A/D converter input
41 P18 Input Floating VDDO
■GPIO: P18
■Keyboard scan output (column): KSO10
■A/D converter input
28 P19 Input Floating VDDO
■GPIO: P19
■Keyboard scan output (column): KSO11
■A/D converter input
33 P20 Input Floating VDDO
■GPIO: P20
■Keyboard scan output (column): KSO12
■A/D converter input
43 P21 Input Floating VDDO
■GPIO: P21
■Keyboard scan output (column): KSO13
■A/D converter input
15 P22 Input Floating VDDO
■GPIO: P22
■Keyboard scan output (column): KSO14
■A/D converter input
48 P23 Input Floating VDDO
■GPIO: P23
■Keyboard scan output (column): KSO15
■A/D converter input
47 P24 Input Floating VDDO
■GPIO: P24
■Keyboard scan output (column): KSO16
■SPI_2: SPI_CLK (master and slave)
■SPI_1: MISO (master only)
■Peripheral UART: puart_tx
19 P25 Input Floating VDDO
■GPIO: P25
■Keyboard scan output (column): KSO17
■SPI_2: MISO (master and slave)
■Peripheral UART: puart_rx
30 P26
PWM0 Input Floating VDDO
■GPIO: P26
■Keyboard scan output (column): KSO18
■SPI_2: SPI_CS (slave only)
■SPI_1: MISO (master only)
■Optical control output: QOC0
■Current: 16 mA
■Alternative function: P15
25 P27
PWM1 Input Floating VDDO
■GPIO: P27
■Keyboard scan output (column): KSO19
■SPI_2: MOSI (master and slave)
■Optical control output: QOC1
■Current: 16 mA
Table 12. WLCSP Package GPIO Pin Descriptionsa (Cont.)
Pin Number Pin Name Default
Direction After POR Power
Domain Alternate Function Description
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49 P28
PWM2 Input Floating VDDO
■GPIO: P28
■Optical control output: QOC2
■A/D converter input
■LED1
■Current: 16 mA
■Alternative function: P13
44 P29
PWM3 Input Floating VDDO
■GPIO: P29
■Optical control output: QOC3
■A/D converter input
■LED2
■Current: 16 mA
50 P30 Input Floating VDDO
■GPIO: P30
■A/D converter input
■Pairing button pin in default FW
■Peripheral UART: puart_rts
39 P31 Input Floating VDDO
■GPIO: P31
■A/D converter input
■EEPROM WP pin in default FW
■Peripheral UART: puart_tx
38 P32 Input Floating VDDO
■GPIO: P32
■A/D converter input
■Quadrature: QDX0
■SPI_2: SPI_CS (slave only)
■SPI_1: MISO (master only)
■Auxiliary clock output: ACLK0
■Peripheral UART: puart_tx
46 P33 Input Floating VDDO
■GPIO: P33
■A/D converter input
■Quadrature: QDX1
■SPI_2: MOSI (slave only)
■Auxiliary clock output: ACLK1
■Peripheral UART: puart_rx
34 P34 Input Floating VDDO
■GPIO: P34
■A/D converter input
■Quadrature: QDY0
■Peripheral UART: puart_rx
■External T/R switch control: tx_pd
29 P35 Input Floating VDDO
■GPIO: P35
■A/D converter input
■Quadrature: QDY1
■Peripheral UART: puart_cts
Table 12. WLCSP Package GPIO Pin Descriptionsa (Cont.)
Pin Number Pin Name Default
Direction After POR Power
Domain Alternate Function Description
Document Number: 002-14883 Rev. *I Page 31 of 47
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62 P36 Input Floating VDDO
■GPIO: P36
■A/D converter input
■Quadrature: QDZ0
■SPI_2: SPI_CLK (master and slave)
■Auxiliary Clock Output: ACLK0
■Battery detect pin in default FW
■External T/R switch control: ~tx_pd
64 P37 Input Floating VDDO
■GPIO: P37
■A/D converter input
■Quadrature: QDZ1
■SPI_2: MISO (slave only)
■Auxiliary clock output: ACLK1
■Alternative function: P38, P39
24 P38 Input Floating VDDO
■GPIO: P38
■A/D converter input
■SPI_2: MOSI (master and slave)
■IR_TX
■XTALO32K (64-BGA only)
■Alternate functions: P37, P39
51 P39 Input Floating VDDO
■GPIO: P39
■SPI_2: SPI_CS (slave only)
■SPI_1: MISO (master only)
■Infrared control: IR_RX
■External PA ramp control: PA_Ramp
■XTALI32K (64-BGA only)
■60Hz_main
■Alternative function: P37, P38
a. During a power-on reset, all inputs are disabled.
Table 12. WLCSP Package GPIO Pin Descriptionsa (Cont.)
Pin Number Pin Name Default
Direction After POR Power
Domain Alternate Function Description
Document Number: 002-14883 Rev. *I Page 32 of 47
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4. Specifications
4.1 Electrical Characteristics
Table 13 shows the maximum electrical rating for voltages referenced to VDD pin.
Table 14 shows the power supply characteristics for the range TJ = 0 to 125°C.
Table 15 shows the digital level characteristics for (VSS = 0V).
Table 13. Maximum Electrical Rating
Rating Symbol Value Unit
DC supply voltage for RF domain – 1.4 V
DC supply voltage for core domain – 1.4 V
DC supply voltage for VDDM domain (UART/I2C) – 3.8 V
DC supply voltage for VDDO domain – 3.8 V
DC supply voltage for VR3V – 3.8 V
DC supply voltage for VDDFE – 1.4 V
Voltage on input or output pin – VSS – 0.3 to VDD + 0.3 V
Operating ambient temperature range Topr –30 to +85 °C
Storage temperature range Tstg –40 to +125 °C
Table 14. Power Supply
Parameter Minimuma
a. Overall performance degrades beyond minimum and maximum supply voltages.
Typical MaximumaUnit
DC supply voltage for RF 1.14 1.2 1.26 V
DC supply voltage for Core 1.14 1.2 1.26 V
DC supply voltage for VDDM (UART/I2C) 1.62 – 3.63 V
DC supply voltage for VDDO 1.62 – 3.63 V
DC supply voltage for LDOIN 1.425 – 3.63 V
DC supply voltage for VDDFE 1.14 1.2b
b. 1.2V for Class 2 output with internal VREG.
1.26 V
Table 15. LDO Regulator Electrical Specifications
Parameter Conditions Min Typ Max Unit
Input voltage range – 1.425 – 3.63 V
Default output voltage – – 1.2 – V
Output voltage
Range 0.8 – 1.4 V
Step size – 40 or 80 – mV
Accuracy at any step –5 – +5 %
Load current – – – 30 mA
Line regulation Vin from 1.425 to 3.63V, Iload = 30 mA –0.2 – 0.2 %VO/V
Load regulation Iload from 1 µA to 30 mA, Vin = 3.3V, Bonding R
= 0.3
–0.10.2%V
O/mA
Quiescent current No load @Vin = 3.3V
*Current limit enabled
–6– µA
Power-down current Vin = 3.3V, worst@70°C – 5 200 nA
Document Number: 002-14883 Rev. *I Page 33 of 47
CYW20736
Table 16 shows the specifications for the ADC characteristics.
Table 17 shows the specifications for the digital voltage levels.
Table 16. ADC Specifications
Parameter Symbol Conditions Min Typ Max Unit
Number of Input channels – – – 9 – –
Channel switching rate fch – – – 133.33 kch/s
Input signal range Vinp –0–3.63V
Reference settling time – Changing refsel 7.5 – – s
Input resistance Rinp Effective, single ended – 500 – k
Input capacitance Cinp –––5pF
Conversion rate fC– 5.859 – 187 kHz
Conversion time TC– 5.35 – 170.7 s
Resolution R – – 16 – bits
Effective number of bits –In specified performance range – See Table 2
on page 8
––
Absolute voltage
measurement error
–Using on-chip ADC firmware driver –±2 –%
Current I Iavdd1p2 + Iavdd3p3 –– 1mA
Power P – – 1.5 – mW
Leakage current Ileakage T = 25°C – – 100 nA
Power-up time Tpowerup – – – 200 µs
Integral nonlinearity3INL In guaranteed performance range –1 – 1 LSBa
a. LSBs are expressed at the 10-bit level.
Differential nonlinearityaDNL In guaranteed performance range –1 – 1 LSBa
Table 17. Digital Levelsa
a. This table is also applicable to VDDMEM domain.
Characteristics Symbol Min Typ Max Unit
Input low voltage VIL ––0.4V
Input high voltage VIH 0.75 × VDDO – – V
Input low voltage (VDDO = 1.62V) VIL ––0.4V
Input high voltage (VDDO = 1.62V) VIH 1.2 – – V
Output low voltageb
b. At the specified drive current for the pad.
VOL ––0.4V
Output high voltagebVOH VDDO – 0.4 – – V
Input capacitance (VDDMEM domain) CIN –0.12– pF
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Table 18 shows the specifications for current consumption.
4.2 RF Specifications
Table 18. Current Consumption a
a. Currents measured between power terminals (Vdd) using 90% efficient DC-DC converter at 3V.
Operational Mode Conditions Typ Max Unit
Receive Receiver and baseband are both operating, 100% ON. 9.8 10.0 mA
Transmit Transmitter and baseband are both operating, 100% ON. 9.1 9.3 mA
Sleep Internal LPO is in use. 12.0 13.0 A
– 0.65 –
Table 19. Receiver RF Specifications
Parameter Mode and Conditions Min. Typ. Max. Unit
Receiver Sectiona
a. 30.8% PER.
Frequency range – 2402 – 2480 MHz
RX sensitivity (standard) 0.1% BER, 1 Mbps, dirty transmitter OFF – –93 – dBm
RX sensitivity (low current) – –90 – dBm
Input IP3 – –16 – – dBm
Maximum input – –10 – – dBm
Interference Performancea,b
b. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).
C/I cochannel 0.1%BER – – 21 dB
C/I 1 MHz adjacent channel 0.1%BER – – 15 dB
C/I 2 MHz adjacent channel 0.1%BER – – –17 dB
C/I 3 MHz adjacent channel 0.1%BER – – –27 dB
C/I image channel 0.1%BER – – –9.0 dB
C/I 1 MHz adjacent to image channel 0.1%BER – – –15 dB
Out-of-Band Blocking Performance (CW)a,b
30 MHz to 2000 MHz 0.1%BERc
c. Measurement resolution is 10 MHz.
– –30.0 – dBm
2003 MHz to 2399 MHz 0.1%BERd
d. Measurement resolution is 3 MHz.
––35–dBm
2484 MHz to 2997 MHz 0.1%BERd––35–dBm
3000 MHz to 12.75 GHz 0.1%BERe
e. Measurement resolution is 25 MHz.
– –30.0 – dBm
Spurious Emissions
30 MHz to 1 GHz – – – –57.0 dBm
1 GHz to 12.75 GHz – – – –55.0 dBm
Document Number: 002-14883 Rev. *I Page 35 of 47
CYW20736
Table 20. Transmitter RF Specifications
Parameter Minimum Typical Maximum Unit
Transmitter Section
Frequency range 2402 – 2480 MHz
Output power adjustment range –20 – 4 dBm
Default output power – 4.0 – dBm
Output power variation – 2.0 – dB
Adjacent Channel Power
|M – N| = 2 – – –20 dBm
|M – N| 3 – – –30 dBm
Out-of-Band Spurious Emission
30 MHz to 1 GHz – – –36.0 dBm
1 GHz to 12.75 GHz – – –30.0 dBm
1.8 GHz to 1.9 GHz – – –47.0 dBm
5.15 GHz to 5.3 GHz – – –47.0 dBm
LO Performance
Initial carrier frequency tolerance – – ±150 kHz
Frequency Drift
Frequency drift – – ±50 kHz
Drift rate – – 20 kHz/50 µs
Frequency Deviation
Average deviation in payload
(sequence used is 00001111)
225 – 275 kHz
Maximum deviation in payload
(sequence used is 10101010)
185 – – kHz
Channel spacing – 2 – MHz
Document Number: 002-14883 Rev. *I Page 36 of 47
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4.3 Timing and AC Characteristics
In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.
4.3.1 UART Timing
Figure 11. UART Timing
Table 21. UART Timing Specifications
Reference Characteristics Min Max Unit
1 Delay time, UART_CTS_N low to UART_TXD valid – 24 Baud out
cycles
2 Setup time, UART_CTS_N high before midpoint of stop bit – 10 ns
3 Delay time, midpoint of stop bit to UART_RTS_N high – 2 Baud out
cycles
Document Number: 002-14883 Rev. *I Page 37 of 47
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4.3.2 SPI Timing
The SPI interface supports clock speeds up to 12 MHz with VDDIO 2.2V. The supported clock speed is 6 MHz when 2.2V > VDDIO
1.62V.
Figure 12 and Figure 13 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively.
Figure 12. SPI Timing – Mode 0 and 2
Figure 13. SPI Timing – Mode 1 and 3
Table 22. SPI Interface Timing Specifications
Reference Characteristics Min Typ Max
1 Time from CSN asserted to first clock edge 1 SCK 100
2 Master setup time – ½ SCK –
3 Master hold time ½ SCK – –
4 Slave setup time – ½ SCK –
5 Slave hold time ½ SCK – –
6 Time from last clock edge to CSN deasserted 1 SCK 10 SCK 100
3
SPI_CSN
SPI_CLK
(Mode0)
SPI_MOSI ‐FirstBit
SPI_MISO NotDriven FirstBit
SecondBit
SecondBit
Lastbit
Lastbit
1
2
6
SPI_CLK
(Mode2)
NotDriven
‐
54
3
SPI_CSN
SPI_CLK
(Mode1)
SPI_MOSI ‐Invalidbit
SPI_MISO NotDriven Invalidbit
Firstbit
Firstbit
Lastbit
Lastbit
1
2
6
‐
NotDriven
SPI_CLK
(Mode3)
54
Document Number: 002-14883 Rev. *I Page 38 of 47
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4.3.3 BSC Interface Timing
Figure 14. BSC Interface Timing Diagram
Table 23. BSC Interface Timing Specifications
Reference Characteristics Min Max Unit
1 Clock frequency –
100
kHz
400
800
1000
2 START condition setup time 650 – ns
3 START condition hold time 280 – ns
4 Clock low time 650 – ns
5 Clock high time 280 – ns
6 Data input hold timea
a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START
or STOP conditions.
0 – ns
7 Data input setup time 100 – ns
8 STOP condition setup time 280 – ns
9 Output valid from clock – 400 ns
10 Bus free timeb
b. Time that the cbus must be free before a new transaction can start.
650 – ns
Document Number: 002-14883 Rev. *I Page 39 of 47
CYW20736
4.4 ESD Test Models
ESD can have serious detrimental effects on all semiconductor ICs and the system that contains them. Standards are developed to
enhance the quality and reliability of ICs by ensuring all devices employed have undergone proper ESD design and testing, thereby
minimizing the detrimental effects of ESD. Three major test methods are widely used in the industry today to describe uniform meth-
ods for assessing ESD immunity at Component level, Human Body Model (HBM), Machine Model (MM), and Charged Device Model
(CDM). The following standards were used to test this device:
4.4.1 Human-Body Model (HBM) – ANSI/ESDA/JEDEC JS-001-2012
The HBM has been developed to simulate the action of a human body discharging an accumulated static charge through a device to
ground, and employs a series RC network consisting of a 100 pF capacitor and a 1500 (Ohm) resistor. Both positive and negative
polarities are used for this test. Although, a 100 ms delay is allowable per specification, the minimum delay used for testing was set
to 300 ms between each pulse.
4.4.2 Machine Model (MM) – JEDEC JESD22-A115C
The MM has been developed to simulate the rapid discharge from a charged conductive object, such as a metallic tool or fixture. The
most common application would be rapid discharge from charged board assembly or the charged cables of automated testers. This
model consists of a 200 pF capacitor discharged directly into a component with no series resistor (0). One positive and one nega-
tive polarity pulses are applied. The minimum delay between pulses is 500 ms.
4.4.3 Charged-Device Model (CDM) - JEDEC JESD22-C101E
CDM simulates charging/discharging events that occur in production equipment and processes. The potential for a CDM ESD
events occurs when there is metal-to-metal contact in manufacturing. CDM addresses the possibility that a charge may reside on the
lead frame or package (e.g., from shipping) and discharge through a pin that subsequently is grounded, causing damage to sensitive
devices in the path. Discharge current is limited only by the parasitic impedance and capacitance of the device. CDM testing consists
of charging package to a specified voltage, then discharging the voltage through relevant package leads. One positive and one neg-
ative polarity pulse is applied. The minimum delay between pulses is 200 ms.
4.4.4 Results Summary
ESD Test Voltage Level Results:
■HBM +/– 2KV PASS
■CDM +/– 500V PASS
■MM +/– 150V PASS
Document Number: 002-14883 Rev. *I Page 40 of 47
CYW20736
5. Mechanical Information
5.1 QFN
Figure 15. 32-pin QFN
Document Number: 002-14883 Rev. *I Page 41 of 47
CYW20736
Figure 16. 80-pin WLCSP
Document Number: 002-14883 Rev. *I Page 42 of 47
CYW20736
Figure 17. WLCSP Keep-Out Areas for PCB Layout (Top View, Bumps Facing Down)
Document Number: 002-14883 Rev. *I Page 43 of 47
CYW20736
5.1.1 Tape Ree l and Packaging Specifications
The top left corner of the CYW20736 package is situated near the sprocket holes, as shown in Figure 18.
Figure 18. Pin 1 Orientation
5.2 WLCSP
Table 25 provides WLCSP package information.
Table 24. CYW20736 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications
Parameter Value
Quantity per reel 2500 pieces
Reel diameter 13 inches
Hub diameter 7 inches
Tape width 12 mm
Tape pitch 8 mm
Table 25. WLCSP Package Information
Parameter Value
Wafer process 65 nm
Chip size without seal ring and scribe line 2104 m × 2085 m
Chip size with seal ring and scribe line 2224 m × 2205 m (S+S 120 m)
Module die size 2184 m × 2165 m
UBM size 88 m
Bump height 90 m
Bump diameter 115 m
Bump pitch 200 m (minimum)
Pin 1: Top left corner of package toward sprocket holes
Document Number: 002-14883 Rev. *I Page 44 of 47
CYW20736
6. Ordering Information
Table 26. Ordering Information
Part Number Package Ambient Operating Temperature
CYW20736A1KML2G 32-pin QFN –30°C to +85°C
CYW20736A1KWBGT 80-pin WLCSP –30°C to +85°C
Document Number: 002-14883 Rev. *I Page 45 of 47
CYW20736
A. Appendix: Acronyms and Abbreviations
The following list of acronyms and abbreviations may appear in this document.
Term Description
ADC analog-to-digital converter
AFH adaptive frequency hopping
AHB advanced high-performance bus
APB advanced peripheral bus
APU audio processing unit
ARM7TDMI-S Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable
BSC Broadcom Serial Control
BTC Bluetooth controller
COEX coexistence
DFU device firmware update
DMA direct memory access
EBI external bus interface
HCI Host Control Interface
HV high voltage
IDC initial digital calibration
IF intermediate frequency
IRQ interrupt request
JTAG Joint Test Action Group
LCU link control unit
LDO low drop-out
LHL lean high land
LPO low power oscillator
LV LogicVision
MIA multiple interface agent
PCM pulse code modulation
PLL phase locked loop
PMU power management unit
POR power-on reset
PWM pulse width modulation
QD quadrature decoder
RAM random access memory
RF radio frequency
ROM read-only memory
RX/TX receive, transmit
SPI serial peripheral interface
SW software
UART universal asynchronous receiver/transmitter
UPI µ-processor interface
WD watchdog
Document Number: 002-14883 Rev. *I Page 46 of 47
CYW20736
Document History
Document Title: CYW20736 Single-Chip Bluetooth Low Energy-Only System-On-Chip with Support for Wireless Charging
Document Number: 002-14883
Revision ECN Orig. of
Change
Submission
Date Description of Change
** – – 01/03/2014 20736-DS100-R:
Initial release.
*A – – 07/11/2014
20736-DS101-R:
Updated:
■Ordering Information on page 44.
*B – – 08/15/2014
20736-DS102-R:
Updated:
■“List of Tables”.
*C – – 04/10/2015
20736-DS103-R:
Updated:
■Table 6 on page 11.
■Pin Information on page 15 with new WLCSP content.
■By moving GPIO Information to the following new GPIO Information on page 24.
*D – – 04/21/2015
20736-DS104-R:
Updated:
■Table 19 on page 34
*E – – 04/27/2015
20736-DS105-R:
Updated:
Features on page 1: added WLCSP package information.
Table 6 on page 11 and Table 6 on page 11: corrected an error in the unit of measure for
drive level and XTAL drive level, respectively.
Ordering Information on page 44.
Added:
Figure 16 on page 41.
Figure 17 on page 42 (Top View, Bumps Facing Down).
*F – – 02/16/2016
20736-DS106-R:
Added:
ESD Test Models on page 39.
*G 5446877 UTSV 09/30/2016 Updated to Cypress template.
*H 5709422 RUPA 04/24/2017 Updated Cypress logo.
Updated Copyright.
*I 5792439 SGUP 06/30/2017
Updated the Title.
Removed (aka Bluetooth Smart) from Page 1.
Replaced Alliance with Wireless Power to AirFuel in Application on Page 1.
Removed Wireless Charging Section from the datasheet.
Document Number: 002-14883 Rev. *I Revised June 30, 2017 Page 47 of 47
© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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CYW20736
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