SPI Interface, Quad SPST Switch, Low QINJ,
Low CON, ±15 V/+12 V, Mux Configurable
Data Sheet ADGS1212
Rev. 0 Document Feedback
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FEATURES
SPI interface with error detection
Includes CRC, invalid read/write address, and SCLK count
error detection
Supports burst mode and daisy-chain mode
Industry-standard SPI Mode 0 and SPI Mode 3 compatible
Guaranteed break-before-make switching allowing external
wiring of switches to deliver multiplexer configurations
VSS to VDD analog signal range
Fully specified at ±15 V and +12 V supply
±4.5 V to ±16.5 V dual-supply operation
5 V to 16.5 V single-supply operation
Ultralow capacitance and leakage allows fast settling time
1 pF typical off switch drain capacitance at 25°C, ±15 V
2.6 pF typical on switch capacitance at 25°C, ±15 V
<1 pC typical charge injection at 25°C
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
APPLICATIONS
Automated test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communications systems
GENERAL DESCRIPTION
The ADGS1212 contains four independent single-pole/single-
throw (SPST) switches. A serial peripheral interface (SPI)
controls the switches. The SPI interface has robust error detection
features such as cyclic redundancy check (CRC) error detection,
invalid read/write address detection, and SCLK count error
detection.
It is possible to daisy-chain multiple ADGS1212 devices together.
Daisy-chain mode enables the configuration of multiple devices
with minimal digital lines. The ADGS1212 can also operate in
burst mode to decrease the time between SPI commands.
iCMOS construction ensures ultralow power dissipation, making
the device ideal for portable and battery-powered instruments.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
supplies.
FUNCTIONAL BLOCK DIAGRAM
S4
S3
S2
S1
D4
SDO
SCLK SDI CS RESET/V
L
D3
D2
D1
ADGS1212
SPI
INTERFACE
15936-001
Figure 1.
In the off condition, signal levels up to the supplies are blocked.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the device suitable for video signal switching.
Multifunction pin names may be referenced by their relevant
function only.
PRODUCT HIGHLIGHTS
1. SPI interface removes the need for parallel conversion,
logic traces, and reduces the general-purpose input/output
(GPIO) channel count.
2. Daisy-chain mode removes additional logic traces when
multiple devices are used.
3. CRC error detection, invalid read/write address detection,
and SCLK count error detection ensure a robust digital
interface.
4. CRC and error detection capabilities allow the ADGS1212
to be used in safety critical systems.
5. Guaranteed break-before-make switching allows the the
ADGS1212 to be used in multiplexer configurations with
external wiring.
6. The ADGS1212 1.8 V logic compatibility with 2.7 V ≤ VL ≤
3.3 V
7. Ultralow capacitance.
8. <1 pC charge injection.
ADGS1212 Data Sheet
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
12 V Single Supply ........................................................................ 5
Continuous Current per Channel, Sx or Dx ............................. 6
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Test Circuits ..................................................................................... 14
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Address Mode ............................................................................. 17
Error Detection Features ........................................................... 17
Clearing the Error Flags Register ............................................. 18
Burst Mode .................................................................................. 18
Software Reset ............................................................................. 18
Daisy-Chain Mode ..................................................................... 18
Power-On Reset .......................................................................... 19
Applications Information .............................................................. 20
Break-Before-Make Switching .................................................. 20
Power Supply Rails ..................................................................... 20
Power Supply Recommendations ............................................. 20
Register Summary .......................................................................... 21
Register Details ............................................................................... 22
Switch Data Register .................................................................. 22
Error Configuration Register .................................................... 22
Error Flags Register .................................................................... 23
Burst Enable Register ................................................................. 23
Software Reset Register ............................................................. 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
9/2017—Revision 0: Initial Version
Data Sheet ADGS1212
Rev. 0 | Page 3 of 24
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 1.
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 120 Ω typ VS = ±10 V, IS = −10 mA,
see Figure 24
190 230 260 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match Between
Channels, ∆RON
2.5 Ω typ VS = ±10 V, IS = −10 mA
6 10 11 Ω max
On-Resistance Flatness, R
FL AT (ON)
20
Ω typ
V
S
= −5 V/0 V/+5 V, I
S
= −10 mA
57 72 79 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (OFF) ±0.02 nA typ VS = ±10 V, VD =
10 V,
see Figure 27
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (OFF) ±0.02 nA typ VS = ±10 V, VD =
10 V,
see Figure 27
±0.1 ±0.6 ±1 nA max
Channel On Leakage, I
D
(ON)
, I
S
(ON)
±0.02
nA typ
V
S
= V
D
= ±10 V, see Figure 23
±0.1 ±0.6 ±1 nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL 0.4 V max ISINK = 5 mA
0.2 V max ISINK = 1 mA
High or Low Output Current, IOL or IOH 0.001 µA typ Output voltage (VOUT) =
ground voltage (V
GND
) or V
L
±0.1 µA max
Digital Output Capacitance, COUT 4 pF typ
DIGITAL INPUTS
Input Voltage
High, VINH 2 V min 3.3 V < VL ≤ 5.5 V
1.35 V min 2.7 V ≤ VL ≤ 3.3 V
Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V
0.8 V max 2.7 V ≤ VL ≤ 3.3 V
Low or High Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VL
±0.1 µA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS1
On Time, tON 375 ns typ Load resistance (RL) = 300 Ω,
load capacitance (CL) = 35 pF
450 450 450 ns max VS = 10 V, see Figure 32
Off Time, tOFF 125 ns typ RL = 300 Ω, CL = 35 pF
160 180 205 ns max VS = 10 V, see Figure 32
Break-Before-Make Time Delay, t
D
205
ns typ
R
L
= 300 Ω, C
L
= 35 pF
150 ns min VS1 = VS2 = 10 V, see Figure 31
Charge Injection, QINJ −0.9 pC typ VS = 0 V, source resistance (RS) = 0 Ω,
CL = 1 nF, see Figure 33
Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 26
ADGS1212 Data Sheet
Rev. 0 | Page 4 of 24
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
Channel to Channel Crosstalk −110 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 25
Total Harmonic Distortion + Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to
20 kHz, see Figure 28
−3 dB Bandwidth 1000 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 29
Insertion Loss −6.5 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 29
Off Switch Source Capacitance, CS (OFF) 0.9 pF typ VS = 0 V, f = 1 MHz
1.1 pF max VS = 0 V, f = 1 MHz
Off Switch Drain Capacitance, CD (OFF) 1 pF typ VS = 0 V, f = 1 MHz
1.2 pF max VS = 0 V, f = 1 MHz
On Switch Capacitances, CD (ON), CS (ON) 2.6 pF typ VS = 0 V, f = 1 MHz
3 pF max VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
Positive Power Supply Current, IDD 0.001 μA typ All switches open
1.0 μA max All switches open
250 μA typ All switches closed, VL = 5.5 V
420 μA max All switches closed, VL = 5.5 V
260 μA typ All switches closed, VL = 2.7 V
440 μA max All switches closed, VL = 2.7 V
Load Current, IL
Inactive 6.3 μA typ Digital inputs = 0 V or VL
8.0 μA max Digital inputs = 0 V or VL
SCLK = 1 MHz 14 μA typ CS and SDI = 0 V or VL, VL = 5 V
7 μA typ
CS and SDI = 0 V or VL, VL = 3 V
SCLK = 50 MHz 390 μA typ CS = VL and SDI = 0 V or VL, VL = 5 V
210 μA typ
CS = VL and SDI = 0 V or VL, VL = 3 V
SDI = 1 MHz 15 μA typ CS and SCLK = 0 V or VL, VL = 5 V
7.5 μA typ
CS and SCLK = 0 V or VL, VL = 3 V
SDI = 25 MHz 230 μA typ CS and SCLK = 0 V or VL, VL = 5 V
120 μA typ
CS and SCLK = 0 V or VL, VL = 3 V
Active at 50 MHz SCLK 1.8 mA typ Digital inputs toggle between
0 V and VL, VL = 5.5 V
2.1 mA max
0.7 mA typ
Digital inputs toggle between
0 V and VL, VL = 2.7 V
1.0 mA max
Negative Power Supply Current, ISS 0.001 μA typ Digital inputs = 0 V or VL
1.0 μA max
VDD/VSS ±4.5/±16.5 V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
Data Sheet ADGS1212
Rev. 0 | Page 5 of 24
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 2.
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance, RON 300 Ω typ VS = 0 V to 10 V, IS = −1 mA,
see Figure 24
475 567 625 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match Between
Channels, ∆RON
Ω typ
V
S
= 0 V to 10 V, I
S
= −1 mA
12 26 27 Ω max
On-Resistance Flatness, RFLAT (O N) 60 Ω typ VS = 3 V/6 V/9 V, IS = −1 mA
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (OFF) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V,
see Figure 27
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, I
D
(OFF)
nA typ
V
S
= 1 V/10 V, V
D
= 10 V/1 V,
see Figure 27
±0.1 ±0.6 ±1 nA max
Channel On Leakage, ID (ON), IS (ON) ±0.02 nA typ VS = VD = 1 V/10 V, see Figure 23
±0.1 ±0.6 ±1 nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL 0.4 V max ISINK = 5 mA
0.2 V max ISINK = 1 mA
High or Low Output Current, IOL or IOH 0.001 µA typ Output voltage (VOUT) =
ground voltage (VGND) or VL
±0.1 µA max
Digital Output Capacitance, COUT 4 pF typ
DIGITAL INPUTS
Input Voltage
High, VINH 2 V min 3.3 V < VL ≤ 5.5 V
1.35
V min
2.7 V ≤ V
L
≤ 3.3 V
Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V
0.8 V max 2.7 V ≤ VL ≤ 3.3 V
Low or High Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VL
±0.1 µA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS1
On Time, tON 395 ns typ Load resistance (RL) = 300 Ω,
load capacitance (CL) = 35 pF
485
490
ns max
V
S
= 8 V, see Figure 32
Off Time, tOFF 135 ns typ RL = 300 Ω, CL = 35 pF
170 195 225 ns max VS = 8 V, see Figure 32
Break-Before-Make Time Delay, tD 230 ns typ RL = 300 Ω, CL = 35 pF
170 ns min VS1 = VS2 = 8 V, see Figure 31
Charge Injection, QINJ −0.5 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF,
see Figure 33
Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF,
f = 1 MHz, see Figure 26
Channel to Channel Crosstalk −110 dB typ RL = 50 Ω, CL = 5 pF,
f = 1 MHz, see Figure 25
−3 dB Bandwidth 900 MHz typ RL = 50 Ω, CL = 5 pF,
see Figure 29
ADGS1212 Data Sheet
Rev. 0 | Page 6 of 24
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
Insertion Loss −8.9 dB typ RL = 50 Ω, CL = 5 pF,
f = 1 MHz, see Figure 29
Off Switch Source Capacitance, CS (OFF) 1.2 pF typ VS = 6 V, f = 1 MHz
1.4 pF max VS = 6 V, f = 1 MHz
Off Switch Drain Capacitance, CD (OFF) 1.3 pF typ VS = 6 V, f = 1 MHz
1.5 pF max VS = 6 V, f = 1 MHz
On Switch Capacitances, CD (ON), CS (ON) 3.2 pF typ VS = 6 V, f = 1 MHz
3.9 pF max VS = 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 13.2 V
Positive Power Supply Current, IDD 0.001 μA typ All switches open
1.0 μA max All switches open
220 μA typ All switches closed, VL = 5.5 V
380 μA max All switches closed, VL = 5.5 V
270 μA typ All switches closed, VL = 2.7 V
440 μA max All switches closed, VL = 2.7 V
Load Current, IL
Inactive 6.3 μA typ Digital inputs = 0 V or VL
8.0 μA max Digital inputs = 0 V or VL
SCLK = 1 MHz 14 μA typ CS and SDI = 0 V or VL, VL = 5 V
7 μA typ
CS and SDI = 0 V or VL, VL = 3 V
SCLK = 50 MHz 390 μA typ CS = VL and SDI = 0 V or VL,
VL = 5 V
210 μA typ
CS = VL and SDI = 0 V or VL,
VL = 3 V
SDI = 1 MHz 15 μA typ CS and SCLK = 0 V or VL, VL = 5 V
7.5 μA typ
CS and SCLK = 0 V or VL, VL = 3 V
SDI = 25 MHz 230 μA typ CS and SCLK = 0 V or VL, VL = 5 V
120 μA typ
CS and SCLK = 0 V or VL, VL = 3 V
Active at 50 MHz SCLK 1.8 mA typ Digital inputs toggle between
0 V and VL, VL = 5.5 V
2.1 mA max
0.7 mA typ
Digital inputs toggle between
0 V and VL, VL = 2.7 V
1.0 mA max
VDD 5/16.5 V min/V max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 3. Four Channels On
Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx1
VDD = 15 V, VSS = −15 V (θJA = 67°C/W) 20 8 2.5 mA maximum
VDD = 12 V, VSS = 0 V (θJA = 67°C/W) 14 6.67 2.4 mA maximum
1 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
Table 4. One Channel On
Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx1
VDD = 15 V, VSS = −15 V (θJA = 67°C/W) 35 9.6 2.5 mA maximum
VDD = 12 V, VSS = 0 V (θJA = 67°C/W) 24.7 8.77 2.5 mA maximum
1 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
Data Sheet ADGS1212
Rev. 0 | Page 7 of 24
TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization
but not production tested.
Table 5.
Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTRISTICS
t1 20 ns min SCLK period
t2 8 ns min SCLK high pulse width
t3 8 ns min SCLK low pulse width
t4 10 ns min CS falling edge to SCLK active edge
t5 6 ns min Data setup time
t6 8 ns min Data hold time
t7 10 ns min SCLK active edge to CS rising edge
t8 20 ns max
CS falling edge to SDO data available
t91 20 ns max SCLK falling edge to SDO data available
t10 20 ns max
CS rising edge to SDO returns to high impedance
t11 20 ns min
CS high time between SPI commands
t12 8 ns min
CS falling edge to SCLK becomes stable
t13 8 ns min
CS rising edge to SCLK becomes stable
1 Measured with the 1 kΩ pull-up resistor to VL and a 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Timing Diagrams
t
1
t
2
t
3
t
4
t
5
t
8
t
9
t
10
t
6
t
7
R/W
CS
SCLK
SDI
SDO
A6 A5 D2 D1 D0
0 0 1 D2 D1 D0
15936-002
Figure 2. Address Mode Timing Diagram
ADGS1212 Data Sheet
Rev. 0 | Page 8 of 24
t
1
t
2
t
3
t
4
t
5
t
8
t
9
t
10
t
6
t
7
CS
SCLK
SDI
SDO
INPUT BYTE FOR DEVICE N INPUT BYTE FOR DEVICE N + 1
ZERO BYTE INPUT BYTE FOR DEVICE N
D7 D6 D0 D7 D6 D1 D0
0 0 0 D7D6 D1D0
15936-003
Figure 3. Daisy-Chain Timing Diagram
t
13
t
11
t
12
CS
SCLK
15936-004
Figure 4. SCLK/CS Timing Diagram
Data Sheet ADGS1212
Rev. 0 | Page 9 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
VL to GND −0.3 V to +6 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs
first
Digital Inputs1 −0.3 V to +6 V
Peak Current, Sx or Dx Pins2 38 mA (pulsed at 1 ms,
10% duty cycle
maximum)
Continuous Current, Sx or Dx Pins2, 3 Data + 15%
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
1 Overvoltages at the digital Sx and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
3 See Table 3 and Table 4.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 7. Thermal Resistance
Package Type
θ
JA
θ
JC
Ψ
JT
Unit
CP-24-151 67 33.7 11.1 °C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with four thermal vias. See JEDEC JESD-51.
ESD CAUTION
ADGS1212 Data Sheet
Rev. 0 | Page 10 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
1
3
4
5
6
18
17
16
15
14
13
GND
VSS
S1
D1
GND
NIC
VDD
S2
D2
NIC
NIC
8
9
10
11
7
D4
NIC
NIC
D3
12S3
S4
20
19
21
SDO
NIC
CS
22 SCLK
23 SDI
24 NIC
ADGS1212
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE EXPOSED PAD BE SOLDERED TO THE
SUBSTRATE, VSS.
2. NIC = NOT INTERNALLY CONNECTED.
RESET/VL
15936-005
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1, 9, 10, 16,
18, 19, 24
NIC Not Internally Connected.
2, 6 GND Ground (0 V) Reference.
3
D1
Drain Terminal 1. This pin can be an input or output.
4 S1 Source Terminal 1. This pin can be an input or output.
5 VSS Most Negative Power Supply Potential. In single-supply applications, tie VSS to GND.
7 S4 Source Terminal 4. This pin can be an input or output.
8 D4 Drain Terminal 4. This pin can be an input or output.
11 D3 Drain Terminal 3. This pin can be an input or output.
12 S3 Source Terminal 3. This pin can be an input or output.
13 VDD Most Positive Power Supply Potential.
14 S2 Source Terminal 2. This pin can be an input or output.
15 D2 Drain Terminal 2. This pin can be an input or output.
17 RESET/VL RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V
supply. Pull the RESET pin low to complete a hardware reset. After a reset, all switches open, and the
appropriate registers are set to their default values.
20 SDO Serial Data Output. This pin can be used for daisy chaining a number of devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge
of SCLK. Pull this open-drain output to VL with an external resistor.
21 CS Active Low Control Input. CS is the frame synchronization signal for the input data.
22 SCLK Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to
50 MHz.
23 SDI Serial Data Input. Data is captured on the positive edge of the serial clock input.
EPAD Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.
Data Sheet ADGS1212
Rev. 0 | Page 11 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
V
DD
= +15V
V
SS
= –15V
V
DD
= +16.5V
V
SS
= –16.5V
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
200
180
160
140
120
100
60
80
0
20
40
–18 –15 –12 –9 –6 –3 3 9 150 6 12 18
V
DD
= +13.5V
V
SS
= –13.5V
T
A
= 25°C
15936-006
Figure 6. On Resistance vs. Source or Drain Voltage (VS or VD) for
Various Dual Supplies
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
450
400
350
300
250
150
200
0
50
100
–5 –4 –3 –2 –1 2 40 1 3 5
VDD = +5.5V
VSS = –5.5V
TA = 25°C
15936-007
Figure 7. On Resistance vs. Source or Drain Voltage (VS or VD) for
±5.5 V Dual Supply
V
DD
= 13.2V
V
SS
= 0V
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
450
400
350
300
250
150
200
0
50
100
02 4 6 8 10 12
V
DD
= 12V
V
SS
= 0V
V
DD
= 10.8V
V
SS
= 0V
T
A
= 25°C
15936-008
Figure 8. On Resistance vs. Source or Drain Voltage (VS or VD) for
Various Single Supplies
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
250
150
200
0
50
100
–15 –10 –5 0510 15
V
DD
= +15V
V
SS
= –15V
T
A
= +125°C
T
A
= +25°C
T
A
= +85°C
T
A
= –40°C
15936-009
Figure 9. On Resistance vs. Source or Drain Voltage (VS or VD) for
Various Ambient Temperatures (TA), ±15 V Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
600
400
500
300
200
0
100
0 2 4 6 8 10 12
V
DD
= 12V
V
SS
= 0V
T
A
= +125°C
T
A
= +25°C
T
A
= +85°C
T
A
= –40°C
15936-010
Figure 10. On Resistance vs. Source or Drain Voltage (VS or VD) for
Ambient Temperatures (TA), 12 V Single Supply
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)
0.20
0.15
0.10
0.05
0
–0.10
–0.05
–0.15
–0.20
20040 60 80 100 120
IS(OFF)
ID(OFF)
ID, IS(ON)
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
15936-011
Figure 11. Leakage Current vs. Temperature, ±15 V Dual Supply
ADGS1212 Data Sheet
Rev. 0 | Page 12 of 24
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)
0.30
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
20040 60 80 100 120
I
S(OFF)
I
D(OFF)
I
D
, I
S(ON)
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1V/10V
15936-012
Figure 12. Leakage Current vs. Temperature, 12 V Single Supply
6
–8
–6
–4
–2
0
2
4
–15 –10 –5 0 5 10 15
CHARGE INJECTION (pC)
VS (V)
15936-013
TA = 25°C
VDD = +5V, VSS = –5V
VDD = +15V, VSS= –15V
VDD = +12V, VSS= 0V
Figure 13. Charge Injection vs. Source Voltage (VS)
450
0
50
100
150
200
250
300
350
400
–40 –20 020 40 60 80 100 120
t
ON
/
t
OFF
(ns)
TEMPERATURE (°C)
15936-014
15V DS,
t
ON
15V DS,
t
OFF
12V SS,
t
ON
12V SS,
t
OFF
Figure 14. tON/tOFF vs. Temperature for
Single Supply (SS) and Dual Supply (DS)
FREQUENCY (Hz)
OFF ISOLATION (dB)
0
–20
–40
–60
–80
–100
–140
–120
100 10k
1k 100k 1M 10M 100M 10G1G
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
15936-015
Figure 15. Off Isolation vs. Frequency, ±15 V Dual Supply
FREQUENCY (Hz)
CROSSTALK (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–140
–110
–120
–130
10k 100k 1M 10M 100M
VDD = +15V
VSS = –15V
TA = 25°C
15936-016
Figure 16. Crosstalk vs. Frequency, ±15 V Dual Supply
FREQUENCY (Hz)
INSERTION LOSS (dB)
0
–10
–5
–15
–25
–20
–30
10k 100k 1M 10M 1G100M 10G
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
15936-017
Figure 17. Insertion Loss vs. Frequency, ±15 V Dual Supply
Data Sheet ADGS1212
Rev. 0 | Page 13 of 24
FREQUENCY (Hz)
THD + N (%)
10
1
0.1
0.01
10 100 1k 10k 100k
R
L
= 10kΩ
T
A
= 25°C
V
DD
= +5V, V
SS
= –5V, V
S
= +3.5Vrms
V
DD
= +15V, V
SS
= –15V, V
S
= +5Vrms
15936-018
Figure 18. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
0245 8
V
OUT
(mV)
TIME (µs)
15936-100
SCLK = 2.5MHz
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
SCLK IDLE
Figure 19. Digital Feedthrough
70
60
50
40
30
20
10
0
5.55.04.54.03.53.02.7
IDD (µA)
VL (V)
15936-101
12V
15V
Figure 20. Positive Power Supply Current (IDD) vs. VL
450
0
050
I
L
(µA)
SCLK FREQUENCY (MHz)
10 20 30 40
50
100
150
200
250
300
350
400
T
A
= 25°C
V
L
= 5V
V
L
= 3V
15936-021
Figure 21. Load Current (IL) vs. SCLK Frequency when CS High
FREQUENCY (Hz)
AC PSRR (dB)
10
–10
–30
–50
–70
–90
–130
–110
100 10k1k 100k 1M 10M
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
15936-102
100nF DECOUPLING
CAPACITOR
10µF + 100nF DECOUPLIG
CAPACITOR
NO DECOUPLING
Figure 22. AC Power Supply Rejection Ratio (PSRR) vs. Frequency
ADGS1212 Data Sheet
Rev. 0 | Page 14 of 24
TEST CIRCUITS
V
D
Sx Dx
V
S
A
I
D
(ON)
15936-022
Figure 23. On Leakage
Sx Dx
V
S
V1
I
DS
R
ON
= V
1
/I
DS
15936-023
Figure 24. On Resistance
CHANNEL TO CHANNEL CROSSTALK = 20 log V
OUT
GND
S1
D2
D1
S2
V
OUT
NETWORK
ANALYZER
R
L
50
R
L
50
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
NC
15936-024
Figure 25. Channel to Channel Crosstalk
OFF ISOLATION = 20 log VOUT
GND
Sx
Dx
VOUT
NETWORK
ANALYZER
RL
50
50
50
VS
VS
VDD VSS
0.1µF
V
DD
0.1µF
VSS
15936-025
Figure 26. Off Isolation
Sx Dx
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
15936-026
Figure 27. Off Leakage
GND
Sx
Dx
V
OUT
AUDIO PRECISION
R
L
1k
R
S
V
S
V p-p
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
15936-027
Figure 28. THD + Noise
INSERTION LOSS = 20 log V
OUT
WITH SWITCH
GND
Sx
Dx
V
OUT
NETWORK
ANALYZER
R
L
50
50
V
S
V
S
WITHOUT SWITCH
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
15936-028
Figure 29. −3 dB Bandwidth
AC PSRR = 20 log V
OUT
GND D1S1
V
OUT
NETWORK
ANALYZER
R
L
50
V
S
V
DD
V
SS
V
SS
NC
INTERNAL
BIAS
V
S
R
L
50
NOTES
1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED
FROM THE AC PSRR MEASUREMENT.
15936-029
Figure 30. AC PSRR
Data Sheet ADGS1212
Rev. 0 | Page 15 of 24
V
DD
V
SS
V
DD
V
SS
0.1µF 0.1µF
GND
INPUT LOGIC
R
L1
100Ω
C
L1
35pF
VS1 S1 D1 V
OUT1
RL2
100Ω
CL2
35pF
VS2 S2 D2 VOUT2
VOUT1
VOUT2
SCLK 50%
80% 80%
80% 80%
50%
0V
0V
0V
t
D
t
D
15936-030
Figure 31. Break-Before-Make Time Delay, tD
V
DD
V
SS
V
DD
V
SS
0.1µF 0.1µF
GND
R
L
300Ω
C
L
35pF
V
S
INPUT LOGIC
Sx Dx V
OUT
SCLK
V
OUT
50% 50%
90%
10%
tON tOFF
15936-031
Figure 32. Switching Times, tON and tOFF
V
DD
V
SS
V
DD
V
SS
GND
INPUT LOGIC
C
L
1nF
Sx Dx V
OUT
R
S
V
S
SCLK
3V
V
OUT
ΔV
OUT
Q
INJ
= C
L
× ΔV
OUT
SWITCH OFF SWITCH ON
15936-032
Figure 33. Charge Injection, QINJ
ADGS1212 Data Sheet
Rev. 0 | Page 16 of 24
TERMINOLOGY
IDD
IDD is the positive supply current.
ISS
ISS is the negative supply current.
VD, VS
VD and VS are the analog voltage on Terminal Dx and Terminal
Sx, respectively.
RON
RON is the ohmic resistance between Terminal Dx and Terminal
Sx.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT (ON)
RFLAT (ON) is defined as the difference between the maximum and
minimum value of on resistance measured over the specified
analog signal range.
IS (OFF)
IS (OFF) is the source leakage current with the switch off.
ID (OFF)
ID (OFF) is the drain leakage current with the switch off.
ID (ON), IS (ON)
ID (ON) and IS (ON) are the channel leakage currents with the
switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH are the low and high input currents of the digital
inputs, respectively.
CD (OFF)
CD (OFF) is the off switch drain capacitance, which is measured
with reference to ground.
CS (OFF)
CS (OFF) is the off switch source capacitance, which is measured
with reference to ground.
CD (ON), CS (ON)
CD (ON) and CS (ON) are the on switch capacitances, which are
measured with reference to ground.
CIN
CIN is the digital input capacitance.
tON
tON is the delay between applying the digital control input and
the output switching on.
tOFF
tOFF is the delay between applying the digital control input and
the output switching off.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. AC PSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the switch.
The dc voltage on the device is modulated by a sine wave of
0.62 V p-p.
Data Sheet ADGS1212
Rev. 0 | Page 17 of 24
THEORY OF OPERATION
The ADGS1212 is a set of serially controlled, quad SPST switches
with error detection features. SPI Mode 0 and SPI Mode 3 can
be used with the device, and it operates with SCLK frequencies
up to 50 MHz. The default mode for the ADGS1212 is address
mode in which the registers of the device are accessed by a
16-bit SPI command that is bounded by CS. The SPI command
becomes 24 bit if the user enables CRC error detection. Other
error detection features include SCLK count error and invalid
read/write error. If any of these SPI interface errors occur, they
are detectable by reading the error flags register. The ADGS1212
can also operate in two other modes: burst mode and daisy-
chain mode.
The interface pins of the ADGS1212 are CS, SCLK, SDI, and
SDO. Hold CS low when using the SPI interface. Data is
captured on SDI on the rising edge of SCLK, and data is
propagated out on SDO on the falling edge of SCLK. SDO has an
open-drain output; thus, connect a pull-up to this output. When
not pulled low by the ADGS1212, SDO is in a high impedance
state.
ADDRESS MODE
Address mode is the default mode for the ADGS1212 on power
up. A single SPI frame in address mode is bounded by a CS
falling edge and the succeeding CS rising edge. It is comprised
of 16 SCLK cycles. The timing diagram for address mode is
shown in Figure 34. The first SDI bit indicates if the SPI
command is a read or write command. When the first bit is set
to 0, a write command is issued, and if the first bit is set to 1, a
read command is issued. The next seven bits determine the target
register address. The remaining eight bits provide the data to the
addressed register. The last eight bits are ignored during a read
command, because during these clock cycles, SDO propagates out
the data contained in the addressed register.
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates out
on SDO from the 9th to the 16th SCLK falling edge during SPI
reads. A register write occurs on the 16th SCLK rising edge
during SPI writes.
During any SPI command, SDO sends out eight alignment bits
on the first eight SCLK falling edges. The alignment bits observed
at SDO are 0x25 by default.
ERROR DETECTION FEATURES
Protocol and communication errors on the SPI interface are
detectable. There are three detectable errors: incorrect SCLK count
error detection, invalid read and write address error detection,
and CRC error detection. Each of these errors has a
corresponding enable bit in the error configuration register. In
addition, there is an error flag bit for each of these errors in the
error flags register.
Cyclic Redundancy Check (CRC) Error Detection
The CRC error detection feature extends a valid SPI frame by
8 SCLK cycles. These eight extra cycles are needed to send the CRC
byte for that SPI frame. The CRC byte is calculated by the SPI block
using the 16-bit payload: the R/W A bit, Register Address Bits[6:0],
and Register Data Bits[7:0]. The CRC polynomial used in the
SPI block is x8 + x2 + x1 + 1 with a seed value of 0. For a timing
diagram with CRC enabled, see Figure 35. Register writes occur
at the 24th SCLK rising edge with CRC error checking enabled.
During a SPI write, the microcontroller/central processing unit
(CPU) provides the CRC byte through SDI. The SPI block checks
the CRC byte just before the 24th SCLK rising edge. On this same
edge, the register write is prevented if an incorrect CRC byte is
received by the SPI interface. The CRC error flag is asserted in
the error flags register in the case of the incorrect CRC byte
being detected.
During a SPI read, the CRC byte is provided to the microcontroller
through SDO.
The CRC error detection feature is disabled by default and can
be configured by the user through the error configuration register.
0 0 1 0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0SDO
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
12345678910 11 12 13 14 15 16
SDI
SCLK
CS
15936-033
Figure 34. Address Mode Timing Diagram
0 0 1 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0SDO
R/W A6 A0 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0
1 2 8 9 10 16 17 18 19 20 21 22 23 24
SDI
SCLK
CS
15936-034
Figure 35. Timing Diagram with CRC Enabled
ADGS1212 Data Sheet
Rev. 0 | Page 18 of 24
SCLK Count Error Detection
SCLK count error detection allows the user to detect if an
incorrect number of SCLK cycles are sent by the microcontroller/
CPU. When in address mode, with CRC disabled, 16 SCLK
cycles are expected. If 16 SCLK cycles are not detected, the
SCLK count error flag asserts in the error flags register. When
less than 16 SCLK cycles are received by the device, a write to
the register map never occurs. When the ADGS1212 receives
more than 16 SCLK cycles, a write to the memory map still
occurs at the 16th SCLK rising edge, and the flag asserts in the
error flags register. With CRC enabled, the expected number of
SCLK cycles becomes 24. SCLK count error detection is enabled
by default and can be configured by the user through the error
configuration register.
Invalid Read/Write Address Error
An invalid read/write address error detects when a nonexistent
register address is a target for a read or write. In addition, this
error asserts when a write to a read only register is attempted.
The invalid read/write address error flag asserts in the error
flags register when an invalid read/write address error occurs.
The invalid read/write address error is detected on the ninth
SCLK rising edge, which means a write to the register never
occurs when an invalid address is targeted. Invalid read/write
address error detection is enabled by default and can be
disabled by the user through the error configuration register.
CLEARING THE ERROR FLAGS REGISTER
To clear the error flags register, write the special 16-bit SPI
frame, 0x6CA9, to the device. This SPI command does not
trigger the invalid R/W address error. When CRC is enabled,
the user must also send the correct CRC byte for a successful
error clear command. At the 16th or 24th SCLK rising edge, the
error flags register resets to zero.
BURST MODE
The SPI interface can accept consecutive SPI commands
without the need to deassert the CS line, which is called burst
mode. Burst mode is enabled through the burst enable register.
This mode uses the same 16-bit command to communicate
with the device. In addition, the response of the device at SDO
is still aligned with the corresponding SPI command. Figure 36
shows an example of SDI and SDO during burst mode.
The invalid read/write address and CRC error checking
functions operate similarly during burst mode as they do
during address mode. However, SCLK count error detection
operates in a slightly different manner. The total number of
SCLK cycles within a given CS frame are counted, and if the
total is not a multiple of 16, or a multiple of 24 when CRC is
enabled, the SCLK count error flag asserts.
SDO
COMMAND0[15:0]
RESPONSE0[15:0]
COMMAND1[15:0]
RESPONSE1[15:0]
COMMAND2[15:0]
RESPONSE2[15:0]
COMMAND3[15:0]
RESPONSE3[15:0]
SDI
CS
15936-035
Figure 36. Burst Mode Frame
SOFTWARE RESET
When in address mode, the user can initiate a software reset.
To do so, write two consecutive SPI commands, 0xA3 followed
by 0x05, targeting Register 0x0B. After a software reset, all
register values are set to default.
DAISY-CHAIN MODE
The connection of several ADGS1212 devices in a daisy-chain
configuration is possible, and Figure 37 shows this setup. All
devices share the same CS and SCLK line, whereas the SDO line
of a device forms a connection to the SDI line of the next device,
creating a shift register. In daisy-chain mode, SDO is an eight
cycle delayed version of SDI. When in daisy-chain mode, all
commands target the switch data register. Therefore, it is not
possible to make configuration changes while in daisy-chain mode.
S4
SDI
SCLK
CS
VL
S3
S2
S1
D4
SDO
VL
D3
D2
D1
ADGS1212
DEVICE 1
S4
S3
S2
S1
D4
SDO
D3
D2
D1
ADGS1212
DEVICE 2
SPI
INTERFACE
SPI
INTERFACE
15936-036
Figure 37. Two ADGS1212 Devices Connected in a Daisy-Chain Configuration
Data Sheet ADGS1212
Rev. 0 | Page 19 of 24
The ADGS1212 can only enter daisy-chain mode when in
address mode by sending the 16-bit SPI command, 0x2500
(see Figure 38). When the ADGS1212 receives this command,
the SDO of the device sends out the same command because
the alignment bits at SDO are 0x25, which allows multiple
daisy-connected devices to enter daisy-chain mode in a single
SPI frame. A hardware reset is required to exit daisy-chain mode.
For the timing diagram of a typical daisy-chain SPI frame, see
Figure 39. When CS goes high, Device 1 writes Command 0,
Bits[7:0] to its switch data register, Device 2 writes Command 1,
Bits[7:0] to its switches, and so on. The SPI block uses the last
eight bits it received through SDI to update the switches. After
entering daisy-chain mode, the first eight bits sent out by SDO
on each device in the chain are 0x00. When CS goes high, the
internal shift register value does not reset back to zero.
An SCLK rising edge reads in data on SDI while data is
propagated out by SDO on an SCLK falling edge. The expected
number of SCLK cycles must be a multiple of eight before CS
goes high. When this is not the case, the SPI interface sends the
last eight bits received to the switch data register.
POWER-ON RESET
The digital section of the ADGS1212 goes through an initialization
phase during VL power up. This initialization also occurs after a
hardware or software reset. After VL power-up or a reset, ensure
that a minimum of 120 µs from the time of power-up or reset
before any SPI command is issued. Ensure that VL does not
drop out during the 120 µs initialization phase because this may
result in incorrect operation of the ADGS1212.
0010010100000000SDO
0010010100000000
12345678910 11 12 13 14 15 16
SDI
SCLK
CS
15936-037
Figure 38. SPI Command to Enter Daisy-Chain Mode
SDO
COMMAND3[7:0]
8’h00
COMMAND2[7:0]
COMMAND3[7:0]
COMMAND1[7:0]
COMMAND2[7:0]
COMMAND0[7:0]
COMMAND1[7:0]
SDI
SDO3
8’h00
8’h00
8’h00
8’h00
COMMAND3[7:0]
8’h00
COMMAND2[7:0]
COMMAND3[7:0]
SDO2
DEVICE 2
DEVICE 1
DEVICE 4
DEVICE 3
CS
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
15936-038
Figure 39. Example of a SPI Frame Where Four ADGS1212 Devices Connect in Daisy-Chain Mode
ADGS1212 Data Sheet
Rev. 0 | Page 20 of 24
APPLICATIONS INFORMATION
BREAK-BEFORE-MAKE SWITCHING
The ADGS1212 exhibits break-before-make switching. This
feature allows the use of the device in multiplexer applications.
Using the device like a multiplexor can be accomplished by
externally hardwiring the device into the desired mux
configuration, as shown in Figure 40.
4 × SPST
S1
S4
S2
S3
Dx
SCLK SDI CS RESET/V
L
SPI
INTERFACE
15936-039
4:1 MUX
Figure 40. A SPI Controlled Switch Configured into a 4:1 Mux
POWER SUPPLY RAILS
To guarantee correct operation of the ADGS1212, 0.1 µF
decoupling capacitors are required.
The ADGS1212 can operate with bipolar supplies between
±4.5 V and ±16.5 V. The supplies on VDD and VSS do not have to
be symmetrical; however, the VDD to VSS range must not exceed
33 V. T h e ADGS1212 can also operate with single supplies
between 5 V and 16.5 V with VSS connected to GND.
The voltage range that can be supplied to VL is from 2.7 V to 5.5 V.
The device is fully specified at ±15 V and +12 V analog supply
voltage ranges.
POWER SUPPLY RECOMMENDATIONS
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
An example of a bipolar power solution is shown in Figure 41.
The ADP5070 (dual switching regulator) generates a positive and
negative supply rail for the ADGS1212, amplifier, and/or a
precision converter in a typical signal chain. Also shown in
Figure 41 are two optional low dropout (LDO) regulators
(ADP7118 and ADP7182 positive and negative LDOs
respectively) that can be used to reduce the output ripple of the
ADP5070 in ultralow noise sensitive applications.
The ADM7160 can be used to generate the VL voltage that is
required to power digital circuitry within the ADGS1212.
ADM7160
LDO
+3.3V
ADP7118
LDO
+15V
ADP7182
LDO
–15V
+16.5V
–16.5V
ADP5070
+5V
INPUT
15936-040
Figure 41. Bipolar Power Solution
Table 9. Recommended Power Management Devices
Product
Description
ADP5070 1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
ADM7160 5.5 V, 200 mA, ultralow noise, linear regulator
ADP7118 20 V, 200 mA, low noise, CMOS LDO linear regulator
ADP7182 −28 V, −200 mA, low noise, LDO linear regulator
Data Sheet ADGS1212
Rev. 0 | Page 21 of 24
REGISTER SUMMARY
Table 10. Register Summary
Register (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W
0x01
SW_DATA
Reserved
SW4_EN
SW3_EN
SW2_EN
SW1_EN
0x00 R/W
0x02 ERR_CONFIG Reserved RW_ERR_EN SCLK_ERR_EN CRC_ERR_EN 0x06 R/W
0x03 ERR_FLAGS Reserved RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG 0x00 R
0x05 BURST_EN Reserved BURST_MODE_EN 0x00 R/W
0x0B SOFT_RESETB SOFT_RESETB 0x00 R/W
ADGS1212 Data Sheet
Rev. 0 | Page 22 of 24
REGISTER DETAILS
SWITCH DATA REGISTER
Address: 0x01, Reset: 0x00, Name: SW_DATA
The switch data register controls the status of the four switches of the ADGS1212.
Table 11. Bit Descriptions for SW_DATA
Bits Bit Name Settings Description Default Access
[7:4] Reserved These bits are reserved; set these bits to 0. 0x0 R
3 SW4_EN Enable bit for SW4. 0x0 R/W
0 SW4 open.
1 SW4 closed.
2 SW3_EN Enable bit for SW3. 0x0 R/W
0 SW3 open.
1 SW3 closed.
1 SW2_EN Enable bit for SW2. 0x0 R/W
0 SW2 open.
1 SW2 closed.
0 SW1_EN Enable bit for SW1. 0x0 R/W
0 SW1 open.
1
SW1 closed.
ERROR CONFIGURATION REGISTER
Address: 0x02, Reset: 0x06, Name: ERR_CONFIG
The error configuration register allows the user to enable and disable the relevant error features as required.
Table 12. Bit Descriptions for ERR_CONFIG
Bits Bit Name Settings Description Default Access
[7:3] Reserved These bits are reserved; set these bits to 0. 0x0 R
2 RW_ERR_EN Enable bit for detecting invalid read/write address. 0x1 R/W
0 Disabled.
1
Enabled.
1 SCLK_ERR_EN Enable bit for detecting the correct number of SCLK cycles in a SPI frame. When
CRC is disabled and burst mode is disabled, 16 SCLK cycles are expected. When
CRC is enabled and burst mode is disabled, 24 SCLK cycles are expected. A multiple
of 16 SCLK cycles are expected when CRC is disabled and burst mode is enabled.
A multiple of 24 SCLK cycles are expected when CRC is enabled and burst mode is
enabled.
0x1 R/W
0 Disabled.
1 Enabled.
0 CRC_ERR_EN Enable bit for CRC error detection. SPI frames are 24 bits wide when enabled. 0x0 R/W
0 Disabled.
1 Enabled.
Data Sheet ADGS1212
Rev. 0 | Page 23 of 24
ERROR FLAGS REGISTER
Address: 0x03, Reset: 0x00, Name: ERR_FLAGS
The error flags register allows the user to determine if an error occurred. To clear the error flags register, write the special 16-bit SPI
command, 0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user
must include the correct CRC byte during the SPI write for the clear error flags register command to succeed.
Table 13. Bit Descriptions for ERR_FLAGS
Bits Bit Name Settings Description Default Access
[7:3] Reserved These bits are reserved and are set to 0. 0x0 R
2 RW_ERR_FLAG Error flag for invalid read/write address. The error flag asserts during a SPI read if
the target address does not exist. The error flag also asserts when the target
address of a SPI write does not exist or is read only.
0x0 R
0 No error.
1 Error.
1 SCLK_ERR_FLAG Error flag for the detection of the correct number of SCLK cycles in a SPI frame. 0x0 R
0 No error.
1 Error.
0 CRC_ERR_FLAG Error flag that determines if a CRC error occurred during a register write. 0x0 R
0 No error.
1
Error.
BURST ENABLE REGISTER
Address: 0x05, Reset: 0x00, Name: BURST_EN
The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI
commands without deasserting CS.
Table 14. Bit Descriptions for BURST_EN
Bits Bit Name Settings Description Default Access
[7:1] Reserved These bits are reserved; set these bits to 0. 0x0 R
0 BURST_MODE_EN Burst mode enable bit. 0x0 R/W
0 Disabled.
1 Enabled.
SOFTWARE RESET REGISTER
Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB
Use the software reset register to perform a software reset. Consecutively, write 0xA3 followed by 0x05 to this register, and the registers of
the device reset to their default state.
Table 15. Bit Descriptions for SOFT_RESETB
Bits Bit Name Settings Description Default Access
[7:0] SOFT_RESETB To perform a software reset, consecutively write 0xA3 followed by 0x05 to this register. 0x0 R
ADGS1212 Data Sheet
Rev. 0 | Page 24 of 24
OUTLINE DIMENSIONS
0.80
0.75
0.70
PKG-004273/5069
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-8
BOTTOM VIEW
TOP VIEW
4.10
4.00 SQ
3.90
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
712
13
18
19
6
03-02-2017-A
0.30
0.25
0.18
0.20 MIN
2.70
2.60 SQ
2.50
EXPOSED
PAD
SEATING
PLANE
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 42. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADGS1212BCPZ −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-15
ADGS1212BCPZ-RL7 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-15
EVAL-ADGS1212SDZ Evaluation Board
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D15936-0-9/17(0)