Nonreflective, Silicon SP4T Switch,
0.1 GHz to 6.0 GHz
Data Sheet HMC7992
Rev. 0 Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Nonreflective, 50 Ω design
High isolation: 45 dB typical at 2 GHz
Low insertion loss: 0.6 dB at 2 GHz
High power handling
33 dBm through path
27 dBm terminated path
High linearity
1 dB compression (P1dB): 35 dBm typical
Input third-order intercept (IIP3): 58 dBm typical
ESD rating: 2 kV human body model (HBM), Class 2
Single positive supply: 3.3 V to 5.0 V
Standard TTL-, CMOS-, and 1.8 V-compatible control
16-lead, 3 mm × 3 mm LFCSP package (9 mm2)
Pin compatible with the HMC241ALP3E
APPLICATIONS
Cellular/4G infrastructure
Wireless infrastructure
Automotive telematics
Mobile radios
Test equipment
FUNCTIONAL BLOCK DIAGRAM
GND RFC GND GND
GND V
DD
BA
RF1
GND
GND
RF2
RF4
GND
GND
RF3
16 15 14 13
11
10
2
3
5678
2:4 T T L DECODER
PACKAGE
BASE
GND
12
9
1
4
13714-001
HMC7992
Figure 1.
GENERAL DESCRIPTION
The HMC7992 is a general-purpose, nonreflective, 0.1 GHz to
6.0 GHz, silicon, single-pole, four-throw (SP4T) switch in a
leadless, surface-mount package. The switch is ideal for cellular
infrastructure applications, offers high isolation of 45 dB typical
at 2 GHz, and a low insertion loss of 0.6 dB at 2 GHz. It offers
excellent power handling capability up to 6.0 GHz, with input
power of 1 dB compression point (P1dB) of 35 dBm at 5 V
operation. The HMC7992 has good low frequency input power
handling below 0.1 GHz and can operate well down to 10 kHz,
with a typical 1 dB compression of 21 dBm (see Figure 21) and
an IIP3 of 37 dBm (see Figure 22) at 1 MHz.
The on-chip circuitry allows the HMC7992 to operate at a single,
positive supply voltage range from 3.3 V to 5 V, and as well as a
single, positive control voltage from 0 V to 1.8 V/3.3 V/5.0 V. A
2:4 decoder integrated in the switch requires only two controlled
input signals, with a positive control voltage range from 0 V to
1.8 V/3.3 V/5.0 V, to select one of the four radio frequency (RF)
paths.
HMC7992 Data Sheet
Rev. 0 | Page 2 of 13
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Digital Control Voltages .............................................................. 4
Bias and Supply Current .............................................................. 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Interface Schematics..................................................................... 6
Typical Performance Characteristics ..............................................7
Insertion Loss, Isolation, and Return Loss ................................7
Input Compression and Input Third-Order Intercept
(0.1 GHz to 6.0 GHz) ....................................................................9
Input Compression and Input Third-Order Intercept (10 kHz
to 1 GHz) ..................................................................................... 10
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
1/16—Revision 0: Initial Version
Data Sheet HMC7992
Rev. 0 | Page 3 of 13
SPECIFICATIONS
VDD = 3.3 V to 5.0 V, VCTL = 0 V/VDD, TA = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INSERTION LOSS 0.1 GHz to 2.0 GHz 0.6 0.9 dB
2.0 GHz to 4.0 GHz 0.7 1.1 dB
4.0 GHz to 6.0 GHz 1.0 1.5 dB
ISOLATION
RFC to RF1to RF4 (Worst Case) 0.1 GHz to 2.0 GHz 40 45 dB
2.0 GHz to 4.0 GHz 32 37 dB
4.0 GHz to 6.0 GHz 25 30 dB
RETURN LOSS
On State 0.1 GHz to 2.0 GHz 25 dB
2.0 GHz to 4.0 GHz 24 dB
4.0 GHz to 6.0 GHz 17 dB
Off State 0.1 GHz to 2.0 GHz 7 dB
0.4 GHz to 1.0 GHz
15
dB
1.0 GHz to 6.0 GHz 20 dB
SWITCHING SPEED
Rise Time and Fall Time tRISE, tFAL L 30 ns
On Time and Off Time tON, tOFF 10%/90% RFOUT 150 ns
RADIO FREQUENCY (RF) SETTLING TIME 50% VCTL to 0.1 dB margin of final RFOUT 320 ns
INPUT POWER 0.1 GHz to 6.0 GHz
1 dB Compression P1dB VDD = 5 V 35 dB
V
DD
= 3.3 V
33
dB
0.1 dB Compression P0.1dB VDD = 5 V 33 dB
VDD = 3.3 V 31 dB
INPUT THIRD-ORDER INTERCEPT
IIP3
0.1 GHz to 6.0 GHz, two-tone input power =
14 dBm/tone
VDD = 5 V 58 dBm
VDD = 3.3 V 56 dBm
RECOMMENDED OPERATING CONDITIONS
Bias Voltage Range VDD 3.0 5.4 V
Control Voltage Range VCTL 0 VDD V
Case Temperature Range TCASE −40 +105 °C
Maximum RF Input Power
0.1 GHz to 6.0 GHz
Through Path VDD/VCTL = 5 V, TCASE = 105°C 30 dBm
VDD/VCTL = 5 V, TCASE = −40°C to +85°C 33 dBm
VDD/VCTL = 3.3 V, TCASE = 105°C 29 dBm
VDD/VCTL = 3.3 V, TCASE = −40°C to +85°C 32 dBm
Terminated Path VDD/VCTL = 3.3 V to 5 V, TCASE = 105°C 21 dBm
VDD/VCTL = 3.3 V to 5 V, TCASE = 85°C 24 dBm
VDD/VCTL = 3.3 V to 5 V, TCASE = 25°C 27 dBm
VDD/VCTL = 3.3 V to 5 V, TCASE = −40°C 27 dBm
Hot Switching VDD/VCTL = 3.3 V to 5 V, TCASE = 105°C 24 dBm
VDD/VCTL = 3.3 V to 5 V, TCASE = −40°C to +85°C 27 dBm
HMC7992 Data Sheet
Rev. 0 | Page 4 of 13
DIGITAL CONTROL VOLTAGES
TCASE = −40°C to +105°C, unless otherwise specified.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT CONTROL VOLTAGE <1 µA typical
Low Voltage VIL 0 8.5 V VDD = 3.3 V (±5% VDD)
0 1.2 V VDD = 5 V (±5% VDD)
High Voltage VIH 1.15 3.3 V VDD = 3.3 V (±5% VDD)
1.55 5.0 V VDD = 5 V (±5% VDD)
BIAS AND SUPPLY CURRENT
Table 3.
Parameter Symbol Min Typ Max Unit
SUPPLY CURRENT IDD
VDD = 3.3 V 0.16 0.20 mA
VDD = 5 V 0.18 0.23 mA
Data Sheet HMC7992
Rev. 0 | Page 5 of 13
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Bias Voltage Range (VDD) −0.3 V to +5.5 V
Control Voltage Range (A, B) −0.5 V to VDD + (+0.5 V)
RF Input Power,1 3.3 V to 5 V (see
Figure 2 and Figure 3)
Through Path 34 dBm
Terminated Path 28 dBm
Hot Switching
Channel Temperature
Storage Temperature Range −65°C to +150°C
Maximum Peak Reflow Temperature
(MSL3)
260°C
Thermal Resistance (Channel to
Package Bottom)
Through Path 115°C
Terminated Path 200°C
ESD Sensitivity
Human Body Model (HBM) 2 kV (Class 2)
Charged Device Model (CDM) 1.25 kV
1 For recommended operating conditions, see Table 1.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
36
34
32
30
28
26
240.1 1
FREQUENCY (GHz)
10
MAXI MUM RF INPUT PO WER ( dBm)
THROUGH AMR
TERMINATED AMR
13714-002
Figure 2. Maximum RF Input Power vs. Frequency
35
29
POWER DERATING (dBm)
31
33
27
25
23
21
190.1 1
FREQUENCY (GHz)
10
THRO UGH (AT 85°C)
THRO UGH (AT 105°C)
TERMINATED (AT 85°C)
TERMINATED (AT 105°C)
13714-003
Figure 3. Power Derating vs. Frequency
ESD CAUTION
HMC7992 Data Sheet
Rev. 0 | Page 6 of 13
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
NOTES
1. THE EXPOSED PAD M US T CONNE CT
TO RF/DC G ROUND.
RF4
GND
GND
RF3
RF1
GND
GND
RFC
GND
GND
GND
RF2
GND
VDD
B
A
HMC7992
TOP VIEW
(Not to Scal e)
13714-004
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 RF4 RF Port 4. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
2, 3, 5, 10,
11, 13, 14, 16
GND Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB)
RF/dc ground. See Figure 5 for the GND interface schematic.
4 RF3 RF Port 3. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
6 VDD Supply Voltage.
7 B Logic Control Input B. See Figure 6 for the control input interface schematic. See Table 6 and the
recommended input control voltages range in Table 2.
8 A Logic Control Input A. See Figure 6 for the control input interface schematic. See Table 6 and the
recommended input control voltages range in Table 2.
9 RF2 RF Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
12 RF1 RF Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
15 RFC RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
EPAD Exposed Pad. The exposed pad must connect to RF/dc ground.
Table 6. Truth Table
Control Input
Signal Path State
A B RFC to
Low Low RF1
High Low RF2
Low High RF3
High
High
RF4
INTERFACE SCHEMATICS
GND
13714-005
Figure 5. GND Interface Schematic
VDD
A/B
13714-006
Figure 6. Logic Control (A/B) Interface Schematic
Data Sheet HMC7992
Rev. 0 | Page 7 of 13
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, ISOLATION, AND RETURN LOSS
–2.5
–2.0
–1.5
–1.0
–0.5
0
01234
FREQUENCY (GHz)
56 7 8
INSERTION LOSS (dB)
+105°C
+85°C
+25°C
–40°C
13714-007
Figure 7. Insertion Loss vs. Frequency for Various Temperatures, VDD = 5 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 1 23456
ISOLATION (dB)
FREQUENCY (GHz)
RFC TO RF2
RFC TO RF3
RFC TO RF4
13714-008
Figure 8. Isolation vs. Frequency, VDD = 3.3 V to 5 V, RFC to RF1 = On
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0123456
ISOLATION (dB)
FREQUENCY (GHz)
RFC TO RF1
RFC TO RF2
RFC TO RF4
13714-009
Figure 9. Isolation vs. Frequency, VDD = 3.3 V to 5 V, RFC to RF3 = On
–2.5
–2.0
–1.5
–1.0
–0.5
0
01234 5 678
INSERTION LOSS (dB)
FREQUENCY (GHz)
13714-010
+105°C
+85°C
+25°C
–40°C
Figure 10. Insertion Loss vs. Frequency for Various Temperatures,
VDD = 3.3 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
012 3 4 5 6
ISOLATION (dB)
FREQUENCY (GHz)
RFC TO RF1
RFC TO RF3
RFC TO RF4
13714-111
Figure 11. Isolation vs. Frequency, VDD = 3.3 V to 5 V, RFC to RF2 = On
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0123456
ISOLATION (dB)
FREQUENCY (GHz)
RFC TO RF1
RFC TO RF2
RFC TO RF3
13714-112
Figure 12. Isolation vs. Frequency, VDD = 3.3 V to 5 V, RFC to RF4 = On
HMC7992 Data Sheet
Rev. 0 | Page 8 of 13
–40
–35
–30
–25
–20
–15
–10
–5
0
0123456
RET URN LOS S ( dB)
FREQUENCY (GHz)
13714-113
Figure 13. Return Loss for RFC vs. Frequency, VDD = 3.3 V to 5 V
–40
–35
–30
–25
–20
–15
–10
–5
0
0123 4 5 6
RET URN LOS S ( dB)
FREQUENCY (GHz)
RF1, RF2, RF 3, AND RF 4 = ON
RF1, RF2, RF 3, AND RF 4 = OF F
13714-114
Figure 14. Return Loss for RF1, RF2, RF3, and RF4 vs. Frequency,
VDD = 3.3 V to 5 V
Data Sheet HMC7992
Rev. 0 | Page 9 of 13
INPUT COMPRESSION AND INPUT THIRD-ORDER INTERCEPT (0.1 GHz TO 6.0 GHz)
26
28
30
32
34
36
38
40
0123456
INPUT COMPRESSION (dBm)
F RE QUE NCY (GHz )
+105°C
+85°C
+25°C
–40°C
13714-011
Figure 15. Input Compression 1 dB Point vs.
Frequency for Various Temperatures, VDD = 5 V
26
28
30
32
34
36
38
40
0123456
INP UT CO M P RESSIO N (dBm)
FREQ UENC Y (G Hz)
+105°C
+85°C
+25°C
–40°C
13714-012
Figure 16. Input Compression 0.1 dB Point vs.
Frequency for Various Temperatures, VDD = 5 V
45
50
55
60
65
0123456
IIP3 (dBm)
FREQUENCY (GHz)
+105°C
+85°C
+25°C
–40°C
13714-013
Figure 17. Input Third-Order Intercept (IIP3) Point vs.
Frequency for Various Temperatures, VDD = 5 V
26
28
30
32
34
36
38
40
0123456
INPUT COMPRESSION (dBm)
FREQUENCY (GHz)
+105°C
+85°C
+25°C
–40°C
13714-014
Figure 18. Input Compression 1 dB Point vs.
Frequency for Various Temperatures, VDD = 3.3 V
26
28
30
32
34
36
38
40
0123456
INPUT COMPRESSION (dBm)
F RE QUE NCY (GHz )
+105°C
+85°C
+25°C
–40°C
13714-015
Figure 19. Input Compression 0.1 dB Point vs.
Frequency for Various Temperatures, VDD = 3.3 V
45
50
55
60
65
0123456
IIP3 (dBm)
F RE QUE NCY (GHz )
+105°C
+85°C
+25°C
–40°C
13714-016
Figure 20. Input Third-Order Intercept (IIP3) Point vs.
Frequency for Various Temperatures, VDD = 3.3 V
HMC7992 Data Sheet
Rev. 0 | Page 10 of 13
INPUT COMPRESSION AND INPUT THIRD-ORDER INTERCEPT (10 kHz TO 1 GHz)
INPUT CO M P RE S S ION ( dBm)
FREQUENCY IN LOG SCALE (MHz)
0.01 0.1 110 10 100
40
35
30
25
20
15
10
P1dB P0.1dB
13714-020
Figure 21. Input Compression (P1dB and P0.1dB Points) vs. Frequency in
Log Scale, VDD = 5 V at 25°C
0.01 0.1 110
FREQUENCY IN LOG SCALE (MHz)
10 100
65
60
55
50
45
40
35
30
25
II P 3 ( dBm)
13714-021
Figure 22. Input Third-Order Intercept (IIP3) vs. Frequency in Log Scale,
VDD = 5 V at 25°C
Data Sheet HMC7992
Rev. 0 | Page 11 of 13
THEORY OF OPERATION
The HMC7992 requires a single positive supply voltage applied
to the VDD pin. A bypassing capacitor is recommended on the
supply line to minimize RF coupling.
The HMC7992 integrates with an internal 2:4 decoder; the four
RF paths are selected via the two digital control voltages applied
to the A and B control inputs. A small value bypassing capacitor
is recommended on these digital signal lines to improve the RF
signal isolation.
The HMC7992 is internally matched to 50 Ω at the RF common
port (RFC) and the RF ports (RF1, RF2, RF3, and RF4); therefore,
no external matching components are required. The RF pins are
dc-coupled and dc blocking capacitors are required on the RF
paths. The design is bidirectional; the RF input signals can apply
at the RFC port or the RF1 to RF4 ports. The inputs and outputs
are interchangeable.
Depending on the logic level applied to the control input pins,
A and B, one RF output port (for example, RF1) is set to on
mode, by which an insertion loss path is provided from the
input to the output. The other RF output ports (for example,
RF2, RF3, and RF4) are then set to off mode, by which the
outputs are isolated from the input. When the RF output ports
(RF1, RF2, RF3, and RF4) are in isolation mode, they are
internally terminated to 50 Ω, and thereby can absorb the
applied RF signal.
The ideal power-up sequence is as follows:
1. Power up GND.
2. Power up VDD.
3. Power up the digital control inputs. The relative order of
the logic control inputs is not important. Powering the
logic control inputs before the VDD supply can inadvertently
forward bias and damage the internal ESD protection
structures.
4. Apply the RF input.
Table 7. Switch Mode Operation
Digital Control Inputs Signal Mode
A B RFC to RFx
Low Low RF Port 1 is in on mode, providing a low insertion loss path from the RFC port to the RF1 port. The remaining RF
ports (RF2, RF3, and RF4) are in off mode; they are isolated from the RFC port and internally terminated to a 50 Ω load.
High Low RF Port 2 is in on mode, providing a low insertion loss path from the RFC port to the RF2 port. The remaining RF
ports (RF1, RF3, and RF4) are in off mode; they are isolated from the RFC port and internally terminated to a 50 Ω load.
Low High RF Port 3 is in on mode, providing a low insertion loss path from the RFC port to the RF3 port. The remaining RF
ports (RF1, RF2, and RF4) are in off mode; they are isolated from the RFC port and internally terminated to a 50 Ω load.
High High RF Port 4 is in on mode, providing a low insertion loss path from the RFC port to the RF4 port. The remaining RF
ports (RF1, RF2, and RF3) are in off mode; they are isolated from the RFC port and internally terminated to a 50 Ω load.
HMC7992 Data Sheet
Rev. 0 | Page 12 of 13
APPLICATIONS INFORMATION
Generate the evaluation PCB with proper RF circuit design
techniques. Signal lines at the RF port must have a 50 Ω
impedance, and the package ground leads and backside ground
slug must connect directly to the ground plane, as shown in
Figure 23. The evaluation board shown in Figure 23 is available
from Analog Devices, Inc., upon request.
Table 8. Bill of Materials for the EV1HMC7992LP3D1
Evaluation Board
Reference Designator Description
J1 to J5 PCB mount SMA connectors
C1 to C5 100 pF capacitors, 0402 package
C8 to C10 100 pF capacitors, 0402 package
C13 0.1 μF capacitor, 0402 package
R1 to R2 0 Ω resistors, 0402 package
U1 HMC7992LP3DE SP4T switch
PCB2 600-01284-00 evaluation PCB
1 Reference this evaluation board number when ordering the complete
evaluation board.
2 Circuit board material: Roger 4350 or Arlon 25FR.
13714-017
Figure 23. EV1HMC7992LP3D Evaluation Board
Data Sheet HMC7992
Rev. 0 | Page 13 of 13
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.25
0.20
1.92
1.70 SQ
1.48
1
0.50
BSC
BO T TOM VIEWTOP VIEW
16
5
8
9
1213
4
EXPOSED
PAD
PIN 1
INDICATOR
*0.35
0.30
0.25
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 RE F
0.20 MI N
COPLANARITY
0.08
PIN 1
INDICATOR
0.95
0.85
0.75
FO R PROPE R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFIGURAT ION AND
FUNCT IO N DE SCRIPTIONS
SECT IO N OF THI S DATA SHE ET.
01-08-2015-A
PKG-000000
*COMPLIANT WI TH JEDEC ST ANDARDS M O-220-VEE D- 4
WITH THE E X CEPTION OF P ACKAGE E DGE T O L E AD E DGE.
Figure 24. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.85 mm Package Height
(CP-16-38)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description
Package
Option Branding3
HMC7992LP3DE –40°C to +105°C MSL3 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-38
XXXX
7992
HMC7992LP3DETR –40°C to +105°C MSL3 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-38
XXXX
7992
EV1HMC7992LP3D Evaluation Board
1 The HMC7992LP3DE and HMC7992LP3DETR are RoHS Compliant Parts.
2 See the Absolute Maximum Ratings section for MSL rating information.
3 4-digit lot number XXXX.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13714-0-1/16(0)