SSM3J115TU - Toshiba - Datasheet.Directory

SSM3J115TU

2007-11-01

TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type

SSM3J115TU

High-Speed Switching Applications

Power Management Switch Applications

• 1.5 V drive

• Low ON-resistance: Ron = 353 mΩ (max) (@VGS = −1.5 V)

on = 193 mΩ (max) (@VGS = −1.8 V)

Ron = 125 mΩ (max) (@VGS = −2.5 V)

Ron = 98 mΩ (max) (@VGS = −4.0 V)

Absolute Maximum Ratings (Ta = 25°C)

Characteristic Symbol Rating Unit

Drain-source voltage VDS −20 V

Gate-source voltage VGSS ± 8 V

DC ID −2.2

Drain current Pulse IDP −4.4 A

PD (Note 1) 800

Drain power dissipation PD (Note 2) 500 mW

Channel temperature Tch 150 °C

Storage temperature range Tstg −55~150 °C

Note: Using continuously under heavy loads (e.g. the application of

high temperature/current/voltage and the significant change in

temperature, etc.) may cause this product to decrease in the

reliability significantly even if the operating conditions (i.e.

operating temperature/current/voltage, etc.) are within the

absolute maximum ratings.

Please design the appropriate reliability upon reviewing the

Toshiba Semiconductor Reliability Handbook (“Handling

Precautions”/“Derating Concept and Methods”) and individual

reliability data (i.e. reliability test report and estimated failure rate, etc).

Note 1: Mounted on a ceramic board.

(25.4 mm × 25.4 mm × 0.8 mm, Cu Pad: 645 mm2)

Note 2: Mounted on an FR4 board.

(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2)

Electrical Characteristics (Ta = 25°C)

Characteristic Symbol Test Conditions Min Typ. Max Unit

V (BR) DSS I

D = −1 mA, VGS = 0 −20 ⎯ ⎯

Drain-source breakdown voltage

V (BR) DSX I

D = −1 mA, VGS = +8 V −12 ⎯ ⎯

Drain cutoff current IDSS V

DS = −20 V, VGS = 0 ⎯ ⎯ −10 μA

Gate leakage current IGSS V

GS = ±8 V, VDS = 0 ⎯ ⎯ ±1 μA

Gate threshold voltage Vth V

DS = −3 V, ID = −1 mA −0.3 ⎯ −1.0 V

Forward transfer admittance ⏐Yfs⏐ V

DS = −3 V, ID = − 0.9 A (Note 3) 2.7 5.4 ⎯ S

ID = −1.0 A, VGS = −4.0 V (Note 3) ⎯ 77 98

ID = −1.0 A, VGS = −2.5 V (Note 3) ⎯ 84 125

Drain-source ON-resistance

ID = −1.0 A, VGS = −1.8 V (Note 3) ⎯ 111 193

mΩ

RDS (ON)

ID = −0.1 A, VGS = −1.5 V (Note 3) ⎯ 126 353

Input capacitance Ciss V

DS = −10 V, VGS = 0, f = 1 MHz ⎯ 568 ⎯ pF

Output capacitance Coss V

DS = −10 V, VGS = 0, f = 1 MHz ⎯ 75 ⎯ pF

Reverse transfer capacitance Crss V

DS = −10 V, VGS = 0, f = 1 MHz ⎯ 67 ⎯ pF

Turn-on time ton ⎯ 29 ⎯

Switching time

Turn-off time toff

VDD = −10 V, ID = −0.9 A,

VGS = 0~−2.5 V, RG = 4.7 Ω ⎯ 39 ⎯

Drain-source forward voltage VDSF I

D = 2.2 A, VGS = 0 V (Note 3)

⎯ 0.8 1.2 V

Unit: mm

JEDEC ―

JEITA ―

TOSHIBA 2-2U1A

Weight: 6.6 mg (typ.)

1: Gate

2: Source

3: Drain

UFM

-0.05

1.7±0.1

2.1±0.1

0.65±0.05

2.0±0.1

0.7±0.05

+0.1

0.3

0.166±0.05

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SSM3J115TU

2007-11-01

Note 3: Pulse test

Switching Time Test Circuit

Marking Equivalent Circuit

(top view)

Precaution

Vth can be expressed as the voltage between gate and source when the low operating current value is ID = −1 mA for

this product. For normal switching operation, VGS (on) requires a higher voltage than Vth, and VGS (off) requires a lower

voltage than Vth.

(The relationship can be established as follows: VGS (off) < Vth < VGS (on).)

Take this into consideration when using the device.

Handling Precaution

When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is

protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that

come into direct contact with devices should be made of antistatic materials.

VDD = -10 V

RG = 4.7 Ω

D.U.

VIN: tr, tf < 5 ns

Common Source

Ta = 25°C

−2.5V

10 μs VDD

OUT

ton

90%

10%

−2.5 V

0 V

90%

10%

toff

tr tf

VDS

(

)

VDD

(b) VIN

(a) Test circuit

JJ8

1 2

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SSM3J115TU

2007-11-01

Drain –source voltage VDS (V)

ID – VDS

Drain current ID (A)

-4

-1.5

0 -0.5 -1 -1.5 -2

-0.5

-3

-3.5

Gate–source voltage VGS (V)

ID – VGS

Drain current ID (mA)

-10000

-0.01

-100

-1000

-1

-10

-0.1

-1.6

-0.2 -0.6

−25°C

Common Source

VDS = -3 V

Ta = 85°C

25°C

-0.4

Drain–source ON-resistance

RDS (ON) (mΩ)

Gate –source voltage VGS (V)

RDS (ON) – VGS

0 -2 -4 -6 -8

100

200

300

400

ID = -0.1 A

Common Source

Ambient temperature Ta (°C)

RDS (ON) – Ta

Drain–source ON-resistance

RDS (ON) (mΩ)

Common Source

500

−50

ID =-0.1A / VGS = -1.5 V

0 50 150

100

200

300

400

100

Drain current ID (A)

RDS (ON) – ID

Drain–source ON-resistance

RDS (ON) (mΩ)

400

100

-2

-6 -8

150

250

350

Common Source

Ta = 25°C

-1.5V

Common Source

Ta = 25°C

VGS=-1.2V

-1.5V

-1.8V

-4V

-1.4 -1.2 -1.0 -0.8

-2.5V

-1.8V

Gate –source voltage VGS (V)

Drain–source -resistance

RDS (ON) (mΩ)

0 -1

-4

-3 -4

100

200

300

400

RDS (ON) – VGS

25°C

Ta = 85°C

−25°C

-1A / -2.5 V

-1A / -1.8 V

-1

-2

-2.5 -2.5V

ID = -1.0 A

Common Source

Ta = 85°C

25°C

−25°C

200

300

450

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2007-11-01

Switching time t (ns)

Drain current ID (A)

t – ID

0.01

100

0.1

1000

1 10

Common Source

VDD = -10 V

VGS = 0∼-2.5 V

Ta = 25°C

RG = 4.7 Ω

toff

ton

Drain reverse current IDR (A)

Drain– source voltage VDS (V)

IDR – VDS

-0.5

-1

0 1.2 0.6 0.2 0.8 0.4 1

-1.5

-2 Common Source

VGS = 0 V

Ta = 25°C

IDR

Ambient temperature Ta (°C)

Vth – Ta

Gate threshold voltage Vth (V)

-0.8

−25 0 25 150

-0.2

-0.4

-0.6

-0.7

50 75 100 125

Common Source

VDS = -3 V

ID = -1 mA

Drain current ID (mA)

Forward transfer admittance ⎪Yfs⎪ (S)

|Yfs| – ID

Common Source

VDS = -3 V

Ta = 25°C

0.01

-100001

0.1

-10 -100 -1000

0.03

0.3

Drain –source voltage VDS (V)

C – VDS

Capacitance C (pF)

-0.1 -1 -10 -100

100

1000

5000

3000

300

500

50 Common

Source

Ta = 25°C

f = 1 MHz

VGS = 0 V

Ciss

Coss

Crss

Total gate charge Qg (nC)

Dynamic Input Characteristic

Gate-source voltage VGS (V)

00 25

-3

-4

51015

-7

-10

-1

-5

-2

-8

-9

Common Source

ID = -1.2 A

Ta = 25°C

-6 VDD = -16 V

-0.5

-0.1

-0.3

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SSM3J115TU

2007-11-01

PD - Ta

200

400

600

800

1000

0 20 40 60 80 100 120 140 160

Ambient temperature Ta(°C)

Drain power dissipation PD(mW)

a: mounted on FR4 boar d

(25.4mm×25.4mm×1.6mm)

Cu Pad :25.4mm×25.4mm

b:mounted on cer amic board

(25.4mm×25.4mm×0.8mm)

Cu Pad :25.4mm×25.4mm

Rth - tw

100

1000

0.001 0.01 0.1 1 10 100 1000

Pulse w idth tw (S)

Transient thermal impedance

Rth(°C/W)

Sing l e pulse

a:M ounted on ceramic board

( 25.4mm× 25. 4mm× 0.8mm)

Cu Pad :25.4mm×25.4mm

b:M ounted on FR 4 board

( 25.4mm× 25. 4mm× 1.6mm)

Cu Pad :25.4mm×25.4mm

c:M ounted on FR 4 Board

( 25.4mm× 25. 4mm× 1.6mm)

Cu Pad :0.45mm×0.8mm×3

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SSM3J115TU

2007-11-01

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responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and

systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily

injury or damage to property, including data loss or corruption. Before creating and producing designs and using, customers must

also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document,

the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the “TOSHIBA

Semiconductor Reliability Handbook” and (b) the instructions for the application that Product will be used with or for. Customers are

solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the

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