MICRON SEMICONDUCTOR INC MT4C40014(L) 1 MEG x 4 DRAM DRAM 1 MEG x 4DRAM STANDARD OR LOW POWER, EXTENDED REFRESH FEATURES * 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J L) Industry-standard x4 pinout, timing, functions and packages High-performance CMOS silicon-gate process Single +5V 10% power supply All inputs, outputs and clocks are TTL-compatible Refresh modes: RAS-ONLY, CAS-BEFORE-RAS (CBR), HIDDEN and BATTERY BACKUP (BBU) (MT4C4001] only) FAST-PAGE-MODE access cycle * Low power, 1mW standby; 275mW active, typical (MT4C4001J L) OPTIONS MARKING * Timing 60s access -6 70ns access 7 8Ons access -8 Packages Plastic SOJ (300 mil) Dj Plastic TSOP (300 mii)* TG Plastic ZIP (400 mil) Z Version 1,024-cycle refresh in l6ms None 1,024-cycle refresh in 128ms L Part Number Example: MT4C4001JDJ-6 L GENERAL DESCRIPTION The MT4C4001J L is a randomly accessed solid-state memory containing 4,194,304 bits organized ina x4 configu- ration. During READ or WRITE cycles, each bit is uniquely addressed through the 20 address bits, which are entered 10 bits (AQ-A9) at a time. RAS is used to latch the first 10 bits and CAS the latter 10 bits. READ and WRITE cycles are selected with the WE input. A logic HIGH on WE dictates READmodewhilealogic LOW on WE dictates WRITEmode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS, whichever occurs last. If WE goes LOW prior to CAS going LOW, the output pin(s) remain open (High-Z) until the next CAS cycle. If WE goes LOW after data reaches the output pins, the outputs (Qs) are activated and retain the selected cell dataas long as CAS remains LOW (regardless of WE or RAS). This late WE pulse results in a PIN ASSIGNMENT (Top View) 20-Pin SOJ 20-Pin ZIP (DD-1) (DD-1) w a c ui > Ww ec Consult factory on availability of reverse pinout TSOP packages. READ-WRITE cycle. The four data inputs and four data outputs are routed through four pins. using common I/O and pin direction is controlled by WE and OE. FAST-PAGE-MODE operations allow faster data opera- tions (READ, WRITE or READ-MODIFY-WRITE) within a row-address-defined (A0-A9) page boundary. The FAST- PAGE-MODE cycle is always initiated with a row-address strobed-in by RAS followed by a column-address strobed- in by CAS. CAS may be toggled-in by holding RAS LOW and strobing-in different column-addresses, thus executing faster memory cycles. Returning RAS HIGH terminates the FAST-PAGE-MODE operation. Returning RAS and CAS HIGH terminates a memory cycle and decreases chip current toa reduced standby level. Also, the chip is preconditioned for the next cycle during the MT4C4001J(L) REV. 3/93. Micron Semiconductor, Inc., reserves the right to change products or specifications without notices. 1993, Micron Semiconductor, Inc. b3E D MM 6111549 0007629 4yo2 BE MRN WVuGMICRON SEMICONDUCTOR INC b3E D MM 6111549 0007630 124 MEMRN Maren iin MICRON 1 MEG x 4 DRAM RAS HIGH time. Memory cell data is retained in its correct dresses (AO-A9) are executed at least every 16ms for the state by maintaining power and executing any RAS cycle MT4C4001J and every 128ms for the MT4C4001J L, regard- (READ, WRITE) or RAS REFRESH cycle (RAS-ONLY, CBR, less of sequence. The CBR REFRESH cycle will invoke the or HIDDEN) so that all 1,024 combinations of RAS ad- internal refresh counter for automatic RAS addressing. 0 wv > = FUNCTIONAL BLOCK DIAGRAM FAST-PAGE-MODE we = DATA-IN pat aoe 1 BUFFER paz pas EARLY-WRITE =f ) pas No 2cLock 4 [DETECTION CIRCUIT DATA-OUT GENERATOR _,| BUFFER o OF >| COLUMN- ADDRESS DECODER ao BUFFER(10) Al AQ REFRESH SENSE AMPLIFIERS AB CONTROLLER VO GATING A4 a J AS : AG REFRESH a COUNTER AT Ag iS 5 ne - 5 Og} 1024x 1024x4 | ROW- 24 Ge zs MEMORY Ea) ADDRESS oko} 2 Os ARRAY BUFFERS (10) ey 2a ze a an o~ I 8 Oo _ NO. 1 CLOCK o Veo RAS >| GENERATOR +o Vss . WE LOW prior to TAS LOW, EW detection circuit output is a HIGH (EARLY-WRITE) *NOTE: 1 2. GAS LOW prior to WE LOW, EW detection circuit output is a LOW (LATE-WRITE) MTSC4001U(L) 1 88 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1993, Micron Semiconductor, Inc. REV. 3/93MICRON SEMICONDUCTOR INC b3E D MM 6111549 0007631 ObLO MEMRN MICRON MT4C4001J(L) Parrott 1 MEG x 4 DRAM TRUTH TABLE ADDRESSES DATA-IN/OUT FUNCTION RAS | caS | WE | bE | oR i Do1-Do4 0 Standby H H--X x x x x High-Z a READ L L H L ROW COL Data-Out > EARLY-WRITE L L L x ROW COL Data-In = READ-WRITE L L HL L-H ROW COL Data-Out, Data-In FAST-PAGE-MODE 1st Cycle L H--L H L ROW COL Data-Out READ 2nd Cycle L HL H L na COL Data-Out FAST-PAGE-MODE Ist Cycle L H>L L x ROW COL Data-In EARLY-WRITE 2nd Cycle L HeL L X wa COL Data-In FAST-PAGE-MODE ist Cycle L H-L HL L>-H ROW COL | Data-Out, Data-In READ-WRITE 2nd Cycle L HL HL L-H Wa COL Data-Out, Data-In RAS-ONLY REFRESH L H Xx xX ROW n/a High-Z HIDDEN READ L>H=L L H L ROW COL Data-Out REFRESH WRITE L-H?-L L L x ROW COL Data-In CBR REFRESH H=>L L H x Xx x High-Z BBU REFRESH (MT4C4001J L only)} H>-L L H x X Xx High-Z MT4C4001J(L) 1 89 Micron Semiconductor. Inc., reserves the right to change products or specifications without notice, REV. 393 - 1993, Micron Semiconductor, Inc.MICRON SEMICONDUCTOR INC b3E D MB 6131549 OO07b3e2 TT? BEMRN MICRON MT4C4001 J(L) 1 MEG x 4 DRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under Absolute Maxi- Voltage on Any Pin Relative to V8S ...sssssseesseoe -1V to +7V mum Ratings may cause permanent damage to the device. Operating Temperature, T, (ambient)........... 0C to +70C This is a stress rating only and functional operation of the 0 Storage Temperature (plastic) ........0 -55C to +150C device at these or any other conditions above those indicated Power Dissipation . 1W in the operational sections of this specification is notimplied. > Short Circuit Output Current .....cccsssscsssnseessesnesesenes 50mA Exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (Notes: 1, 3, 4, 6, 7) (Voc = 5V 10%) PARAMETER/CONDITION SYMBOL | MIN | MAX | UNITS | NOTES Supply Voltage Vec 4.5 5.5 Vv 1 Input High (Logic 1) Voltage, all inputs Vin 2.4 | Vec+1 Vv 1 Input Low (Logic 0) Voltage, all inputs Vit -1.0 0.8 v 1 INPUT LEAKAGE CURRENT Any input OV < Vin < 6.5V Mt -2 2 LA (All other pins not under test = OV) OUTPUT LEAKAGE CURRENT (0 is disabled; OV < Vout < 5.5V) loz -10 10 pA OUTPUT LEVELS VoH 2.4 Vv Output High Voltage (lout = -5mA) Output Low Voltage (lout = 4.2mA) VoL 0.4 Vv MAX PARAMETER/CONDITION VERSION SYMBOL | -6 | -7 | -8 UNITS | NOTES STANDBY CURRENT: (TTL) lect 2 2 2 | mA (RAS = CAS = Vir) STANDBY CURRENT: (CMOS) MT4C4001J Ioc2 1 1 1 mA (RAS = CAS = Vcc -0.2V) MT4C4001U LL] Icc2 | 200 | 200 | 200 | WA OPERATING CURRENT: Random READ/WRITE Average power supply current Icc3 110 |} 100} 90 | A 3, 4, (RAS, CAS, Single Address Cycling: 'RC = 'RC [MIN]) 30 OPERATING CURRENT: FAST-PAGE-MODE Average power supply current loca 80 | 70 | 60 | pA 3, 4, (RAS = Vi, CAS, Address Cycling: 'PC = 'PC [MIN]) 30 REFRESH CURRENT: RAS-ONLY Average power supply current lecs 110 | 100] 90 | pA 3, 30 (RAS Cycling, CAS = Vin: "RC = 'RC [MIN}) REFRESH CURRENT: CBR Average power supply current Icc6 110 | 100] 90 | pA 3,5 (RAS, CAS, Address Cycling: RC = 'RC [MIN}) REFRESH CURRENT: BBU Average power supply current during BBU REFRESH: CAS = 0.2V or CBR cycling; RAS = RAS (MIN) to 300ns; | MT4C4001JL] Icc7 | 300 | 300 | 300 | pA 3, 5, WE, AO-AQ and Din = Vcc -0.2V or 0.2V; (Din may be 7,2 left open); RC = 125s (1,024 rows at 125ys = 128ms) a MT4C4001 J(L) 1 -90 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 4/93 1993, Micron Semiconductor, Inc.MICRON SEMICONDUCTOR INC BSE D MM 6111549 0007633 933 MEMRN Wiesmiay NAZI) Parotid Ca rN CAPACITANCE PARAMETER SYMBOL | MIN | MAX | UNITS | NOTES Input Capacitance: AO-A9 cn 5 pF 2 Oo Input Capacitance: RAS, CAS, WE, OE Ci2 7 pF 2 ad Input/Output Capacitance: DQ Cio 7 pF 2 2 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23} (Veo = 5V 410%) AC CHARACTERISTICS 6 7 8 PARAMETER SYM MIN MAX MIN MAX MIN MAX UNITS NOTES Random READ or WRITE cycle time 'RC 110 130 150 ns READ-WRITE cycle time RWC 150 180 200 ns FAST-PAGE-MODE 'PC 35 40 45 ns READ or WRITE cycle time FAST-PAGE-MODE 'PRWC 85 100 105 ns READ-WRITE cycle time Access time from RAS RAC 60 70 80 ns 14 Access time from CAS CAC 15 20 20 ns 15 Output Enable OE 15 20 20 ns 23 Access time from column-address TAA 30 35 40 ns Access time from CAS precharge CPA 35 40 45 ns RAS pulse width RAS 60 100,000 70 100,000 80 100,000 ns RAS pulse width (FAST-PAGE-MODE) "RASP 60 200,000 70 200,000 80 200,000 ns RAS hold time 'RSH 15 20 20 ns RAS precharge time 'RP 40 50 60 ns CAS pulse width CAS 15 100,000 20 100,000 20 100,000 ns CAS hold time 'CSH 60 70 80 ns CAS precharge time (CBR REFRESH)| CPN 10 10 10 ns 16 CAS precharge time (FAST-PAGE-MODE)| CP 10 10 10 ns RAS to CAS delay time RCD 20 45 20 50 20 60 ns 17 CAS to RAS precharge time CRP 10 10 10 ns Row-address setup time 'ASR 0 0 0 ns Row-address hold time RAH 10 10 10 ns RAS to column- RAD 15 30 15 35 18 40 ns 18 address delay time Column-address setup time asc QO 0 0 ns Column-address hold time 'CAH 10 15 16 ns Column-address hold time AR 50 55 60 ns (referenced to RAS) Column-address to 'RAL 30 35 40 ns RAS lead time Read command setup time 'RCS 0 0 0 ns Read command hold time 'RCH 0 0 0 ns 19 (referenced to CAS) Read command hold time RRH 0 0 0 ns 19 (referenced to RAS) CAS to output in Low-Z 'CLZ 0 0 0 ns Output buffer tum-off delay OFF 3 15 3 20 3 20 ns 20, 29 REV. 980 1-91 Sacron Somerset, in eserves fn doo charge procs spectators without noon.MICRON SEMICONDUCTOR INC 63E D Ml 6222549 OOO7b34 57T MMMRN MICRON MT4C40014J(L) 1 MEG x 4 DRAM | ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vcc = 5V 10%) 0 AC CHARACTERISTICS 6 7 8 a PARAMETER SYM MIN MAX MIN MAX MIN MAX UNITS NOTES > WE command setup time twcs 0 0 0 ns 21,27 = Write command hold time 'WCH 10 15 15 ns Write command hold time 'WCR 45 55 60 ns (referenced to RAS) Write command pulse width twp 10 15 15 . ns Write command to RAS lead time tRWL 15 20 20 ns Write command to CAS lead time 'CWL 15 20 20 ns Data-in setup time ps 0 0 0 ons 22 Data-in hold time DH 10 15 15 ns 22 Data-in hold time DHR 45 55 60 ns (referenced to RAS) RAS to WE delay time RWD 90 100 110 ns 21 Column-address 'awD 55 65 70 ns 24 to WE delay time CAS to WE delay time CwD 40 50 50 ns 21 Transition time (rise or fall) T 3 50 3 50 3 50 ns 9, 10 Refresh period (1,024 cycles) MT4C4001J / MT4C4001J L 'REF 16/128 16/128 16/128 ms RAS to CAS precharge time tRPC 0 0 0 ns CAS setup time (CBR REFRESH) CSR 10 10 10 ns 5 CAS hold time (CBR REFRESH) CHR 10 10 10 ns 5 WE hold time (CBR REFRESH) twRH 10 10 10 ns 25 WE setup time (CBR REFRESH) | 'WRP 10 10 10 ns 25 WE hold time (WCBR test cycle) WTH 10 10 10 ns 25 WE setup time (WCBR test cycle) twTs 10 10 10 ns 25 OE setup prior to RAS during toRD 0 0 0 ns HIODEN REFRESH cycle Output disable oD 15 20 20 ns 27 OE hold time from WE during OEH 15 20 20 ns 26 READ-MODIFY-WRITE cycle MT4C4001J(L) Micron Semiconductor, Inc., reserves the righl to change products or specifications without notice. 1-92 REV. 3/93 - 1999, Micron Semiconductor, inc.MICRON SEMICONDUCTOR INC MICRON MT4C4001J(L) 1 MEG x 4 DRAM NOTES 1. All voltages referenced to Vss. 2. This parameter is sampled. Vcc = 5V +10%; f=1MHz. 3. Icc is dependent on cycle rates. 4. Icc is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 5. Enables on-chip refresh and address counters. 6. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is assured. 7. An initial pause of 100us is required after power-up followed by eight RAS refresh cycles (RAS-ONLY or CBR with WE HIGH) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the 'REF refresh requirement is exceeded. AC characteristics assume T = 5ns. Via (MIN) and Vit (MAX) are reference levels for measuring timing of input signals. Transition times are measured between ViH and Vin (or between VIL and Vin). 10. In addition to meeting the transition rate specifica- tion, all input signals must transit between Vii and Vit (or between Vit and Vim) in a monotonic manner. 11. If CAS = Vin, data output is High-Z. 12. If CAS = Vin, data output may contain data from the last valid READ cycle. 13. Measured with a load equivalent to two TTL gates and 100pF. 14. Assumes that "RCD < RCD (MAX). If RCD is greater than the maximum recommended value shown in this table, RAC will increase by the amount that RCD exceeds the value shown. 15. Assumes that RCD = *RCD (MAX). 16, If CAS is LOW at the falling edge of RAS, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS must be pulsed HIGH for CPN. 17. Operation within the RCD (MAX) limit ensures that 'RAC (MAX) can be met. RCD (MAX) is specified as a reference point only; if RCD is greater than the specified RCD (MAX) limit, then access time is controlled exclusively by CAC. 18. Operation within the RAD (MAX) limit ensures that *RAC (MIN) and *CAC (MIN) can be met. RAD (MAX) is specified as a reference point only; if RAD is greater than the specified RAD (MAX) limit, then access time is controlled exclusively by AA. 19, Either RCH or RRH must be satisfied for a READ cycle. sO @ 20. OFF (MAX) defines the time at which the output achieves the open circuit condition, and is not referenced to Vou or VoL. 21. WCS, RWD, AWD and 'CWD are not restrictive operating parameters. WCS applies to EARLY- WRITE cycles. RWD, AWD and 'CWD apply to READ-MODIFY-WRITE cycles. If 'WCS > WCS (MIN), the cycle is an EARLY-WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If RWD 2 RWD (MIN), AWD > tAWD (MIN) and CWD 2 CWD (MIN), the cycle is a READ-MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW results in a LATE-WRITE (OE- controlled) cycle. 'WCS, 'RWD, 'CWD and AWD are not applicable in a LATE-WRITE cycle. 22. These parameters are referenced to CAS leading edge in EARLY-WRITE cycles and WE leading edge in LATE-WRITE or READ-MODIFY-WRITE cycles. 23. If OE is tied permanently LOW, LATE-WRITE or READ-MODIFY-WRITE operations are not possible. 24. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE = LOW and OE = . HIGH. 25. WTS and WTH are setup and hoid specifications for the WE pin being held LOW to enable the JEDEC test mode (with CBR timing constraints). These two parameters are the inverts of WRP and WRH in the CBR refresh cycle. 26. LATE-WRITE and READ-MODIFY-WRITE cycles must have both OD and OEH met (OF HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. If OE is taken back LOW while CAS remains LOW, the DQs will remain open. 27. The DQs open during READ cycles once OD or OFF occur, If CAS goes HIGH before OE, the DQs will open regardless of the state of OE. If CAS stays LOW while OE is brought HIGH, the DQs will open. If OE is brought back LOW (CAS still LOW), the DQs will provide the previously read data. 28. BBU current is reduced as RAS is reduced from its maximum specification during the BBU cycle. 29. The 3ns minimum is a parameter guaranteed by design 30. Column-address changed once while RAS = Vi. and CAS = Vin. MT4C40015(L) REV. 3/93 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1998, Micron Semiconductor, Inc. BIE D MM 6111549 0007635 70b MBNRN WVudMICRON SEMICONDUCTOR INC 63E D MMM 6232549 O00763b Bue MMNRN MICRON Neu 1 MEG x 4 DRAM READ CYCLE Vie - rast > WVHd i YH- ms te Vv appr vit Vin Yi MIOH ~. de VioL VALID DATA v ow vt EARLY-WRITE CYCLE Yin vin = zl Vn - cas yi > appr yt we vit oa vige VALID DATA m= Re WWW MLL DONT CARE RY UNDEFINED MT4C4001J(L) 1 94 Micron Semiconductor, Inc., reserves the righl to change products or specifications without notice. REV, 393 1993, Micron Semiconductor, Inc.MICRON SEMICONDUCTOR INC &3E D Ml 6422549 0007637 585 MMMRN MICRON Naor him) 1 MEG x 4 DRAM READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES) vin = Vit - al WVud =< Yn CaS yt T ADDR ve Vin Vit al Vion - vet =< VALIOD our VALID D yy 8 Yin Vit al FAST-PAGE-MODE READ CYCLE Vi - Ras vit > a os Y= , poor Yin vie al Yio Vion 8 be OMIM DON'T CARE RRQ UNDEFINED MT4C4001J(L) 1 95 Micron Semiconductor, Inc., reserves the right to change products or spacificalions without notice. REV, 999 - 1993, Micron Semiconductor, Inc.MICRON SEMICONDUCTOR INC B3E D MM 6111549 0007636 415 EEMRN MICRON MT4C4001J(L) 1 MEG x 4 DRAM FAST-PAGE-MODE EARLY-WRITE CYCLE _-S = ws Ye cas NIK - ADDR wu = Y, we Yt v be vat VALID DATA VALID DATA VALID DATA = Yn OF vA Li FAST-PAGE-MODE READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES) V ~_ mas vit 7 ome Ving cs vil T v appr yj = we vit too toe: toe oe Mt LLL LLL DONT CARE BJ UNOEFINED *tPC is for LATE-WRITE only. MT4Ca00TJ(L) 4 96 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 3/93. - 1993, Micron Semiconductor, Inc.MICRON SEMICONDUCTOR INC BJE D MMH 6111549 0007639 351 MMRN Wale TN MT4C4001J(L) 1 MEG x 4 DRAM FAST-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) oO ms YH W 2 a You ve Mt Ds NOTE: 1. Do not drive data prior to tristate: CPP(MIN) or CP(whichever is greater) + 'DS(MIN) + any guardband between data-out and driving the bus with the new data-in. RAS-ONLY REFRESH CYCLE (ADDR = A0-A9; WE = DONT CARE) tras "e tae oni | tcrp , rs ve : 1, t soon Vit 7 ROW LLL ROW DON'T CARE BY UNDEFINED MTACAOO tL) 1 -97 Micron Semiconductor, Inc., renarvs eft to change products o spactiatons witout ratiosMICRON SEMICONDUCTOR INC 63E D MM 6122549 0007640 073 MENRN MICRON Teer le, 1 MEG x 4 DRAM CBR REFRESH CYCLE (A0-A9 and OE = DONT CARE) Oo yD tae tras tap tras > Ras vit! = N y N ~~ = tapc_ ,_cpn | csr tcHR APC, tosr__||_'cHR as woo 4 /_ pa > OPEN dwre| | WR twee || IWAH, al tt LLL ILL MM BBU REFRESH CYCLE (MT4C4001J L only) (A0-A9 and OE = DONT CARE) 125ps tap tRas fAP tras a a N y i f tAPG_ itcpn_|,_ csr tcoR APC, tose __||_tcHR ans YH ~ i f } \ y pa, = OPEN twap|| twRH, _twaP||_twrH, . { | | wet LLL ULL LLL, DON'T CARE RY] UNDEFINED MT4C4001J(L) Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. a3 1-98 1993, Micron Semiconductor, Inc.MICRON SEMICONDUCTOR INC 63E D WM 61213545 9007641 TOT Me MRN MICRON MT4C4001J(L) 1 MEG x 4 DRAM HIDDEN REFRESH CYCLE (WE = HIGH; OE = LOW) (READ) (REFRESH) ae VIH- RAS Vite INVYG CAS WIH- tasc Vin- appr yitt, COLUMN DQ vioH _- VALID DATA de MIH OE VIL DON'T CARE RX UNDEFINED MT4C4001 JL) 1 99 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. REV. 293 - 1993, Micron Semiconductor, inc.MICRON SEMICONDUCTOR INC 0 BY > bB3E D MM 6111549 OOO?bYe FW46 MEMRN MT4C4001J(L) em em el arAU 4 MEG POWER-UP AND REFRESH CONSTRAINTS The ELA/JEDEC 4 Meg DRAM introduces two potential incompatibilities compared to the previous generation 1 Meg DRAM. The incompatibilities involve refresh and power-up. Understanding these incompatibilities and pro- viding for them will offer the designer and system user greater compatibility between the 1 Meg and 4 Meg. REFRESH The most commonly used refresh cycle of the 1 Meg is the CBR REFRESH cycle. The CBR for the 1 Meg specifies the WE pin as a dont care. The 4 Meg, on the other hand, specifies the CBR REFRESH mode with the WE pin held at a voltage HIGH level. A CBR cycle with WE LOW will put the 4 Meg into the JEDEC-specified test mode (WCBR). WCBR TEST MODE: WE vd 4MEG DRAM CBR REFRESH: WE yi4 > POWER-UP The 4 Meg JEDEC test mode constraint may introduce another problem. The 1 Meg POWER-UP cycle requires a 100s delay followed by any eight RAS cycles. The 4 Meg POWER-UP is more restrictive in that eight RAS-ONLY REFRESH or CBR REFRESH (WE held HIGH) cycles must be used. The restriction is needed since the 4 Meg may power-up in the JEDEC-specified test mode and must exit out of the test mode. The only way to exit the 4 Meg JEDEC test mode is with either a RAS-ONLY REFRESH cycle or a CBR REFRESH cycle (WE held HIGH). SUMMARY 1. The 1 Meg CBR REFRESH allows the WE pin to be dont care while the 4 Meg CBR requires WE to be HIGH. 2. The eight RAS: wake-up cycles on the 1 Meg may be any valid RAS cycle while the 4 Meg may only use RAS- ONLY or CBR REFRESH cycles (WE held HIGH). CBR REFRESH: WE Mt (LLL DON'T CARE 1 MEG DRAM COMPARISON OF 4 MEG TEST MODE AND WCBR TO 1 MEG CBR Micron Semiconductor, inc., reserves the right to change products or epecifications without notica. 1993, Micron Semiconductor, inc. MTsca001J(L) REV. 3993 1-100