MTA85811-10I/SS - Microchip Technology, Inc.

 1995 Microchip Technology Inc. DS40115C-page 1

FEATURES

• Multi-chip module

• PIC16C54A or PIC16C58A Microcontrollers with

24LC01B or 24LC02B Serial EEPROMs (S EEs)

in a single package

• Wide operating voltage range: VDD = 3.0V to

6.25V

• Microcontroller contr ol of SEE power for low

standby current: MTA85X1X series

• Industrial grade only

High Performance RISC-like CPU

• Only 33 single-word instructions to learn

• All instructio ns are single-cycle except for

program branches, which are two cycle

• Operating speed: MTA854XX, DC - 4 MHz

MTA858XX, DC - 4 and 10 MHz

• 12-bit wide instr u ctions

• 8-bit wide data pat h

• 512 or 2048 x 12 on-chip EPROM program

memory

• 25 or 73 x 8 general purpose registers (SRAM)

• Seven special function hardware registers

• Two-level deep hardw are stack

• Direct, indirec t, and relative addressing modes fo r

data a n d instructio ns

Peripheral Features

• 12 I/O pins with indivi dual direction control (RB7

dedicated for SEE VDD in MTA85X1X devices)

• 8-bit real time clock/counter (T0CKI) with 8-bit

programmable prescaler

• Power-On R e set

• Oscillator Start-Up timer

• Watchdog timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Security EPROM bit for code-protection

• Power saving SLEEP mode

• EPROM selectable oscillator options:

- Low-cost RC oscillator: RC

- Standard cry stal/resonator: XT

- High-speed crystal/resonator: HS

- Power-saving low fr equency crystal: LP

PACKAGE TYPE

Serial EEPROM Features

• 1K or 2K of EEPROM memory, organized as a

single block: 128 x 8 or 256 x 8

• Two-wire ser ial interf a ce bus, I2C compatible

• 100 kHz and 400 kHz compatibility

• Self-timed write cycle (in cluding auto-erase)

• Pa ge-writ e buffer for up to 8 byt es

• 2 ms typical cycle times f or page-write

• 1,000,000 ERASE/WRITE cycles typical

• Data retention > 40 year s

CMOS Techn ol og y

• Low-power, high-speed CMOS EPROM and

EEPROM technologies, in a single package

• Fully static design

• Low-power consumption (PIC16C54/58A)

- < 2 mA typical @ 5V, 4 MHz

-15 µA typical @ 3V, 32 kHz

-< 0.3 µA typical standby current (with WDT

disabled) @ 3V, 0°C to 70°C

• Low-power consumption (24LC01B/02B)

- 1 mA active current typi cal

-10 µA standby c urrent typical @ 5.5V

-5 µA standby current typical @ 3.0V

VDD

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VSS

SDA

SCL

OSC2

OSC1

RA0

RA1

RA2

RA3

T0CKI

NMCLR

•1

MTA85X0X

SSOP

PVDD

N/C

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VSS

SDA

SCL

OSC2

OSC1

RA0

RA1

RA2

RA3

T0CKI

NMCLR

•1

MTA85X1X

MTA85XXX

PICSEE 2 0-Pin MCU with Serial EEPROM Multi-Chip Module

MTA85XXX

DS40115C-page 2  1995 Microchip Technology Inc.

PIN DESCRIPTIONS

Name Function Description

RA3: RA0 I/O PORTA 4 input/output lines.

RB7: RB0 I/O PORTB 8 input/output lines.

SVDD/RB7 Shared VDD-I/O pin Input/Output pin dedicated t o EEPROM VDD.

No external connection needed. MTA85X1X only.

T0CKI* Clock input to TMR0 Register Schmitt Trigger Input.

Clock input to T0CKI register. Must be tied to VSS or VDD if not in

use t o avoid unintended entering of test modes and to reduce

current consumption.

MCLR Master Clear Schmitt Trigger Input.

A low voltage on this i nput generates a RESET for the

microcontroller.

A risi n g vol tage triggers the on- chip oscillator start-up t imer which

keeps the chip in RESET mode for about 18 ms. This input must be

tied directly, or via a pull-up resistor, to VDD.

OSC1 Oscillator (input) XT, HS and LP devices:

Inpu t terminal for crystal, c eramic re sonator, or external clock

generator.

RC devices:

Driver terminal for extern al RC combinatio n to establi sh o scillation.

OSC2/CLKOUT Oscillator (output) For XT, HS an d LP d evi ces :

Output terminal for crystal and ceram ic resonat or.

Do not connect a ny ot her load to t his out put.

Leave open if external clock generator is used.

For RC devices:

A CLKOUT signal with a frequency of 1/4 FOSC1 is put out on this

pin.

SDA Serial EEPROM Data EEPROM data line.

SCL Serial EEPROM Clo ck EEPROM clock line.

VDD Power supply

VSS Ground

* Formerly RTCC.

 1995 Microchip Technology Inc. DS40115C-page 3

MTA85XXX

Table of Contents

1.0 General Description................................................................................................................................................................... 4

2.0 Architectural Description............................................................................................................................................................ 5

3.0 Factory Programming Options................................................................................................................................................... 7

4.0 Pro gra m Mem ory... .... .... ... .................................................................................................................. . .... .... ... .... .... ................... 8

5.0 Dat a Me mo ry and Ope rat io nal Regi st er Fil es.. .... .... ................................................................................................................ 10

6.0 Special Purpose Registers....................................................................................................................................................... 18

7.0 Reset Condition ....................................................................................................................................................................... 19

8.0 Prescaler.................................................................................................................................................................................. 20

9.0 Basic Instruction Set Summary................................................................................................................................................ 21

10.0 Watchdog Timer (WDT)........................................................................................................................................................... 23

11.0 Oscillator Configurations.......................................................................................................................................................... 24

12.0 Reset........................................................................................................................................................................................ 26

13. 0 Pow er-Do wn Mode (SLEE P) .... .... .... ... .... ............................................................................................................... ................. 3 0

14.0 Configuration Fuses................................................................................................................................................................. 31

15.0 Electrical Characteristics.......................................................................................................................................................... 32

16.0 DC and AC Characteristics...................................................................................................................................................... 44

17.0 EEPROM Bus Description ....................................................................................................................................................... 52

18. 0 Wri te Ope rat ion.. ...................................................................................................................................................................... 54

19. 0 Rea d Ope rati on........................................................................................................................................................................ 56

20.0 General EEPROM Information................................................................................................................................................. 58

21.0 Development Support.............................................................................................................................................................. 59

22.0 Packaging Diagrams and Dimensions..................................................................................................................................... 63

23. 0 Packag e Markin g Info rmat ion ................................................................................................................................. ................. 6 4

MTA85XXX

DS40115C-page 4  1995 Microchip Technology Inc.

1.0 GENERAL DESCRIPTION

The MTA85XXX devices from Microchip Technology

Inc. are a family of multi-chip products which offer a

unique combination of EPROM-based Microcontrollers

and Serial EEPROM data memory in a single package.

The MTA85XXX line features the PIC16C5XA family of

Microcontrollers combined with Microchip’s 24LC0XB

family of Serial EEPROMs.

The Microcontroller and Serial EEPROM portions of

these multi-chip devices are equivalent to their

re spective individual components chips, except for t he

electrical specifications on shared pins. Please refer to

the dat asheets of the component die for information on

each device’s architecture, functionality, and other

im portant u ser informati on.

Two unique pinouts are available in this family of

devices, regardless of which combination of

component chips are used. The first pinout

(MTA85X0X series) features shared power and grou nd

pins for the Microcontroller and Serial EEPROM. All

other Microcontroller and Serial EEPROM pins are

electrically independent. The second available pinout

(MTA 85X1X serie s) fe at ures Micro controller c ontrol of

the Serial EEPROM VDD. This allows the Serial

EEPROM to be powered down when going into a

standby mode. This is often desirable in power con-

scious applications to reduce current when the Serial

EEPROM is not being accessed. In this configuration

the Microcontroller I/O pin RB7 is used to supp ly power

to the Serial EEPROM. I t is the user’s responsibility to

ensure that RB7 is driving a '1' while the Serial

EEPROM is being used.

The MTA85XXX devices are supported by an in-circuit

emulator, an assembler, and a production quality

programmer. All tools are supported by IBM PC and

compatible machines.

1.1 Applications

The MT A85XXX family is ideally suited to a wide variety

of applications including, but not limited to: keyless

entry, remote control, smart cards and automotive

controllers. The EPROM program memory makes

customization of application programs fast and

convenient. The EEPROM data memory is ideal for

storing c onfigurati on inform ation, access codes, serial

numbers, and adaptive look-up tables. The small

footprint package makes the MTA85XXX devices

perfe ct for applicati ons wit h physic al space limitations.

This small size coupled with the low-cost, low-power,

wide voltage range, and high performance of this

flexible family of devices makes the MTA85XXX the

microcontroller of choice for a wide variety of

applications which utilize EEPROM mem ory.

1.2 MTA85XXX Series Overview

A variety of EPROM program memory sizes , EEPROM

data memory sizes and frequency ranges are

available. Depe nding on the application and production

req uirements, the proper device option ca n be selected

using the information in Table 1 -1 and Table 1-2. When

placing orders, please use the “MTA85XXX Product

Identification System” on the back page of this data

sheet to sp ecify the corr e ct part.

TABL E 1-1: FAMILY OVERVIEW

Part Number Microcont rolle r SEE PGM EPROM EEPROM RAM I/O

MTA85401 PIC16C54A 24LC01B 512 x 12 128 x 8 32 x 8 12

MTA85402 PIC16C54A 24LC02B 512 x 12 256 x 8 32 x 8 12

MTA85411 PIC16C54A 24LC01B 512 x 12 128 x 8 32 x 8 12 note 1

MTA85412 PIC16C54A 24LC02B 512 x 12 256 x 8 32 x 8 12 note 1

MTA85801 PIC16C58A 24LC01B 2048 x 12 128 x 8 80 x 8 12

MTA85802 PIC16C58A 24LC02B 2048 x 12 256 x 8 80 x 8 12

MTA85811 PIC16C58A 24LC01B 2048 x 12 128 x 8 80 x 8 12 note 1

MTA85812 PIC16C58A 24LC02B 2048 x 12 256 x 8 80 x 8 12 note 1

Note: RB7 dedi cate d to SEE VDD

 1995 Microchip Technology Inc. DS40115C-page 5

MTA85XXX

2.0 ARCHITECTURAL

DESCRIPTION

2.1 Harvard Arc hitecture

The MTA85XXX mi crocont rollers are low-power, high-

speed, full static CMOS devices containing E EPR OM,

EPROM, RAM, I/O and a central processing unit in a

single package.

The architecture is based on a register file co ncept with

separate bus and memories for data and instructions

(Harvard architecture). The data bus and memory

(RAM) are 8-bits wide while the program bus and

program memory (EPROM) have a width of 12-bits.

This concept allows a simple yet powerful instruction

set designed to emphasize bit, byte and register

operations under high speed with overlapping

instruction fetch and execution cycles. That means

that, while one instruction is executed, the following

instruction is already being read from the program

memory. A block diagram of the MTA85XXX is given in

Figure 2-1.

2.2 Clo c kin g Schem e/ Instru ctio n Cycl e

The cloc k input ( from pin OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, PC is

incremented every Q1, instruction is fetched from

program memory and latched into instruction register in

Q4. I t is decoded a nd executed during the following Q1

through Q4. The clocks and instruction execution flow

is shown in Figure 2-2 .

FIGURE 2-1: MTA8 5XXX SERIE S BLOCK DIAG RAM

MTA85X0X devices have PIC16C5XA VDD tied to EEPROM VDD.

MTA 85X1X devices h ave PIC1 6C5XA RB7 tied to EEPROM VDD.

Page

Latches

EEPROM

Array

Generator

Memory

Control

Logic

Sense

AMP R/W

Control

I/O

Control

Logic

YDEC

XDEC

SDA SCL

VDD

VSS

RB7

VDD

VSS

WDT

Time Out

STACK1

STACK 2

EPROM

512 X 12 To

2048 X 12

Instruction

Decoder

Watchdog

Timer

Configuration WORD

Oscillator/

Timing &

Control

General

Purpose

File

(SRAM)

24-72

Bytes

WDT/TMR0

Prescaler

Option

Reg. “OPTION”

“SLEEP”

“Code

Protect”

“OSC

Select”

Direct

TMR0

From W

“TRIS 5” “TRIS 6” “TRIS 7”

FSR

TRISA PORTA

From W

T0CKI

9-11

Data

ALU

STATUS

From W

CLKOUT

55-7

OSC1

OSC2

MCLR

Literals

PC “Disable"

RA3:RA0 RB7:RB0 RC7:RC0

(28-Pin

Devices Only)

Direc t RAM

Address

TRISB PORTB TRISC PORTC

PIC16C5XA Portion

Block Diag ram EEPROM Portion

Block Diagram

MTA85XXX

DS40115C-page 6  1995 Microchip Technology Inc.

2.3 Data Register File

The 8-bit data bus connects two basic functional

elements together: the Register File composed of

addressable 8-bit registers including the I/O Ports, and

an 8-bit wide Arithmetic Logic Unit. The 32 bytes of

RAM are directly addressable while a "banking"

scheme, with banks of 16 bytes each, is employed to

address larger data memories (Figure 5-1). Data can

be addressed direct, or indirect using the file select

by special "literal" instructions which load data from

program memory into the W register.

The register file is divided into two functional groups:

operational registers and general purpose registers.

The operational registers in cl ude the Real Ti me Clock

Counter (T0CKI) register, the Program Counter (PC),

the Status Register, the I/O registers (PORTs), and the

File Select Register. The general purpose re gisters are

used for data and control informat ion under comma nd

of the instructions.

In addition, special purpose registers are used to

control the I/O port configuration, and the prescaler

options.

2.4 Arithmetic/Logic Unit (ALU)

The 8-bit wide ALU contains one temporary working

Boolean func tions between data he ld in the W Register

and any file register. It also does single operand

operatio ns on either the W register or any file register.

2.5 Program Memory

512 or 2048 words of 12-bit wide on-chip program

memory (EPROM) can be directly addressed.

Sequencing of microinstructions is controlled via the

Program Counter (PC) which automaticall y increm ents

to execute in-line programs. Program control

operations, supporting direct, indirect, relative

addressing modes, can be performed by Bit Test and

Skip instructions, Call instructions, J ump ins tructions or

by loading computed addresses into the PC. In

addition, an on-chip two-level stack is employed to

provide easy to use subroutine nesting.

FIG URE 2-2: CLOCKS/INSTRUCTION CYCLE

Note: For additi o nal details on the PIC16C5X archi tecture, please refer to document # DS30236.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(Program cou nter)

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

 1995 Microchip Technology Inc. DS40115C-page 7

MTA85XXX

3.0 FACTORY PROGRAMMING

OPTIONS

A variety of EPROM program memory sizes , EEPROM

data memory sizes and frequency ranges are

available. Depe nding on the application and production

req uirements, the proper device option ca n be se lected

using the information in Table 1-1 and Table 1 -2. When

placing orders, please use the “MTA85XXX Product

Identification System” on the back page of this data

sheet to sp ecify the corr e ct part.

3.1 One-Time-Programmable (OTP)

Devices

The availability of O TP d evices i s e specially u s eful for

customers expecting frequent code changes and

updates.

With OTP devices the program EPROM is erased,

allowing the user to write the application code into it.

Additionally the watchdog timer can be disabl ed, and/

or the code protection logic can be activated by

programming special EPROM fuses. 16 non -dedic ated

EPROM bits are available for t he custom er ID or other

cus tomer information and are also user programmable.

3.2 Qui ck-Turn-Pr od ucti on (QTP ) Devices

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for volume users with stable code, who

choo se not t o program the devices themselves. A QTP

device is identical to an OTP device, except that the

program memory and special EPROM fuses are

programmed at the factory, with the customer ’s code.

Certain c ode and prototype verificatio n pr ocedures do

apply before production shipments are available.

Please contact your Microchip Technology Inc. sales

office for more details.

3.3 Serialized-Quick-Turnaround-

Pro du ctio n (SQTP) De vices

Microchip offers the unique programming service

where few locations in each device are programmed

with different serial numbers. The serial numbers ma y

be random, pseudo-random or sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

MTA85XXX

DS40115C-page 8  1995 Microchip Technology Inc.

4.0 PROGRAM MEMORY

The MTA854XX devices contain 512 12-bit words of

program memory. The MTA858XX devices contain

2048 12-bit words. Refer to Figure 4- 1 a nd Fig ure 4-2

for a description of the program memory organization.

4.1 P ro gram Memory Organization

Up to 512 words of 12-bit wi d e on-chip program mem-

ory (EPROM/ROM) can be directly addressed. Larger

program memories can be addre ssed by selecting one

of up to four available pages of 512 words each

(Figure 4-2). Sequencing of instructions is controlled

via the Program Counter (PC) which automatically

increm ents to execute in-lin e programs. Pr ogram con -

trol operations supporting direct, indirect, and relative

addressin g modes, can be performed b y bit test, skip,

call, and jump type instructions, or by loading com-

puted addresses into the PC. In addition, an on-chip

two-level stack is employed to provide ea sy to use sub-

ro utine nesting.

4.2 Pro gram C o unter

The program counter generates addresses for on-chip

EEPROM containing the pro gram instruction wor ds.

The program counter is set to all '1's upon a RESET

condition. During program execution, it is auto

incremented with each instruction unless the result of

that instruction changes the PC itself:

a) GOTO instructions allow the direct loading of the

lower nine prog ram counter bits (PC8:PC0). For

MTA858XX devices, the upper two bits of PC

(PC10:PC9) are loaded with page select bits

PA1:PA0 (STATUS <6:5>). Thus GOTO permits

jumping to any locati on on any page.

b) CALL instructions load the lower 8-bits of the PC

directly while the 9-bits are cleared. The PC

value, incremented by one, will be PUSH’ed

onto the stack. For MTA858XX, the upper two

bits of PC (PC10:PC9) are loaded with Page

Select bits PA1:PA0 (S TATUS <6:5>).

c) RETLW instructions load the program counter

with the top of stack contents.

d) If the PC is the destination in any instruction

(e.g., MOVWF PC, ADDWF PC, or BS F PC, 5),

then the compu ted 8-bit result will be loaded into

the low 8-bits of program counter. The ninth bit

of PC will be cleared. In MTA858XX devices

PC10:PC9 will be loaded with the page select

bits.

The MTA858XX devices have multiple program

memory pages. It should be noted for the MTA858XX

products that because bit 8 (nint h bit) of PC is c l eared

in CALL instruction or any instruction which writes to

the PC (e.g., MOVWF PC), all subroutine calls or com-

puted jumps are limited to the first 256 locations of any

progr am memor y page ( 51 2 words long).

Incrementing the program coun te r when i t is pointing to

the last address of a selected memory page is also

possible and will cause the program to contin ue in the

next page. However, the page pre-select bits in the

STATUS register will not be changed and the next

GOTO, CALL, ADDWF PC, MOVWF PC instruction will

return to the previous p age unless the p age pre-select

bits have been updated under program control. For

example, a NOP at locat ion 1FFh (page 0) increments

the PC to 200h (page 1). A “GOTO xxx” at 200h will

return the program to address “ xxx” on page 0 (a ssum-

ing that the page preselect bits in the STATUS register

are '0').

Upon a RESET condition, page 0 is pre-selected while

the program counter addresses the last l ocation in the

last page. Thus, a GOTO instructi on at this location wi ll

automatically cause th e program to continue in page 0.

Note: The MTA854XX devices only ha ve a single

page, page 0 (Figure 4-1).

 1995 Microchip Technology Inc. DS40115C-page 9

MTA85XXX

4.3 Stack

The MTA85XXX employs a two-l evel hardware PUSH/

POP stack (Figure 4-1 and Figure 4- 2).

The CALL instruction pushes the current program

counter value, incremented by one, into stack le vel 1.

Stack level 1 is automatically pushed to level 2. If more

than 2 subsequent CALLs are executed, only t h e most

re cent two r eturn addr esses are store d.

The page preselect bits of the STATUS register will be

loaded into the most significant bits of the program

counter. The ninth bit is always cleared upon a CALL

instruction. This means that subroutine entry

addresses have to be lo cat ed always within the lower

half of a memory page (addresses 000h-0FFh, 200h-

2FFh, 400h-4FFh, 600h-6FFh). However, as the stack

has the same width as the PC, subroutines can be

called from anywhere in the program.

The RETLW instructio n loads the conte nts of the stack

level 1 into the program counter while stack leve l 2 gets

copied into le vel 1. If more than 2 subsequent RETLWs

are executed, the stack will be filled with the address

previously stored in lev el 2. The return will be alway s to

the page from where the subroutine was called,

re gardle ss of the current s etting of the page pre-select

bits in the STA TUS register . Note that the W register will

be loaded with the literal valu e specified in t he RETLW

instruction. This is particularly useful for the

implementation of “data” tables within the program

memory.

FIG URE 4-1: PROGRAM ME MORY

ORGANIZATION MTA854XX

Page 0

000

0FF

100

1FF

18 S tack Level 1

S tack Level 2

RETLW, CALL

9-bit

A8 A<7:0>

GOTO... Direct from instruction word

CALL, Inst with PC as Destination ... Always '0'

GOTO, CALL ... Direct from Instruction Word

Inst with PC as Destination .. . From ALU

FIGURE 4-2: PROGRA M MEMO RY

ORGANIZATION MTA858XX

Pag e 0

000

0FF

100

1FF

St a c k Le ve l 1

St a c k Le ve l 2

RETLW,

9-11 bit

A8 A<7:0>

GOTO - Direct from instruction WORD

CALL, Inst with PC as Destination -

GOTO, CALL - Direct from Instruction WORD

Inst wi th PC as Destination - From ALU

A9A10 CALL

GOTO, CALL, Inst with P C as destination -

from P A1 (STATUS<6>) (Note1)

GOTO, CALL, Inst with PC as destina tion -

from P A0 (STATUS<5>) (Note1)

Always '0'

Pag e 1

200

2FF

300

3FF

Pag e 2

400

4FF

500

5FF

Pag e 3

600

6FF

700

7FF

Ma x EPROM

Address for :

PIC16C54A

PIC16C58A

/CR58A

Note 1: PIC16C58A/CR58A only.

MTA85XXX

DS40115C-page 10  1995 Microchip Technology Inc.

5.0 DATA MEMORY AND

OPERATIONAL REGISTER

FILES

For MTA854XX devices, there are seven special

function registers (operational register files) and 25

general purpose registers. Data addresses 00h-06h

are reserved for the operational register files,

addresses 07h-1Fh are used for the general purpose

file registers. FSR bits (STATUS <6:5>) are not u sed.

For MTA858XX devices, there are seven special

function register (operational register files) and

73 general purpose registers. These registers are

mapped according to Figure 5-1. Note that several

address blocks are mapped to the same physical

re gi st ers. To address t he banked registers (addresses

above 0Fh) bits (STATUS <6:5>) of the FSR are used.

FIG URE 5-1: DAT A M EMORY MA P

General

Purpose

File

A10 TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC (**)

A9 A8

CALL

RETLW STACK 1

OPTION

TRISA

TRISB

TRISC

From Program Memory

To and from

re gi st er fil e

via ALU

STACK 2

10 9 8 7 6 5 4 3 2 1 0 10 9 8 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

5 4 3 2 1 0

7 6 5 4 3 2 1 0

File

Address

Bit 6, 5 o f FSR: Bank Select

(C58A, CR58A Only)

01 10 11

50 70

General

Purpose

File

(All Types)

General Purpose

(C58 A, CR58 A Only)

(Bank 0) (***) (Bank 1) (***) (Bank 2) (***) (Bank 3) (***)

3F 5F 7F

(*) Not a ph ysical ly imple men ted regist er. See Section 4 .5 for det ails.

(**) File address 7h is a ge neral purp ose registe r on the PIC16C54 A, and PIC16C58 A/CR 58A.

(***) Bank 0 is ava ilable on al l mi crocontro llers while Bank 1 , Ban k 2, and Bank 3 a re only available on th e

C58A, CR58A. (Section 4.5).

INDF (*)

 1995 Microchip Technology Inc. DS40115C-page 11

MTA85XXX

5.1 Data Memory Organization

The 8-bit data bus connects two basic functional ele-

ments together: the register f ile composed of up to 80

addressable 8-bit registers including the I/O ports, and

an 8-bit wide Arithmetic Logic Unit (ALU). 32 bytes of

RAM are directly addressable while a “banking”

scheme, with banks of 16 bytes each, is employed to

address larger data memories (Figure 5-1). Data can

be addressed directly, o r indirec tly using the F ile Select

ported by special “literal” instructions which load data

from program memory into the W register.

The register file is divided into two functional groups:

Special Function regist ers and General Purpose regis-

ters. The special function re gi sters include the Timer0

(TMR0) register, the Program Counter (PC), the Status

used for data and control informat ion under comma nd

of the instructions.

In ad dition, s pecial purpose registers are u sed to con-

trol the I/O port configuration and prescaler options.

5.1.1 GENERAL PURPOSE REGISTER FILE

The register file is accessed either directly or indirectl y

thro ugh the file select register FSR.

5.1.2 SPECIAL FUNCTION REGISTERS:

The Special Function Registers are registers used by

the CPU and peripheral f u nctions to control t he opera-

tion of the device (Table 5-1).

The special registers can be classified into two sets.

The special registers associated with the “core” func-

tions are d escribed in this sec tion. Those related to the

operation of the peripheral features are described in

the sectio n for ea ch per ipheral feature.

TABL E 5-1: PI C16C5X REG ISTER FILE SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-On

Reset

Value on

MCLR and

WDT resets

00h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----

01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu

02h PCL Low order 8 bits of PC 1111 1111 1111 1111

03h STATUS PA2 PA1 PA0 TO PD ZDCC0001 1xxx 000? ?uuu

04h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu

05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

07h PORTC 2RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxx x xx xx uuuu uuuu

Le gend: x = un kno wn, u = un ch a nged . - = uni m pl e m ente d, read as '0 ' .

Note 1: The upper byte of the program counter is not directly accessible. The upper bits can be set or cleared by writing to

PA1 :PA0 (STATUS< 6: 5>).

2: File address 7h is a general purpose register on the PIC16C54A and PIC16C58A/CR58A.

3: Shading indicates unimplemented bits.

MTA85XXX

DS40115C-page 12  1995 Microchip Technology Inc.

5.2 Indirect Data Addres sing (INDF ) f0

This is not a physically implemented register.

Addressing INDF calls for the contents of the File

Select Register to be used to select a file register. The

INDF register is useful as an indirect address pointer.

For example, in the instruction ADDWF INDF, W will

add the contents of the r egi ster pointe d to by the FS R

to the content of the W Register and place the result in

If INDF itself is read through indirect addressing

(i.e., FSR = 0h), then 0 0h i s read. I f the INDF r egister

is writ ten to via indir ect ad dressing, the result will be a

no operation (NOP).

5.3 Rea l Time Clo ck/ Cou nter Reg ister

(T0CKI) f 1

This register can be loaded and read by the program as

any other register. In addition, its contents can be

incremented by an external signal edge applie d to the

T0CKI pin or by the internal instruction cycle clock

(CLKOUT = FOSC/4). Figure 5-2 is a simplified block

diagram of the T0CKI module.

An 8-bit prescaler can be assigned to the T0CKI by

writing the proper v alues to the PSA bit and the PS bits

in the OPTION register. The OPTION register is a

special register (not mapped in data memory)

addressable using the OPTION instruction

(Se ction 6.4). If the prescaler is assigned to the T0CKI,

instructions writing to the T0CKI register (e.g., CLRF

T0CKI, or B SF T0 CKI, 5,...etc.) clear the prescaler.

The bit RTS (T0CKI Signal Source) in the OPTION

internally or externally.

RTS = 1: The clock source for the T0CKI or the

prescaler, if assigned to it, is the signal on the T0CKI

pin. Bit4 of the OPTION register (RTE) determines if an

increment occurs on the falling (RTE = 1) or rising

(RTE = 0) edge of the signal presented to the T0CKI

pin.

RTS = 0: The T0CKI register or its prescaler,

respectively, will be incremented with the internal

instruction clock (= FOSC/4). The RTE bit in the

OPTION register an d th e T0CKI pin are "don't care" in

this case. However, the T0CKI pin must not be left

floating (tie to VDD or VSS). This prevents unintended

operation and to reduce the current consumption in

low-power applications.

As long as clocks are applied to the T0CKI (from

internal or external source, with or without prescaler),

the T0CKI register keeps incrementing and just rolls

over when the value FFh is reached. All increment

pulses for the T0CKI register are delayed by two

instruction cycles. After writing to the T0CKI register,

for example, no increment takes place for the following

two instruction cycles. This is independent if internal or

external clock source is selected. If a prescaler is

as si gned to the T0CKI, the output of the pr escaler will

be delayed by two cycles before the T0CKI re gi st er is

incremented. This is true for instructions that either

write to or read-modify-write T0CKI (e.g., MOVF

T0 CKI, CL RF T0 CK I). For applications whe re T0CKI

needs to b e tested for '0' without affecting its count, use

of the MOVF T0CKI, W instruction is recommended.

Timing diagrams in Figure 5-3 and Figure 5-4 show

T0CKI read, write and increment timi ng.

5.3.1 USING T0CKI WITH EXTERNAL CLOCK

When external clock input is used for T0CKI, it is

synchronized with internal phase clocks. Therefore,

external clock input must meet certain requirements.

Also there is some delay from the occurrence of the

external clock edge to the actual incrementing of

T0CKI. Referring to Figure 5-5, the synchronization is

done after the prescaler. Output of the prescaler is

sampled twice in every instruction cycle to detect rising

or falli ng edges. Therefore, it i s necessary for PSOUT

to be high for at least 2 TOST and low for at least 2 TOSC

where:

TOSC = oscillator time period.

When no prescaler is used, PSOUT (Prescaler output,

Figure 5-3) is the same as T0CKI clock input and,

therefore, the re quirements are:

TRTH = T0CKI high time ≥ 2 TOSC + 20 ns

TRTL = T0CKI low time ≥ 2 TOSC + 20 ns

When prescaler is used, the T0CKI input is di vided by

the asynchronous ripple counter-type prescaler so t he

prescaler outp ut is symmetrical.

Then:

PSOUT high time = PSOUT low time =

where T RT = T0CKI input period and N = prescale valu e

(2, 4, ...., 256).

The requir ement is, therefore,

≥ 2 TOSC + 20 ns, or

The user will notice that no requirement on T0CKI high

time or low time is specified. However, if the high time

or l ow time on T0CKI i s too small, then th e pulse m ay

not be detected. Hence, a minimum hig h or low time of

10 ns is required. In summary, the T0CKI input

requi rements are:

TRT = T0CKI period ≥ (4 TOSC + 40 ns)/N

TRTH = T0CKI high time ≥ 10 ns

TRTL = T0CKI low time ≥ 10 ns

Delay from external clock edge: Since the prescaler

output is synchronized with the internal clocks, there is

a small delay from the time the external clock edge

occurs to the time the T0CKI is actually incremented.

This delay is between 3 TOSC and 7 TOSC (Figure 5-5).

Thus, for example, measu ring the interval between two

edges (e.g., period) will be accurate within ±4 TOSC

(±200 ns @ 20 MHz).

N • TRT

4 TOSC + 40 ns

TRT ≥

 1995 Microchip Technology Inc. DS40115C-page 13

MTA85XXX

FIGURE 5-2: T0CKI BLOCK DIAGRAM (SIMPLIFIED)

FIGURE 5-3: T0CKI TIMING: INT CLOCK/NO PRESCALE

FIGURE 5-4: T0CKI TIMING: INT CLOCK/PRESCALE 1:2

FIG URE 5-5: T0 CKI TIMING WITH EX TERNAL CLOCK

Note 1: Bits, RTE, RTS, PS2, PS1, PS0 an d PSA are locat ed in t h e OPTION register.

Note 2: T he prescaler is shared with Wat chdog Timer.

T0CKI

RTE

RTS

fOSC/4

Programmable

Prescaler

Sync with

Internal

clocks T0CKI (8)

PSout

(2 cycl e delay)

Data bus

PSA

PS2, PS1, PS0

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

T0CKI

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

RT RT+1 RT+2 NRT NRT NRT+1 NRT+2 NRT+3 T0

MOVW F T0CKI MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W

Write T0CKI

executed Read T0CKI

reads NRT Read T0CKI

reads NRT+1 Read T0CKI

reads NRT+2 Read T0CKI

reads NRT+3

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

T0CKI

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

RT NRT+1

MOVWF T0CKI MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W MOVF T0CKI,W

Write T0CKI

executed Read T0CKI

reads NRT Read T0CKI

reads NRT + 1

RT+1 NRT

INCREMENT T0CK I (Q4)

EXT CLOCK INPUT OR Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

T0CKI RR + 1R + 2

Sm a ll pu ls e

misses sampling

EXT CLOCK/PRESCALER

OUTPUT AFTER SAMPLING (note 3)

Delay from clock input change to T0CKI increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC).

Ther efo re, the error in me asuri ng the inter va l b et wee n two edge s on T0CKI inpu t = ± 4 TOSC ma x i mum.

Externa l cloc k if no prescaler selecte d, Pre scaler outp ut other wise.

The arro w s indi ca te th e poin t s in time where sam p ling oc curs .

Notes:

PRESCALER OUT (NOTE 2)

MTA85XXX

DS40115C-page 14  1995 Microchip Technology Inc.

5.4 P ro gram Counter (PC) f2

See Section 4.2

5.5 Stack

See Section 4.3

5.6 Status Word Register (STATUS) f3

This register contains the arithmetic status of the ALU,

the RESET status.

The STATUS register can be destination for any

instru ction like any other register. However, the status

bits are set aft er the fol lowing write. Furthermore, TO

and PD bits are not writable. Therefore, the result of an

instruction with STATUS register as destination may be

different than intended. For example, CLRF STATUS

will clear all bits except for TO and PD and the n s et the

Z bi t and leave STATUS register as 000uu100 (where

u = unchanged).

It is recommended, therefore, that only BCF, BSF and

MOVWF instructions are used to alter the STATUS

registers because these instructions do not affect any

status bit.

For other instructions, affecting any status bits, see

Section "Instruction Set Summary" (Table 9-1).

FIGURE 5-6: STATUS WORD REGI STER

C: Carry/borrow bit.

For ADDWF and ADDLW instructions.

1 =

0 =

A carry-out from the most significant bit of the result occurred

Note that a subtraction is executed by adding the two's

complement of the second operand. For rotate (RRF, RLF)

instructions, this bit is loaded with either the high or low order bit

of the source register.

No carry-out from the most signifi cant bit of the result

DC: Digit carry/borr o w bit

For ADDWF and ADDLW ins t ruc ti o ns .

1 =

0 =

Z: Zer o bit

1 =

0 =

PD: Power down bit

1 =

0 =

TO: Time-out bit

1 =

0 =

PA1:PA0: Two general purpose read/write bits for MTA854XX

PA2 PA1 PA0 TO PD ZDCC

bit0

R/W R/W R/W R R R/W R/W R/W

bit7

A carry-out from the 4th low order bit of the result occurred

No carry-out from the 4th low order bit of the result

The result of an arithmetic or logic operation is zero

The result of an arithmetic or logic operation is not zero

After power-up or by a CLRWDT instruction

By execution of the SLEEP instruction

After power-up and by the CLRWDT and SLEEP instruction

A watchdog timer time-out has occurred

PA2: Genera l purpose re ad/write bit

TO, PD are uniquely set or cleared

W: Writable

R: Readable

U: Unimplemented,

read as '0'

Address:

POR value:

Note: For borrow the polarity is reversed.

In MTA858XX these are page select bits.

(reserved for future use)

 1995 Microchip Technology Inc. DS40115C-page 15

MTA85XXX

5.6.1 CARRY/BORROW AND

DIGIT CARRY/BORROW BITS:

The carry bit (C) is a carry out in addition operation

(ADDWF) and a borrow out in subtract operation

(SUBWF).

It is also affected by RRF and RLF instructions. The

following examples explain carry/ borrow bit operation:

;SUBWF Example #1

;

clrf 0x1f ;f(1fh)=0

movlw 1 ;wreg=1

subwf 0x1f ;f(1fh) =f(1fh)- wreg

;=0-1=FFh

;Carry=0: Result is

;negative

;

;SUBWF Example #2

movlw 0xFF ;

movwf 0x1F ;f(0x1F)=FFh

clrw ;wreg=0

subwf 0x1F ;f(0x1F)=f(0x1F)- wreg

;=FFh-0=FFh

;Carry=1:Result is

;positive

;

The digit carry operates in the same way as the carry

bit, (i.e., it is a bo rrow in a subtract operation).

5.6.2 TIME OUT AND PO WER DOWN STATUS

BITS (TO, PD)

The TO and PD bits (STATUS<4:3>) can be tested to

determine if a RESET condition has been caused by a

Watchdog Timer time-out, a power-up condition, or a

wake-up from SLEEP by the Watchdog Timer or MCLR

pin.

Thes e status bits are only affected by events listed in

Table 5-2.

TABLE 5-2: EVENTS AFFECTING TO/PD

STATUS BITS

Event TO PD Remarks

Power-Up 11

No eff ec t on PD

WDT Time-out 0x

SLEEP instruct ion 10

CLRWDT instruction 11

Note 1: A WDT time-out will occur regardless of the

status of the bit TO. A SLEEP instructi on

will be executed, regardless of the status of

the PD bit. Table 5-3 refle cts the statu s of

TO and PD after the corresponding event.

TABL E 5-3: TO/PD STATUS AFTER

RESET

5.6.3 PROGRAM PAGE PRESELECT FOR

MTA858XX

Bits (STATUS <6:5>) ar e defined as page address bits

PA1:PA0 and are used to preselect a program memory

page. When executing a GOTO, CALL, or an instruc-

tion with PC as destination (e.g., MOVWF PC), PA1:PA0

are loaded into bit A10:A9 of the program counter,

selecting one of the available program mem ory pages.

The direct address specified in the instruction is only

valid within this particular memory page.

RETLW instructions do not change the page preselect

bits.

Upon a RESET condition, PA2:PA0 are cleared to '0's.

5. 7 File Select Reg ister (FS R) f4

Bits (STATUS <4:0>) select one of th e 32 available file

registers in the indirect addressing mode (that is,

calling for the INDF register in any of the file oriented

instructions).

Bit7 of the FSR is read-only and is a lway s read as a '1'.

If no indirect addressing is used, the FSR can be used

as a 5-bit wide general purpose regi ster.

Bits (S TATUS <6:5 >) of the FSR wi ll always read as a

'1' for MTA854XX devices. For MTA858XX products,

bits (STATUS <6:5>) of the FSR will sele ct the current

data memory bank (Figure 5-1).

The lower 16 bytes of each bank are physically

identical and are always selected when bit4 of the FSR

(in case of indirect addres sing) is '0', or bit4 of the direct

file register address of the currently executing

instruction is '0' (e.g., M OVW F DA TAMEM).

Only if bit4 in the above mentioned cases is '1',

(STATUS <6:5>) of the FSR select one of the four

available register banks with 16 bytes each

(MTA858XX only).

TO PD Reset was caused by

WDT wake-up from SLEEP

WDT time-out (not during SLEEP)

MCLR wake-up from SLEEP

Power-up

Low pulse on MCLR input

Note 1: The TO and PD bit maintain th eir status (u)

until an event of Table 5-2 occur s. A low

pulse on the MCLR input does not change

the T O and PD status bits.

MTA85XXX

DS40115C-page 16  1995 Microchip Technology Inc.

5.8 I/O Registers (Ports)

The I/O registers can be written and read under

program control like any other register of the register

file. However, "read" instructions (e.g., MOVF

PORTB,W) alwa ys read t he I/O pins, regardless if a pin

is defined as "input" or "output." Upon a RESET, all I/O

ports are defined a s "input" (= hi im pedance mode) as

the I/O control registers (TRISA, TRISB) are all set to

'1's.

The execution of a "TRIS f" instruction with

corresponding ’0’s in the W register is necessary to

define any of the I/O pins as output.

5.8.1 PORTA f5

4-bit I/O register. Low-order 4-bit s only are used (RA3:

RA0). Bits (STATUS <7:4>) are unimplemented and

read as '0's.

5.8.2 PORTB f6

8-bit I/O regist er. Note that RB7 i s tied to SE E VDD on

MTA85XIX devices.

5.8.3 I/O INTERFACING

The equivalent circuit for an I/O port bit is shown in

Figure 5-7. All ports may be used for both input and

output operations. For input operations these ports are

non-latching. Any input must be present until read by

an input instructi on (e.g., MOVF PORTB, W). The o ut-

puts are latched and remain unchange d until the output

latch is rewritten. To use a port pin as output, the

corresponding direction control bit (in TRISA, TRISB)

must be set to '0'. For use as an input, the

corre sponding TRIS bit must be '1'. Any I/O pin can be

programmed individually as an i nput or outp ut.

FIG URE 5-7: EQUI VALE NT CIRCUIT FOR A SINGLE I/ O PIN

FIG URE 5-8: I/O PORT REA D/WRIT E TIMING

CK Q

VDD

VSS

I/O Pin

From

Data

Bus

Write

To Data Bus

From

W-Register

TRIS f

"Read"

Reset

Data

Latch Q1

CK Q

Set

I/O

Control

Latch

Note:

This example shows a write to PORTB

followed by a read from PORTB.

Note that:

data setup time = (0.25 TCY - TPD)

where TCY = instruction cycle.

Therefore, at higher cl ock fre quencies,

a write followed by a read may be problematic.

TPD = propagation delay

PC PC + 1 PC + 2 PC + 3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

fetched

RB7:RB0>

MOVW F PORTB

write to

PORTB NOP

Port pin

sampled here

NOP

MOVF PORTB,W

Instruction

executed

MOVW F PORTB NOP

Read PORTB

TPD

Execute MOVF PORTB,W

Execute Execute

 1995 Microchip Technology Inc. DS40115C-page 17

MTA85XXX

5.8.4 BIDIRECTION AL I/O PORTS

Some instructions operate internally as read followed

by wr ite operations. The BCF and BSF i n structions, for

example, read the entire port into the CPU, exec ute the

bit operation, and re-output the result. Caution must be

used when these instructions are applied to a port

where one or more pins are used as input/outputs.

For example, a BSF operation on bit5 of PORTB will

cause all eight bits of PORTB to be read into the CPU.

Then the BSF operation takes place on bit5 and

PORTB is re-output to the output latches. If another bit

of PORTB is used as a bidirectional I/O pin (say bit0)

and it is defined as a n input at this t ime, the input signal

present on the pin i tself would b e read into the CPU and

re-written to the data latch of this particular pin, over-

writing the previous content. As long as the pin stays in

the input m ode, no problem occurs. However, if bit0 is

switched into output mode l ater on, the co nt ent of the

data latch may now be unknown.

A pin actively outputting a '0' or '1' should not be driven

from external devices at the same time in order to

change the level on this pin ("wired-or", "wired-and").

The resulting high output currents may damage the

chip.

5.8.5 SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port will happen at the end of

an instruction cycle, whereas fo r readin g, the data must

be valid at the beginning of the instruction cycle

(Figure 5-8). Therefore, care must be exercised if a

write foll ow ed by a read operat ion is carried out on the

same I/O port. The sequence of instructions should be

such to allow the pin voltage to stabilize (load

dependent) before the next instruction which causes

that file to be read into the CPU is executed. Otherwise,

the previous state of that pin may be read into the CPU

rather th an the new state. When in doubt, it is better to

separate these instructions with a NOP or an other

instruction not accessing this I/O port.

MTA85XXX

DS40115C-page 18  1995 Microchip Technology Inc.

6.0 SPECIAL PURPOSE

REGISTERS

6.1 W (Worki ng) Register

Holds second o perand in two op erand ins tructions and/

or supports the internal dat a transfer.

6. 2 TRIS A I/ O Control Register For

PORTA

Only bits (STATUS <3:0>) are available. The

corre sponding I/O port (f5) is only 4-bit wide.

6.3 T RIS B I/O Con trol Regi ster Fo r

PORTB

The I/O control registers will be loaded with the content

of the W register, by e xecuting of the TRIS f instruction.

A '1' in the I/O control register will put the correspon ding

I/O pin into a high impedance mod e. A '0' puts the con-

tents of file register PORTA or PORTB, respectively,

out on the selected I/O pins.

These registers are "write-only" and are set to all '1's

upon a RESET.

6.4 OPTION Pre scal er/T0CKI OP TI ON

Defines prescaler assignment (T0CKI or WDT),

prescaler value, signal source and signal edge for the

T0CKI. The OPTION register is "write-only" and is 6-

bits wide.

By executing the OPTION instruction, the contents of

the W register will be transferred to the OPTION

re gister. Upon a RESET, the OPTION register i s set.

FIG URE 6-1: OPTION R EGISTER

PSA PS2 PS1 PS0

U U R/W R/W R/W R/W R/W R/W

bit0

— — RTS RTE

bit7

PS2 PS1 PS0

PSA: Prescaler assignment bit

RTE: T0CK I signal edge

RTS: T0CK I signal source

PRESCALER VALUE

1 : 2

1 : 4

1 : 8

1 : 1 6

1 : 3 2

1 : 6 4

1 : 1 28

1 : 2 56

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Address:

POR value: 111111b

W: Writable

R: Readable

U: Unimplemented.

Read as '0'

T0CKI RATE WDT RATE

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to T0CKI

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

PS2:PS0

111

Unimplemented: reads as 0

 1995 Microchip Technology Inc. DS40115C-page 19

MTA85XXX

7.0 RESET CONDITION

A RESET can be caused by applying powe r to the chip

(power-up), pulling the MCLR input "low" or by a

Watchdog Timer time-out. The device will stay in

RESET as long as the Oscillator Start-Up Timer (OST)

is active or the MCLR input is "low."

The Oscillator Start-Up Timer is activated as soon as

MCLR input is sensed to be high. This implies that in

cas e of Power-On Reset (POR) with MCLR tied to VDD

the OST starts from power-up. In case of WDT time-

out, it will star t at the e nd of t he time- o ut (sinc e MCLR

is high). In cas e of MCLR reset, the OST will start when

MCLR goes high. The nominal OST time-out period is

18 ms. See Section 12.0 for detailed information on

OST and Power-On Reset.

During a RESET the state of the microcontroller is

defined as:

a) The oscillator is running or will be started

(p ower-up or wake-up from SLEEP).

b) All I/O port pins (RA3:RA0 and RB7:RB0) are

put into the hi impedance state by setting the

TRIS registers to all '1's (= input mode).

c) The Program Counter is set to all '1's.

d) The OPTION register is set to all '1's.

e) The Watchdog Timer and its prescaler are

cleared.

f) The upper-three bits (page select bits) in the

STATUS Register are cleared.

g) RC mode only: The CLKOUT signal on the

OSC2 pin is held at a"low" level.

TABL E 7-1: RES ET CONDITION FOR REG ISTERS

Registe r Addre ss Power-on Reset

MCLR Reset during:

- normal operation

- SLEEP

WDT time-out

during normal

operation

Wake up from

SLEEP through

WDT time-out

W—

xxxx xxxx uuuu uuuu uuuu uuuu

OPTION — 0011 1111 0011 1111 0011 1111

INDF 00h ———

T0CKI 01h xxxx xxxx uuuu uuuu uuuu uuuu

PC 02h 1FFh MTA854XX

7FFh MTA858XX 1FFh MTA854XX

7FFh MTA858XX

STATUS 03h 0001 1xxx 000? ?uuu uuu? ?uuu

FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu

PORTA 05h xxxx xxxx uuuu uuuu uuuu uuuu

PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu

Legend: u = unchanged, x = unknown, reads as '0', ? = value depends on condition.

MTA85XXX

DS40115C-page 20  1995 Microchip Technology Inc.

8.0 PRESCALER

An 8-bit counter is available as a prescaler for the

T0CKI, or as a post-scaler for the Watchdog Timer.

(Figure 8-1). For simplicity, this counter is being

referred to as "prescaler" throughout this data sheet.

Note that there is only one prescaler available which is

mutually exclusively shared between the T0CKI and

the Watchdog Timer. Thus, a pre scaler assignment for

the T0CKI means that there is no prescaler for the

Watchdog Timer, and vice-versa.

The PSA and PS0-PS2 bits in the OPTION register

determine the prescaler assignment and pre-scale

ratio. When assigned to the T0CKI, all instructions

writing to the T0CKI (e.g., CLRF T0CKI, MOVWF

T0CKI, BSF T0CKI,x . ...etc.) will clear the prescaler.

When assigned t o WDT, a CLRWDT instruction will clear

the prescaler along with the Wat chdog Timer.

8.1 Switching Prescaler Assignment

Changing prescaler from T0CKI to WDT

The prescaler assignment is fully under software

control, (i.e., it can be changed "on the fly" during

program execution). To avoid an unintended device

RESET, the following instruction sequence must be

executed when changing the prescaler assignment

from T0CKI to WDT:

1. MOVLW 'xx0x0xxx'b ; Select internal

; clock and select new

2. OPTION ; prescaler value. If

; new prescale value

; is = '000' or '001',

; then select any

; other prescale

; value temporarily.

3. CLRF 1 ; Clear T0CKI and

; prescaler.

4. MOVLW xxxx1xxx'b ; Select WDT, do not

; change prescale

; value.

5. OPTION ;

6. CLRWDT ; Clears WDT and

; prescaler.

7. MOVLW 'xxxx1xxx'b ; Select new prescale

; value.

8. OPTION ;

Steps 1 and 2 are only required if an external T0CKI

source is us ed. Steps 7 and 8 are n ecessary only if the

desired prescale value is '000' or '001'.

Changing prescaler from WDT to T0CKI

To change prescaler from WDT to T0CKI use the fol-

lowing sequence:

1. CLRWDT ; Clear WDT and

; prescaler.

2. MOVLW 'xxxx0xxx'b ; Select T0CKI, new

; prescale value

; and clock source

3. OPTION ;

FIG URE 8-1: BL OCK DIA GRAM T0C KI/WDT PR ESCAL ER

T0CKI

RTE

CLKOUT (= Fosc/4)

SYNC

Cycles T0CKI

8-bit Counter

8 - to - 1MUX

M U X

Watchdog

timer

PSA

WDT

Time-out

PS2:PS0

Not e: RTS , RT E, PSA, PS2 -PS0 are bit s

PSA

WDT Enable

Data Bus

PSA

RTS

in the OPTION register.

EEPROM Fuse

 1995 Microchip Technology Inc. DS40115C-page 21

MTA85XXX

9.0 BASIC INSTRUCTION SET

SUMMARY

Each instruction is a 12-bit word divided into an

OPCODE which specifies the instruction type and one

or more operands which further specify the operation of

the instruction. The Instruction Set Summary in

Table 9-1 lists byte-oriented, bit-oriented, and literal

and control operations.

For byte-oriented instructions, 'f' represents a file

designator. The fi le re gister designator speci fies which

one of the file registers is to be utilized by the

instruction.

The destination design ator specifies where the result of

the operation is to be placed. If 'd' is '0', the result is

placed in t he W register. If 'd' is '1', the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, 'b' represents a bit field

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

file in which the bit is located.

For literal and control operations, 'k' represents an

eight or nine bit constant or literal value.

All instructions are executed within one single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of an

instruction. In this case, the execution takes two

instruction cycles. One instruction cycle consists of four

oscillator periods. Thus, for an oscillator frequency of

4 M Hz, the normal instruction e xecution t ime is 1 µs. If

a conditional test is true or the program counter is

changed as a result of an instruction, the instruction

execution time is 2 µs.

Notes to Table 9-1

Note 1: T he ninth bit of th e program count er will be

forced to a '0' b y an y instr uctio n that writ e s

to the PC except for GOTO (e.g., CALL,

MOVWF PC, ...etc.). See Section 5.6.3

for details.

Note 2: When an I/O register is modifi e d as a func -

tion of itself (e.g., MOVF PORTB,1), the

value used will be that value present on the

pins themselves. For example, if the data

latch is '1' for a pin con figured as output and

is driven low by an external device, the data

will be written back with a '0'.

Note 3: T he instru ction "TRIS f", where f = PORTA,

PORTB, or PORTC causes the contents of

the W register to be written to the three-

state latches of the sp ecified file (port). A '1'

forces th e pin to a hi im pedance state and

disables the output buffers.

Note 4: If this instruct ion is execut ed on the T0CKI

prescaler will be cleared if assigned to the

T0CKI.

MTA85XXX

DS40115C-page 22  1995 Microchip Technology Inc.

TABL E 9-1: INSTRUCT ION SET SUMMARY

BYTE-ORIE NTED FILE REGISTER OPERATIONS

Ins truc tion -Bina ry (Hex) Nam e Mnemonic,

Operands Operation Sta tus

Affected Notes

0001 11df ffff 1Cf Add W and f ADDWF f, d W + f → d C,DC,Z 1,2,4

0001 01df ffff 14f AND W and f ANDWF f, d W ∧ f → dZ2,4

0000 011f ffff 06f Clear f CLRF f 0 → f Z 4

0000 0100 0000 040 Clear W CLRW - 0 → WZ

0010 01df ffff 24f Complement f COMF f, d f → dZ2,4

0000 11df ffff 0Cf Decrement f DECF f, d f -1 → dZ2,4

0010 11df ffff 2Cf Decrement f,Skip if Zero DECFSZ f, d f - 1 → d , ski p if zero None 2,4

0010 10df ffff 28f Increment f INCF f, d f + 1 → dZ2,4

0011 11df ffff 3Cf Increm ent f,Skip if zero INCFSZ f, d f + 1 → d, skip if zero None 2,4

0001 00df ffff 10f Inclusive OR W and f IORWF f , d W ∨ f → dZ2,4

0010 00df ffff 20f Move f MOVF f, d f → dZ2,4

0000 001f ffff 02f Move W to f MOVWF f W → f None 1,4

0000 0000 0000 000 No Operati on NOP - - None

0011 01df ffff 34f Rotate left f RLF f, d f(n) → d(n+1), C → d(0), f(7) → CC 2,4

0011 00df ffff 30f Rotate right f RRF f, d f(n) → d(n -1), C → d(7), f(0) → CC 2,4

0000 10df ffff 08f Subtract W from f SUBWF f, d f - W → d [f + W + 1 → d] C,DC,Z 1,2,4

0011 10df ffff 38f Swap halve s f SWAPF f, d f(0-3) ↔ f(4-7) → d None 2,4

0001 10df ffff 18f Exclusive OR W and f XORWF f, d W ⊕ f → dZ2,4

BIT-ORIENTED FILE REGISTER OPERATIONS

Ins truc tion -Bina ry (Hex) Nam e Mnemonic,

Operands Operation Sta tus

Affected Notes

0100 bbbf ffff 4bf Bit Clear f BCF f, b 0 → f(b) None 2,4

0101 bbbf ffff 5bf Bit Set f BSF f, b 1 → f(b) None 2,4

0110 bbbf ffff 6bf Bit Test f,Skip if Clear BTFSC f, b Test bit (b) in file (f): Skip if clear None

0111 bbbf ffff 7bf Bit Test f, Skip if Set BTFSS f, b Test bit (b) in file (f): Skip if set None

LITERAL AND CONTROL OPERATIONS

Ins truc tion -Bina ry (Hex) Nam e Mnemonic,

Operands Operation Sta tus

Affected Notes

1110 kkkk kkkk Ekk AND Literal and W ANDLW k k ∧ W→ WZ

1001 kkkk kkkk 9kk Call subroutine CALL k PC + 1 → Stack, k → PC None 1

0000 0000 0100 004 Clear Watchdo g t imer CLRWDT - 0 → WDT (and presc aler, if assigne d) TO, PD

101k kkkk kkkk Akk Go To address (k is 9 bit) GOTO k k → PC (9 bits) None

1101 kkkk kkkk Dkk Incl. OR Literal and W IORLW k k ∨ W → WZ

1100 kkkk kkkk Ckk M ove Literal to W MOVLW k k → W None

0000 0000 0010 002 Load OPTION register OPTION - W → OPTION register None

1000 kkkk kkkk 8kk Return,place Literal in W RETLW k k → W, Stack → PC None

0000 0000 0011 003 Go into standby mode SLEEP - 0 → WDT, stop oscillator TO, PD

0000 0000 0fff 00f Tri-State port f TRIS f W→ I/O control register f None 3

1111 kkkk kkkk Fkk Excl. OR Literal and W XORLW k k ⊕ W → WZ

Note 1: S ee previous p age.

OPCODE d f(FILE #)

(11-6) (5) (4-0)

d = 0 for destination W

d = 1 for destination f

OPCODE b(bit #) f(FILE #)

(11-8) (7-5) (4-0)

OPCODE k(literal)

(11-8) (7-0)

 1995 Microchip Technology Inc. DS40115C-page 23

MTA85XXX

10.0 WATCHDOG TIMER (WDT)

The watchdog timer is realized as a free running on-

chip RC oscill ator which does not require any external

components. This RC oscillator is separate from the

RC oscillator of the O SC 1/CLKIN pin. That means that

the WDT will run even if the clock on the OSC1/CLKIN

and OSC2/CLKOUT pins of the device have been

stopped (i.e., by executing the SLEEP instruction).

During normal operation a WDT time-out generates a

device RESET. If the device is in SLEEP mode, a WDT

time-out causes the device to wake-up and continue

with normal operation. The WDT can be permanently

disabled by programming the configuration bit WDTE

as a '0'.

10 .1 W DT Pe rio d

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). These periods vary with temperature,

VDD and process variations from part to part (see DC

specifications). If longer t ime-out periods are desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by

writin g to the OPTION register. Thus, time-out periods

up to 2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the postscaler (if assigned to the WDT) and pre-

vent it from timing out and gen erating a d evice RESET.

The TO bit (STATUS<4>) will be cleared upon a WDT

time-out.

10 .2 W DT Prog ram m ing Con si dera tions

At worst case conditions (VDD = Min., Temperature =

Max., max. WDT prescaler) it may take several

seconds before a WDT time-out occurs .

FIG URE 10-1: WATCHDOG TI MER BLOCK DIAGR AM

TABL E 10-1: SUM MARY OF REGISTERS ASSO CIAT ED WITH THE WAT CHDOG TIMER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Co nfig. Word CP CP CP CP CP WDTE FOSC1 FOSC0

OPTION — — T0CS T0SE PSA PS2 PS1 PS0

Note 1: CP7:CP4 are u sed by the PIC16CCR58A only. Unused in all other devices.

2: Sh aded cells are not used by the Watchdog Timer.

From TMR0 Clock Source

(Figure 6-6)

To TMR0 (Figure 6-6)

Postscaler

Note: PSA and PS2:PS0 are bits in the OPTION register.

WDT Enable

EPROM Fuse PSA

WDT

Time-out

PS2:PS0

PSA

MUX

8 - to - 1 MUX

Postscaler

Watchdog

Timer

MTA85XXX

DS40115C-page 24  1995 Microchip Technology Inc.

1 1.0 OSCILLATOR

CONFIGURATIONS

11.0.1 OSCILLATOR TYPES

The PIC16C5X can be operated in four different

oscillator modes. The user can program two

configuration bits (FOSC1:FOSC0) to select one of

these four modes:

• LP: L ow Power Crystal

• XT: Crystal/Resonator

• HS: High Speed Crystal/ Resonator

• RC: Resistor/Capacitor

11.0.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 11-1). The

PIC16C5X oscillator design requires the use of a

parallel cut crystal. Use of a series cut crystal may give

a frequency out of the crystal manufacturers

specifications. When in XT, LP or HS modes, the device

can have an external clock source drive the OSC1/

CLKIN pin (Figure 11-2).

FIGURE 11-1: CRYSTAL /CERAMIC

RES ONA T OR OPE RATI ON

(HS, X T OR LP OSC

CONFIGURATION)

FIGURE 11-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

O SC MO DE )

Note: The MTA854XX operates at 4 MHz and

the MTA858XX operates up to 10 MHz.

See Table 11-1 and Table 11-2 for recommended

values of C1 a nd C2.

Note 1: A series resistor may be re quired for AT

strip cut crystals.

XTAL

OSC2

Note1

OSC1

RF SLEEP

To internal

logic

PIC16C5X

Clock from

ext. system OSC1

OSC2PIC16C5X

Open

TABL E 11-1: C APACITOR SELECTION

FOR CERAMIC RESONATORS

TABL E 11-2: CAP ACITO R SELECT ION

FOR C RY ST AL OS CI LL ATO R

Osc

Type R esonator

Freq. Cap. Range

C1 Cap. Range

XT 4 55 kHz

2.0 MHz

4.0 MHz

22-100 pF

15-68 pF

22-100 pF

15 - 68 pF

HS 8.0 MHz 10-68 pF 10- 68 pF

These values are for design guidance only. Since

each re sonator has its own char acteristi cs, the user

should consult the resonator manufacturer for

appropriate values of external component s.

Osc

Type Resonator

Freq. Cap. Range

C1 Cap. Range

LP 32 kHz†

200 kHz 33-68 pF

15-47 pF 33 - 68 pF

15 - 47 pF

XT 100 kHz

2 MHz

4 MHz

47-100 pF

15-33 pF

10-33 pF

47-100 pF

15 - 33 pF

10 - 33 pF

HS 8 MHz 1 5-47 pF 15-47 pF

† For VDD > 4.5V, C1 = C2 ≈ 30 pF is r ecommended.

These values are for design guidance only. Rs may

be required in HS mode as well as XT mode to avoid

overdriving crystals with low drive level specification.

Since each crystal has its own characteristics, the

user should consult the crystal manufacturer for

appropriate values of external component s.

 1995 Microchip Technology Inc. DS40115C-page 25

MTA85XXX

11.1 External Crystal Osc illato r cir cui t

A prepackaged oscillator can be used or a simple

os ci llator circ ui t with TTL gates can be built. Prep ac k-

aged oscillators provide a wide operating range and

better stability. A well-designed crystal oscillator will

provide good performance with TTL gates. Two types

of crystal oscillator circuits can be used; one with series

resonance, or one with paral lel resonance.

Figure 11-3 shows implementation of a parallel

resonant oscillator circuit. The ci rcu it is designed to us e

the fundamental frequency of the crystal. The 74AS04

inverter performs the 180-degree phase shift that a par-

allel oscillator requires. The 4.7 kΩ resistor provides

the n egati ve feedback for stability. The 10 kΩ potenti-

ometers bias the 7 4AS04 in the linear region. This cir-

cuit c ould b e used f or ext ern al os cillat or designs.

FIGURE 11-3: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR C IRCUIT

Figure 11-4 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the cryst al. The inverter perform s a 180°

phase shift in a series resonant oscillator circuit. The

330 Ω re sistors pr ovide the negative f eedback to bias

the inverters in their l inear region.

FIGURE 11-4: EXTERNAL SERIES

RESONANT CRYSTAL

O SCILLATOR CIRCUIT

20 pF

+5V

20 pF

10k 4.7k

10k

74AS04

XTAL

10k

74AS04 PIC16C5X

CLKIN

To Other

Devices

330Ω

74AS04 74AS04 PIC16C5X

CLKIN

To Other

Devices

XTAL

330Ω

74AS04

0.1 µF

11.1.1 RC OSCILLATOR

For timing insens itive app lications the RC device option

offers additional cost savings. RC oscillator frequency

is a function of the supply voltage, the resistor (Rext)

and capacitor (Cext) values, and the operating temper-

ature. In addition to this, the oscillator frequency will

vary from unit to unit due to normal process parameter

variation. Furthermore, the difference in lead frame

capa citance between package types will also affect the

oscillation frequency, especially for low Cext values.

The user also needs to take into account variati on due

to tolerance of external R and C components used.

Figure 11-5 shows how the R/C combination is con-

nected to the PIC16C5X. For Rext values below 2.2

kΩ, the oscillator operation may become unstable, or

stop completely. For v ery high Rext values (e.g., 1 MΩ)

the oscillator becomes se nsitive to noise, humidity and

leakage. Thus, we recommend keeping Rext b et ween

3kΩ and 100 k Ω.

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or pack-

age lead frame capacitance.

Se e Secti on 15.0 for RC fr equency variatio n f rom p ar t

to part du e to normal process variation. The var iation is

larger for larger R (since leakage current variati on will

affect RC frequency more for large R) and for smaller

C (since variation of input capacitance will affect RC

frequency more).

See Section 15.0 for variation of oscillator frequency

due to VDD for given Rext/Cext values as well as

frequency variation due to operating temperature for

given R, C, a nd VDD values.

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin, and can be used for test

purposes or to synchronize other logic.

FIGURE 11-5: RC OSCILLATOR MODE

VDD

Rext

Cext

VSS

OSC1 Internal

clock

OSC2/CLKOUT

Fosc/4

PIC16C5X

MTA85XXX

DS40115C-page 26  1995 Microchip Technology Inc.

12.0 RESET

The PIC1 6C5X differentiates between various kinds of

re sets:

• Power-On R eset (POR)

• MCLR res et during normal operation

• MCLR reset during SLEEP

• WDT time-out reset

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in all

other resets. Most other registers are reset to a “reset

state” on Power-On Reset (POR), MCLR or a WDT

reset. Note that the PIC16C5X does not differentiate

between a WDT reset during SLEEP or during normal

operation. The TO and PD bits are set or cleared

depe nding upo n th e re set situation (Table 12-1). These

bits may be used to determi n e the nature of the reset.

See Table 12-3 for a full description of rese t states of all

registers.

Figure 12-1 shows the simplif ied block diagr am of the

on-chip reset circuit.

12.1 Power-On Reset (POR) and Device-

Reset Timer (DRT)

12.1.1 POWER-ON RESET (POR)

The PIC16C5X famil y incorporate s an on-chip Power-

On Reset (POR) circuitry which provides an internal

chip reset for most power-up situations. To use this fea-

ture the u ser merely needs to tie t h e MC LR/VPP p in to

VDD. Figure 12-8 shows the electrical structure of

TMR0 inputs. The Power-On Reset circuit and the

Device Reset Timer circuit are closely related. On

power-up the reset latch is set and the DRT is reset.

The DRT timer begins counting on ce it detects MCLR

to be high. After the time-out period, which is t ypically

18 ms, it will reset the r eset-latch and thus end the on-

chip reset signal.

Figure 12-2 and Figure 12-3 are two power-up

situations with relatively fast rise time on VDD. VDD is

allowed to rise and stabilize (Figure 12-2) before

bringing MCLR high. The chip will actually come out of

reset (T DRT msec) aft er MCLR g oes high. The on-chip

Power-On Reset feature (Figure 12-3) is being used

(MCLR and VDD are tied toge ther). VDD i s stable before

the start-up timer t imes out a nd there is no pr oblem in

getting a proper reset. Figure 12-4 depicts a potentially

problematic situation where VDD rises too slowly. In this

situation, when the start-up timer times out, VDD has

not reached the V DD (min) value and the c hip is, th e re -

fore, not guaranteed to function correctly.

To summ arize, the on-chip POR is guaranteed t o work

if the rate of rise of VDD is no slower than 0.05V/ms, and

VDD starts from 0 V. The o n-chip POR ti me delay is t oo

short for low frequency crystals which require much

longer than 18 ms to start-up and stabilize. For such si t-

uations, we recommend that external RC circuits be

used to achieve longer POR delay ti mes.

FIG URE 12-1: ON-CHIP RESE T CI RCUIT BLOCK DIAGRAM

VDD

MCLR/VPP pin

Power-Up

Detect

On-Chip

RC OSC

POR (Power-On Reset)

WDT Time-out

RESET

CHIP RESET

8-bit Async

Ripple Counter

(Start-up Timer)

 1995 Microchip Technology Inc. DS40115C-page 27

MTA85XXX

12.1.2 DEVICE RESET TIMER ( DRT)

The Device Reset Timer provides a fixed 18 ms

nominal time-out on RESET. The Device Reset Timer

operates with an internal RC oscillator. The processor

is kept in RESET as long as the DR T is active. The DR T

delay allows VDD to rise above VDD min., and allows

the oscillator to stabilize.

Oscillator circuits based on crystals or ceramic

resonators require a certain time after power-up to

establish a stable oscillation. The on-chip DRT keeps

the device in a RESET condition for approximately

18 ms after the voltage on the MCLR/VPP pin has

reached a logic high (VIHMC) level. Thus, external RC

networks connected to the MCLR input are not required

in most cases, allowing for savings in cost-sensitive

and/or space rest ricted applications.

The Device Re set time delay will vary from chip to chip

and due to VDD, temperature, and process variation.

The DRT will also be tr igger ed upon a WDT time- out.

This is particularly imp or tant for applications using the

WDT to waken the PIC16C5X from SLEEP

automatically.

12.1.3 TIME-OUT SEQUENCE

Table 12-2 lists the reset conditions for the special

function registers while Table 12-3 lists the reset

conditions for all the registers.

TABLE 12-1: TO/PD STATUS AFTER

RESET

TO PD RESET was caused by

WDT wake-up from SLEEP

WDT time-out (not durin g SLEEP)

MCLR wake-up from SLEEP

Power-up

= Low pulse on MCLR input

The TO and PD bits maintain their status (u) until a

reset occurs. A low-pulse on the MCLR input does

not change the TO and PD status bit s.

TABL E 12-2: RESET CONDITIONS FOR SPECIAL REGISTERS

Condition STATUS

A ddr: 03h PCL

Addr: 0 2h

Power-On Reset 0001 1xxx 1111 1111

MCLR res et during normal operation 000u uuuu(1) 1111 1111

MCLR reset during SLEEP 0001 0uuu 1111 1111

WDT reset during SLEEP 0000 0uuu 1111 1111

WDT reset during normal operation 0000 1uuu 1111 1111

Lege nd: u = u ncha n ge d, x = u nkno wn , - = un impl eme nte d rea d as '0 '.

Note 1: The TO and PD bit s retain their last value unt il one of the other reset condit ions occur.

2: The CLRWDT instruction will set the TO and PD bits

TABL E 12-3: RE S ET CONDITI ONS FO R ALL REGI STER S

Registe r Address Pow er-on Reset MCLR or WDT Reset

W N/A xxxx xxxx uuuu uuuu

TRIS N/A 1111 1111 1111 1111

OPTION N/A --11 1111 --11 1111

INDF 00h — —

TMR0 01h xxxx xxxx uuuu uuuu

PCL 02h 1111 1111 1111 1111

STATUS 03h 0001 1xxx 000? ?uuu (1)

FSR 04h xxxx xxxx uuuu uuuu

PORTA 05h ---- xxxx ---- uuuu

PORTB 06h xxxx xxxx uuuu uuuu

PORTC 07h xxxx xxxx uuuu uuuu

General Purpose

Legend: u = unchanged, x = unknown, - = unimplemented read as '0', ? = value depends on condition.

Note 1: See Table 12-2 for reset value for specific conditions.

MTA85XXX

DS40115C-page 28  1995 Microchip Technology Inc.

FIG URE 12-2: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): Case 1

FIG URE 12-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): Case 2

FIG URE 12-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIE D TO VDD)

TDRT

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

TDRT

VDD

MCLR

INTERNAL P OR

DRT TIME-OUT

INTERNAL RESET

TDRT

 1995 Microchip Technology Inc. DS40115C-page 29

MTA85XXX

FIGURE 12-5: EXTERNAL POWER -ON

RES E T CIRCUIT (FOR SLOW

VDD POWER-UP )

Note 1: External Power-On Reset circuit is

required onl y if VDD power-up is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not

exceed 0.2V (max lea kage c urrent spec on

MCLR pin is 5 µA). A larger voltage drop

will degrade VIH level on the MC LR/VPP

pin.

3: R1 = 100Ω to 1 kΩ will limit an y current

flowin g into MCLR from external capacitor

C in the event of MCLR/VPP pin breakdown

due to ESD or EOS.

MCLR

PIC16C5X

VDDVDD

FIGURE 12-6: BROWN-OUT PROTECTION

CIRCUI T 1

FIGURE 12-7: BROWN-OUT PROTECTION

CIRCUI T 2

This circuit will activate reset when VDD goes

below Vz + 0.7V (where Vz = Zener voltage).

33k

10k

40k

VDD

MCLR

PIC16C5X

VDD

This brown-out circuit is less expensive, although

less accurate. Transistor Q1 turns off when VDD

is below a certain level such that:

VDD • R1

R1 + R2 = 0.7V.

R2 40k

VDD

MCLR

PIC16C5X

VDD

FIGURE 12-8: ELECT RICAL STRUCTUR E OF THE MCLR/VPP AND T0CKI PINS

VSS

RIN

Schm itt Trigger

MCLR/VPP N

T0CKI pins Input Buffer

and

MTA85XXX

DS40115C-page 30  1995 Microchip Technology Inc.

13.0 POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set , the PD

bit (STATUS<3>) i s cleared, and th e os cillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low, or hi-impedance).

It shoul d be noted that a RESET generated by a WDT

time-out d oes not dri ve the MCLR /VPP pin l ow.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

MCLR/VPP pin must be at a logic high level (VIHMC).

13.0.1 WAKE-UP FROM SLEEP

The device can wake from SLEEP through one of the

following events:

1. An external reset input on the MCLR/VPP pin.

2. A WDT time-out reset (if WDT was enabled).

Both of the se events cause a d evice reset. The TO an d

PD bits can be used to determine the cause of device

reset. The TO bit is cleared if a WDT time-out occurred

(and caused wake-up). The PD bit, which is set on

power-up, is cleared when SLEEP is invoked.

The WDT is cleared when the device wakes from

SLEEP, regardles s of the w ake-up source.

 1995 Microchip Technology Inc. DS40115C-page 31

MTA85XXX

14.0 CONFIGURATION FUSES

The configuration EPROM consists of four EPROM

fuses.

Two are for the selection of the oscillator type, one is

the watchdog timer enable fuse and one is the code

protection fuse.

FIG URE 14-1: CONFIGURAT ION WORD

14.1 ID Locations

Four memory locations are designated as ID locations

where the user can store check sum or other code-iden-

tification numbers. These locations are not accessible

during normal e xecution but are readable and writable

during program/ verify.

Use only the lower 4 -bits of the ID locations an d always

progr am the upper 8-bits as '1's.

* Note: Microchip will assign a unique pattern

number for QTP and SQTP requests and

for ROM devices . This p attern number will

be unique and traceable to the submitted

code.

CP WDTE OT1 OT0 Register: FUSES

Address: N/A

bit0

protected

OT1:OT0: OSC selection fuses

11: RC oscillator

10: HS oscillator

01: XT oscillator

00: LP oscillator

WDTE: WDT enable fuse

1 = WDT enabled

0 = WDT disabled

CP: Code protection fuse

1 = Code protection off

0 = All memory is code

Unimplemented

14.2 Code Protec tion

The code in the program memory ca n be protected by

clearin g the code protect bits.

In code protected mode, the configuration word will not

be protected, allowing reading of all bits.

14.2.1 PIC16C54A AND PIC16C58A

Once code pr otected, all memor y locations read out in

a scrambled fashion. For EPROM devices, program

memory locations 40h and above cannot be further

programmed. However, the first 64 locations, 00h -

3Fh, may be programmed. These locations are not

considered secure.

14.2.2 PIC16CR58A

In a protected device, pro gram memory locations 00h-

3Fh read out normally. Locations 40h and higher

cannot be read out.

MTA85XXX

DS40115C-page 32  1995 Microchip Technology Inc.

15.0 ELECTRICAL CHARACTERISTICS

15 .1 Ab sol ute M axi mum Ratin gs*

Ambient temperature under bias. .. ..........................................................................................................-55°C to +125°C

Storage Temperature............................. ................. ................. ...................... ................. ................. ....... -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR). .. ..... .. ........ .. ....... ... ..... .. ... .... ... .....-0. 6V to (VDD + 0.6V)

Voltage on VDD with respect to VSS ............................... ...................... ...................... ...................... ............... 0 to +7.5V

Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V

Total power Dissipation (Note 1) ....................................................................................................... ..... ..............800 mW

Maximum Curre nt out of VSS pi n. .................................................................. ........................................................ 150 mA

Maximum Curre nt into VDD pin................................................................................................................................50 mA

Maximum Current into an input pin..................................................................................................................................± 500 µA

Maximum Output Curr ent s u nk by any I/O pin.... ....................................................................................................25 mA

Maximum Output Current sourced by any I/O pin................................................................................................... 20 mA

Maximum Output Current sourced by a singl e I/O port (PortA or B).......................................................................40 mA

Maximum Output Current sunk by a single I/O port (PortA or B)............... ............................. ................................50 mA

Note 1: Total power dissipation should not exceed 800 mW for the package. Power di ssipation is calculated as fol-

lows: Pdis = VDD x {I DD - ∑ IOH} + ∑ {( V DD-VOH) x IOH} + ∑(VOL x IOL)

Note 2: V oltag e spikes b elow VSS at the MCLR pin, inducing currents greater than 80 mA, may cau se latch-up. Thus,

a seri es resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling

this pin directly to VSS.

TABL E 15-1: CRO SS REFERE NCE OF DEVICE SPECS FOR OS CILLAT OR CONF IGURATI ON S

AND FREQ UE NCIE S OF OPERATI ON (COM M ER CIAL DEV ICES)

* Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a st ress rating only and functional operation of the device at thos e or any other c onditions

above those indicated in the operation listings of this specification is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliabili ty.

OSC PIC16C54A-04

RC VDD: 3.0V to 6.25V

IDD: 2.4 mA max. at 5.5V

IPD: 4 µA max. at 3.0V WDT di s

Freq: 4 MHz max.

XT VDD: 3.0V to 6.25V

IDD 2.4 mA max. at 5.5V

IPD: 4 µA m ax. at 3.0V WDT dis

Freq: 4 MHz max.

HS VDD: 4.5V to 5.5V

IDD: 2. 4 m A t yp . at 5.5 V

IPD: 0.25 µA typ. at 3.0V WDT dis

Fre q: 4 MHz ma x.

LP VDD: 3.0V to 6.25V

IDD: 14 µA typ. at 32kHz , 3.0 V

IPD: 0.25 µA typ. at 3.0V WDT dis

Freq: 200 kHz max.

* Note: The shaded sections indicate oscillator

selections which are tested for functionalit y,

but not for MIN/MAX specifications. It is

recommended that the user select the

device type that guarantees the

specifications required.

 1995 Microchip Technology Inc. DS40115C-page 33

MTA85XXX

15 .2 DC Cha racteri sti cs

TABL E 15-2: DC CHARACTE RISTICS OF MICROCONT ROL LER MTA 854X X-04 (INDUS TRIAL)

DC CHARACTERISTICS

Power Supply Pins Standard Operat ing Conditions

Operating temperature -40°C≤ TA ≤ +85°C for industrial

Characteristic Sym Min Typ* Max Units Conditions

Supply Volta ge VDD 3.0

4.5 6.25

5.5 V

VXT, RC and LP options

HS option

RAM Data Retention

Volta ge (Note 3) VDR 1.5 V Device in SLEEP mode

VDD start voltage to

guarantee Power-On Reset VPOR VSS V See POR section in microcontroller dat a sheet

for details on Power- On Reset

VDD rise rate to guarantee

Power-On Reset SVDD 0.05* V/ms See POR sect ion in microcontroller dat a sheet

for details on Power- On Reset

Supply Current (Not e 2) IDD 1.8 2.4 mA XT and RC options (C-04)

FOSC = 4 MHz, VDD = 5.5V

5.8 13 mA HS option (C-10)

FOSC = 10 MHz, V DD = 5.5V

17 70 µALP option, Industrial, EEPROM standby

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

Power Down Current (Note 4)

WDT enabled

WDT disabled IPD 5

13 14

5µA

µAVDD = 3.0V, Industrial

VDD = 3.0V, Industrial

* These parameters are characterized but not tested.

Note 1: Data in the column labeled "Typ" is based on characterization results at 25°C. These parameters are for

design guidance only and are not tested for, or guaranteed by Micr ochip Technology.

Note 2: T he supply curre nt is mainly a function of the operating voltage and frequency. Other factor s such as bus

loading, oscillator ty pe, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1= external square wave, from rail to rail; all I/O pins tr istat ed, pulled to VDD, RT = VDD,

MCLR = VDD; WDT enabled/ disabled as specified; EEPROM in write c o ndition (e xcept LP mode).

b) For standby current m easurements, the conditio ns are the same, except that the device is in S LEEP

mode a nd SDA and SCL are tied to VSS.

Note 3: T his is th e limit to which VDD can be lowered in SLEEP mode without losing RAM data.

Note 4: T he power down cur rent in SLEEP mode does not depend on the oscill ator type. Power down c urrent is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS;

SDA and SCL tied to VSS.

Note 5: Does not include current through Rext. The current through the resistor can be estimated by the formula

Ir = VDD/2Rext ( mA) with R ext in kΩ.

MTA85XXX

DS40115C-page 34  1995 Microchip Technology Inc.

TABL E 15-3: DC CHARACT ERISTICS OF MICROCONT ROL LER MTA858X X-04 (INDUS TRI AL)

MTA858XX-10 (INDUSTRIAL)

DC CHARACTERISTICS

Power Supply Pins Standard Operat ing Conditions

Operating temperature -40°C≤ TA ≤ +85°C for industrial

Characteristic Sym Min Typ* Max Units Conditions

Supply Volta ge VDD 3.0

4.5 6.25

5.5 V

VXT, RC and LP options

HS option

RAM Data Retention

Volta ge (Note 3) VDR 1.5 V Device in SLEEP mode

VDD start voltage to

guarantee Power-On Reset VPOR VSS V See POR section in microcontroller dat a sheet

for details on Power-On Reset

VDD rise rate to guarantee

Power-On Reset SVDD 0.05* V/ms See POR sect ion in microcontroller dat a sheet

for details on Power-On Reset

Supply Current (Not e 2) IDD 1.8 2.4 mA XT and RC options (C-04)

FOSC = 4 MHz, VDD = 5.5V

5.8 13 mA HS option (C-10)

FOSC = 4 MHz, VDD = 5.5V

17 40 µALP option, Industrial, EEPROM standby

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

Power Down Current (Note 4)

WDT enabled

WDT disabled IPD 5

0.8 14

12 µA

µAVDD = 3.0V, Industrial

VDD = 3.0V, Industrial

* These parameters are characterized but not tested.

Note 1: Data in the column labeled "Typ" is based on characterization results at 25°C. These parameters are for

design guidance only and are not tested for, or guaranteed by Microchip Technology.

Note 2: T he supply curre nt is mainly a function of the operating voltage and frequency. Other factor s such as bus

loading, oscillator ty pe, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements i n active operation mo de are:

OSC1= external squar e wave, from rail to rail; all I /O pin s tr istated, p ulled to VDD, except RB7 driving ' 1'

for SEE VDD, RT = VDD, MCLR = VDD; WDT enabled/disabled as specified; EEPROM in write condition

( except LP mode).

b) For standby current m easurements, the conditio ns are the same, except that the device is in S LEEP

mode and SDA and SCL are tied to VSS.

Note 3: T his is th e limit to which VDD can be lowered in SLEEP mode without losing RAM data.

Note 4: T he power down cur rent in SLEEP mode does not depend on the oscill ator type. Power down c urrent is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS;

SDA and SCL tied to VSS.

Note 5: Does not include current through Rext. The current through the resistor can be estimated by the formula

Ir = VDD/2Rext ( mA) with R ext in kΩ.

 1995 Microchip Technology Inc. DS40115C-page 35

MTA85XXX

TABL E 15-4: DC CHARACT ERISTICS OF INPUTS/OUTPUTS : MTA8 54X X-04 (INDUSTRIAL)

MTA858XX-04 (INDUSTRIAL)

MTA858XX-10 (INDUSTRIAL

DC CHARACTERISTIC S

All Pins Except Power Supply Standard Operati ng Conditions

Operating temperatur e -40°C≤ TA ≤ +85 °C for industrial

Characteristic Sym Min Typ Max Units Conditions

Input Low Voltage

I/O p orts VIL VSS 0.2 VDD V Pin at hi-impedance

MCLR (Schmitt tri gger) VSS 0.15 VDD V

T0CKI (Schmitt trigger) VSS 0.15 VDD V

O SC1 (Schmit t trigger) V ss 0.1 5 VDD V RC option only (Note 5)

OSC1, SCL Vss 0.3 VDD V X T, HS and LP options

Input High Voltage

I/O p orts VIH 0.45 VDD

2.0

0.36VDD

VDD

For all VDD (Note 6)

4.0V < VDD ≤ 5.5V (Note 6)

VDD > 5.5V

MCLR (Schmitt trigger) 0.85 VDD VDD V

T0CKI (Schmitt trigg er) 0.85 VDD VDD V

OSC 1 (Schmitt trigger) 0.85 VDD VDD V RC optio n only (Note 5)

OSC1, SCL 0.7 VDD VDD V X T, HS, and LP options

Inp ut Leakage Current (Note 4)

I/O p orts IIL -1 0.5 +1 µAVSS ≤ VPIN ≤ VDD, Pin at hi-im pedance

MCLR -5 µAVPIN = VSS + 0.25V (Note 3)

MCLR 0.5 +5 µAVPIN = VDD (Note 3)

T0CKI -3 0.5 +3 µAV

SS ≤ VPIN ≤ VDD

OSC1 -3 0.5 +3 µAVSS ≤ VPIN ≤ VDD

SDA, SCL -10 10 µA XT, HS and LP options

O utput Low Voltage

I/O p orts VOL 0.6 V IOL = 8.7 mA, VDD = 4.5V

OSC2/CLKOUT

(RC optio n only) 0.6 V IOL = 1.6 mA, VDD = 4.5V

SDA 0.4 V IOL = 3.0 mA, VDD = 3.0V

O utput High Volt age

I/O ports ( Note 4) VOH VDD-0.7 V IOH = -5.4 mA, VDD = 4.5V

OSC2/CLKOUT

(RC option only) VDD-0.7 V IOH = -1.0 mA, VDD = 4.5V

Note 1: Data in “Typ” colum n is based on characterizati on results at 25°C. These parameters are for design guidance

only and are not te ste d for, or guaranteed by M icrochip Technology.

Note 2: Total power dissipation as stated under absolute maximum ratings must not be exceeded.

Note 3: The leakage current on the MCLR pin is strongly depende n t on the applied voltage level. The sp ecified levels

represen t normal operating conditions. Higher leakage current may be measured at different input voltages.

Note 4: Negative current is defined as coming out of the pin.

Note 5: In RC oscillator mode, the OSC1 pin is a Schmitt trigger input. It is not recommended that the mi crocontroller

be driven with external clock in RC mode.

Note 6: The user may use better of t h e two specifi cations.

MTA85XXX

DS40115C-page 36  1995 Microchip Technology Inc.

15 .3 AC Cha racteri sti cs

TABL E 15-5: AC CHARACT ERISTICS OF MICROCONT ROL LER: MTA8 54X X-04 (INDUSTRIAL)

MTA858XX-04 (INDUSTRIAL)

MTA858XX-10 (INDUSTRIAL)

AC CHARACTERISTICS Standard Operating Condi tions

Operating temperature -40°C≤ TA ≤ +85°C for industrial

Characteristic Sym Min Typ Max Units Conditions

External C LOCKIN

Frequency (Note 2) FOSC DC

MHz

kHz

RC mode

XT mode

HS mode ( Com/Ind) (Note 5)

LP mode

O sci llat or Frequency (Note 2) FOSC DC

0.1

MHz

kHz

RC mode

XT mode

HS mode ( Com/Ind) (Note 5)

LP mode

Instruction Cycle Time (Note 2) TCY 1.0

1.0

0.2

100

4/Fosc DC

µs

RC mode

XT mode

HS mode (Note 5)

LP mode

External Clock in Timing (Note 4)

Clock in (OSC1) High or Low time

XT oscillator type TCKHLXT 50* ns

LP oscillator type TCKHLLP 2* µs

HS oscillator type TCKHLHS 20* ns

Clock in (OSC1) Rise or fall time

XT oscillator type TCKRFXT 25* ns

LP oscillator type TCKRFLP 50* ns

HS oscillator type TCKRFHS 25* ns

RESET Timing

MCLR Pulse Width (low) TMCL 100* ns

T0CKI Input Ti ming, No prescaler

T0CKI High Pulse Width TRTH 0.5 TCY+20* ns Note 3

T0CKI Low Pulse Width TRTL 0.5 TCY+20* ns Note 3

* Guaranteed by character i zation but not tested.

Note 1: Data in the column labeled "Typ" is based on characteriza tion results at 25°C. This data is f or design guidan ce

only and i s not t ested for, or guaranteed by Microchip Technology.

Note 2: I n struction cycle period (TCY) equals four times th e input oscill ator time base perio d. All specified values are

based o n characterization data for that particular oscillator ty pe under stan dard operating conditions with th e

device executi ng code. Exceeding these specified limits may result in unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at "minimum" values with an

external clock applied to the OSC1 pin. When an external clock input is used, the "maximum" cycle time limi t

is "DC" (no clock) for all devices.

Note 3: For a detailed explanation of T0CKI input clock requirements see microcontr oller data sheet Section 5.2.1.

Note 4: Clock-in high-time is the durat ion for which clock input is at VIHOSC or higher.

Clo ck-in low-tim e is t he duration for which clock input is at VILOSC or lower.

Note 5: This HS specification is only for the -20 device. The -10 device has a maximum of 10 MHz and the -04 device

has a maximum of 4 MHz.

 1995 Microchip Technology Inc. DS40115C-page 37

MTA85XXX

T0CKI Input Timing,

Wi th pres cal er

T0CKI High Pulse Width TRTH 10* ns Note 3

T0CKI Low Pulse Width TRTL 10* ns Note 3

T0CKI period TRTP TCY +40*

Nns Note 3. Where N = prescale

value (2,4,...,256)

Watchdog Timer Time-out Period,

No prescaler TWDT 9* 18* 30* ms VDD = 5.0V

Oscillation Start-up Timer Period TOST 9* 18* 30* ms VDD = 5.0V

I/O Tim ing

I/O pin input val id before

CLKOUT↑ (RC mode) TDS 0.25 TCY+30* ns

I/O Pin input hold aft er CLKOUT↑

(RC mode) TDH 0* ns

I/O pin output valid after CLKOUT↓

(RC Mode) TPD 40* ns

I/O pin input valid before OSC↑

(I/O setup time) TioV2osHTBD ns

OSC1↑ to I/O pin inpu t invalid

(I/O holdup time) TosH2ioLTBD ns

OSC1↑ to I/O pin output valid TosH2ioVTBD ns

I/O pin output rise t ime TioRTBD ns

I/O pin output fall time TioFTBD ns

Capacitive loading specs on

output pins

OSC2 pin COSC215pF

In Xt, HS or LP modes when

external clock is used to drive

OSC1

All I/O pins CIO 50 pF E xcludes RB7 on MTA85X1X

devices

AC CHARACTERISTICS Standard Operating C ondi tions

Operating temperature -40°C≤ TA ≤ +85°C for industrial

Characteristic Sym Min Typ Max Units Conditions

* Guaranteed by character i zation but not tested.

Note 1: Data in the column labeled "Typ" is based on characteriza tion results at 25°C. This data is f or design guidan ce

only and i s not t ested for, or guaranteed by Microchip Technology.

Note 2: I n struction cycle period (TCY) equals four times th e input oscill ator time b ase perio d. All specified values are

based o n characterization data for that particular oscillator ty pe under stan dard operating conditions with th e

device executi ng code. Exceeding these specified limits may result in unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at "minimum" values with an

external clock a pplied to the OSC1 pin. When an external clock input is used, the " maximum" cycle t ime limi t

is "DC" (no clock) for all devices.

Note 3: For a detailed explanation of T0CKI input clock requirements see microcontr oller data sheet Section 5.2.1.

Note 4: Clock-in high-time is the durat ion for which clock input is at VIHOSC or higher.

Clock-in low-time is the duration for which clock input is at VILOSC or lower.

Note 5: This HS specification is only for the -20 device. The -10 device has a maximum of 10 MHz and the -04 device

has a maximum of 4 MHz.

MTA85XXX

DS40115C-page 38  1995 Microchip Technology Inc.

TABL E 15-6: AC CHARACTE RISTICS OF EEPROM

AC CHARACTERISTICS

Parameter Symbol

Stan dard Mode VCC = 4.5-5.5V

Fast Mode Units Remarks

Min Max Min Max

Clock frequency FCLK 01000400kHz

Clock high tim e THIGH 4000 — 600 — ns

Clock low time TLOW 4700 — 1300 — ns

SDA and SCL rise time TR— 1000 UF 300 ns Note 2

SDA and SCL fall time TF— 300 UF 300 ns Note 2

START condition hold time THD:STA 4000 — 600 — ns Aft er this period th e first clock

pulse is generated

START condition setup time TSU:STA 47 00 — 6 00 — n s Only rele vant for repeated

STAR T condition

Data input hold time THD:DAT 0 — 0 — ns Note 1

Data input setup time TSU:DAT 250 — 100 — ns

STOP condition setup time TSU:STO 4000 — 600 — ns

O utput valid from clock TAA — 3500 — 900 ns Note 1

Bus free time TBUF 4700 — 1300 — ns Time the bus must be free

before a new transmission can

start

Output fall time from VIH minimum to

VIL maximum TOF — 250 20+0.1

CB250 ns Note 2, CB ≤ 100 pF

In put filter spike suppre ssion

(SDA and SCL pins) TSP N/A N/A 0 50 ns Note 3

Write cycle time TWR — 10 — 10 ms Byte or Page mode

Endurance — 100,000 — 100,000 — E/W

cycles

Note 1: As a transmitter, the de vice must provide an internal minimum delay time to bridge the undefined reg ion (minimum

300 ns) of th e falling edge of SCL to avoid unintended generation of START or STOP conditions.

Note 2: Not 100% tested. CB = total capacitance of one bus line i n pF.

Note 3: The combined TSP and VHYS specificati o ns are due to new Schmi tt trigger inputs which provide improved noise

spike suppression. This eliminates the need for a TI specification for standard operation.

15 .4 El ectri cal S tructure of Pi ns

FIG URE 15-1: ELE C TRICAL S TRUCTURE OF

I/O PINS (RA, RB)

VDD

VSS

RIN Input

Buffer

I/O pin

VSS

FIG URE 15-2: ELE C TRICAL S T RUCTURE OF

MCLR AND T0C KI PINS

VSS

RIN

Schmitt Trigger

MCLR,N

T0CKI Input Buffer

Notes to Figure 15-1 and Figure 15-2: The diodes and the grounded gate (or output driver) NMOS device are carefully

desig ned to protect against ESD (Electrostatic discharge) and EOS (Electr ical overstress). RIN is a small resistance to

further protect the input buffer from ESD.

 1995 Microchip Technology Inc. DS40115C-page 39

MTA85XXX

15.5 Timing Diagrams

FIG URE 15-3: LOAD CONDITIONS

VSS

CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or

LP modes when external clock

is used to drive OSC1.

MTA85XXX

DS40115C-page 40  1995 Microchip Technology Inc.

FIG URE 15-4: EXTERNAL CLOCK TIMING

TABL E 15-7: E XTE RNAL CLOCK TIMING REQ UIRE M ENTS

P arame ter

No. Sym Characteristic Min Typ† Max Units Conditions

Fosc External CLKIN Frequency

(No te 1) DC — 4 MHz XT and RC osc mode

DC — 4 MHz HS osc mode (PIC16C5XA-04)

DC — 10 MHz HS osc mode (PIC16C5XA-10)

DC — 20 MHz HS osc mode (PIC16C5XA-20)

DC — 200 kHz LP osc mode

Oscillator Frequency

(No te 1) DC — 4 MHz RC osc mode

0.1 — 4 MHz XT osc mode

4 — 4 MHz HS osc mode (PIC16C5XA-04)

4 — 10 MHz HS osc mode (PIC16C5XA-10)

4 — 20 MHz HS osc mode (PIC16C5XA-20)

5 — 2 00 kHz LP osc mode

OSC External CLKIN Period

(No te 1) 250 — — ns XT and RC osc mode

250 — — ns HS osc mode (PIC16C5XA-04)

100 — — ns HS osc mode (PIC16C5XA-10)

50 — — ns HS osc mode (PIC16C5XA-20)

5.0 — — µs LP osc mode

Oscillator Period

(No te 1) 250 — — ns RC osc mod e

250 — 10,000 ns XT osc mode

250 — 250 ns HS osc mode (PIC16C5XA-04)

100 — 250 ns HS osc mode (PIC16C5XA-10)

50 — 250 ns HS osc mode (PIC16C5XA-20)

5—200 µs LP osc mo de

CY Instruction C y cle Time (Note 1 ) 1.0 — DC µs

3 TosL, TosH Clock in (OSC1) Low or High Time 50 — — ns XT oscillator

2.5 — — µs LP oscillator

10 — — ns HS oscillator

4 To sR, To sF Cloc k i n (OSC1) Rise or Fall Ti me 25 — — ns XT o scillato r

50 — — ns LP oscillator

15 — — ns HS oscillator

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. Th ese parameters are for design guida nce only

and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are

based on character ization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

high er than expected current consumption. All devices are tested to operate at “min." values with an external

clock applied to the OSC1/CLKIN pin.

When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

 1995 Microchip Technology Inc. DS40115C-page 41

MTA85XXX

FIGURE 15-5: CL K OUT AND I/O TIMING

TABL E 15-8: CLKOUT AND I /O TIMING REQUIREMENTS

P arame ter

No. Sym Characteristic Min Typ† Max Units Conditions

10 TosH2ckL OSC1↑ to CLKOUT↓ — 15 30 ns Note 1

11 TosH2ckH OSC1↑ to CLKOUT↑ — 15 30 ns Note 1

12 TckR CLKOUT rise time — 5 15 ns Note 1

13 TckF CLKOUT fall time — 5 15 ns Note 1

14 TckL2ioV CLKOUT↓ to Port out valid — — 0.5 TCY+2 0 ns Note 1

15 Ti oV2ckH Port in valid before CLKOUT↑ 0.25 TCY+25 — — ns Note 1

16 TckH2ioI Port in hold after CLKOUT↑ 0 — — ns Note 1

17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — — 80 - 100 ns Note 2

18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid

(I/O in hold time) TBD — — ns

19 Ti oV2osH Port input valid to OSC1↑

(I/O in setup time) TBD — — ns

20 Ti oR Port output rise time — 10 25 ns Note 2

21 TioF Port outp ut fall time — 10 2 5 ns Note 2

* These parameters are character iz ed but not tested.

† Data in "Typ" column is at 5V, 25°C u nless otherwise stated. These p arameters are for design guidance

only and are not tested.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

2: Se e Figure 15-3 for loading conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

AAAA

AAA

Q4 Q1 Q2 Q3

20, 21

19 18

old value new value

Note : All tests mu st be done with specified capa citi ve loads (see datasheet) 50 pF on I/O pins and CLKOUT.

MTA85XXX

DS40115C-page 42  1995 Microchip Technology Inc.

FIG URE 15-6: RES ET, WATCHDOG TIMER, AND DEVICE RESE T TI MER TIMING

TABL E 15-9: RESE T, WATCHDOG TIMER, AND DEVICE RESE T TI MER

P arame ter

No. Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 1 00 — — ns VDD = 5V, -40°C to

+125°C

31 Twdt Watc hdog Timer Tim eout Period 9* 18 3 0* ms VDD = 5V, -40°C to

+125°C

(No Prescaler)

32 TDRT Device Reset Timer Period 9* 1 8* 30* ms VDD = 5V, -40°C to

+125°C

34 TioZ I/O Hi-im pedance from MCLR Low

or WDT timeout 100 ns

* These parameters are character iz ed but not tested.

† Data in "Typ" column is at 5V, 25°C u nless otherwise stated. These p arameters are for design guidance

only and are not tested.

VDD

MCLR

Internal

POR

DRT

Timeout

Internal

RESET

Watchdog

Timer

RESET

I/O pin

32 32

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

 1995 Microchip Technology Inc. DS40115C-page 43

MTA85XXX

FIGURE 15-7: T IMER0 CLOCK TIMI N GS

TABL E 15-10: TIMER0 CLOCK REQUIRE MENTS

Para mete r

No. Sym Characteristic Min Typ† Max Units Conditions

40 Tt0H T0CK I High Pulse Width No Prescal er 0 .5 TCY + 2 0* — — ns

Wi th Presc al er 10* — — ns

41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 2 0* — — ns

Wi th Presc al er 10* — — ns

42 Tt0P T0CKI Period TCY + 40*

N— — ns N = prescale value

(1, 2, 4, ..., 256)

* These parameters are characterized but not tested.

† Da ta in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not teste d.

T0CKI

40 41

MTA85XXX

DS40115C-page 44  1995 Microchip Technology Inc.

16.0 DC / AC CHARACTER ISTICS

The graphs and tables provided in this s ection are for

design guidance and ar e not te st ed or guaranteed. In

some graphs or tables the data presented are outside

specified operating range (e.g., outside specified VDD

range). This is for information only and devices are

guaranteed to operate properly only within the

specified range.

The data presented in this section is a statistical

summary of data collected on units from different lots

over a period of time. "Typical" represents the mean of

the distribution w hi le "ma x" or "min" represents (mean

+ 3σ) and (mean - 3σ) re spectively where σ is s tandard

deviation.

FIG URE 16-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEM PERATURE

TABL E 16-1: RC OS CI LLATO R FREQ UE NCIE S

Cext Rext Average

Fosc @ 5V, 25°C

20 pF 3.3k 4.973 MHz ± 27%

5k 3.82 MHz ± 21%

10k 2.22 MHz ± 21%

100k 262.15 kHz ± 31%

100 pF 3.3k 1.63 MHz ± 13%

5k 1.19 MHz ± 13%

10k 684.64 kHz ± 18%

100k 71.5 6 kHz ± 25%

300 pF 3.3k 660.0 kHz ± 10 %

5. k 4 84.1 k Hz ± 14%

10k 267.63 kHz ± 15%

160k 29.4 4 kHz ± 19%

Note 1: The frequencies are measur ed on DIP package s.

Note 2: The percentage variatio n indicated here i s part to par t variation due t o normal process distribution.

The variation indicated is ±3 standard deviation from average value for VDD = 5V.

FOSC

FOSC (25°C)

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

01020253040506070

T(°C)

Frequency normalized to +25°C

VDD = 5.5V

VDD = 3.5V

Rext ≥ 10 kΩ

Cext = 100 pF

0.88

 1995 Microchip Technology Inc. DS40115C-page 45

MTA85XXX

FIGURE 16-2: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

FOSC (M Hz )

R = 3.3k

R = 5k

R = 10k

R = 100k

Cext = 20 pF, T = 25°C

Measured on DIP Packages

FIGURE 16-3: TYPICAL RC OSCI LLATOR

FREQUENCY vs. VDD

FIGURE 16-4: TYPICAL RC OSCI LLATOR

FREQUENCY vs. VDD

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

FOSC (M Hz )

R = 3.3k

R = 5k

R = 10k

R = 100k

Measured on DIP Packages

Cext = 100 pF, T = 25°C

800

700

600

500

400

300

200

100

3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

FOSC (kHz)

R = 3.3k

R = 5k

R = 10k

R = 100k

Measured on DIP Packages

Cext = 300 pF, T = 25°C

MTA85XXX

DS40115C-page 46  1995 Microchip Technology Inc.

FIG URE 16-5: TYP ICAL IPD vs. VDD

WATCHDOG DISABLE D 25°C

FIG URE 16-6: MAXIM UM IPD vs. VDD

WATCHDOG DISABLE D

2.5

2.0

1.5

1.0

0.5

0.02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IPD (µA)

VDD (Volts)

02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IPD (µA)

VDD (Volts)

6.5 7.0

100

Temp. = 125°C

-40

-55

FIG URE 16-7: TYP ICAL IPD vs. VDD

WATCHDOG ENABLED 25°C

FIG URE 16-8: MAXIM UM IPD vs. VDD

WATCHDOG ENABLE D

02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IPD (µA)

VDD (Volts)

02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IPD (µA)

VDD (Volts) 6.5 7.0

Temp. (°C)

-40

-55

125 70

IPD, with WDT enabled, has two components:

The leakage current which increases with higher temperature

and the operating current of the WDT logic which increases

with lower temperature. At -40°C, the latter dominates

explaining the apparently anomalous behavior.

 1995 Microchip Technology Inc. DS40115C-page 47

MTA85XXX

FIG URE 16-9: VTH (INPUT THRE SHOLD VOLT AGE ) OF I/O PINS vs. VDD

FIG URE 16-10: VIH, VIL OF MCLR, T0CKI AND O SC1 (IN RC M ODE ) v s. VDD

FIGURE 16-11: VTH (IN PUT THRE SHOLD VOLT AGE ) OF I/O PINS vs. VDD

2.00

1.80

1.60

1.40

1.20

1.00

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

Min (-40°C to 85°C)

0.80

0.60 5.5 6.0

Max (-40°C to 85°C)

Typ (25°C)

VTH (Volts)

3.5

3.0

2.5

2.0

1.5

1.0

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

0.5

0.0 5.5 6.0

VIH, V IL (Volts )

4.0

4.5

min (-40°C to 85°C)

max (-40°C to 85°C)

typ 25°C

min (-40°C to 85°C)

max (-40°C to 85°C)

typ 25°C

Not e: These inp u t p ins h ave Schmit t Tri gg er inpu t buffer s.

2.4

2.2

2.0

1.8

1.6

1.4

2.5 3.0 3.5 4.0 4.5 5.0

VDD (Volts)

1.2

1.0 5.5 6.0

Typ (25°C)

VTH (Volts )

2.6

2.8

3.0

3.2

3.4

Max (-40°C to 85°C)

Min (-40°C to 85°C)

MTA85XXX

DS40115C-page 48  1995 Microchip Technology Inc.

FIG URE 16-12: TYPICAL IDD vs. FREQUE NCY (EX TERNAL CL OCK 25°C)

FIG URE 16-13: M AXIMUM IDD vs. FREQUE NCY (EX TERNAL CL OCK -40°C TO +85°C)

10k 100k 1M 10M 100M

0.01

0.1

1.0

IDD (mA)

External Clock Frequency (Hz)

5.04.5

4.0

2.5

3.0

3.5

5.5 6.0

6.5

7.0

10k 100k 1M 10M 100M

0.01

0.1

1.0

IDD (mA )

External Clock Frequency (Hz)

4.5

4.0

2.5

3.0

3.5

5.5 6.0

6.5

7.0

5.0

 1995 Microchip Technology Inc. DS40115C-page 49

MTA85XXX

FIG URE 16-14: M AXIMUM IDD vs. FREQUE NCY (EX TERNAL CL OCK -55°C TO +125°C)

10k 100k 1M 10M 100M

0.01

0.1

1.0

IDD (mA)

External C lock Frequency (Hz)

5.0 4.5

4.0

2.5

3.0

3.5

5.5

6.0

6.57.0

FIG URE 16-15: W DT TIMER TIME -OUT

PERIOD vs. VDD

5234567

DD (Volts)

WDT period (ms)

Max 85°C

Max 70 °C

Ty p 25 °C

MIn 0°C

MIn -40°C

FIGURE 16-16: TRANSCONDUCTANCE (gm )

OF H S OSCILLATOR vs. VDD

9000

8000

7000

6000

5000

4000

3000

2000

100

0234567

DD (Volts)

gm (µA/V)

Min 85°C

Max 40°C

Typ 25°C

MTA85XXX

DS40115C-page 50  1995 Microchip Technology Inc.

FIGURE 16-17: TRANS C O NDUCTANCE (gm)

OF LP OSCIL LAT O R vs. VDD

FIG URE 16-18: IOH vs. VOH, VDD = 3V

0234567

DD (Volts)

gm (µA/V)

Min 85°C

Max -40°C

Typ 25°C

-5

-10

-15

-20

-250 0.5 1.0 1.5 2.0 2.5

VOH (Volts)

IOH (mA)

Min +85°C

3.0

Typ 25°C

Max -40°C

FIGURE 16-19: TRANS C O NDUCTANCE (gm)

OF XT OSCIL LAT O R vs. VDD

FIG URE 16-20: IOH vs. VOH, VDD = 5V

2500

2000

1500

1000

500

0234567

DD (Volts)

gm (µA/V)

Min 85°C

Max -40°C

Ty p 25 °C

-10

-20

-30

-40

1.5 2.0 2.5 3.0 3.5 4.0

VOH (Volts)

IOH (mA)

Min 85°C

Max -40°C

4.5 5.0

Typ 25°C

 1995 Microchip Technology Inc. DS40115C-page 51

MTA85XXX

FIG URE 16-21: IOL vs. VOL, V DD = 3V

00 0.5 1.0 1.5 2.0 2.5

VOL (Volts)

IOL (mA )

Min +85°C

Max -40°C

Typ 25°C

3.0

FIGURE 16-22: I OL vs. VOL, V DD = 5V

00 0.5 1.0 1.5 2.0 2.5

VOL (Volts)

IOL (mA )

Min 85°C

Max -40°C

Typ 25°C

3.0

MTA85XXX

DS40115C-page 52  1995 Microchip Technology Inc.

17.0 EEPROM BUS DESCRIPTION

The MTA85XXX supports a bidirectional two wire bus

and data transmission protocol. A device that sends

data onto the bus is defined as transmitter, and a

device receiving data as receiver. The bus has to be

controlled by a master device (microcontroller) which

generates the serial clock (SCL), controls the bus

access, and generates the START and STOP

conditions, while the EEPROM (24LC01B/02B) works

as slave. Both master and slave can operate as

transmitter or receiver but the master device

determines which mode is activated.

17 .1 Bus Characteristics

The following bus protocol has been defined:

- Data transfer may be initiated only when the

bus is not busy.

- During data transfer, the data line must

remain stable whenever the clock line is

HIGH. Changes in the data line while the

clock line is HI GH will be interpreted as a

START or STOP condition.

Accordingly, the following bus conditions have been

defined (Figure 17-1):

17.1.1 BUS NOT BUSY (A)

Both data and clock lines remai n HIGH.

17.1.2 START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START c ondition. All

commands must be preceded by a START condition.

17.1.3 STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH det ermines a STO P condition. All

operations must be ended with a STOP condition.

17.1.4 DATA VALID (D)

The state of the data line represents vali d data when,

after a S TART condition, the data line is stable for t he

duration of the HIGH period of the clo ck signal.

The data on the line must be changed during the LOW

perio d of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a S TOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last

sixteen will be stored when doing a write operation.

When an overwrite does occur it will replace data in a

first in first out fashion.

17.1.5 ACKNOWLEDGE

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master d evice must generate an extra clock

pulse which is a ssociated with this acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA li ne is sta bl e LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by n ot generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable

the master to generate th e STOP condition.

* Note: The EEPROM does not generate any

acknowledge bits if an internal pro-

gramming cycle is in progress.

FIG URE 17-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

AAA

AAAA

SCL

SDA

(A) (B)

START

Address

Acknowledge

Valid

Data Allowed

to Change STOP

ConditionCondition

 1995 Microchip Technology Inc. DS40115C-page 53

MTA85XXX

17.1.6 SLAVE ADDRESS

The 24LC01B/02B (EEPROM) are software-

compatible with older devices such as the 24C01A,

24C02A, 24LC01, and the 24LC02. A single 24LC02B

can be used in place of two 24LC01’s, for example,

without any modifications to software. The "chip select"

portion of the control byte is a don't care.

After generating a START condition, the bus master

transmits the slave address consisting of a 4-bit device

code ( 1010) for the EEPROM, fol lowed by three don't

care bits.

The eigh th bit o f slave ad dress determine s if the master

device wants to read or write to the EEPROM

(Figure 17-3).

The EEPROM monitors the bus for its corresponding

slave address all the time. It generates an

acknowledge bit if the slave address was true and it is

not in a programming mode.

FIGURE 17-2: EEPROM CONTROL CODES

FIGURE 17-3: CONTROL BYTE

ALLOCATION

Operation Control

Code Chip

Select R/W

Read 1010 xxx 1

Write 1010 xxx 0

1XXX010

SLAVE ADDRES S

START READ/WRITE

R/W

X = don’t care

MTA85XXX

DS40115C-page 54  1995 Microchip Technology Inc.

18.0 WRITE OPERATION

18.1 Byte Write

Following the START signal from the master, the

device code (4 -bi ts), the don't care bits (3-bits), and the

R/W bit which is a logic low is pl aced onto the bu s by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will

follow after it has generated an acknowledge bit during

the ninth clock cycle. Therefore the next byte

transmitte d by the master is the word address and will

be written into the address pointer of the EEPROM.

After receiving another acknowledge signal from the

EEPROM the maste r device wi ll t rans mit the data word

to be written into the addressed memory location. T he

EEPROM acknowledges again and the master

generates a stop condition. This initiates the internal

write cycle, and during this time the EEPROM will not

generate acknowledge signals (Figure 18-1).

18.2 Page Write

The write control byte, word address and the first data

byte are transmitted to the EEPROM in the same way

as in a byte write. But instead of generating a STOP

condition the master transmits up to eight data bytes to

the EEPROM which are temporarily stored in the on-

chip page buffer and will be written into the memory

after the master has transmitted a STOP condition.

After the receipt of each word, the three lower order

address point er bits are internally incremented by one.

The higher order five bits of t he word address remain s

constant. I f the master should transmit more than eight

words prior to generating the STOP condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the STOP condition is received an

internal write cycle will begin (Fi gure 18-2).

FIG URE 18-1: BYT E WRITE

FIG URE 18-2: P AGE WRITE

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

CONTROL

BYTE WORD

ADDRESS DATA S

BUS

MASTER

SDA LINE

BUS

CONTROL

BYTE WORD

ADDRESS (n) DATA n S

ACTIVITY:

DATA n+1 DATA n+7

 1995 Microchip Technology Inc. DS40115C-page 55

MTA85XXX

18.3 Acknowledge Polling

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the STOP condition for a write

command has been issue d from the master , the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

send ing a START c ondition followed by th e control byte

for a write command (R/W = 0 ). If the de vic e is s till busy

with the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can th en proceed with the next read or

write comm and. Se e Figure 18- 3 for flow diagram.

FIGURE 18-3: ACKNOWLEDGE POL LING

FLOW

Did Device

Acknowledge

(ACK = 0)?

Send

Write Comman d

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Operation

Yes

MTA85XXX

DS40115C-page 56  1995 Microchip Technology Inc.

19.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to. There are t hree basic types of

read operations:

• Current address read

• Random read

• Sequential read.

19 .1 Current Ad dress Read

The EEPROM contains an address counter that

maintains the address of the last word accessed,

internally incremented by one. Therefore, if the

previous access (either a read or write operation) was

to address "n", the next current address read operation

would acces s data from a ddr ess " n + 1". Upon receipt

of the slave address with R/W bit set, the EEPROM

is sues an acknowled ge an d t rans m its the eight-bit data

word. The master will not ack nowledge the transfer but

does generate a STOP condition and the EEPROM

discontinues transmission (Figure 19-1). If a current

address read is performed after a Power-Up, the last

address will be read.

19.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by s ending the word address to th e

EEPROM as part of a write operation. After the word

address is sent, the master generates a START

condition following the acknowledge. This terminates

the write operation, but not bef ore the inter nal address

pointer i s set. Then the master issues the control byte

again but with the R/W bit set to a '1'. The EEPROM will

then issue an acknowle dge and transmits the eight-bit

data word. The master will not acknowledge the

transfer but does generate a STOP condition and the

EEPROM discontinues transmission (Figure 19-2).

19.3 Sequential Read

Sequential reads are initiated in the same way as a

ra ndom r ead ex cept that after the EEPROM transmits

the first data byte, the master issues an acknowledge

as opposed to a STOP condition in a ran dom read. T his

directs the EEPROM to transmit the next sequentially

addressed 8-bit word (Figure 19-3).

FIGURE 19-1: CURRE NT ADDRESS READ

FIGURE 19-2: RANDOM READ

CONTROL

BYTE DATA n

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE WORD

ADDRESS (n)

DATA n

RCONTROL

BYTE

 1995 Microchip Technology Inc. DS40115C-page 57

MTA85XXX

FIG URE 19-3: S EQUE NTIAL REA D

To provide sequential r e ads the EEPROM contains an

internal address pointer which is incremented by one at

the completion of each operation. This address p ointer

allows the entire memory contents to be serially read

during one operatio n.

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DA TA n+1 DATA n+2 DAT A n+X

AAAA

MTA85XXX

DS40115C-page 58  1995 Microchip Technology Inc.

20.0 GENERAL EEPROM

INFORM ATION

20.1 Noise Protection

The EEPROM employs a VCC threshold detector circuit

which disables the i nternal erase/write logic if the VCC

is below 1.5V at nominal conditions.

The SCL and SDA inpu ts have Schmitt tr igger and f i lter

circuits which suppress noise spikes to as sur e proper

device o peration even on a noisy bus.

20 .2 SDA Seria l Address/ Data Inpu t/

Output

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pullup

resistor to VCC (typical 10 kΩ for 1 00 kHz and 1 kΩ for

400 kHz).

For normal data transfer SDA is allowed to change o nly

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP

conditions.

20.3 SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

 1995 Microchip Technology Inc. DS40115C-page 59

MTA85XXX

21.0 DEVELOPMENT SUPPORT

21.1 Development Tools

The PIC16/17 microcontrollers are supported with a full

ra nge of hardware and software development tools:

• PICMASTER Real- Time In-Ci rcuit Emulator

• PRO MATE Universal Programmer

• PICSTART Low-Co st Prototype Programm er

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• MPASM Assembler

• MPSIM Softw are Simulator

• C Compiler (MP-C)

• Fuzzy logic development system

(

fuzzy

TECH−MP)

21 .2 PICMAS T ER: Hi gh Perfor mance

Universal In-Circuit Emulator

The PICMASTER Universal In-Circuit Emulator is

inte nded to provide the pro duct develo pment engineer

with a complete microcontroller design tool set for all

microcontrollers in the PIC16C5X, PIC16CXX and

PIC17CXX families. A PICMASTER System

configuration is shown in Figure 21-1.

Interchangeable target probes allow the system to be

easily reconfigured for emulation of different

processors. The universal architecture of the

PICMASTER allows expansion to support all new

PIC16C5X, PIC16CXX and PIC17CXX microcontrol-

lers.

The Emulator System is designed to operate on PC

compatible 386 (and better) machines in the M icrosoft

Windows 3.x environment. Thus, allowing the

operator acces s to a wide range of supporting software

and accessories.

The PICMASTER has been designed as a real-time

emulation system with advanced features that are

generally fou nd on more expensive developme nt tools.

The AT platform and Windows 3.x environment was

chosen to best make these features available to you,

the end user.

The PICMA S TER Universal Emulator System consists

primari ly of four major components:

• Host-Interface Card

• Emulator Control Pod

• Target-S pecific Emulator Probe

• PC-Host Emulation Control S oftwar e

The Windows 3.x operating system allows the

developer to take full advantage of the m any powerful

features and functions of the PI CMASTER system.

PICMASTER emulation can operate in one window,

while a text editor is running in a second window.

PC-Host Emulation Control software takes full

advantage of Dynamic Data Exchange (DDE), a fea-

ture of Windows 3.x. DDE allows data to be dynami-

cally transferred between two or more Windows

programs. With this feature, data collected with

PICMASTER can be automatically transferred to a

spreadsheet or database program for fur ther analysis.

Under Windows 3.x, two or more PICMASTER

emulators can be run simultaneously from the same

PC making development of multi-microcontroller

systems possible (e.g., a system containing a

PIC1 6CXX processor and a PIC17CXX processor ).

The PICMASTER probes specifications are shown in

Table 21-1.

MTA85XXX

DS40115C-page 60  1995 Microchip Technology Inc.

FIG URE 21-1: P ICMAS TER SYSTEM CONFIGURATION

TABL E 21-1: P ICMAS T ER PROBE SPECI FICATI ON

PICMASTER Pro be Devices Support e d

PROBE

Maximum

Frequency Operating

Voltage

PROBE-16B PIC16C71 10 MHz 4.5V - 5.5V

PROBE-16C PIC16C84 10 MHz 4.5V - 5.5V

PROBE-16D PIC16C54, PIC16 C54A, PIC16CR54, PIC16C55,

PIC16C56, PIC1 6C57, PIC16C58A, and PIC16CR58A 20 MHz 4.5V - 5.5V

PROBE-16E PIC16C64 10 MHz 4.5V - 5.5V

PROBE-16F PIC16C65*, PIC16C73 and PIC16C74 10 MHz 4.5V - 5.5V

PROBE-16G PIC16C61 10 MHz 4.5V - 5.5V

PROBE-16H PIC16C620, PIC16C621 and PIC16C622 10 MHz 4.5V - 5.5V

PROBE-17A PIC17C42 16 MHz 4.5V - 5.5V

* PROBE-16F i ndirectly supports the PIC16C65.

Windows 3.x

Common Interface Card

PC Compatible Computer

Power Switch

Power Connector

PC-Interface

In-Line

Power Supply

(Optional)

5 VDC

PICMASTER Emulator Pod

Interchangeable

Emulator Probe

PC Bus

90 - 250 VAC

Logic Probes

21.3 PRO M AT E: Uni versal Prog ram mer

The PRO MATE Universal Programmer is a full-

featured programmer capable of operating in stand-

alone mode as well as PC-hosted mode.

The PRO MATE has programmable VDD and VPP

supplies whi ch allows it to ver ify programmed memor y

at VDD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MA TE can read, ve rify or program

PIC16C5X, PIC 16CXX and PIC17CXX devices. It can

also set fuse config uration and code-protect bits in this

mode.

In PC-hosted mode, the PRO MATE connects to the

PC via one of the COM (RS-232) ports. PC ba sed us er-

interface software makes using the programmer simple

and efficient. The user interface is full-screen and

menu-based. Full screen display and editing of data,

easy selec tion of fuse configuration and part type, easy

selection of VDD min, VDD max and VPP levels, load

and store to and fr om disk files (hex format) are some

of the features of the software. Essential commands

such as read, veri fy, program and blank check can be

issued from the screen. Additionally, serial program-

ming support is possible where each part is pro-

grammed with a different serial number, sequential or

random.

The PRO MATE has a modular “programming socket

module”. Different socket modules are required for

different processor types and/or package types.

PRO MATE supports all PIC16C5X, PIC16CXX and

PIC17CXX processors.

21.4 PICSTART Low-Cost Development

System

The PICSTART programmer is an easy to use, very

low-cost prototype programmer. It connects to the PC

via one of the COM (RS- 232) ports. A PC-based user

interface software makes using the programmer simple

and efficient. The user interface is full-screen and

menu-based. PICSTART is not recommended for

production programming.

 1995 Microchip Technology Inc. DS40115C-page 61

MTA85XXX

21 .5 PICDEM -1 Lo w-Cos t PIC1 6/1 7

Demo ns tratio n Board

The PICDEM- 1 is a simple board which demonstrat e s

the capabilities of several of Microchip’s

microcontrollers. The microcontrollers supported are:

PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61,

PIC 16C62X, PIC16C71, PIC16C84 and PIC17C42. All

necessary hardware and software is included to run

basic demo pr ograms. The users can program sample

m icro con trollers p rovided wi th the PICDEM-1 board,

on a PRO MATE or PICSTART-16B programmer,

and easily test firmware. The user can also connect

the PICDEM-1 board to the PICMASTER emulator

and download the firmware to the emulator for testing.

Additional prototype area is available for the user to

build some additional hardware and connect it to the

microcontroller socke t(s). Some of the features inclu de

an RS-232 interface, a potentiometer for simulated

analog input, push-button switches and eight LEDs

connected to PORTB.

21 .6 PICDEM -2 Lo w-Cos t PIC16CX X

Demo ns tratio n Board

The PICDEM-2 is a simple demonstration board that

supports the PIC16C63, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can pr o gram the sam pl e mi crocontr oller s provi d ed

with the PICDEM-2 board, on a PRO MATE

prog ramme r or PICSTART-16C, and easily test firm-

ware. The PICMASTER emulator may also be used

with the PICDEM-2 board to test firmware. Additional

prototype area has been provided to the user for

adding additional hardware and connecting it to the

microcontroller socke t(s). Some of the features inclu de

a RS-232 interface, push-button switches, a

potentiometer for simulated analog input, a Serial

EEPROM to demonstrate usage of the I2C bus and

separate headers for connection to an LCD module

and a keypad.

21 .7 As s em bl er (MPASM )

The MP ASM Cross Ass embler is a PC-hosted s ymbolic

assembler. It supports all microcontroller series

including the PIC16C5X, PIC16CXX, and PIC17CXX

families.

MPASM offers full featured Macro capabilities,

conditional assembly, and several source and listing

formats. It generates various object code formats to

support Microchip's development tools a s well as third

party programmers.

MPASM allows full symbolic debugging from

the Microchip Universal Emulator System

(PICMASTER).

MPASM has the following features to assist in

develo ping software for specific use applications.

• Provides translation of Assembler source code to

obje ct code for all Microchip mi crocontrollers.

• Macro assembly capability

• Produces all the files (Object, Listing, Symbol,

and special) r equire d for symbol ic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listin g formats .

MPASM provides a full feature directive language

re presented by four basic classes of directives:

•Data Directives are those that control the

allocation of memory and provide a way to refer to

data items symbolically (i.e., by m eaningful

names).

•Listing Directives control the MPASM listing

displa y. They allow the specification of titles and

sub-titles, page ejects and other listing control.

•Control Directives permit sections of

conditionally assembled code.

•Macro Directiv es c ont rol the executio n and data

allocation within macro bo dy definitions.

MTA85XXX

DS40115C-page 62  1995 Microchip Technology Inc.

21.8 Software Simulator (MPSIM)

The MPSIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PIC16/17 series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The input /

output radix can be s et by the user and the e xecution

can be performed in; single step, execu te until break, or

in a trace mode. MPSIM fully supports symbolic d ebug-

ging using MP-C and MPASM. The Software Simulator

offers the low cost f lexibility to develop and debu g code

outside of the laboratory environment making it an

ex cellent multi-project software development tool.

21 .9 C Com p iler (MP-C)

The MP-C Code Development System is a complete 'C'

compiler and integrated development environment for

Microchip’s PIC16/17 family of microcontrollers. The

compiler provides powerful integrati on capabilities and

ease of use not found wit h other compilers.

For easier source level debugging, the compiler

provides symbo l i nformation that is compatible with the

PICMASTER Universal Emulator memory display

(emulator software ver sio ns 1.1 3 and later).

The MP-C Code Development System is supplied

directly by Byte Craft Limited of Waterloo, Ontario,

Canada. If you have any questions, please contact

your regional Microchip FAE or Microchip technical

support personnel at (602) 786-7627.

21 .10 Fuzzy Log ic Developm ent System

(

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is

available in two versions - a low cost introductory

version, MP Explorer, for designers to gain a

comprehensive working knowledge of fuzzy logic

system design; and a full-featured version,

fuzzy

TECH-MP Edition, for implementing more

complex systems.

Both versions include Microchip’s

fuzzy

LAB

demonstration board for hands-on experience with

fuzzy logic systems implementation.

21.11 Development Systems

For convenience, the development to ols are packaged

into comprehensive systems as listed in Table 21-2 .

TABL E 21-2: DE VE LOPME NT SYSTEM PACKAGE S

Item Name System Description

1. PICMASTER System PICMASTER In-Circuit Emulator, PRO MATE Programm er, Assembler,

Software Simulator, Samples and your choice of Target Probe.

2. PICSTART System PICSTART Low-Cost Prototype Programmer, Assembler, Software Simulator

and Sam ples.

3. PRO MATE Syste m PRO M ATE Universal Pro grammer, full fea tured stand-alone or PC-hosted pro-

grammer, Assembler, Simulator

4. PICSEE-85A

Introduction Design Kit Kit contains the programming adaptor (item 3) , a PICMASTER interface board

and microcontroller samples of the MTA85XXX component d e vices

5. PICSEESTART-85A

Development Kit Kit contains a PICSTART System (item 2) and PICSEE- 8 5A Introd uction

Design Lit (item 4)

6. PICSEE-85A

PRO MATE Header SSOP PRO M ATE header for the M TA85XXX products. No programming

adaptor needed

 1995 Microchip Technology Inc. DS40115C-page 63

MTA85XXX

22.0 PACKAGING DIAGRAMS AND DIMENSIONS

22 .1 20 -Lead Pl astic Surfac e Mou nt (SSO P - 209 mil Body 5. 30mm )

Package Group: Plastic SSOP

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

α0°8°0°8°

A 1.730 1.990 0.068 0.078

A1 0.050 0.210 0.002 0.008

B 0.250 0.380 0.010 0.015

C 0.130 0.220 0.005 0.009

D 7.070 7.330 0.278 0.289

E 5.200 5.380 0.205 0.212

e 0.650 0.650 Reference 0.026 0.026 Reference

H 7.650 7.900 0.301 0.311

L 0.550 0.950 0.022 0.037

N2020 2020

CP - 0.102 - 0.004

AAAAAAAAA

AAAA

AAAAAAAAAA

Index

area

123

AAAAAAAAAAAA

AAAAAA

B ase plane

S eat ing pl ane

AAAAAAAA

AAAA

MTA85XXX

DS40115C-page 64  1995 Microchip Technology Inc.

23.0 PACKAGE MARKING INFORMATION

Legend: MM...M

XX...X

Mic roch ip part num ber inf ormat ion

Customer specif ic inform at ion*

Year code (last 2 digit s of calender year)

Week code (week o f January 1 is week '01’)

Facilit y code of the plant at which wafer is manuf actured.

C = Chandler, Arizona, U.S.A.

Mask revision num ber for mi crocontrol ler

Mask revision num ber for EEPR OM

Assembly code of the plant or country of origin in which

part was assembled.

In the event the f ull M icrochip part num ber cannot be m arked on one

line, it will be carried over to the next line thus limi ting the num ber of

a vailabl e chara cters for custom er specific inf orma tio n.

Note:

Standard OT P marking consist s of Microchip part numbe r, year code, week code,

facil ity code, mask revision numbe r, and assembly code. For OTP marking beyond

this, certain price adders apply. Please ch ec k with yo ur Microchip Sales Office.

For QTP devices, any special mar king adders are included in QTP price.

20-Lead SSOP

XXXXXXXXXX

AABBCDE

XXXXXXXXXX

Example

10/SS

9512CAP

MTA85401

 1995 Microchip Technology Inc. DS40115C-page 65

MTA85XXX

INDEX

Absolute Maximum Ratings ...............................................33

AC Cha racte risti cs (0 4, 10, 20) COM/IND ...... .... .... .... .37–3 9

Assembler ..........................................................................63

Block Diagram

Ch ip .............................................................................. 5

I/O Pin ........................................................................ 17

On -Chi p Reset Circu it ... .... ... .... ........ ................... ....... 2 7

RTCC (Simplified) ......................................................14

RTCC and WDT .........................................................21

Br own -Out Pro tecti on Circuit .... ... .... .... .... .... ... .... ............... 3 0

C Compi le r (MP-C) ... .... .... .... ............................................. 6 3

Code Protection .................................................................32

Co nfigu ra tio n Fuse s .. .... .... .... ............................................. 3 2

Data Memory Map .............................................................10

DC Cha racte risti cs (04, 10, 20) COM/IND ... ... .... .... .... .34 –36

De velo pme nt Sup p ort ... .... .... .... ... .... .................................. 6 0

De velo pme nt S y stems .. .... .... ............................................. 6 3

Exte rnal Powe r-On Reset Cir cuit . .... .... ............... ............... 3 0

Features Overview ...............................................................1

File Register Descriptions

FSR ............................................................................16

IN DF ... .... .... ... ............................................................. 1 3

PC ..............................................................................15

RTCC .........................................................................13

ST ATUS . ....... .... ........ .... ....... ........ .... ....... .... ........ .... ...1 5

Fuzzy Logic Dev. System (

fuzzy

TECH-MP) ...................63

I/O Ports .............................................................................17

Ind ire ct Add re ssin g ... ......................................................... 1 3

Instruction Set ....................................................................22

MPASM A ssemb le r ... ......................................................... 6 3

MP-C C Comp il er .. .... ......................................................... 6 3

MPSI M Sof twa re Sim ulato r ... .... ... .... .... .............................. 6 3

OPTION Register ............................................................... 19

OTP Devices ........................................................................7

Package Information ....................................................64, 65

Page Select (program memory) ...........................................8

PD bit . .... .... ........................................................................ 1 6

PICMASTER Probe ...........................................................61

PI CMASTER System Configu ration ...................................6 1

Pinout Information ..........................................................1, 40

PORTime-Out Sequence on Power-Up .............................29

Prescaler (RTCC/WDT) ...............................................19, 21

Program Counter .................................................................8

Program memory map .........................................................9

QTP Devices ........................................................................ 7

Real Time Clock/Counter (RTCC) ......................... 13, 14, 19

RE SET ..... ....... .... ........ ....... ........ .... ........ ....... ........ .... ....... .. 2 0

Software Simulator (MPSIM) ............................................. 63

Stack .............................................................................. 9, 15

Status Register .................................................................. 15

Timing Diagrams

I/O Pin ........................................................................ 17

RTCC Timing ............................................................. 14

TO bit ................................................................................. 16

TRIS Registers .................................................................. 19

UV Erasable Devices ........................................................... 7

W Register ......................................................................... 19

WDT .................................................................................. 24

Table of Figures

Figure 2-1: MTA85XXX Series Block Diagram............... 5

Figure 2-2: Clocks/Instruction Cycle............................... 6

Figure 4-1: Program Memory Organization MTA854XX. 9

Figure 4-2: Program Memory Organization MTA858XX. 9

Figure 5-1: Data Memory Map...................................... 10

Figure 5-2: T0CKI Block Diagram (Simplified).............. 13

Figure 5-3: T0CKI Timing: INT Clock/No Prescale....... 13

Figure 5-4: T0CKI Timing: INT Clock/Prescale 1:2....... 13

Figure 5-5: T0CKI Timing With External Clock............. 13

Figure 5-6: Status WORD Register .............................. 14

Fig ure 5-7: Eq u ival ent Cir cuit For a Singl e I/O P in....... 1 6

Figure 5-8: I/O Port Read/Write Timing ........................ 16

Figure 6-1: OPTION Register ....................................... 18

Figure 8-1: Block Diagram T0CKI/WDT Prescaler ....... 20

Figure 10-1: Watchdog Timer Block Diagram................. 23

Figure 11-1: Crystal /Ceramic Resonator Operation

(HS, XT or LP OSC Configuration)............. 24

Fig ure 11 -2 : Extern al Clock Inp ut Ope rati on

(HS, XT or LP OSC Mode)......................... 24

Figure 11-3: External Paral lel Resonant Crystal

Oscillator Circuit ......................................... 25

Figure 11-4: External Series Resonant Crystal

Oscillator Circuit ......................................... 25

Fig ure 11-5 : RC O scilla tor Mod e .................................... 25

Figure 12-1: On-Chip Reset Circuit Block Diagram........ 26

Figure 12-2: Time-Out Sequence on Power-Up

(MCLR Not Tied to VDD): Case 1 ............... 28

Figure 12-3: Time-Out Sequence on Power-Up

(MCLR Not Tied to VDD): Case 2 ............... 28

Figure 12-4: Time-Out Sequence on Power-Up

(MCLR Tied to VDD) ................................... 28

Figure 12-5: External Power-On Reset Circuit

(For Slow VDD Power-Up) .......................... 29

Fig ure 12-6 : Brown -Out Pro tecti on Circu it 1.. .... .... ... .... .. 2 9

Fig ure 12-7 : Brown -Out Pro tecti on Circu it 2.. .... .... ... .... .. 2 9

Figure 12-8: Electrical Structure of the MCLR/VPP and

T0CKI Pins................................................. 29

Figure 14-1: Configuration Word .................................... 32

Figure 15-1: Electrical Structure of I/O Pins (RA, RB).... 39

MTA85XXX

DS40115C-page 66  1995 Microchip Technology Inc.

Figure 15-2: Electrical Structure of MCLR and

T0CKI Pins..................................................39

Figure 15-3: Load Conditions..........................................39

Figure 15-4: External Clock Timing.................................40

Figure 15-5: CLKOUT and I/O Timing.............................41

Figure 15-6: Reset, Watchdog Timer, and

Device Reset Timer Timing ........................42

Figure 15-7: TIMER0 Clock Timings...............................43

Figure 16-1: Typical RC Oscillator Frequency vs.

Temperature ...............................................44

Figure 16-2: Typical RC Oscillator Frequency vs. VDD ...45

Figure 16-3: Typical RC Oscillator Frequency vs. VDD ...45

Figure 16-4: Typical RC Oscillator Frequency vs. VDD ...45

Figure 16-5: Typical IPD vs. VDD Watchdog

Disabled 25°C.............................................46

Figure 16-6: Maximum IPD vs. V DD Watchdog

Disabled......................................................46

Figure 16-7: Typical IPD vs. VDD Watchdog

En ab le d 25 °C..............................................46

Figure 16-8: Maximum IPD vs. V DD Watchdog Enabled..46

Figure 16-9: VTH (Input Threshold Voltage)

of I/O Pins vs. VDD......................................47

Figure 16-10: VIH, VIL of MCLR, T0CKI and OSC1

(in RC Mode) vs. VDD .................................47

Figure 16-11: VTH (Input Threshold Voltage)

of I/O Pins vs. VDD......................................47

Figure 16-12: Typical IDD vs. Frequency

(External Clock 25°C) .................................48

Figure 16-13: Maximum IDD vs. Frequency

(External Clock -40°C to +85°C).................48

Figure 16-14: Maximum IDD vs. Frequency

(External Clock -55°C to +125°C)...............49

Figure 16-15: WDT Timer Time-out Period vs. V DD..........49

Figure 16-16: Transconductance (gm)

of HS Oscillator vs. VDD..............................49

Figure 16-17: Transconductance (gm)

of LP Oscillator vs. VDD ..............................50

Figure 16-18: IOH vs. VOH, VDD = 3V ................................50

Figure 16-19: Transconductance (gm)

of XT Oscilla tor vs. VDD ..............................50

Figure 16-20: IOH vs. VOH, VDD = 5V ................................50

Figure 16-21: IOL vs. VOL, VDD = 3V.................................51

Figure 16-22: IOL vs. VOL, VDD = 5V.................................51

Figu re 17-1 : Data Transfe r Sequ ence on the Seri al Bus 52

Figure 17-2: EEPROM Control Codes ............................53

Figure 17-3: Control Byte Allocation ...............................53

Figure 18-1: Byte Write ...................................................54

Figure 18-2: Page Write ..................................................54

Figure 18-3: Acknowledge Polling Flow..........................55

Figure 19-1: Current Address Read................................56

Figure 19-2: Random Read.............................................56

Figure 19-3: Sequential Read .........................................57

Figure 21-1: PICMASTER System Configuration ...........60

Table of Tables

Table 1-1: Family Overview ...........................................4

Table 5-1: PIC16C5X Re gister Fil e Summary ...........11

Table 5-2: Events Affecting TO/PD Status bits............15

Table 5-3: TO/PD Status After Reset...........................15

Tab le 7-1: Re se t Con di tion For Reg ister s .. .... ..............19

Table 9-1: Instruction Set Summary ............................22

Table 10-1: Summary of Registers Associated

wi th th e W at chdo g Time r...... ......................23

Table 11-1: Capacitor Selection for

Ceramic Resonators...................................24

Table 11-2: Capacitor Selection For Crystal Oscillator..24

Table 12-1: TO /PD Status After Reset .......................... 27

Table 12-2: Reset Conditions for Special Registers...... 27

Tab le 12-3: Re set Con di tio ns for All Registe r s . .... .... ..... 2 7

Tab le 15-1: Cro s s Reference of Device Spe c s

for Oscillator Configurations

and Frequencies of Operation

(Commercial Devices)................................ 32

Table 15-2: DC Characteristics of Microcontroller

MTA854XX-04 (Industrial).......................... 33

Table 15-3: DC Characteristics of Microcontroller

MTA858XX-04 (Industrial) /

MTA858XX-10 (Industrial).......................... 34

Table 15-4: DC Characteristics of Inputs/Outputs:

MTA854XX-04 (Industrial) /

MTA858XX-04 (Industrial) /

MTA858XX-10 (Industrial).......................... 35

Table 15-5: AC Characteristics of Microcontroller:

MTA854XX-04 (Industrial) /

MTA858XX-04 (Industrial) /

MTA858XX-10 (Industrial).......................... 36

Table 15-6: AC Characteristics of EEPROM ................. 38

Table 15-7: External Clock Timing Requirements......... 40

Table 15-8: CLKOUT and I/O Timing Requirements..... 41

Table 15-9: Reset, Watchdog Timer,

and Device Reset Timer............................. 42

Table 15-10: TIMER0 Clock Requirements..................... 43

Tab le 16 -1 : RC O scilla tor Fre qu enci es.......................... 44

Table 21-1: PICMASTER Probe Specification............... 60

Table 21-2: Development System Packages................. 62

 1995 Microchip Technology Inc. DS40115C-page 67

MTA85XXX

CONNECTING TO MICROCHIP BBS

Connect worldwide to the Microchip BBS using the

CompuServe communications network. In most

cases a local call is your only expense. The Microchip

BBS connection does not use CompuServe

membership services, therefore you do not need

CompuServe membership to join Microchip's BBS.

There is no charge for connecting to the BBS, except

for a toll charge to the CompuServe access number,

where applicable. You do not need to be a

CompuServe member to take advantage of this

connection (you never actually log in to CompuServe).

The p rocedure to c onnec t will vary s lightly from country

to country. Please check with your local CompuServe

agent for details if you have a problem. CompuServe

service allows multiple users at baud rates up to

14400 bps.

The following connect procedure applies in most

locations:

1. Set your modem to 8 bit, No p arity, and One stop

(8N1). This is not the normal CompuServe

setting which is 7E1.

2. Dial your local CompuServe access number.

3. Depress <ENTER↵> and a garbage string will

appear because CompuServe is expecting a

7E1 setting.

4. Type +, depress <ENTER↵> and Host N ame:

will appear.

5. Type MCHI PBBS, depress < ENTER↵ > and

you will be connected to th e Microchip BBS.

In the United States, to find CompuServe's phone

number close st to you, set your modem to 7E1 an d dial

(800) 848-4480 for 300-2400 baud or (800) 331-7166

for 9600-14400 baud connection. After the system

responds with Host Name:, type

NETWORK, depress < ENTER↵ >

and follow CompuServe's directions.

For voice information (or calling from overseas), you

may call (614) 457-1550 for your local CompuServe

number.

Trademarks:

I2C is a trademark of Philips Corporation.

PICSEE, PRO MATE a n d

fuzzy

LAB trademarks of

Microchip Technolo gy Incorporated.

The Microchip logo and name are registered

trademarks of Microchip Technology Incorporated.

IBM, IBM PC-AT are registered trademarks of

International Business Ma chines Corp.

PICMASTER and PICSTART are trademarks of

Microchip Technolo gy Incorporated. PIC i s a

registered trademark of Microchip Technology

Incorporated in the U.S.A.

Tri-State is a tra demark of National

Semiconductor.

fuzzy

TECH is a registered trademark of Inform

Software Corporation.

Pentium is a trademark of Intel Corporatio n.

Intel is a registered trademark of Intel Corpor ation.

MS-DOS a n d Microsoft Windows are registered

trademarks of Microsoft Corporation. Wind ows is a

trademark of Microsoft Corporation.

CompuServe is a registered trademark of

CompuServe Incor porated.

All other trademarks mentioned herein are th e

property of t heir r e spective companies.

MTA85XXX

DS40115C-page 68  1995 Microchip Technology Inc.

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publi catio ns Manager a t area code

(602) 786- 7 5 78.

Please list the followin g information, an d use this outline to provide us with your comments about this Data Sheet.

1. What are the best features of t his do cument?

2. How does this document m eet your hardware and software development needs?

3. Do you find the organizati on of t his data sheet easy to f ollow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting t he overall usefulness?

6. Is th ere any incorrect or misleading informati on (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

To: Technical Publications Manager

RE: Reader Response Total Pa ges Sent

From: Name

Company

Address

City / State / ZIP / Country

Telephone : (_______) _________ - ___ ______

Application (optional) :

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS40115C

MTA85XXX

 1995 Microchip Technology Inc. DS40115C-page 69

MTA85XXX

NOTES:

MTA85XXX

DS40115C-page 70  1995 Microchip Technology Inc.

NOTES:

 1995 Microchip Technology Inc. DS40115C-page 71

MTA85XXX

NOTES:

MTA85XXX

DS40115C-page 72  1995 Microchip Technology Inc.

MTA85XXX Prod uc t Identific ation Sy s tem

To order or to obtai n inform atio n (e.g., on pricing or de live ry), please use the liste d part nu mber s, and ref er to the facto ry or the liste d

sales offices.

Pattern:

3-Digit Pattern Code for QTP (blank otherwise)

Package:

SS = 209 mill SSOP

Temperature

I = -40°C to +85°C (S for tape/reel)

Range:

Fre quenc y

04 = 4 M Hz (MT A854XX and 858XX)

Range:

10 = 10 MHz (MTA858 XX only)

Device:

MTA8540 1 :Refer to Table 1-1

PART NO. -XX X /XX XXX

Examples:

a) MTA85402 - 04/SS 301 = C ommercial temperature, SSO P package, 4 MHz, QTP p attern #301

b) MTA85811 - 10I/SS = Industrial temperature, SSOP package, 10 M Hz

AMERICAS (continued)

San Jose

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408 436-7950 Fax: 408 436-7955

ASIA/PACIFIC

Hong Kong

Microchip Technology Inc.

Unit No. 3002-3004, Tower 1

Metroplaza

223 Hing Fong Road

Kwai Fong, N.T. Hong Kong

Tel: 852 2 401 1200 Fax: 852 2 401 3431

Korea

Microchip Technology Korea

168-1, Youngbo Bldg. 3 Floor

Samsung -Dong, Kangnam- Ku ,

Seoul, Korea

Tel: 82 2 554 7200 Fax: 82 2 558 5934

Singapore

Microchip Technology Taiwan

Singapore Branch

200 Middle Road

#10-03 Prime Centre

Singapore 0718

Tel: 65 334 8870 Fax: 65 334 8850

Taiwan

Microchip Technology Taiwan

10F-1C 207

Tung Hua North Road

Taipei, Taiwan, ROC

Tel: 886 2 717 7175 Fax: 886 2 545 0139

EUROPE

United Kingdom

Arizona Microchip Technology Ltd.

Unit 6, The Courtyard

Meadow Bank, Furlong Road

Bourne End, Buckinghamshire

SL8 5AJ

Tel: 44 0 1628 8 51077 Fax: 44 0 1628 8502 59

France

Arizona Microchip Technology SARL

2 Rue du Buisson aux Fraises

91300 Massy - France

Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79

Germany

Arizona Microchip Technology GmbH

Gustav-Heinemann-Ring 125

D-81739 Muenchen, Germany

Tel: 49 89 627 144 0 Fax: 49 89 627 144 44

Italy

Arizona Microchip Technology SR L

Centro Direzionale Colleoni

Palazzo Pegaso Ingresso No. 2

Via Paracelso 23, 20041

Agrate Bria nza (MI) Italy

Tel: 39 039 689 9939 Fax: 39 039 689 9883

JAPAN

Microchip Technology Intl. Inc.

Benex S-1 6F

3-18-20, Shin Yokohama

Kohoku-Ku, Yokohama

Kanagawa 222 Japan

Tel: 81 45 471 6166 Fax: 81 45 471 6122

AMERICAS

Co rpora te Of fice

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 602 786-7200 Fax: 602 786-72 77

Atlanta

Microchip Technology Inc.

500 Sugar Mill Road, Suite 200B

Atlanta, GA 30350

Tel: 404 640-0034 Fax: 404 640-03 07

Boston

Microchip Technology Inc.

5 Mount Royal Avenue

Marlborough, MA 01752

Tel: 508 480-9990 Fax: 508 480-8575

Chicago

Microchip Technology Inc.

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 708 285-0071 Fax: 708 285-00 75

Dallas

Microchip Technology Inc.

14651 Dallas Parkway, Suite 816

Dallas, TX 75240-8809

Tel: 214 991-7177 Fax: 214 991-85 88

Dayton

Microchip Technology Inc.

35 Rockridge Road

Englewood, OH 45322

Tel: 513 832-2543 Fax: 513 832-28 41

Lo s Angele s

Microchip Technology Inc.

18201 Von Karman, Suite 455

Irvine, CA 92715

Tel: 714 263-1888 Fax: 714 263-13 38

Ne w York

Microchip Technology Inc.

150 Motor Parkway, Suit e 416

Hauppauge, NY 11788

Tel: 516 273-5305 Fax: 516 273-53 35

" Info rmation contained in this publicat ion regarding device appli catio ns and the like is intended through suggestion only and may be superseded by updates. No representation or warr a n ty is given and no liabi lity is assum ed

b y Microchip Technol ogy Incorporated with respect to t he accuracy or use of such info rmation, or infringement of patents arising from su ch use or ot h erwise. Use of M icrochip's products as critical components in life support

syst ems is not authorized except wi th express written approval by Microchip. No licenses are conveyed, implicit ly or otherwise, under any intellect ual p roperty rights." The Microchip logo and name are regist ered trademarks

Printed in the USA, 8/95

 1995, Microchip Technology Inc.