THS7313 www.ti.com SLOS483 - NOVEMBER 2005 3-Channel Low Power SDTV Video Amplifier with I2C Control, 6-dB Gain, SAG Correction, 2:1 Input MUX, and Selectable Input Bias Modes FEATURES APPLICATIONS * * * * * * * * * * * * * * * 3 SDTV Video Amplifiers for CVBS, S-Video, Y'P'BP'R 480i/576i, or G'B'R' Video Systems I2CTM Control of All Functions on Each Channel Integrated Low-Pass Filters - 5th Order, 8-MHz Butterworth * 0.5-dB Attenuation at 5.5 MHz * 48-dB Attenuation at 27 MHz Selectable Input Bias Modes - AC-Coupled with Sync-Tip Clamp - AC-Coupled with Bias - DC-Coupled with 135-mV Input Shift - DC-Coupled 2:1 Input MUX Allows Multiple Input Sources Built-in 6-dB Gain (2 V/V) SAG Correction Capable 2.7-V to 5-V Single Supply Operation Individual Disable (<1 A) and Mute Control Rail-to-Rail Output: - Output Swings within 100 mV from the Rails Which Allows AC or DC Output Coupling - Able to Drive up to 2 Video Lines - 75 Low 16.6-mA (3.3 V) Total Quiescent Current Low Differential Gain/Phase of 0.07% / 0.12 Set Top Box Output Video Buffering PVR/DVDR Output Buffering USB/Portable Low Power Video Buffering DESCRIPTION Fabricated using the new complimentary silicon-germanium (SiGe) BiCom-III process, the THS7313 is a low-power, single-supply 2.7-V to 5-V, 3-channel integrated video buffer. It incorporates a 5th order Butterworth filter which is useful as a digital-to-analog converter (DAC) reconstruction filter or an analog-to-digital converter (ADC) anti-aliasing filter. The 8-MHz filter is a perfect choice for SDTV video which includes composite (CVBS), S-Video, Y'U'V', G'B'R', and Y'P'BP'R 480i/576i. Each channel of the THS7313 is individually I2C configurable for all functions which makes it flexible for any application. Its rail-to-rail output stage allows for both ac and dc coupling applications. The 6-dB gain along with the built-in SAG correction allows for maximum flexibility as an output video buffer. The 16.6 mA total quiescent current at 3.3 V (55 mW) makes it an excellent choice for USB powered or portable video applications. While fully disabled, the THS7313 consumes less than 1 A. The THS7313 is available in a small lead-free and RoHS compliant TSSOP-20 package. 3.3 V Video DAC / Encoder In A In B 2 :1 X1 R 8 MHz DC + 135 mV External Input 75 W + LPF DC AC BIAS SDA AC Sync TIP Clamp SCL Out 47 mF 75 W - 675 W Video Out SAG MUTE 1 kW I2C-A1 I2C-A0 878 W 150 W 33 mF 75 W 3.3 V Figure 1. 3.3 V Single-Supply DC-Input/AC-Video Output System w/SAG Correction (1 of 3 Channels Shown) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of Philips Electronics. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2005, Texas Instruments Incorporated THS7313 www.ti.com SLOS483 - NOVEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION (CONTINUED) As part of the THS7313 flexibility, the 2:1 MUX input can be selected for ac or dc coupled inputs. The ac coupled modes include a sync-tip clamp option for CVBS or Y' signals, or a fixed bias for the C/P'B/P'R channels. The dc input options include a dc input or a dc + 135-mV input offset shift to allow for a full sync dynamic range at the output with 0-V input. PACKAGING/ORDERING INFORMATION PACKAGED DEVICES (1) PACKAGE TYPE THS7313PW (1) Rails, 70 TSSOP-20 THS7313PWR TRANSPORT MEDIA, QUANTITY Tape and reel, 2000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VSS Supply voltage, VS+ to GND VI Input voltage IO Output current 5.5 V -0.4V to VS+ 125 mA Continuous power dissipation See Dissipation Rating Table TJ Maximum junction temperature, any condition (2) TJ Maximum junction temperature, continuous operation, long term reliability (3) Tstg Storage temperature range 150C 125C -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ESD ratings (1) (2) (3) 300C HBM 2000 V CDM 750 V MM 100 V Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability. The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process. The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. DISSIPATION RATINGS (1) (2) 2 PACKAGE JC (C/W) JA (C/W) TSSOP - 20 (PW) 32.3 83 (2) POWER RATING (1) (TJ = 125C) TA = 25C TA = 85C 1.2 W 0.48 W Power rating is determined with a junction temperature of 125C. This is the point where distortion starts to substantially increase and long-term reliability starts to be reduced. Thermal management of the final PCB strives to keep the junction temperature at or below 125C for best performance and reliability. This data was taken with the JEDEC High-K test PCB. For the JEDEC low-K test PCB, the JA is 125.8C. THS7313 www.ti.com SLOS483 - NOVEMBER 2005 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VSS Supply voltage, VS+ 2.7 5 V TA Ambient temperature -40 85 C ELECTRICAL CHARACTERISTICS, VS+ = 3.3 V RL = 150 to GND, Input Bias = dc, SAG pin shorted to the output pin (unless otherwise noted) TYP PARAMETER TEST CONDITIONS OVERTEMPERATURE 25C 25C 0C to 70C -40C to 85C UNITS MIN/MAX 6.7/9.3 6.55/9.45 6.5/9.5 MHz Min/Max AC PERFORMANCE Small-signal bandwidth (-3 dB) VO- 0.2 VPP (1) 8 Large-signal bandwidth (-3 dB) VO- 2 VPP (1) 8 MHz Group delay f = 100 kHz 63 ns Group delay variation with respect to 100 kHz f = 5.1 MHz 13 ns Group delay matching Channel-to-Channel 0.5 Attenuation with respect to 100 kHz f = 5.75 MHz 0.5 -0.2 / 2 -0.4 / 2.2 -0.5 / 2.3 dB Min/Max f = 27 MHz 48 36 35 34 dB Min Mute feed-thru f = 1 MHz -80 Differential gain NTSC/PAL 0.07%/0.15 % Differential phase NTSC/PAL 0.12/0.1 Total harmonic distortion f = 1 MHz, VO = 2 VPP -62 dB Signal to noise ratio Unified weighting 100 kHz to 6 MHz 82 dB Channel-to-Channel crosstalk f = 1 MHz -63 dB MUX Isolation f = 5.1 MHz 73 AC gain - All channels f = 100 kHz 6 Output impedance f = 10 MHz 0.75 ns dB dB 5.7/6.3 5.65/6.35 5.65/6.35 dB Min/Max DC PERFORMANCE Output offset voltage Bias = dc Average offset voltage drift Bias = dc 35 90 95 95 mV 20 V/C Max Bias = dc + 135 mV, VI = 0 V 290 235/345 215/360 200/375 mV Min/Max Bias = ac 1.65 1.5/1.8 1.45/1.85 1.45/1.85 V Min/Max Sync tip clamp output voltage Bias = ac STC 290 210/370 200/380 195/385 mV Min/Max Input bias current Bias = dc - implies Ib out of the pin -0.6 -4 -5 -5 A Max Average bias current drift Bias = dc 10 nA/C Bias output voltage Sync tip clamp bias current Bias = ac STC, Low bias 1.8 0.6/3.3 0.5/3.5 0.4/3.6 A Min/Max Bias = ac STC, Mid bias 5.8 4.3/8.2 4.1/8.4 4/8.5 A Min/Max Bias = ac STC, High bias 7.8 6.2/10.8 6/11 5.9/11.1 A Min/Max 0/1.57 0/1.52 0/1.47 0/1.47 V Min/Max INPUT CHARACTERISTICS Input voltage range Input resistance Bias = dc - limited by output Bias = ac bias mode 19 k Bias = dc, dc + 135 mV, ac STC 3 M 2 pF Input capacitance OUTPUT CHARACTERISTICS High output voltage swing (1) RL = 150 to Midrail 3.15 2.9 2.8 2.8 V Min RL = 150 to GND 3.05 2.85 2.75 2.75 V Min RL = 75 to Midrail 3.05 2.8 2.7 2.7 V Min RL = 75 to GND 2.9 2.65 2.55 2.55 V Min The Min/Max values listed are specified by design only. 3 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 ELECTRICAL CHARACTERISTICS, VS+ = 3.3 V (continued) RL = 150 to GND, Input Bias = dc, SAG pin shorted to the output pin (unless otherwise noted) TYP PARAMETER TEST CONDITIONS OVERTEMPERATURE 25C 25C 0C to 70C -40C to 85C UNITS MIN/MAX RL = 150 to Midrail 0.14 0.24 0.27 0.28 V Max RL = 150 to GND 0.09 0.17 0.2 0.21 V Max RL = 75 to Midrail 0.24 0.33 0.36 0.37 V Max RL = 75 to GND 0.09 0.17 0.2 0.21 V Max RL = 10 to Midrail, sourcing 70 45 42 40 mA Min RL = 10 to Midrail, sinking 70 45 42 40 mA Min Maximum operating voltage 3.3 5.5 5.5 5.5 V Max Minimum operating voltage 3.3 2.6 2.6 2.6 V Min 6 7.2 7.4 7.5 mA Max 6 4.8 4.6 4.5 mA Min Low output voltage swing Output current POWER SUPPLY Maximum quiescent current Per channel VI = 200 mV Minimum quiescent current Per channel VI = 200 mV Total quiescent current All channels ON, VI = 200 mV Power supply rejection (+PSRR) VS+ = 3.5 V to 3.1 V (2) 16.6 59 mA 37 35 35 dB Min DISABLE CHARACTERISTICS (3) Quiescent current All 3 channels disabled Turn-on time delay (tON) Time reaches 50% of final value after I2C control is completed Turn-on time delay (tOFF) (2) (3) 4 0.1 A 5 s 2 s Due to sharing of internal bias circuitry, the quiescent current, with all channels operating, is less than the single individual channel quiescent current channels added together. Note that the I2C circuitry is still active while in disable mode. The current shown has no activity with the THS7313 I2C circuitry. THS7313 www.ti.com SLOS483 - NOVEMBER 2005 ELECTRICAL CHARACTERISTICS, VS+ = 5 V RL = 150 to GND, Input Bias = dc, SAG pin shorted to the output pin (unless otherwise noted) TYP PARAMETER TEST CONDITIONS OVERTEMPERATURE 25C 25C 0C to 70C -40C to 85C UNITS MIN/MAX 6.7/9.3 6.55/9.45 6.5/9.5 MHz Min/Max AC PERFORMANCE Small-signal bandwidth (-3 dB) VO- 0.2 VPP (1) 8 Large-signal bandwidth (-3 dB) VO- 2 VPP (1) 8 MHz Group delay f = 100 kHz 67 ns Group delay variation with respect to 100 kHz f = 5.1 MHz 13.5 ns Channel-to-Channel group delay variation f = 5.1 MHz 0.5 ns Attenuation with respect to 100 kHz f = 5.75 MHz 0.5 -0.2 / 2 -0.4 / 2.2 -0.5 / 2.3 dB Min/Max f = 27 MHz 48 36 35 34 dB Min Mute feed-thru f = 1 MHz -80 Differential gain NTSC/PAL 0.08%/0.16 % Differential phase NTSC/PAL 0.18/0.18 Total harmonic distortion f = 1 MHz, VO = 2 VPP -67 dB Signal to noise ratio Unified weighting 100 kHz to 6 MHz 82 dB Channel-to-Channel Crosstalk f = 1 MHz -64 dB MUX Isolation f = 5.1 MHz 73 AC gain - All channels f = 100 kHz 6 Output impedance f = 10MHz 0.7 Output offset voltage Bias = dc 30 Average offset voltage drift Bias = dc dB dB 5.7/6.3 5.65/6.35 5.65/6.35 dB Min/Max DC PERFORMANCE 90 95 95 mV 20 V/C Max Bias = dc + 135 mV, VI = 0 V 290 235/345 215/360 200/375 mV Min/Max Bias = ac 2.5 2.3/2.7 2.25/2.75 2.25/2.75 V Min/Max Sync tip clamp output voltage Bias = ac STC 300 230/375 215/385 210/390 mV Min/Max Input bias current Bias = dc - implies Ib out of the pin -0.6 -4 -5 -5 A Max Average bias current drift Bias = dc 10 nA/C Bias output voltage Sync tip clamp bias current Bias = ac STC, low bias 1.9 0.6/3.3 0.5/3.5 0.4/3.6 A Min/Max Bias = ac STC, mid bias 6 4.3/8.2 4.1/8.4 4/8.5 A Min/Max Bias = ac STC, high bias 8.2 6.2/10.8 6/11 5.9/11.1 A Min/Max 0/2.4 0/2.35 0/2.3 0/2.3 V Min/Max INPUT CHARACTERISTICS Input voltage range Input resistance Bias = dc - limited by output Bias = ac bias mode 19 k Bias = dc, dc + 135 mV, ac STC 3 M 2 pF Input capacitance OUTPUT CHARACTERISTICS High output voltage swing Low output voltage swing (1) RL = 150 to midrail 4.8 4.4 4.3 4.3 V Min RL = 150 to GND 4.65 4.2 4.1 4.1 V Min RL = 75 to midrail 4.7 4.3 4.2 4.2 V Min RL = 75 to GND 4.4 4.1 4 4 V Min RL = 150 to midrail 0.2 0.34 0.37 0.37 V Max RL = 150 to GND 0.1 0.23 0.26 0.27 V Max RL = 75 to Midrail 0.35 0.46 0.5 0.5 V Max RL = 75 to GND 0.1 0.23 0.26 0.27 V Max The Min/Max values listed are specified by design only. 5 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 ELECTRICAL CHARACTERISTICS, VS+ = 5 V (continued) RL = 150 to GND, Input Bias = dc, SAG pin shorted to the output pin (unless otherwise noted) TYP PARAMETER Output current TEST CONDITIONS OVERTEMPERATURE 25C 25C 0C to 70C -40C to 85C UNITS MIN/MAX RL = 10 to Midrail, sourcing 85 60 57 55 mA Min RL = 10 to Midrail, sinking 85 60 57 55 mA Min 5 5.5 5.5 5.5 V Max POWER SUPPLY Maximum operating voltage Minimum operating voltage Maximum quiescent current Per channel VI = 200 mV Minimum quiescent current Per channel VI = 200 mV Total quiescent current All channels ON, VI = 200 mV Power supply rejection (+PSRR) VS+ = 3.5 V to 3.1 V (2) 5 2.6 2.6 2.6 V Min 6.6 7.9 8.1 8.2 mA Max 6.6 5.3 5.1 5 mA Min 18.9 59 mA 38 36 36 dB Min 0.1 A Max 5 s 2 s DISABLE CHARACTERISTICS (3) Quiescent current All 3 channels disabled Turn-on time delay (tON) Time reaches 50% of final value after I2C control is completed Turn-on time delay (tOFF) (2) (3) 6 Due to sharing of internal bias circuitry, the quiescent current, with all channels operating, is less than the single individual channel quiescent current channels added together. Note that the I2C circuitry is still active while in disable mode. The current shown has no activity with the THS7313 I2C circuitry. THS7313 www.ti.com SLOS483 - NOVEMBER 2005 TIMING REQUIREMENTS (1) VS+ = 2.7 V to 5 V STANDARD MODE PARAMETER FAST MODE MIN MAX MIN MAX 0 100 0 400 UNIT fSCL Clock frequency, SCL tw(H) Pulse duration, SCL high 4 0.6 tw(L) Pulse duration, SCL low 4.7 1.3 tr Rise time, SCL and SDA tf Fall time, SCL and SDA tsu(1) Setup time, SDA to SCL 250 100 ns th(1) Hold time, SCL to SDA 0 0 ns t(buf) Bus free time between stop and start conditions 4.7 1.3 s tsu(2) Setup time, SCL to start condition 4.7 0.6 s th(2) Hold time, start condition to SCL 4 0.6 s tsu(3) Setup time, SCL to stop condition 4 0.6 s Cb Capacitive load for each bus line (1) 1000 300 400 kHz s s 300 ns 300 ns 400 pF The THS7313 I2C address = 01011(A1)(A0)(R/W). See the application information section for more information. t w(H) t w(L) tr tf SCL t su(1) t h(1) SDA Figure 2. SCL and SDA Timing SCL t su(2) t h(2) t su(3) t (buf) SDA Start Condition Stop Condition Figure 3. Start and Stop Conditions 7 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 FUNCTIONAL DIAGRAM C h an n e l 1 In p u t A C h an n e l 2 In p u t A C h an n e l 3 In p u t A 2 :1 X1 + LP F 8 MHz DC + 135 mV DC ACBIAS 2:1 AC Sync TIP Clamp MUTE X1 C h an n e l 1 In p u t B DC ACBIAS AC Sync TIP Clamp 675 W 1 kW 878 W - C h an n e l 1 SA G C h an n e l 2 Ou tp u t 675 W 878 W 1 kW MUTE 150 W + LP F 8 MHz DC + 135 mV C h an n e l 1 Ou tp u t - 150 W C h an n e l 2 SA G C h an n e l 2 In p u t B C h an n e l 3 In p u t B 2:1 DC + 135 mV X1 AC Sync TIP Clamp DC ACBIAS SD A SC L NOTE: The I2C Address of the THS7313 is 01011(A1)(A0)(R/W) 8 + LP F 8 MHz 1 kW MUTE I2C A1 I2 C A0 - C h an n el 3 Ou tp u t 675 W 878 W Vs+ 150 W C h an n e l 3 SA G THS7313 www.ti.com SLOS483 - NOVEMBER 2005 PIN CONFIGURATION THS7313PW TSSOP (20-Pin) (Top View) A. NC indicates there is no internal connection to these pins. It is recommended, but not required, to connect these pins to GND. TERMINAL FUNCTIONS TERMINAL NAME NO. N/C 1, 20 DESCRIPTION No Internal Connection. It is recommended, but not required, to connect these pins to GND CH. 1 - INPUT A 2 Video Input Channel 1. Input A CH. 2 - INPUT A 3 Video Input Channel 2. Input A CH. 3 - INPUT A 4 Video Input Channel 3. Input A CH. 1 - INPUT B 5 Video Input Channel 1. Input B CH. 2 - INPUT B 6 Video Input Channel 2. Input B CH. 3 - INPUT B 7 Video Input Channel 3. Input B I2C-A1 8 I2C Slave Address Control Bit A.1 Connect to Vs+ for a logic 1 preset value or GND for a logic 0 preset value. I2C-A0 9 I2C Slave Address Control Bit A0. Connect to Vs+ for a logic 1 preset value or GND for a logic 0 preset value. GND 10 Ground reference pin for all internal circuitry Vs+ 11 Positive Power Supply Input Pin. Connect to 2.7 V to 5 V SDA 12 Serial data line of the I2C bus. The pull-up resistor should have a minimum value = 2-k and a maximum value = 19-k. Pull up to Vs+ SCL 13 I2C bus Clock Line. The pull-up resistor should have a minimum value = 2-k and a maximum value = 19 k. Pull up to Vs+ CH. 3 - SAG 14 Video output channel 3 SAG Correction Pin. If SAG is not used, connect directly to CH. 3 - OUTPUT pin. CH. 3 - OUTPUT 15 Video output channel 3 from either CH. 3 - INPUT A or CH. 3 - INPUT B CH. 2 - SAG 16 Video output channel 2 SAG correction pin. If SAG is not used, connect directly to CH. 2 - OUTPUT pin. CH. 2 - OUTPUT 17 Video output channel 2 from either CH. 2 - INPUT A or CH. 2 - INPUT B CH. 1 - SAG 18 Video output channel 1 SAG correction pin. If SAG is not used, connect directly to CH. 1 - OUTPUT pin. CH. 1 - OUTPUT 19 Video output channel 1 from either CH. 1 - INPUT A or CH. 1 - INPUT B 9 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 TYPICAL CHARACTERISTICS SMALL AND LARGE SIGNAL FREQUENCY RESPONSE SMALL AND LARGE SIGNAL FREQUENCY RESPONSE 10 6.5 5 6 0 -5 Signal Gain - dB Signal Gain - dB 5.5 5 4.5 VS = 3.3 V RL = 150 W || 13 pF 4 -10 -15 -20 -25 VS = 3.3 V -30 RL = 150 W || 13 pF -35 Solid Line = 200 mVPP, Dashed Line = 2.6 VPP 3.5 Solid Line = 200 mVPP, Dashed Line = 2.6 VPP -40 -45 3 0.1 1 -50 0.1 10 10 Figure 4. Figure 5. GROUP DELAY vs FREQUENCY 1000 PHASE RESPONSE vs FREQUENCY 45 80 VS = 3.3 V VO = 200 mVPP 75 RL = 150 W || 13 pF VS = 3.3 V VO = 200 mVPP 0 RL = 150 W || 13 pF -45 70 -90 Phase - o 65 60 -135 -180 55 -225 50 45 -270 40 -315 35 0.1 1 10 f - Frequency - MHz -360 0.1 100 1 10 f - Frequency - MHz Figure 6. 3.3 V DIFFERENTIAL GAIN 0.18 100 Figure 7. 3.3 V DIFFERENTIAL PHASE 0.2 0.12 VS = 3.3 V VS = 3.3 V RL = 150 W || 13 pF 0.1 PAL 0.16 RL = 150 W || 13 pF NTSC Differential Phase - o Differential Gain - % 100 f - Frequency - MHz 90 Group Delay - ns 1 f - Frequency - MHz 0.14 0.12 0.1 0.08 0.06 0.08 PAL 0.06 0.04 NTSC 0.04 0.02 0.02 0 0 1st 2nd 3rd 4th Figure 8. 10 5th 6th 1st 2nd 3rd 4th Figure 9. 5th 6th THS7313 www.ti.com SLOS483 - NOVEMBER 2005 TYPICAL CHARACTERISTICS (continued) HD2 vs OUTPUT VOLTAGE HD3 vs OUTPUT VOLTAGE -40 VS = 3.3 V, f = 1 MHz, RL = 150 W || 13 pF -45 3rd Order Harmonic distortion - dB 2nd Order Harmonic Distortion - dB -40 -50 -55 -60 -65 -70 VS = 3.3 V, f = 1 MHz, RL = 150 W || 13 pF -50 -60 -70 -80 -90 -75 -80 -100 0 0.5 1 1.5 2 2.5 3 0 0.5 1.5 1 2.5 2 VO - Output Voltage - VPP VO - Output Voltage - VPP Figure 10. Figure 11. SMALL SIGNAL FREQUENCY RESPONSE vs CAPACITIVE LOAD LARGE SIGNAL PULSE RESPONSE 3 3.25 10 3 0 CL = 23 pF -20 CL = 13 pF -30 CL = 35 pF -40 -50 -60 2.5 2.25 2 1.75 1.5 1.25 1 VS = 3.3 V, VO = 0.2 VPP, VS = 3.3 V, 0.75 RL = 150 W || CL -70 0.1 1 RL = 150 W || 13 pF 0.5 10 100 1000 0.25 -100 0 100 200 300 400 500 600 f - Frequency - MHz t - Time - ns Figure 12. Figure 13. NTSC NTC7 COMPOSITE RESPONSE 480i G'B'R' PULSE RESPONSE VS = 3.3 V CVBS B' Luma G' Figure 14. 800 R' Chroma t - Time = 1000 ns/div 700 VS = 3.3 V 143 mV/div 200 mV/div Signal Gain - dB -10 VO - Output Voltage - V 2.75 t - Time = 100 ns/div Figure 15. 11 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 TYPICAL CHARACTERISTICS (continued) 480i G'B'R' INPUT SOURCE 576i PULSE RESPONSE P'R 143 mV/div 143 mV/div Input Source R' P'B B' G' VS = 3.3 V Y' t - Time = 2 ms/div t - Time = 100 ns/div Figure 16. Figure 17. OUTPUT IMPEDANCE vs FREQUENCY SLEW RATE vs OUTPUT VOLTAGE 100 60 VS = 3.3 V, VS = 3.3 V RL = 150 W || 13 pF SR - Slew Rate - V/ms ZO - Output Impedance - W 50 10 1 40 30 20 0.1 10 0.01 0.1 1 10 f - Frequency - MHz 0 100 0.5 1 1.5 Figure 18. VS = 5 V 70 -55 60 Mux Feed Through - dB PSRR - Power Supply Rejection Ratio - dB -50 50 VS = 3.3 V 30 20 10 Applied Signal to Unselected MUX Measured Output of Channel Referred to Applied Signal Input VS = 3.3 V, RL = 150 W || 13 pF -60 -65 -70 -75 -80 -85 0.1 1 10 f - Frequency - MHz Figure 20. 12 3 MUX FEED THROUGH vs FREQUENCY 80 0 0.01 2.5 Figure 19. POWER SUPPLY REJECTION RATIO vs FREQUENCY 40 2 VO - Output Voltage - VPP 100 -90 0.1 1 10 f - Frequency - MHz Figure 21. 100 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 TYPICAL CHARACTERISTICS (continued) MUTE FEED THROUGH vs FREQUENCY CROSSTALK vs FREQUENCY -50 -40 Worst Case Crosstalk Referred to Input RL = 150 W || 13 pF VS = 3.3 V and 5 V Mute Feed Through - dB -50 RL = 150 W || 13 pF -55 -60 Crosstalk - dB -60 -70 -65 VS = 3.3 V -70 VS = 5 V -80 -75 -90 -80 -100 0.1 1 10 100 -85 0.1 1000 1 10 Figure 22. Figure 23. INPUT BIAS CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs SUPPLY VOLTAGE 9 9 8 8 STC - High IIB - Input Bias Current - mA IIB - Input Bias Current - mA 7 6 STC - Mid 5 4 VS = 3.3 V 3 2 STC - Low 1 0 -40 100 f - Frequency - MHz f - Frequency - MHz 7 6 0 20 40 60 80 5 o TA = 25 C 3 2 STC - Low 1 -1 2.6 100 STC - Mid 4 0 -20 STC - High DC Input 3 3.4 o TA - Ambient Temperature - C 3.8 4.6 4.2 5 VS - Supply Voltage - V Figure 24. Figure 25. SMALL AND LARGE SIGNAL FREQUENCY RESPONSE SMALL AND LARGE SIGNAL FREQUENCY RESPONSE 10 6.5 5 6 0 -5 Signal Gain - dB Signal Gain - dB 5.5 5 4.5 4 3.5 3 0.1 VS = 5 V RL = 150 W || 13 pF -10 -15 -20 -25 -30 VS = 5 V RL = 150 W || 13 pF -35 Solid Line = 200 mVPP, Dashed Line = 2.6 VPP -40 -45 1 10 -50 0.1 Solid Line = 200 mVPP, Dashed Line = 2.6 VPP 1 10 f - Frequency - MHz f - Frequency - MHz Figure 26. Figure 27. 100 1000 13 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 TYPICAL CHARACTERISTICS (continued) GROUP DELAY vs FREQUENCY PHASE vs FREQUENCY 45 85 VS = 5 V VO = 200 mVPP 80 RL = 150 W || 13 pF 0 -45 75 -90 Phase - Group Delay - ns 90 70 65 -135 -180 60 -225 55 50 -270 45 -315 40 0.1 1 10 f - Frequency - MHz VS = 5 V, VO = 200 mVPP, RL = 150 W || 13 pF -360 0.1 100 1 Figure 28. 5 V DIFFERENTIAL GAIN 5 V DIFFERENTIAL PHASE 0.2 VS = 5 V 0.18 RL = 150 W || 13 pF VS = 5 V RL = 150 W || 13 pF PAL 0.16 Differential Phase - o 0.16 Differential Gain - % 100 Figure 29. 0.2 0.18 10 f - Frequency - MHz 0.14 0.12 0.1 0.08 0.06 0.14 PAL 0.12 0.1 NTSC 0.08 0.06 NTSC 0.04 0.04 0.02 0.02 0 0 1st 2nd 3rd 4th 5th 6th 1st 2nd Figure 30. HD2 vs FREQUENCY 3rd Order Harmonic distortion - dB 2nd Order Harmonic distortion - dB 6th HD3 vs FREQUENCY VS = 5 V, VO = 2 VPP, RL = 150 W || 13 pF -65 -70 -75 1 f - Frequency - MHz Figure 32. 14 5th -70 -60 -80 0.1 4th Figure 31. -50 -55 3rd 10 -75 VS = 5 V, VO = 2 VPP, RL = 150 W || 13 pF -80 -85 -90 -95 -100 0.1 1 f - Frequency - MHz Figure 33. 10 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 TYPICAL CHARACTERISTICS (continued) HD2 vs OUTPUT VOLTAGE HD3 vs OUTPUT VOLTAGE -40 VS = 5 V, f = 1 MHz, RL = 150 W || 13 pF -50 3rd Order Harmonic Distortion - dB 2nd Order Harmonic Distortion - dB -40 -60 -70 -80 VS = 5 V, f = 1 MHz, RL = 150 W || 13 pF -50 -60 -70 -80 -90 -100 -90 -110 0 1 2 3 4 5 0 1 2 3 4 5 VO - Output Voltage - VPP VO - Output Voltage - VPP Figure 34. Figure 35. SMALL SIGNAL FREQUENCY RESPONSE vs CAPACITIVE LOAD SMALL SIGNAL PULSE RESPONSE 10 1.25 0 1.15 VO - Output Voltage - V Signal Gain - dB -10 CL = 23 pF -20 CL = 35 pF -30 CL = 13 pF -40 -50 -60 VS = 5 V, VO = 0.2 VPP, 1.05 0.95 0.85 0.75 VS = 5 V, RL = 150 W || 13 pF 0.65 RL = 150 W || CL -70 0.1 1 10 100 0.55 -100 1000 0 100 200 300 400 f - Frequency - MHz t - Time - ns Figure 36. Figure 37. LARGE SIGNAL PULSE RESPONSE 500 600 700 800 SLEW RATE vs OUTPUT VOLTAGE 3 80 VS = 5 V, 2.75 70 RL = 150 W || 13 pF 60 SR - Slew Rate - V/ms VO - Output Voltage - V 2.5 2.25 2 1.75 1.5 1.25 RL = 150 W || 13 pF 0 100 200 300 30 10 0.75 0.5 -100 40 20 VS = 5 V, 1 50 400 t - Time - ns Figure 38. 500 600 700 800 0 0.5 1 1.5 2 2.5 3 3.5 4 VO - Output Voltage - VPP Figure 39. 15 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 TYPICAL CHARACTERISTICS (continued) OUTPUT IMPEDANCE vs FREQUENCY MUX FEED THROUGH vs FREQUENCY 100 -50 VS = 5 V Applied Signal to Unselected MUX Measured Output of Channel Referred to Applied Signal Input 10 Mux Feed Through - dB ZO - Output Impedance - W -55 1 0.1 VS = 5 V RL = 150 W || 13 pF -60 -65 -70 -75 -80 -85 0.01 0.1 1 10 f - Frequency - MHz 100 -90 0.1 1 10 Figure 40. Figure 41. NTSC NTC7 COMPOSITE RESPONSE PAL MULTIPULSE RESPONSE VS = 5 V VS = 5 V 250 mV/div 200 mV/div 100 f - Frequency - MHz CVBS CVBS Input Chroma Luma CVBS Output t - Time = 500 ns/div t - Time = 1000 ns/div Figure 42. Figure 43. 480i G'B'R' PULSE RESPONSE 576i PULSE RESPONSE 143 mV/div 143 mV/div VS = 5 V R' P'R P'B B' t - Time = 100 ns/div Figure 44. 16 VS = 5 V Y' G' t - Time = 2 ms/div Figure 45. THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION The THS7313 is targeted for video output buffer applications. Although it can be used for numerous other applications, the needs and requirements of the video signal are the most important design parameters of the THS7313. Built on the complimentary silicon germanium (SiGe) BiCom-3 process, the THS7313 incorporates many features not typically found in integrated video parts while consuming low power. Each channel configuration is completely independent of the other channels. This allows for configurations for each channel to be dictated by the end user and not device. The resulting highly flexible system contains the following features: * I2C Interface for easy interfacing to the system. * Single-supply 2.7-V to 5-V operation with low total quiescent current of 16.6 mA with 3.3-V supply and 18.9 mA with 5-V supply. * 2:1 input MUX. * Input configuration accepting dc, dc + 135 mV shift, ac bias, or ac sync-tip clamp selection. * 5th order low-pass filter for DAC reconstruction or ADC image rejection : - 8-MHz for SDTV NTSC/PAL/SECAM, S-Video, component 480i/576i Y'P'BP'R, and G'B'R' (R'G'B') signals. * Internal fixed gain of 2 V/V (6 dB) buffer that can drive 2 video lines with dc coupling, traditional ac coupling, or SAG corrected ac coupling. * Shutdown mode which reduces quiescent current to as low as 0.1-A or a mute function that keeps the THS7313 powered on, but does not allow a signal to pass through. * Signal flow-through configuration using a 20-pin TSSOP package that complies with the latest lead-free (RoHS compatible) and green manufacturing requirements. OPERATING VOLTAGE The THS7313 is designed to operate from 2.7 V to 5 V over a -40C to 85C temperature range. The impact on performance over the entire temperature range is negligible due to the implementation of thin film resistors and low-temperature coefficient capacitors. The power supply pins should have a 0.1-F to 0.01-F capacitor placed as close as possible to these pins. Failure to do so may result in the THS7313 outputs ringing or oscillating. Additionally, a large capacitor, such as 22 F to 100 F, should be placed on the power supply line to minimize issues with 50/60 Hz line frequencies. INPUT VOLTAGE The THS7313 input range allows for an input signal range from Ground to (VS+- 1.4 V). But, due to the internal fixed gain of 2 V/V (6 dB), the output is the limiting factor for the allowable linear input range. For example, with a 5-V supply, the linear input range is from GND to 3.6 V. But due to the gain, the linear output range limits the allowable linear input range to be from GND to a maximum of 2.5 V. INPUT OVERVOLTAGE PROTECTION The THS7313 is built using a high-speed complementary bipolar and CMOS process. The internal junction breakdown voltages are low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 46. 17 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) VS+ External Input/ Output Pin Internal Circuitry Figure 46. Internal ESD Protection These diodes provide moderate protection to input overdrive voltages above and below the supplies. The protection diodes can typically support 30-mA of continuous current when overdriven. TYPICAL CONFIGURATION and VIDEO TERMINOLOGY A typical application circuit using the THS7313 as a video buffer is shown in Figure 47. It shows a DAC (or encoder such as the THS8200) driving the three input channels of the THS7313. Although the S-Video Y' and C' channels and the composite video baseband signal (CVBS) channel of a standard definition video (SD) system are shown, these channels can also be the Y'P'BP'R (sometimes labeled Y'U'V' or incorrectly labeled Y'C'BC'R) signals of a 480i or 576i system. These signals could be G'B'R' (R'G'B') signals or other variations. Note that for computer signals the sync should be embedded within the signal for a system with only 3-outputs. This is sometimes labeled as R'G'sB' (sync on green) or R'sG'sB's (sync on all signals). The second set of inputs (B-Channels) shown are being driven from an external input typically used as a pass-through function. These are traditional SD or professional G'B'R' video signals. The THS7313's flexibility allows for almost any input signal to be driven into the THS7313 regardless of the other set of inputs. Control of the I2C configures the THS7313. For example, the THS7313 can be configured to have Channel 1 Input connected to input A while Channels 2 and 3 are connected to input B. The various sections explaining the I2C interface later in this data sheet. Note that the Y' term is used for the luma channels throughout this document rather than the more common luminance (Y) term. The reason is to account for the definition of luminance as stipulated by the CIE International Commission on Illumination. Video departs from true luminance since a nonlinear term, gamma, is added to the true GBR signals to form G'B'R' signals. These G'B'R' signals are then used to mathematically create luma (Y'). Thus luminance (Y) is not maintained providing a difference in terminology. This rationale is also used for the chroma (C') term. Chroma is derived from the nonlinear G'B'R' terms and thus it is nonlinear. Chominance (C) is derived from linear GBR giving the difference between chroma (C') and chrominance (C). The color difference signals (P'B / P'R / U' / V') are also referenced this way to denote the nonlinear (gamma corrected) signals. R'G'B' (commonly mislabeled RGB) is also called G'B'R' (again commonly mislabeled as GBR) in professional video systems. The SMPTE component standard stipulates that the luma information is placed on the first channel, the blue color difference is placed on the second channel, and the red color difference signal is placed on the third channel. This is consistent with the Y'P'BP'R nomenclature. Because the luma channel (Y') carries the sync information and the green channel (G') also carries the sync information, it makes logical sense that G' be placed first in the system. Since the blue color difference channel (P'B) is next and the red color difference channel (P'R) is last, then it also makes logical sense to place the B' signal on the second channel and the R' signal on the third channel respectfully. Thus, hardware compatibility is better achieved when using G'B'R' rather than R'G'B'. Note that for many G'B'R' systems, sync is embeded on all three channels; however, this may not be true in all systems. 18 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) 3.3 V DAC / Encoder (THS8200) CVBS R SDTV CVBS S-Video Y' S-Video C' 480i 576i G'B'R' 470 mF + DC + 135 mV Y' 1 NC 2 CH.1 IN A R DC + 135 mV R AC STC AC Bias 0.1 mF CVBS 75 W 0.1 mF CH. 1 SAG 18 CH.2 OUT 17 5 CH.1 IN B CH. 2 SAG 16 6 CH.2 IN B CH.3 OUT 15 7 CH.3 IN B CH. 3 SAG 14 8 I 2C-A1 SCL 13 9 I 2C-A0 SDA 12 10 GND 75 W CH.1 OUT 19 4 CH.3 IN A AC STC (See Note A) NC 20 3 CH.2 IN A DC + 135 mV C' 75 W CVBS Out 470 mF + (See Note A) Y' Out S-Video 0.1 mF + C' Out 75 W 75 W 75 W +Vs VS+ 11 S-Video Y' 75 W + 75 W 0.1 mF 0.01 mF 100 mF 2 IC Controller S-Video C' 75 W External Input A. Due to the high frequency content of the video signal, it is recommended, but not required, to add a 0.01-F capacitor in parallel with these large capacitors. Figure 47. Typical SDTV CVBS/Y'/C' Inputs From DC-Coupled Encoder/DAC and AC-Coupled External Inputs With AC-Coupled Line Driving INPUT MODES OF OPERATION - DC The inputs to the THS7313 allows for both ac coupled and dc coupled inputs. Many DAC's or video encoders can be dc connected to the THS7313. But, one of the drawbacks to dc coupling is when 0 V is applied to the input of the THS7313. Although the input of the THS7313 allows for a 0-V input signal, the output swing of the THS7313 cannot yield a 0-V signal. This applies to any traditional single-supply amplifier due to the limitations of the output transistors. Both CMOS and bipolar transistors cannot go to 0 V while sinking a significant amount of current. This trait of a transistor is also the same reason why the highest output voltage is always less than the power supply voltage when sourcing a significant amount of current. The internal gain is fixed at 6 dB (2 V/V) regardless of the configuration of the THS7313, and dictates what the allowable linear input voltage range is without clipping concerns. For example, if the power supply is set to 3 V, the maximum output is about 2.9 V. Thus, to avoid clipping, the allowable input is 2.9 V / 2 = 1.45 V. This is true for up to the maximum recommended 5-V power supply that allows about a 4.9 V / 2 = 2.45 V input range while avoiding clipping on the output. The input impedance of the THS7313 in this mode of operation is >1 M. This is due to the input buffer being configured as a unity gain amplifier as shown in Figure 48. 19 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) VS+ Input Internal Circuitry Input Pin Figure 48. Equivalent DC Input Mode Circuit The input stage of the THS7313 is designed with PNP bipolar transistors. There is a finite amount of bias current flowing out of the THS7313 input pin. This bias current, typically about 0.6 A, must have a path to flow or else the input stage voltage increases. For example, if there is a 1-M resistance to ground on the input node, the resulting voltage appearing at the input node is 0.6 A x 1 M = 0.6 V. Therefore, it should be noted that if a channel is powered on and has no input termination, the input bias current causes the input stage to float high until saturation of the input stage exists - about 1.4 V from the power supply. Typically, this is not a concern as most terminations result in an equivalent source impedance of 75- to 300-. INPUT MODES OF OPERATION - DC + 135 mV SHIFT Clipping occurs with a 0-V applied input signal when the input mode is set to dc. The clipping can reduce the sync amplitudes (both horizontal and vertical sync amplitudes) on the video signal. A problem occurs if the receiver of this video signal uses an AGC loop to account for losses in the transmission line. Some video AGC circuits derive gain from the horizontal sync amplitude. If clipping occurs on the sync amplitude, then the AGC circuit can increase the gain too much - resulting in too much luma and/or chroma amplitude gain correction. This may result in a picture with an overly bright display with too much color saturation. Other AGC circuits use the chroma burst amplitude for amplitude control, and a reduction in the sync signals does not alter the proper gain setting. But, it is good engineering design practice to ensure saturation/clipping does not take place. Transistors always take a finite amount of time to come out of saturation. This saturation could possibly result in timing delays or other aberrations on the signals. To eliminate saturation / clipping problems, the THS7313 has a dc + 135 mV shift input mode. This mode takes the input voltage and adds an internal +135 mV shift to the signal. Since the THS7313 also has a gain of 6 dB (2 V/V), the resulting output with a 0-V applied input signal is be 270 mV. The THS7313 rail-to-rail output stage can create this level while connected to a typical video load. This ensures that no saturation / clipping of the sync signals occurs. This is a constant shift regardless of the input signal. For example, if a 1-V input is applied, the output is at 2.27 V. As with the dc-input mode, the input impedance of the THS7313 is > 1 M. Additionally, the same input bias current of about 0.6 A appears at the input. Following the same precautions as stipulated with the dc-input mode of operation minimizes any potential issues. Figure 49 shows the equivalent input circuit while in the dc + 135 mV shift mode of operation. Note that the internal voltage shift does not appear at the input pin, only the output pin. 20 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) VS+ Internal Circuitry Input Pin Input Level Shifter Figure 49. Equivalent DC + 135 mV Input Mode Circuit INPUT MODES OF OPERATION - AC BIAS Other applications require an ac-coupled input. The ac coupling ensures that a source dc-input level does not alter, or clip, the resulting output video signal. The first ac coupling mode is the AC Bias mode where a simple internal dc bias voltage is applied to the input signal on the THS7313 side of the external 1-F coupling capacitor. The applied dc bias voltage is set internally by a resistor divider circuit as shown in Figure 50. The dc bias voltage is set to VS+/ 4. With a 3.3-V power supply, the input bias voltage is nominally 0.825 V, and with 5-V supply, the input bias voltage is nominally 1.25 V. The input impedance with this mode is approximately 19-k. With a 1-F input capacitor, it sets a high-pass corner frequency of about 9-Hz. If a lower frequency is desired, increasing the capacitor decreases the corner frequency proportionally. For example, using a 4.7-F capacitor results in a 1.8-Hz high pass corner frequency, and results in lower droop (tilt). Using any capacitor value is acceptable for this mode of operation. It is sometimes desirable to adjust the bias voltage to another level other than the one dictated by the internal resistors. There are two ways this is accomplished: 1. The first is to add an external resistor between the input pin and either the +Vs or GND. This creates a new bias voltage equal to +Vs x [25 k / {25 k + (75 k || Rpu)}] for raising the bias voltage, or +Vs x [(25 k || Rpd) / {(25 k || Rpd) + 75 k}] for reducing the bias voltage. 2. The second method to set the AC-Bias voltage is to use the Rpu and Rpd external resistors, but place the THS7313 in dc input bias mode. Since the dc mode is very high impedance, the resulting bias voltage is equal to +Vs x (Rpd / {Rpd + Rpu}). This mode of operation is recommended for use with chroma (C'), P'B, P'R, U', V', and nonsync B' and R' signals. VS+ VS+ Rpu (See Note A) Internal Circuitry VS+ 75 kW Input Pin Input CI Rpd (See Note A) 25 kW NOTE: Use external pull-up and/or pull-down resistors if changing the ac-bias input voltage is desired. Figure 50. Equivalent AC Bias Input Mode Circuit 21 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) INPUT MODES OF OPERATION - AC SYNC TIP CLAMP The last input mode of operation is the ac with sync-tip-clamp (STC) which also requires a capacitor in series with the input. Note that while the term sync-tip-clamp is used throughout this document, the THS7313 is better termed as a dc restoration circuit based on the way this function is performed. This circuit is an active clamp circuit and not a passive diode clamp function. This function should be used when ac coupling is desired with signals that have sync signals embedded such as CVBS, Y', and G' signals. The input to the THS7313 has an internal control loop which sets the lowest input applied voltage to clamp at approximately 135 mV. Like the dc + 135 mV input shift, the resulting output voltage low level is about 270 mV. If the input signal tries to go below the 135-mV level, the internal control loop of the THS7313 sources up to 2 mA of current to increase the input voltage level on the THS7313 input side of the coupling capacitor. As soon as the voltage goes above the 135-mV level, the loop stops sourcing current. One of the concerns about the sync-tip-clamp level is how the clamp reacts to a sync edge that has overshoot - common in VCR signals or reflections found in poor PCB layouts. Ideally the STC should not react to the overshoot voltage of the input signal. Otherwise, this could result in clipping on the rest of the video signal because there may be too much increase in the bias voltage. To help minimize this input signal overshoot problem, the patent-pending internal STC control loop in the THS7313 has an I2C selectable low-pass filter as shown in Figure 51. This filter can be selected to be about 500 kHz, 2.5 MHz, or 5 MHz. The effect of this filter is to slow down the response of the control loop so as not to clamp on the input overshoot voltage, but rather the flat portion of the sync signal. If the input signal is known to be well controlled - such as coming from a video encoder - then selecting the 5-MHz filter should yield excellent results. But, if the input signal is coming from an unknown source, then selecting the 2.5-MHz or 500-kHz filter may yield the best results. There is a noticeable delay of the STC loop when the 500-kHz filter is selected. As a result of this selectable delay, the sync has an apparent voltage shift occurring between 15 ns and 2 s - depending on the STC LPF. The amount of shift is dependant upon the amount of droop in the signal as dictated by the input capacitor and the STC input bias current selection. Because the sync is primarily for timing purposes with syncing occurring on the edge of the sync signal, this shift is transparent in most systems. Note that if the source signal is known to be good, selecting the 5-MHz STC LPF is recommended for all sources While this feature may not fully eliminate overshoot issues on the input signal in case of bad overshoot and/or ringing, the STC system helps minimize improper clamping levels. As an additional method to help minimize this issue, an external capacitor (example: 10 pF to 47 pF) to ground in parallel with the external termination resistors can help filter overshoot problems. It should be noted that this STC system is dynamic and does not rely upon timing in any way. It only depends on the voltage appearing at the input pin at any given point in time. The STC filtering helps minimize level shift problems associated with switching noises or short spikes on the signal line. This helps ensure a robust STC system. VS+ Input Pin Input 0.1 mF VS+ 135 mV STC LPF Internal Circuitry Comparator 1.8 mA STC 5.8 mA Bias 7.8 mA Select Figure 51. Equivalent AC Sync Tip Clamp Input Mode Circuit 22 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) When the ac sync-tip-clamp (STC) operation is used, there must also be some finite amount of discharge bias current. As previously described, if the input signal goes below the 135-mV clamp level, the internal loop of the THS7313 sources current to increase the voltage appearing at the input pin. As the difference between the signal level and the 135-mV reference level increases, the amount of source current increases proportionally - supplying up to 2-mA of current. Thus the time to re-establish the proper STC voltage can be fast. If the difference is small, then the source current is also small to account for minor voltage droop. But, what happens if the input signal goes above the 135-mV input level? The problem is the video signal is always above this level and must not be altered in any way. But, if the Sync level of the input signal is above the 135-mV level, then the internal discharge (sink) current reduces the ac-coupled bias signal to the proper 135-mV level. This discharge current must not be large enough to alter the video signal appreciably or picture quality issues may arise. This is often seen by looking at the tilt (droop) of a constant luma signal being applied, and looking at the resulting output level. The associated change in luma level from the beginning of the video line to the end of the video line is the amount of line tilt (droop). The amount of tilt can be seen by the general formula: I = C dV/dt where I is the discharge current and C is the external coupling capacitor which is typically 0.1 F. If the current (I) and the capacitor (C) are constant, then the tilt is governed by: i/C = dV/dt If the discharge current is small the amount of tilt is low which is good. But, the amount of time for the system to capture the sync signal could be too long. This is also termed hum rejection. Hum arises from the ac line voltage frequency of 50 Hz or 60 Hz. The value of the discharge current and the ac-coupling capacitor combine to dictate the hum rejection and the amount of line tilt. Because many users have different thoughts as to the proper amount of hum rejection and line tilt, the THS7313 has incorporated a variable sink bias current selectable through the I2C interface. The Low Bias mode selects about 1.8-A of dc sink bias current for low line tilt. But, if more hum rejection is desired, then selecting the Mid Bias mode increases the dc sink bias current to about 5.8 A. For severe environments, the high bias mode has about 7.8 A of dc sink bias current. This drawback to these higher bias modes is an increase in line tilt, but with an increase in hum rejection. The other method to change the hum rejection and line tilt is to change the input capacitor used. An increase in the capacitor from 0.1 F to 0.22 F decreases the hum rejection and line tilt by a factor of 2.2. A decrease of this input capacitor accomplishes the opposite effect. Note that the amplifier input bias current of nominally 0.6 A has already been taken into account when stipulating the 1.8-A/5.8-A/7.8-A current sink values. The input impedance of the THS7313 in ac STC mode is typically >1 M. When the STC control loop needs to source current to increase the bias voltage up to 135 mV, the impedance is altered. But, this typically happens quickly and only on the sync signals such that it does not alter the video signal impedance. To ensure proper stability of the ac STC control loop, the source impedance must be less than 600- with the input capacitor in place. Otherwise, there is a possibility of the control loop ringing. The ringing appears on the output of the THS7313. Similar to the dc modes of operation, many DACs and Encoders use a resistor to establish the output voltage. These resistors are typically less than 300 . Thus, stability of the ac STC loop is ensured. But, if the source impedance looking from the THS7313 input perspective is high or open, then adding a 300- resistor to GND ensures proper operation of the THS7313. If a MUX channel is not required in the system, then it is recommended to place a 75- resistor to GND. This is not required, but helps minimize any potential issues. 23 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) OUTPUT MODES OF OPERATION - DC COUPLED The THS7313 incorporates a rail-to-rail output stage that can be used to drive the line directly without the need for large ac-coupling capacitors. This is accomplished by connecting the output pin of each channel directly to the SAG output pin of the corresponding channel as shown in Figure 52. This offers the best line tilt and field tilt (or droop) performance since there is no ac coupling occurring. Keep in mind that if the input is ac coupled, then the resulting tilt due to the input ac coupling is still seen on the output regardless of the output coupling. The 70-mA output current drive capability of the THS7313 is designed to drive two video lines simultaneously - essentially a 75- load - while keeping the output dynamic range as wide as possible. One concern of dc coupling is if the line is terminated to ground. When the ac-bias input mode is selected, the output of the THS7313 is at mid-rail. With 2 lines terminated to ground, this creates a dc current path to exist which results in a slightly decreased high output voltage swing resulting in an increase in power dissipation of the THS7313. While the THS7313 is designed to operate with a junction temperature of up to 125C, care must be taken to ensure that the junction temperature does not exceed this level or else long term reliability could suffer. Although this configuration adds less then 10 mW of power dissipation per channel, the overall low power dissipation of the THS7313 design minimizes potential thermal issues even when using the TSSOP package at high ambient temperatures. 3.3 V DAC / Encoder (THS8200) CVBS SDTV CVBS S-Video Y' S-Video C' 480i 576i G'B'R' R 75 W DC + 135 mV Y' 1 NC 2 CH.1 IN A R DC + 135 mV CH. 1 SAG 18 4 CH.3 IN A CH.2 OUT 17 AC STC R AC STC AC Bias 0.1 mF CVBS 75 W 0.1 mF 5 CH.1 IN B CH. 2 SAG 16 6 CH.2 IN B CH.3 OUT 15 7 CH.3 IN B CH. 3 SAG 14 8 I 2C-A1 SCL 13 9 I 2C-A0 SDA 12 10 GND 75 W NC 20 CH.1 OUT 19 3 CH.2 IN A DC + 135 mV C' CVBS Out 75 W S-Video C' Out 75 W 75 W 75 W +Vs VS+ 11 S-Video Y' Y' Out + 75 W 0.1 mF 0.01 mF 100 mF 2 IC Controller S-Video C' 75 W External Input Figure 52. Typical SDTV CVBS/Y'/C' System With DC-Coupled Line Driving Note that the THS7313 can drive the line with dc coupling regardless of the input mode of operation. The only requirement is to make sure the video line has proper termination in series with the output pin - typically 75-. This helps isolate capacitive loading effects from the THS7313 output. Failure to isolate capacitive loads may result in instabilities with the output buffer potentially causing ringing or oscillations to appear. The stray capacitance appearing directly at the THS7313 output pins should be kept below 25-pF for best performance. When driving 2 video lines, each line should have its own 75- source termination resistors to isolate the lines from each other. 24 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) OUTPUT MODES OF OPERATION - AC COUPLED The most common method of coupling the video signal to the line is by using a large capacitor. This capacitor is typically between 220 F and 1000 F, although 470 F is most common. This value of this capacitor must be this large to minimize the line tilt (droop) and/or field tilt associated with ac coupling as described previously in this document. Just like the dc output configuration, connection of the output pin of each channel directly to the SAG output pin of the corresponding channel should be as close as possible to the output pins of the THS7313. The most common reason ac coupling is to ensure full interoperability with the receiving video system. This eliminates possible ground loops. It also ensures that regardless of the reference dc voltage used on the transmit side, the receive side re-establishes the dc reference voltage to its own requirements. As with the dc output mode of operation, each line should have a 75- source termination resistor in series with the ac-coupling capacitor. If 2 lines are to be driven, it is best to have each line use its own capacitor and resistor rather than sharing these components as shown in Figure 53.This helps ensure line-to-line dc isolation and potential problems. Using a single 1000-F capacitor for 2-lines can be done, but there is a chance for ground loops and interference creation between the two receivers. CVBS Out 1 470 mF (See Note A) + 75 W 3.3 V DAC / Encoder (THS8200) CBVS 75 W R SDTV CVBS S-Video Y' S-Video C' 480i 576i G'B'R' 75 W CVBS Out 2 470 mF (See Note A) + Y' 1 NC R C' R 0.1 mF CVBS 75 W 0.1 mF NC 20 2 CH.1 IN A CH.1 OUT 19 3 CH.2 IN A CH.1 SAG 18 4 CH.3 IN A CH.2 OUT 17 5 CH.1 IN B CH.2 SAG 16 6 CH.2 IN B CH.3 OUT 15 7 CH.3 IN B CH.3 SAG 14 8 I2C-A1 SCL 13 9 I2C-A0 SDA 12 10 GND 470 mF (Note A) + 75 W 75 W 470 mF (Note A) + 75 W S-Video 2 S-Video 1 0.1 mF 0.1 mF 75 W 0.1 mF C' Out 1 Y' Out 1 75 W 75 W C' Out 2 Y' Out 2 75 W 75 W 3.3 V VS + 11 S-Video Y' 75 W 100 mF 0.01 mF 0.1 mF 2 IC Controller S-Video C' 75 W External Input A. Due to the high frequency content of the video signal, it is recommended, but not required, to add a 0.01-F capacitor in parallel with these large capacitors. Figure 53. Typical SDTV CVBS/Y'/C' System Driving 2 AC-Coupled Video Lines Due to the edge rates and frequencies of operation, it is recommended - but not required - to place a 0.1-F to 0.01-F capacitor in parallel with the large 220-F to 1000-F capacitors. These large value capacitors are most commonly aluminum electrolytic. It is known that these capacitors have significantly large equivalent series resistance (ESR), and their impedance at high frequencies is large due to the associated inductances involved with their construction. The small 0.1-F to 0.01-F capacitors help pass these high frequency (>1 MHz) signals with lower impedance than the large capacitors. 25 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) Although it is common to use the same capacitor values for all the video lines, the frequency bandwidth of the chroma signal in a S-Video system are not required to go as low or as high as the frequency of the luma channels. Thus, the capacitor values of the chroma line(s) can be smaller - such as 0.1 F. OUTPUT MODES OF OPERATION - AC COUPLED WITH SAG CORRECTION Other than the line droop issue, ac coupling has another potential issue - size and cost. A 330-F to 1000-F capacitor is large and can be quite costly in a system. Multiply these items by the number of channels, and the size and costs can be significant. But, it is still desirable to use ac coupling to eliminate ground loop issues and insure interoperability among video devices. The SAG nomenclature represents signal amplitude gain correction in this document. SAG correction is a method which is used to ac couple the video signal while using much smaller value capacitors. SAG correction is accomplished by manipulating the feedback network of the output buffer. The THS7313 was designed to take advantage of this compensation scheme while minimizing the number of external components required. Figure 54 shows the basic configuration of the output buffer stage along with the SAG configuration driving a single video line. Internal Circuitry Signal Out 47 mF Video Out 75 W 675 W 33 mF SAG 878 W 1 kW 150 W 75 W Figure 54. THS7313 Output Buffer Using SAG Corrected AC-Coupling SAG compensation can be analyzed by looking at low frequency operation and high frequency operation. At low frequencies, the impedance of the capacitors are high and the corresponding gain of the amplifier is: 1 (675 1k 878) 2.55 VV ( 8.1 dB). (1) But, at high frequencies, the impedance of the capacitors are low and the resulting gain of the amplifier is: 1 (675 150) 878 1k 1 1k 2 VV ( 6.0 dB) 1k (2) which is needed to counter-act the doubly terminated 75- output divider (-6 dB) circuit. Resulting in the video out signal equaling the Input signal amplitude. When the SAG output pin is connected directly to the amplifier output, as found in the dc-coupled and the ac-coupled configurations, the gain is configured properly at 2 V/V (6 dB). The SAG pin is part of the negative feedback network. Thus, the capacitors and traces should be constructed as close as possible to the THS7313 to minimize parasitic issues. Failure to do so may result in ringing of the video signal. If these large capacitors must be placed further than 15 mm away from the THS7313, it is recommended that a 0.01-F capacitor be placed between the output of the channel and the SAG pin. This capacitor should be placed as close as possible to the THS7313 to minimize stray capacitance and inductance issues. Since SAG correction targets the low frequency operation area, there is no drawback of adding this high frequency capacitor to the circuit. 26 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) When SAG correction is used, low frequency gain is higher than the high frequency gain (8.1 dB vs. 6 dB). This gain counter acts the attenuation of the signal due to the increase in the 47-F capacitor impedance. This amplifier gain increase is determined by the 33-F capacitor (and associated internal resistor values) and causes a Q enhancement to occur at low frequencies - typically at about 15-Hz. The ratio of these capacitors determines the frequency and amplitude of this enhancement. The internal resistor values were chosen to optimize the system while using the 47-F and 33-F capacitors and to approximate the performance of a single 330-F capacitor. These capacitors can be a different value if desired, but the characteristics of the system are altered accordingly. For example, if 22-F capacitors is used for both sections, then there are increases in line tilt and field tilt. But, for some systems this may be considered acceptable depending on the application. Using larger values, such as 68 F and 47 F respectively, decreases field time distortion even further approaching performance of a single 470-F capacitor. It is important to note that the dc gain is about 2.55 V/V. Thus, if the input has a dc bias, the output dc bias is 2.55 times the input. For example, this results in an output bias point of 345 mV for the dc + 135 mV shift. Additionally, if the ac bias input mode is selected, the dc operating point is Vs/4 X 2.55, or 2.1 V with 3.3-V supply and 3.2 V with 5-V supply. This additional offset should not hinder the performance of the THS7313 as there is still plenty of voltage headroom between the dc operating point and the rail-to-rail output capability. One possible concern about this configuration is the low frequency gain enhancement may cause saturation of the signal when low power supply voltages - such as 3 V - are used. Thus, the internal resistors were chosen to minimize the low frequency gain such that saturation is minimized. Other SAG correction parts have much higher low frequency gain (10 dB or higher), which when coupled with low power supply voltages, can easily create clipping on the output of the amplifier both dynamically and dc. Other SAG correction parts do not use a resistor in series with the SAG pin. Neglecting this resistor can result in a large Q enhancement causing possible saturation issues. These systems typically require much larger feedback capacitor values to minimize this problem which ultimately minimizes the benefits of SAG correction. Figure 55 shows a SAG corrected configuration for the THS7313. If a s-video chroma channel is being configured, there is no reason for SAG correction as the coupling capacitor is typically small at 0.1 F. Thus, tying the output pin directly to the SAG output pin is recommended along with a 0.1-F capacitor. 3.3 V DAC / Encoder (THS8200) 47 mF + CVBS R SDTV CVBS S-Video Y' S-Video C' 480i 576i G'B'R' R DC + 135 mV 1 NC 2 CH.1 IN A CH.1 OUT 19 3 CH.2 IN A CH. 1 SAG 18 4 CH.3 IN A CH.2 OUT 17 5 CH.1 IN B CH. 2 SAG 16 6 CH.2 IN B CH.3 OUT 15 7 CH.3 IN B CH. 3 SAG 14 8 I 2C-A1 SCL 13 I 2C-A0 SDA 12 NC 20 AC STC R AC STC AC Bias 0.1 mF CVBS 75 W 0.1 mF 9 10 GND 0.01 mF 75 W 0.1 mF 75 W Y' Out 33 mF + S-Video * 0.1 mF + C' Out 75 W 75 W 75 W +Vs VS + 11 S-Video Y' 75 W 47 mF + * DC + 135 mV C' CVBS Out 33 mF + DC + 135 mV Y' 75 W + * (See Note A) 100 mF 2 IC Controller S-Video C' 75 W External Input A. If the SAG correction capacitors are more than 15 mm from the THS7313, add a 0.01F capacitor as shown. Figure 55. Typical SDTV CVBS/Y'/C' System Driving SAG Corrected AC-Coupled Video Lines 27 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) LOW PASS FILTER MODE Each channel of the THS7313 incorporates a 5th-Order Low Pass Filter. These video reconstruction filters minimize DAC images from being passed onto the video receiver. Depending on the receiver design, failure to eliminate these DAC images can cause picture quality problems due to aliasing of the ADC. Another benefit of the filter is to smooth out aberrations in the signal which some DACs can have if their own internal filtering is not good. This helps with picture quality and helps insure the signal meets video bandwidth requirements. Each filter has a Butterworth characteristic associated with it. They have been modified with a slightly lower Q than the traditional Q associated with the Butterworth response. The benefit of the Butterworth response is the frequency response is flat with a relatively steep initial attenuation at the corner frequency. The problem is that the group delay rises near the corner frequency. Group delay is defined as the change in phase (radians/second) divided by a change in frequency. An increase in group delay corresponds to a time domain pulse response that has overshoot and some possible ringing associated with the overshoot. The use of other types of filters such as elliptic or chebyshev is not recommended for video applications due to their large group delay variations near the corner frequency which results in overshoot and ringing. While these elliptic or chebyshev filters may help meet the video standard specifications with respect to amplitude attenuation, their group delay is beyond the standards specifications. Couple this with the fact that video can go from a white pixel to a black pixel over and over again, ringing occurs. Ringing typically causes a display to have ghosting or fuzziness appear on the edges of a sharp transition. However, a Bessel filter has an ideal group delay response, but the rate of attenuation is typically too low for acceptable image rejection. Thus, the Butterworth filter is a respectable compromise for both attenuation and group delay. The THS7313 filter has a slightly lower group delay variation near the corner frequency compared to an ideal Butterworth filter. This results in a time domain pulse response which still has some overshoot, but not as much as a true Butterworth filter. Additionally, the initial rate of attenuation in the frequency response is not as fast as an ideal Butterworth response, but it is an acceptable initial rate of attenuation considering the pulse and group delay characteristic benefits. One concern about an active filter in an integrated circuit is the variation of the filter characteristics when the ambient temperature and the subsequent die temperature changes. To minimize temperature effects, the THS7313 uses thin-film metal resistors and high quality - low temperature coefficient capacitors found in the BiCom-3 process. The filters have been specified by design to account for process variations and temperature variations to maintain proper filter characteristics. This maintains a low channel-to-channel time delay which is required for proper video signal performance. The THS7313 filters have a nominal corner (-3 dB) frequency selectable at 8 MHz. The 8-MHz filter is ideal for standard definition (SD) NTSC, PAL, and SECAM composite video (CVBS) signals. It is also useful for S-Video signals (Y'/C'), 480i / 576i Y'P'BP'R , and Y'U'V' video signals. The -3-dB corner frequency was designed to be 8 MHz to allow a maximally flat video signal while achieving 48-dB of attenuation at 27 MHz - a common frequency between the ADC 2nd and 3rd Nyquist zones found in many video receivers. This is important because any signal appearing around this frequency can appear in the baseband due to aliasing effects of an analog to digital converter found in a receiver. The 8-MHz filter frequency was chosen to account for process variations in the THS7313. To ensure the required video frequencies are the least affected, the filter corner frequency must be high enough to allow for component variations. The other consideration is the attenuation must be large enough to ensure the anti-aliasing / reconstruction filtering meets the system demands. Thus, the selection of the filter frequencies was not chosen arbitrarily. The I2C interface of the THS7313 allows each channel to be configured totally independent of the other channels. One of the benefits is that a multiple output encoder (or DAC) can be routed through one THS7313 with the proper input configuration regardless of the signal. This is useful for a portable system or in a low cost system where only one set (or 2 sets in parallel) is desired on the output of the system. An update of the I2C commands changes the THS7313 channels. An example is shown in Figure 56 where the input MUX allows for one set of component video signals to be put into the THS7313, and then through an I2C update, a CVBS/S-Video set of signals is sent through the THS7313 with the proper input mode. 28 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) 3.3 V Y' R DC + 135 mV 1 NC P' B R 75 W NC 20 2 CH.1 IN A CH.1 OUT 19 3 CH.2 IN A CH.1 SAG 18 4 CH.3 IN A CH.2 OUT 17 DC + 135 mV P'R DC + 135 mV R DC + 135 mV S-Video Y' DC + 135 mV R S-Video C' 5 CH.1 IN B CH.2 SAG 16 6 CH.2 IN B CH.3 OUT 15 7 CH.3 IN B CH.3 SAG 14 8 I2C-A1 SCL 13 9 I2C-A0 SDA 12 10 GND 330 mF (See Note A) Video Out 2 75 W Video Out 3 330 mF (See Note A) 75 W + 75 W +Vs + 0.01 mF 75 W + VS + 11 R 100 mF 2 CVBS R A. 75 W + DC + 135 mV DAC / Encoder Video Out 1 330 mF (See Note A) IC Controller Due to the high frequency content of the video signal, it is recommended, but not required, to add a 0.01-F capacitor in parallel with these large capacitors. Figure 56. Typical SDTV and 480i/576i Encoder DAC Driving a Single THS7313 Although the circuit of Figure 56 conserves space and cost, the re-use of the output connections may not be the best solution. For a complete 6-channel system, it is better to use the THS7313 and the THS7303 (see SLOS479) together as shown in Figure 57. The THS7303 is targeted for HDTV signals, and has a 9-MHz, 16-MHz, 35-MHz, and a 190-MHz bypass mode amplifier targeting the faster HDTV signals and the high end computer R'G'B' signals. As the I2C section discusses, it is easy to have both parts in one system as the I2C address of each part can be one of 4 discrete addresses by the logic appearing on the I2C-A1 and I2C-A0 lines. 29 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) 470 mF (See Note A) + DC + 135 mV R (130 W) THS7303 1 NC R (130 W) DC + 135 mV DAC / Encoder CH.1 OUT 19 3 CH.2 IN A CH.1 SAG 18 4 CH.3 IN A CH.2 OUT 17 5 CH.1 IN B CH.2 SAG 16 6 CH.2 IN B CH.3 OUT 15 7 CH.3 IN B CH.3 SAG 14 AC Bias AC Bias 0.1 mF Y' 75 W 8 I2C-A1 SCL 13 9 I2C-A0 SDA 12 10 GND 1 mF P'B 470 mF (See Note A) 75 W + 470 mF (See Note A) + P'R Out 75 W 75 W 75 W 3.3 V VS + 11 + P'B 0.01 mF 75 W 1 mF P'R 75 W P'B Out AC STC R (130 W) Y' Y' Out NC 20 2 CH.1 IN A DC + 135 mV 3.3 V 75 W 100 mF 2 IC Controller 2 I C Address = 0101100 P'R 75 W CVBS External Input (See Note A) THS7313 1 NC R (130 W) S-Video C' CVBS Out 470 mF DC + 135 mV R (130 W) S-Video Y' DC + 135 mV + 75 W NC 20 2 CH.1 IN A CH.1 OUT 19 3 CH.2 IN A CH. 1 SAG 18 4 CH.3 IN A CH.2 OUT 17 5 CH.1 IN B CH. 2 SAG 16 6 CH.2 IN B CH.3 OUT 15 7 CH.3 IN B CH. 3 SAG 14 470 mF (See Note A) AC STC AC Bias +VS CVBS 75 W 8 I2C-A1 SCL 13 9 I2C-A0 SDA 12 10 GND 0.1 mF 0.1 mF C' Out 75 W 75 W 75 W 3.3 V VS+ 11 S-Video Y' Y' Out S-Video AC STC 0.1 mF 75 W + DC + 135 mV R (130 W) 75 W + 0.1 mF 75 W 2 0.1 mF I C Address = 0101110 100 mF 2 IC Controller S-Video C' 75 W External Input A. Due to the high frequency content of the video signal, it is recommended, but not required, to add a 0.01-F capacitor in parallel with these large capacitors. Figure 57. Typical 6-Channel HDTV and SDTV Encoder Interfacing to a THS7303 and a THS7313 30 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) 2 I C INTERFACE NOTES The I2C interface is used to access the internal registers of the THS7313. I2C is a two-wire serial interface developed by Philips Semiconductor (see the I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The THS7313 works as a slave and supports the standard mode transfer (100 kbps) and fast mode transfer (400 kbps) as defined in the I2C-Bus specification. The THS7313 has been tested to be fully functional but not ensured with the high-speed mode (3.4 Mbps). The basic I2C start and stop access cycles are shown in Figure 58. The basic access cycle consists of the following: * A start condition * A slave address cycle * Any number of data cycles * A stop condition SDA SCL S P Start Condition Stop Condition Figure 58. I2C Start and Stop Conditions GENERAL I2C PROTOCOL * * * * The master initiates data transfer by generating a start condition. The start condition exist when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 58. All I2C-compatible devices should recognize a start condition. The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 59). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 60) by pulling the SDA line low during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a communication link with a slave has been established. The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So, an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary (See Figure 61). To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 58). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. 31 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 59. I2C Bit Transfer Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 8 2 9 S Clock Pulse for Acknowledgement Start Condition Figure 60. I2C Acknowledge 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA Stop MSB Acknowledge Slave Address Acknowledge Data 2 Figure 61. I C Address and Data Cycles During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting device after the last byte is transferred. An example of a write cycle can be found in Figure 62 and Figure 63. Note that the THS7313 does not allow multiple write transfers to occur. See example section - Writing to the THS7313 for more information. During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its address. Following this initial acknowledge by the slave, the master device becomes a receiver and 32 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 64 and Figure 65. Note that the THS7313 does not allow multiple read transfers to occur. See example section - Reading from the THS7313 for more information. From Receiver S Slave Address W A DATA A DATA A = No Acknowledge (SDA High) A = Acknowledge S = Start Condition P = Stop Condition W = Write R = Read P A From Transmitter Figure 62. I2C Write Cycle Acknowledge (Receiver) Acknowledge (From Receiver) Start Condition A6 A5 A1 A0 R/W ACK D7 D6 D0 D1 ACK Acknowledge (Transmitter) D6 D7 D1 D0 ACK SDA 2 First Data Byte I C Device Address and Read/Write Bit Other Data Bytes Stop Condition Last Data Byte Figure 63. Multiple Byte Write Transfer S Slave Address R A DATA A DATA A A = No Acknowledge (SDA High) A = Acknowledge S = Start Condition P = Stop Condition W = Write R = Read P Transmitter Receiver Figure 64. I2C Read Cycle Start Condition SDA Acknowledge (From Receiver) A6 A0 R/W ACK I 2 C Device Address and Read/Write Bit D7 Acknowledge (From Transmitter) D0 First Data Byte ACK Not Acknowledge (Transmitter) D7 Other Data Bytes D6 D1 D0 Last Data Byte ACK Stop Condition Figure 65. Multiple Byte Read Transfer 33 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 APPLICATION INFORMATION (continued) Slave Address Both the SDA and the SCL must be connected to a positive supply voltage via a pullup resistor. These resistors should comply with the I2C specification that ranges from 2 k to 19 k. When the bus is free, both lines are high. The address byte is the first byte received following the START condition from the master device. The first 5 Bits (MSBs) of the address are factory preset to 01011. The next two bits of the THS7313 address are controlled by the Logic levels appearing on the I2C-A1 and I2C-A0 pins. The I2C-A1 and I2C-A0 address inputs can be connected to VS+ for Logic 1, GND for Logic 0, or it can be actively driven by TTL/CMOS logic levels. The device address is set by the state of these pins and is not latched. Thus, a dynamic address control system can be used to incorporate several devices on the same system. Up to four THS7313 devices can be connected to the same I2C-Bus without requiring additional glue logic. Table 1 lists the possible addresses for the THS7313 Table 1. THS7313 Slave Addresses SELECTABLE WITH ADDRESS PINS FIXED ADDRESS READ/WRITE BIT Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 (A1) Bit 1 (A0) Bit 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1 0 0 1 0 1 1 1 1 1 Channel Selection Register Description (Subaddress) The THS7313 operates using only a single byte transfer protocol similar to Figure 62 and Figure 64. The internal subaddress registers and the functionality of each are found in Table 2. When writing to the device, it is required to send one byte of data to the corresponding internal subaddress. If control of all three channels is desired, then the master has to cycle through all the subaddresses (channels) one at a time, see the example section -Writing to the THS7313 for the proper procedure of writing to the THS7313. During a read cycle, the THS7313 sends the data in its selected subaddress (or channel) in a single transfer to the master device requesting the information. See the example section -Reading from the THS7313 for the proper procedure on reading from the THS7313. On power up, the THS7313 registers are in a random state from part-to-part. It remains in this random state until a valid write sequence is made to the THS7313. A total of 9 bytes of data completely configures all channels of the THS7313. As such, configuring the THS7313 should be done on power-up of the system. Note that one such random state (acknowledge state) can be engaged. To circumvent this state, have one SCL cycle run, and the acknowledge state disengages. Table 2. THS7313 Channel Selection Register Bit Assignments 34 REGISTER NAME BIT ADDRESS (b7b6b5....b0) Channel 1 0000 0001 Channel 2 0000 0010 Channel 3 0000 0011 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 Channel Register Bit Descriptions Each bit of the sub-address (channel selection) control register as described above allows the user to individually control the functionality of the THS7313. The benefit of this process allows the user to control the functionality of each channel independent of the other channels. The bit description is decoded in Table 3. Table 3. THS7313 Channel Register Bit Decoder Table BIT FUNCTION BIT VALUE(S) RESULT (MSB) 7, 6 STC Low Pass Filter Selection 00 500-kHz Filter - Useful for poor video sync signals 01 2.5-MHz Filter - Useful for reasonable sync signals 10 5-MHz Filter - Useful for good sync signals 11 5-MHz Filter - Useful for good sync signals 5 Input MUX Selection 0 Input A Select 1 Input B Select 4,3 Reserved XX 2, 1, 0 (LSB) Input Bias Mode Selection and Disable Control 000 Disable Channel - Conserves Power 001 Channel On - Mute Function - No Output 010 Channel On - DC Bias Select 011 Channel On - DC Bias + 135 mV Offset Select 100 Channel On - AC Bias Select 101 Channel On - Sync Tip Clamp with Low Bias 110 Channel On - Sync Tip Clamp with Mid Bias 111 Channel On - Sync Tip Clamp with High Bias Do Not Care Bits 7 (MSB) and 6 - Controls the AC-Sync Tip Clamp Low Pass Filter function. If AC-STC mode is not used, this function is ignored. Bit 5 - Controls the input MUX of the THS7313. Bits 4 and 3 - Reserved for future functionality. The values of these bits do not affect the THS7313. Bits 2, 1, and 0 (LSB) - Selects the input biasing of the THS7313 and the power-savings function. When Sync-Tip Clamp is selected, the DC input sink bias current is also selectable. EXAMPLE - WRITING TO THE THS7313 The proper way to write to the THS7313 is illustrated as follows: An I2C master initiates a write operation to the THS7313 by generating a start condition (S) followed by the THS7313 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the THS7313, the master presents the subaddress (channel) it wants to write consisting of one byte of data, MSB first. The THS7313 acknowledges the byte after completion of the transfer. Finally the master presents the data it wants to write to the register (channel) and the THS7313 acknowledges the byte. The I2C master then terminates the write operation by generating a stop condition (P). Note that the THS7313 does not support multi-byte transfers. To write to all three channels - or registers - this procedure must be repeated for each register one series at a time (i.e., repeat steps 1 through 8 for each channel). Step 1 0 I2C Start (Master) S Step 2 7 6 5 4 3 2 1 0 I2C 0 1 0 1 1 X X 0 General Address (Master) Where each X Logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND. Step 3 9 I2C Acknowledge (Slave) A 35 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 Step 4 7 6 5 4 3 2 1 0 I2C 0 0 0 0 0 0 Addr Addr Write Channel Address (Master) Where Addr is determined by the values shown in Table 2. Step 5 9 I2C Acknowledge (Slave) A Step 6 I2C Write Data (Master) 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Where Data is determined by the values shown in Table 3. Step 7 9 I2C Acknowledge (Slave) A Step 8 0 I2C Stop (Master) P For Step 6, an example of the proper bit control for selecting Input B of the MUX, a SDTV Y' channel signal with the lowest line tilt ans a known good STC is 1111 0101. EXAMPLE - READING FROM THE THS7313 The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the THS7313 by generating a start condition (S) followed by the THS7313 I2C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the THS7313, the master presents the sub-address (channel) of the register it wants to read. After the cycle is acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P). The second phase is the data phase. In this phase, an I2C master initiates a read operation to the THS7313 by generating a start condition followed by the THS7313 I2C address (as shown below for a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the THS7313, the I2C master receives one byte of data from the THS7313. After the data byte has been transferred from the THS7313 to the master, the master generates a not acknowledge followed by a stop. Similar to the Write function, to read all channels Steps 1 through 11 must be repeated for each and every channel desired. THS7313 Read Phase 1: Step 1 0 I2C S Start (Master) Step 2 7 6 5 4 3 2 1 0 I2C General Address (Master) 0 1 0 1 1 X X 0 Where each X Logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND. Step 3 9 I2C Acknowledge (Slave) A Step 4 7 6 5 4 3 2 1 0 I2C Read Channel Address (Master) 0 0 0 0 0 0 Addr Addr Where Addr is determined by the values shown in Table 2. Step 5 9 I2C A Acknowledge (Slave) Step 6 0 I2C P 36 Start (Master) THS7313 www.ti.com SLOS483 - NOVEMBER 2005 THS7313 Read Phase 2: Step 7 0 I2C S Start (Master) Step 8 7 6 5 4 3 2 1 0 I2C General Address (Master) 0 1 0 1 1 X X 1 Where each X Logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND. Step 9 9 I2C Acknowledge (Slave) A Step 10 I2C Read Data (Slave) 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Where Data is determined by the Logic values contained in the Channel Register. Step 11 9 I2C A Not-Acknowledge (Master) Step 12 0 I2C P Stop (Master) 37 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 Evaluation Module An evaluation module (EVM) is available for the TPS7313. Because the THS7313 is controlled by the I2C lines, additional control is required--rather than simple switches. To ease control, an USB-to-I2C interface was designed onto the EVM. A computer running either Windows 2000 or XP is then connected to the EVM through the USB cable. A computer program interface allows graphical control of the THS7313 that allows both read and write functions to be performed. The EVM comes with a CD-ROM loaded with all the required software to install the command software on to the computer. To program the THS7313, the user selects the channel, the filter, and the mode of operation, and selects the Execute button. The Req Done light on the computer screen is lit to confirm that the command was executed by the THS7313. The same procedure is done for each and every channel. To read the THS7313 registers, change the switch to Read, select the channel, and then select the Execute button. The resulting register content appears in hexadecimal code. Note that the USB-to-I2C interface circuitry must be powered by a 3.3-V supply only. Additionally, the I2C circuitry section must be powered on either at the same time as the THS7313 or before power is applied to the THS7313. This is due to the reading of the EEPROM, the TAS1020 device must complete to program its core. The yellow LED in the I2C section is lit if the TAS1020 was programmed properly. If this LED is not lit, then cyclng the power should be done to reset the USB-to-I2C TAS1020 chip. Table 4 is a bill of materials, the board layout is found in Figure 66 through Figure 69. Table 4. Bill Of Materials DESCRIPTION SMD SIZE REFERENCE DESIGNATOR PCB QUANTITY MANUFACTURER'S PART NUMBER (1) DISTRIBUTER'S PART NUMBER 1 BEAD, FERRITE, 2.5A, 80 OHM 0805 FB1, FB2, FB3 2 CAP, 22uF, TAN, 6.3V, 10%, LO ESR 3 (TDK) MPZ2012S331A (DIGI-KEY) 445-1569-1-ND C30 1 (AVX) TPSA226K006R0900 A (DIGI-KEY) 478-1754-1-ND 3 CAP, 100uF, TAN, 10V, 10%, LO ESR C C5 1 (AVX) TPSC107K010R0100 (DIGI-KEY) 478-1765-1-ND 4 OPEN 0805 C2, C3, C8, C11, C12, C14, C17, C21, C23 9 5 CAP, 33pF, CERAMIC, 50V, NPO 0805 C31, C32 2 (AVX) 08055A330JAT2A (DIGI-KEY) 478-1310-1-ND 6 CAP, 47pF, CERAMIC, 50V, NPO 0805 C27, C29 2 (AVX) 08055A470JAT2A (DIGI-KEY) 478-1312-1-ND 7 CAP, 100pF, CERAMIC, 50V, NPO 0805 C34 1 (AVX) 08055A101JAT2A (DIGI-KEY) 478-1316-1-ND 8 CAP, 1000pF, CERAMIC, 100V, NPO 0805 C33 1 (AVX) 08051A102JAT2A (DIGI-KEY) 478-1290-1-ND 9 CAP, 0.01uF, CERAMIC, 100V, X7R 0805 C19, C28 2 (AVX) 08051C103KAT2A (DIGI-KEY) 478-1358-1-ND 10 CAP, 0.1uF, CERAMIC, 50V, X7R 0805 C4, C6, C9, C13, C16, C22, C25, C26, C43, C44, Z4 11 (AVX) 08055C104KAT2A (DIGI-KEY) 478-1395-1-ND 11 CAP, 1uF, CERAMIC, 16V, X7R 0805 C18, C35, C36, C37, C38, C39, C40, C41, C42, Z5, Z6 11 (TDK) C2012X7R1C105K (DIGI-KEY) 445-1358-1-ND 12 CAP, ALUM, 470uF, 10V, 20% F C1, C10, C20 3 (CORNELL) AFK477M10F24B (NEWARK) 97C7597 13 CAP, ALUM, 33uF, 25V, 20% C C7, C15, C24 3 (CORNELL) AFK336M25C12B (NEWARK) 97C7564 14 OPEN 0603 R47, R48, R49, R51 4 9 (ROHM) MCR03EZPJ000 (DIGI-KEY) RHM0.0GCT-ND (ROHM) MCR03EZPFX2741 (DIGI-KEY) RHM2.7KHCT-ND (ROHM) MCR10EZHJ000 (DIGI-KEY) RHM0.0ACT-ND ITEM 15 RESISTOR, 0 OHM 0603 R1, R2, R3, R4, R6, R7, R19, R20, R23 16 RESISTOR, 2.74K OHM, 1/8W, 1% 0603 R41, R61 2 17 OPEN 0805 R15, R16, R28 3 0805 R9, R13, R21, Z1, Z2, Z3 6 18 (1) 38 RESISTOR, 0 OHM Manufacturer's part numbers are used for test purposes only. THS7313 www.ti.com SLOS483 - NOVEMBER 2005 Table 4. Bill Of Materials (continued) DESCRIPTION SMD SIZE REFERENCE DESIGNATOR MANUFACTURER'S PART NUMBER (1) DISTRIBUTER'S PART NUMBER 19 RESISTOR, 10 OHM, 1/8W, 1% 0805 R39, R44, R45, R52 4 (ROHM) MCR10EZHF10R0 (DIGI-KEY) RHM10.0CCT-ND 20 RESISTOR, 27.4 OHM, 1/8W, 1% 0805 R30, R31 2 (ROHM) MCR10EZHF27.4 (DIGI-KEY) RHM27.4CCT-ND 21 RESISTOR, 75 OHM, 1/8W, 1% 0805 R5, R8, R10, R11, R12, R14, R17, R18, R22 9 (ROHM) MCR10EZHF75.0 (DIGI-KEY) RHM75.0CCT-ND 22 RESISTOR, 100 OHM, 1/8W, 1% 0805 R50 1 (ROHM) MCR10EZHF1000 (DIGI-KEY) RHM100CCT-ND 23 RESISTOR, 200 OHM, 1/8W, 1% 0805 R26, R27 2 (ROHM) MCR10EZHF2000 (DIGI-KEY) RHM200CCT-ND 24 RESISTOR, 649 OHM, 1/8W, 1% 0805 R33, R60 2 (ROHM) MCR10EZHF0649 (DIGI-KEY) RHM649CCT-ND 25 RESISTOR, 1.0K OHM, 1/8W, 1% 0805 R29 1 (ROHM) MCR10EZHF1001 (DIGI-KEY) RHM1.00KCCT-ND 26 RESISTOR, 1.5K OHM, 1/8W, 1% 0805 R32 1 (ROHM) MCR10EZHF1501 (DIGI-KEY) RHM1.50KCCT-ND 27 RESISTOR, 2.21K OHM, 1/8W, 1% 0805 R34, R35 2 (ROHM) MCR10EZHF2211 (DIGI-KEY) RHM2.21KCCT-ND 28 RESISTOR, 3.09K OHM, 1/8W, 1% 0805 R43 1 (ROHM) MCR10EZHF3091 (DIGI-KEY) RHM3.09KCCT-ND 29 RESISTOR, 10K OHM, 1/8W, 1% 0805 R24, R25, R40, R42 4 (ROHM) MCR10EZHF1002 (DIGI-KEY) RHM10.0KCCT-ND 30 RESISTOR, 20K OHM, 1/8W, 1% 0805 R46 1 (ROHM) MCR10EZHF2002 (DIGI-KEY) RHM20.0KCCT-ND 31 LED, GREEN 0805 D1 1 (LITE-ON) LTST-C171GKT (DIGI-KEY) 160-1423-1-ND 32 LED, YELLOW 0805 D2 1 (LITE-ON) LTST-C171YKT (DIGI-KEY) 160-1431-1-ND 33 IC, CONV, SERIAL TO USB U3 1 (TI) TAS1020BPFB (DIGI-KEY) TAS1020BPFB (DIGI-KEY) 24LC64-I/SN-ND ITEM PCB QUANTITY 34 IC, SERIAL, EEPROM, 64K 8-SOIC U2 1 (MICROCHIP) 24LC64-I/SN 35 CRYSTAL, 6.00MHz., SMT HCM49 X1 1 (CITIZEN) HCM49-6.000MABJT (DIGI-KEY) 300-6112-1-ND 36 OPEN SOT-23 U4, U5 2 37 JACK, BANANA RECEPTANCE, 0.25" DIA. HOLE J4, J5, J16, J17 4 (SPC) 813 (NEWARK) 39N867 38 SWITCH, SMD GULL WING S1 1 (BOURNS) 7914G-1-000E (DIGI-KEY) 7914G-000ETR-ND 39 CONNECTOR, RCA, JACK, R/A J1, J2, J12 3 (CUI) RCJ-32265 (DIGI-KEY) CP-1446-ND 40 CONNECTOR, USB, RTANG, FEMALE J15 1 (ASSMANN) AU-Y1007 (DIGI-KEY) AE1085-ND 41 CONNECTOR, BNC, JACK, 75 OHM J3, J6, J7, J8, J9, J10, J11, J13, J14 9 (AMPHENOL) 31-5329-72RFX (NEWARK) 93F7554 42 HEADER, 0.1" CTRS, 0.025" SQ. PINS JP1, JP2, JP3 3 (SULLINS) PZC36SAAN (DIGI-KEY) S1011-36-ND 43 SHUNTS JP1, JP2, JP3 3 (SULLINS) SSC02SYAN (DIGI-KEY) S9002-ND 44 TEST POINT, RED TP1, TP2, TP5, TP6, TP7 5 (KEYSTONE) 5000 (DIGI-KEY) 5000K-ND 45 TEST POINT, BLACK TP3, TP4 2 (KEYSTONE) 5001 (DIGI-KEY) 5001K-ND 46 IC, THS7313 U1 1 (TI) THS7313PW 47 STANDOFF, 4-40 HEX, 0.625" LENGTH 4 (KEYSTONE) 1808 (NEWARK) 89F1934 48 SCREW, PHILLIPS, 4-40, .250" 4 (BF) PMS 440 0031 PH (DIGI-KEY) H343-ND 49 BOARD, PRINTED CIRCUIT 1 EDGE # 6469006 REV.B 4MM B 2 POS. 39 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 EVM Board Layers Figure 66. Top Layer - Signal Layer 40 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 Figure 67. Layer Two - Ground Layer 41 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 Figure 68. Layer Three - Power and Ground Layer 42 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 Figure 69. Bottom Layer - Signal Layer 43 THS7313 www.ti.com SLOS483 - NOVEMBER 2005 Table 5. EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage and the output voltage ranges as specified in the table below. Input Range, VS 2.7 V to 5 V Input Range, VI 0 V to 3 V NOT TO EXCEED VS+ or VS- Output Range, VO 0 V to 5 V NOT TO EXCEED VS+ or VS- Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 100C. The EVM is designed to operate properly with certain components above 100C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2005, Texas Instruments Incorporated 44 + + + + + + + D G D G S S + PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device THS7313PWR Package Package Pins Type Drawing TSSOP PW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS7313PWR TSSOP PW 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2012, Texas Instruments Incorporated