NCP1612BDR2G - ON SEMICONDUCTOR - Datasheet.Directory

January, 2018 − Rev. 11 1Publication Order Number:

NCP1612/D

NCP1612A, NCP1612B,

NCP1612A1, NCP1612A2,

NCP1612A3, NCP1612B2

Enhanced, High‐Efficiency

Power Factor Controller

The NCP1612 is designed to drive PFC boost stages based on an

innovative Current Controlled Frequency Fold-back (CCFF) method.

In this mode, the circuit classically operates in Critical conduction

Mode (CrM) when the inductor current exceeds a programmable

value. When the current is below this preset level, the NCP1612

linearly decays the frequency down to about 20 kHz when the current

is null. CCFF maximizes the ef ficiency at both nominal and light load.

In particular, the stand-by losses are reduced to a minimum.

Like in FCCrM controllers, an internal circuitry allows near-unity

power factor even when the switching frequency is reduced. Housed in

a SO−10 package, the circuit also incorporates the features necessary

for robust and compact PFC stages, with few external components.

General Features

•Near-unity Power Factor

•Critical Conduction Mode (CrM)

•Current Controlled Frequency Fold-back (CCFF): Low Frequency

Operation is Forced at Low Current Levels

•On-time Modulation to Maintain a Proper Current Shaping in CCFF

Mode

•Skip Mode Near the Line Zero Crossing

•Fast Line/Load Transient Compensation

(Dynamic Response Enhancer)

•Valley Turn On

•High Drive Capability: −500 mA/+800 mA

•VCC Range: from 9.5 V to 35 V

•Low Start-up Consumption

•Six Versions: NCP1612A, B, A1, A2, A3 and B2 (see Table 1)

•Line Range Detection

•pfcOK Signal

•This is a Pb-Free Device

Safety Features

•Separate Pin for Fast Over-voltage Protection (FOVP)

for Redundancy

•Soft Over-voltage Protection

•Brown-out Detection

•Soft-start for Smooth Start-up Operation

(A, A1, A2 and A3 Versions)

•Over Current Limitation

•Disable Protection if the Feedback is Not Connected

•Thermal Shutdown

•Latched Off Capability

•Low Duty-cycle Operation if the Bypass Diode is

shorted

•Open Ground Pin Fault Monitoring

•Saturated Inductor Protection

•Detailed Safety Testing Analysis

(Refer to Application Note AND9079/D)

Typical Applications

•PC Power Supplies

•All Off Line Appliances Requiring Power Factor

Correction

SOIC−10

CASE 751BQ

PIN CONNECTIONS

MARKING DIAGRAM

(Top View)

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1612x = Specific Device Code

x = A, A1, A2, A3, B or B2

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb-Free Package

See detailed ordering and shipping information on page 30 o

this data sheet.

ORDERING INFORMATION

1612x

ALYW

pfcOK

VCC

DRV

GND

FOVP 1

CS/ZCD

Vcontrol

Vsense

Feedback

FFcontrol

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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Figure 1. Typical Application Schematic

Table 1. FIVE NCP1612 VERSIONS

Part Number Typical UVLO

Hysteresis

Condition for

BUV Tripping

(typical threshold)

Maximum

Dead-time

(typical value)

Condition for

Latching-off

(typical threshold) UVP2 if

VFOVP<VUVP2

Dynamic Re-

sponse

Enhancer (DRE)

NCP1612A 1.5 V VFOVP < 76%.VREF 48.5 msVpfcOK > 7.5 V YES Disabled until

pfcOK turns high

NCP1612A1 1.5 V VFOVP < 40%.VREF 48.5 msVpfcOK > 7.5 V YES Disabled until

pfcOK turns high

NCP1612A2 1.5 V VFB < 76%.VREF 48.5 msVFOVP > 107%.VREF NO Disabled until

pfcOK turns high

NCP1612A3 1.5 V VFOVP < 40%.VREF 41.5 msVpfcOK > 7.5 V YES Disabled until

pfcOK turns high

NCP1612B 8.0 V VFOVP < 76%.VREF 48.5 msVpfcOK > 7.5 V YES Enabled as soon

as the circuit

turns on to

speed-up the

startup phase

NCP1612B2* 8.0 V VFB < 76%.VREF 48.5 msVFOVP > 107%.VREF NO Enabled as soon

as the circuit

turns on to

speed-up the

startup phase

*Please contact local sales representative for availability

Recommended Applications:

•The NCP1612B and NCP1612B2 large UVLO hysteresis (6 V minimum) avoids the need for large VCC capacitors and

help shorten the start-up time without the need for too dissipative start-up elements in self-powered PFC applications

(where high-impedance start-up resistors are generally implemented to pre-charge the VCC capacitor).

•The A, A1, A2 and A3 versions are preferred in applications where the circuit is fed by an external power source (from

an auxiliary power supply or from a downstream converter). Its maximum start-up level (11.25 V) is set low enough so

that the circuit can be powered from a 12-V voltage rail.

•A2 and B2 versions are to be preferred when a signal other than a portion of the output voltage is applied to the FOVP

pin (e.g., a voltage representative of the output voltage provided by an auxiliary winding) and/or if the pfcOK pin

voltage must be able to rise up to the VCC level without latching the part. Note that with the A2 and B2 versions, the

fast OVP protection latches-off the circuit when triggered.

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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Table 2. MAXIMUM RATINGS (Note 1)

Symbol Pin Rating Value Unit

VCC 9Power Supply Input −0.3, +35 V

FOVP 1 FOVP Pin −0.3, +10 V

Feedback 2 Feedback Pin −0.3, +10 V

VCONTROL 3 VCONTROL Pin (Note 2) −0.3, VCONTROLMAX V

Vsense 4 Vsense Pin (Note 3) −0.3, +10 V

FFcontrol 5 FFcontrol Pin −0.3, +10 V

CS/ZCD 6 Input Voltage (Note 4)

Current Injected to Pin 4 (Note 5) −0.3, +35

+5 V

DRV 8 Driver Voltage (Note 2)

Driver Current −0.3, VDRV

−500, +800 V

pfcOK 10 pfcOK Pin −0.3, VCC V

RqJA

Power Dissipation and Thermal Characteristics

Maximum Power Dissipation @ TA = 70°C

Thermal Resistance Junction-to-Air 550

145 mW

°C/W

TJOperating Junction Temperature Range −40 to +125 °C

TJmax Maximum Junction Temperature 150 °C

TSmax Storage Temperature Range −65 to 150 °C

TLmax Lead Temperature (Soldering, 10s) 300 °C

MSL Moisture Sensitivity Level 1 −

ESD Capability, Human Body Model (Note 6) > 2000 V

ESD Capability, Machine Model (Note 6) > 200 V

ESD Capability, Charged Device Model (Note 6) 1000 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.

2. “VCONTROLMAX” is the pin3 clamp voltage and “VDRV” is the DR V clamp voltage (VDRVhigh). If VCC is below VDRVhigh, “VDRV” is VCC.

3. Recommended maximum Vsense voltage for optimal operation is 4.5 V.

4. The recommended maximum voltage not to exceed remains −0.3 V but Figure 2 short negative spike on the CS/ZCD pin is typically

acceptable. However, it implies the full characterization of the circuit embedding the NCP1612, including at maximum temperature

conditions, during which no erratic operation is observed. If otherwise noted, we recommend to clamp the negative voltage on the CS/ZCD

pin to avoid carrier injection within the die.

5. Maximum CS/ZCD current that can be injected into pin6 (see Figure 3).

6. This device(s) contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC Standard JESD22−A114E

Machine Model Method 200 V per JEDEC Standard JESD22−A115−A

Charged Device Model Method 1000 V per JEDEC Standard JESD22−C101E

Figure 2.

0 V

−0.3 V

−1.0 V

250 ns

VCS/ZCD (t)

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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Figure 3.

VCC

GND

CS/ZCD

NCP1612

ESD Diode

CS/ZCD

Circuitry

7.4 V

R1 Ipin6

Maintain Ipin6

below 5 mA

2 kW

Table 3. TYPICAL ELECTRICAL CHARACTERISTICS

(Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified)

Symbol Rating Min Typ Max Unit

START-UP AND SUPPLY CIRCUIT

VCC(on) Start-up Threshold, VCC increasing:

A, A1, A2 and A3 versions

B and B2 versions 9.75

15.80 10.50

17.00 11.25

18.20

VCC(off) Minimum Operating Voltage, VCC falling 8.5 9.0 9.5 V

VCC(HYST) Hysteresis (VCC(on) − VCC(off))

A, A1, A2 and A3 versions

B and B2 versions 0.75

6.00 1.50

8.00 −

−

VCC(reset) VCC level below which the circuit resets 2.5 4.0 6.0 V

ICC(start) Start-up Current, VCC = 9.4 V − 20 50 mA

ICC(op)1 Operating Consumption, no switching (VSENSE pin being grounded) − 0.5 1.0 mA

ICC(op)2 Operating Consumption, 50 kHz switching, no load on DRV pin − 2.0 3.0 mA

CURRENT CONTROLLED FREQUENCY FOLD-BACK

TDT1 Dead-time, VFFcontrol = 2.60 V (Note 7) − − 0 ms

TDT2 Dead-time, VFFcontrol = 1.75 V 14 18 22 ms

TDT3 Dead-time, VFFcontrol = 1.00 V 32 38 44 ms

TDT4 Dead-time, VFFcontrol = VSKIP_L + 30 mV (NCP1612A3 Only) @ 25°C

Over the Temperature Range 34.0

32.0 41.5

41.5 45.0

47.0 ms

IDT1 FFcontrol Pin current, Vsense = 1.4 V and Vcontrol maximum 180 200 220 mA

IDT2 FFcontrol Pin current, Vsense = 2.8 V and Vcontrol maximum 110 135 160 mA

VSKIP−H FFcontrol pin Skip Level, VFFcontrol rising All Versions Except NCP1612A3

NCP1612A3 −

−0.75

1.00 0.85

1.05 V

VSKIP−L FFcontrol pin Skip Level, VFFcontrol falling All Versions Except NCP1612A3

NCP1612A3 0.55

0.85 0.65

0.90 −

−V

HSKIP−L FFcontrol pin Skip Hysteresis 50 − − mV

GATE DRIVE (Note 8)

TROutput voltage rise-time @ CL = 1 nF, 10−90% of output signal − 30 − ns

TFOutput voltage fall-time @ CL = 1 nF, 10−90% of output signal − 20 − ns

ROH Source resistance − 10 − W

ROL Sink resistance − 7.0 − W

ISOURCE Peak source current, VDRV = 0 V (guaranteed by design) − 500 − mA

ISINK Peak sink current, VDRV = 12 V (guaranteed by design) − 800 − mA

VDRVlow DRV pin level at VCC close to VCC(off) with a 10 kW resistor to GND 8.0 − − V

VDRVhigh DRV pin level at VCC = 35 V (RL = 33 kW, CL = 220 pF) 10 12 14 V

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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Table 3. TYPICAL ELECTRICAL CHARACTERISTICS (continued)

(Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified)

Symbol UnitMaxTypMinRating

REGULATION BLOCK

VREF Feedback Voltage Reference:

@ 25°C

Over the temperature range 2.44

2.42 2.50

2.50 2.54

2.54

IEA Error Amplifier Current Capability −±20 − mA

GEA Error Amplifier Gain 110 220 290 mS

VCONTROL

−VCONTROLMAX

−VCONTROLMIN

VCONTROL Pin Voltage:

− @ VFB = 2 V

− @ VFB = 3 V −

−4.5

0.5 −

−

VOUTL/VREF Ratio (VOUT Low Detect Threshold/VREF) (guaranteed by design) 95.0 95.5 96.0 %

HOUTL/VREF Ratio (VOUT Low Detect Hysteresis/VREF) (guaranteed by design) − − 0.5 %

IBOOST VCONTROL Pin Source Current when (VOUT Low Detect) is activated 180 220 250 mA

CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS

VCS(th) Current Sense Voltage Reference 450 500 550 mV

TLEB,OCP Over-current Protection Leading Edge Blanking Time (guaranteed by design) 100 200 350 ns

TLEB,OVS “OverStress” Leading Edge Blanking Time (guaranteed by design) 50 100 170 ns

TOCP Over-current Protection Delay from VCS/ZCD > VCS(th) to DRV low

(dVCS/ZCD / dt = 10 V/ms) − 40 200 ns

VZCD(th)H Zero Current Detection, VCS/ZCD rising 675 750 825 mV

VZCD(th)L Zero Current Detection, VCS/ZCD falling 200 250 300 mV

VZCD(hyst) Hysteresis of the Zero Current Detection Comparator 375 500 − mV

RZCD/CS VZCD(th)H over VCS(th) Ratio 1.4 1.5 1.6 −

VCL(pos) CS/ZCD Positive Clamp @ ICS/ZCD = 5 mA − 15.6 − V

IZCD(bias) Current Sourced by the CS/ZCD Pin, VCS/ZCD = VZCD(th)H0.5 − 2.0 mA

IZCD(bias) Current Sourced by the CS/ZCD Pin, VCS/ZCD = VZCD(th)L0.5 − 2.0 mA

TZCD (VCS/ZCD < VZCD(th)L) to (DRV high) − 60 200 ns

TSYNC Minimum ZCD Pulse Width −110 200 ns

TWDG Watch Dog Timer 80 200 320 ms

TWDG(OS) Watch Dog Timer in “Overstress” Situation 400 800 1200 ms

TTMO Time-out Timer 20 30 50 ms

IZCD(gnd) Source Current for CS/ZCD pin impedance Testing − 250 − mA

STATIC OVP

DMIN Duty Cycle, VFB = 3 V, Vcontrol pin open − − 0 %

ON-TIME CONTROL

TON(LL) Maximum On Time, Vsense = 1.4 V and Vcontrol maximum (CrM) 22.0 25.0 29.0 ms

TON(LL)2 On Time, Vsense = 1.4 V and Vcontrol = 2.5 V (CrM) 10.5 12.5 14.0 ms

TON(HL) Maximum On Time, Vsense = 2.8 V and Vcontrol maximum (CrM) 7.3 8.5 9.6 ms

TON(LL)(MIN) Minimum On Time, Vsense = 1.4 V (not tested, guaranteed by characterization) − − 200 ns

TON(HL)(MIN) Minimum On Time, Vsense = 2.8 V (not tested, guaranteed by characterization) − − 100 ns

FEED-BACK OVER AND UNDER-VOLTAGE PROTECTION (SOFT OVP AND UVP)

RsoftOVP Ratio (soft OVP Threshold, VFB rising) over VREF (VsoftOVP/VREF)

(guaranteed by design) 104 105 106 %

RsoftOVP(HYST) Ratio (Soft OVP Hysteresis) over VREF (guaranteed by design) 1.5 2.0 2.5 %

RUVP Ratio (UVP Threshold, VFB rising) over VREF (VUVP/VREF)

(guaranteed by design) 8 12 16 %

RUVP(HYST) Ratio (UVP Hysteresis) over VREF (guaranteed by design) − − 1 %

(IB)FB FB Pin Bias Current @ VFB = VsoftOVP and VFB = VUVP 50 200 450 nA

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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Table 3. TYPICAL ELECTRICAL CHARACTERISTICS (continued)

(Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified)

Symbol UnitMaxTypMinRating

FAST OVER VOLTAGE PROTECTION AND BULK UNDER-VOLTAGE PROTECTION (FAST OVP AND BUV)

VfastOVP Fast OVP Threshold, VFOVP rising 2.560 2.675 2.750 V

RfastOVP1 Ratio (Fast OVP Threshold, VFOVP rising) over (soft OVP Threshold,

VFB rising) (VfastOVP/VsoftOVP) (guaranteed by design) 101.5 102.0 102.5 %

RfastOVP2 Ratio (Fast OVP Threshold, VFOVP rising) over VREF (VfastOVP/VREF)

(guaranteed by design) 106 107 108 %

VBUV BUV Threshold:

NCP1612A, NCP1612B, VFOVP falling

NCP1612A1, NCP1612A3, VFOVP falling

NCP1612A2 and NCP1612B2, VFB falling

1.80

0.90

1.80

1.90

1.00

1.90

2.00

1.10

2.00

RBUV Ratio (BUV Threshold) over VREF (VBUV/VREF)

NCP1612A, NCP1612B, VFOVP falling

NCP1612A1, NCP1612A3, VFOVP falling

NCP1612A2 and NCP1612B2, VFB falling

(IB)FOVP/BUV Pin1 Bias Current

@ Vpin1 = VfastOVP (all versions)

@ Vpin1 = VBUV (NCP1612A, NCP1612A1, NCP1612B, NCP1612A3 only) 50

50 200

200 450

450

VUVP2 UVP2 Threshold for Floating Pin Detection

(NCP1612A, NCP1612A1, NCP1612A3 and NCP1612B only) 0.2 0.3 0.4 V

BROWN-OUT PROTECTION AND FEED-FORWARD

VBOH Brown-out Threshold, Vsense rising 0.96 1.00 1.04 V

VBOL Brown-out Threshold, Vsense falling 0.86 0.90 0.94 V

VBO(HYST) Brown-out Comparator Hysteresis 60 100 − mV

TBO(blank) Brown-out Blanking Time 35 50 65 ms

ICONTROL(BO) VCONTROL Pin Sink Current, Vsense < VBOL 40 50 60 mA

VHL High-line Detection Comparator Threshold, Vsense rising 2.1 2.2 2.3 V

VLL High-line Detection Comparator Threshold, Vsense falling 1.6 1.7 1.8 V

VHL(hyst) High-line Detection Comparator Hysteresis 400 500 600 mV

THL(blank) Blanking Time for Line Range Detection 15 25 35 ms

IBO(bias) Brown-out Pin Bias Current, Vsense = VBO −250 − 250 nA

pfcOK SIGNAL

(VpfcOK)LpfcOK low state voltage @ IpfcOK = 5 mA − − 250 mV

VSTDWN Shutdown Threshold Voltage (NCP1612A, NCP1612A1, NCP1612A3 and

NCP1612B only) 7.0 7.5 8.0 V

RpfcOK Impedance of the pfcOK pin in high state (all versions) 150 300 − kW

THERMAL SHUTDOWN

TLIMIT Thermal Shutdown Threshold − 150 − °C

HTEMP Thermal Shutdown Hysteresis − 50 − °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

7. There is actually a minimum dead-time that is the delay between the core reset detection and the DRV turning on (TZCD parameter of the

“Current Sense and Zero Current Detection Blocks” section).

8. Guaranteed by design, the VCC pin can handle the double of the DRV peak source current, that is, 1 A typically.

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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Table 4. DETAILED PIN DESCRIPTION

Pin Number Name Function

1 FOVP Vpin1 is the input signal for the Fast Over-voltage (FOVP). The circuit disables the driver if

Vpin1 exceeds the FOVP threshold which is set 2% higher than the reference for the soft OVP

comparator (that monitors the feedback pin) so that pins 1 and 2 can receive the same portion

of the output voltage.

With the NCP1612A, NCP1612A1, NCP1612A3 and NCP1612B, Vpin1 is also used for

under-voltage detection (UVP2) and Bulk Under Voltage (BUV) detection. The BUV

comparator disables the driver and grounds the pfcOK pin when Vpin1 drops below 76% of the

2.5 V reference voltage in the A and B versions and below 40% of the 2.5 V reference voltage

in the A1/A3 version. The BUV function has no action whenever the pfcOK pin is in low state.

A 250 nA sink current is built-in to ground the pin if the pin is accidentally open.

2 Feedback This pin receives a portion of the PFC output voltage for the regulation and the Dynamic

Response Enhancer (DRE) that drastically speeds-up the loop response when the output

voltage drops below 95.5% of the desired output level.

Vpin2 is also the input signal for the Over-voltage (OVP) and Under-voltage (UVP)

comparators. The UVP comparator prevents operation as long as Vpin2 is lower than 12% of

the reference voltage (VREF). A soft OVP comparator gradually reduces the duty-ratio to zero

when Vpin2 exceeds 105% of VREF (soft OVP). With the NCP1612A2 and the NCP1612B2,

Vpin2 is used for Bulk Under Voltage (BUV) detection.

A 250 nA sink current is built-in to trigger the UVP protection and disable the part if the

feedback pin is accidentally open.

3 VCONTROL The error amplifier output is available on this pin. The network connected between this pin and

ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high

Power Factor ratios.

Pin3 is grounded when the circuit is off so that when it starts operation, VCONTROL slowly

charges up to provide a soft-start function with the A, A1, A2 and A3 versions which disables

the dynamic response enhancer (DRE) until the startup phase is completed. With the versions

optimized for self-powered PFC stages (NCP1612B and NCP1612B2), DRE speeds-up the

VCONTROL charge for a shortened startup phase.

4 VSENSE A portion of the instantaneous input voltage is to be applied to pin4 in order to detect brown-out

conditions. If Vpin4 is lower than 0.9 V for more than 50 ms, the circuit stops pulsing until the pin

voltage rises again and exceeds 1 V.

This pin also detects the line range. By default, the circuit operates the “low-line gain” mode.

If Vpin4 exceeds 2.2 V, the circuit detects a high-line condition and reduces the loop gain by 3.

Conversely, if the pin voltage remains lower than 1.7 V for more than 25 ms, the low-line gain is

set.

Connecting the pin 4 to ground disables the part once the 50-ms blanking time has elapsed.

5 FFCONTROL This pin sources a current representative to the line current. Connect a resistor between pin5

and ground to generate a voltage representative of the line current. When this voltage exceeds

the internal 2.5 V reference (VREF), the circuit operates in critical conduction mode. If the pin

voltage is below 2.5 V, a dead-time is generated that approximately equates

[66 ms•(1 − (Vpin5/VREF))]. By this means, the circuit forces a longer dead-time when the

current is small and a shorter one as the current increases.

The circuit skips cycles whenever Vpin5 is below 0.65 V to prevent the PFC stage from

operating near the line zero crossing where the power transfer is particularly inefficient. This

does result in a slightly increased distortion of the current. If superior power factor is required,

offset pin 5 by more than 0.75 V offset to inhibit the skip function.

6 CS/ZCD This pin monitors the MOSFET current to limit its maximum current.

This pin is also connected to an internal comparator for Zero Current Detection (ZCD). This

comparator is designed to monitor a signal from an auxiliary winding and to detect the core

reset when this voltage drops to zero. The auxiliary winding voltage is to be applied through a

diode to avoid altering the current sense information for the on-time (see application schematic).

7 Ground Connect this pin to the PFC stage ground.

8 Drive The high-current capability of the totem pole gate drive (−0.5/+0.8 A) makes it suitable to

effectively drive high gate charge power MOSFETs.

9 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 10.5 V

(A, A1, A2 and A3 versions, 17.0 V for the B and B2 versions) and turns off when VCC goes

below 9.0 V (typical values). After start-up, the operating range is 9.5 V up to 35 V. The A, A1,

A2 and A3 versions are preferred in applications where the circuit is fed by an external power

source (from an auxiliary power supply or the downstream converter). Its maximum start-up

level (11.25 V) is set low enough so that the circuit can be powered from a 12 V rail. The B and

B2 versions are optimized for applications where the PFC stage is self-powered.

10 pfcOK This pin is grounded until the PFC output has reached its nominal level. It is also grounded if

the NCP1612 detects a fault. For the rest of the time, i.e., when the PFC stage outputs the

nominal bulk voltage, pin10 is in high-impedance state.

The NCP1612A, NCP1612A1, NCP1612A3 and NCP1612B latch off if Vpin10 exceeds 7.5 V.

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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Figure 4. Block Diagram

DRV

VDD Regul

Vcc

Output

Buffer

Internal

Thermal

Shutdown

TSD

OFF UVLO

Vcontrol

FFcontrol

Vton

processing

circuitry

GND

STDWN

OFF

Iref

−

Error Amplifier

Vref

−

0.955*Vref

hyst<0.5%Vref

Dynamic Response

Enhancer

+/−20mA

Vcc

fastOVP

OFF

OVLflag1

All the RS latches are

RESET dominant

Vcc_OK

REGUL

pfcOK 200 mA

VDD

Vref

OVLflag1

LpfcOK

Fault

management

staticOVP

(0.5−V bottom

clamp

is activated)

UVP

Vcc(on) / Vcc(off)

BO_NOK

Brown−out

and Line Range

Detection

LLine

OFF

staticOVP

OCP STOP

Lpwm1

Vpwm

STOP

IBO

IBO IREGUL

SKIP

Current Information

Generator and

dead−time control

−

Internal

timing

ramp

DRV

LLine

CLK

−

UVP

softOVP

12%*Vref

hyst<1%Vref

105%*Vref /

103% *Vref

ZCD

DRV

50mA

staticOVP

BO_NOK

BUV_fault

pfcOK

−

STDWN

2.5 V

BUV

−OFF

pfcOK

Lstdwn

Vcc(reset)

staticOVP

BUV

LBO

OCP +

−

−750mV /

250mV

ZCD

Detection

of excessive

currents

DRV 200−ns

blanking

time

DRV

500mV

Overstress

FOVP

−

107% Vref

hyst<1% Vref

fastOVP

−

BUVcomp

−

12*Vref

UVP2

0.5V

LLine

100−ns

blanking

time

DRV

staticOVP

BONOK

LBUV BUV_fault

BO_fault

softOVP

SKIP

CLK

DT Overstress

0.5−V bottom clamp

Overstress

BONOK

Vcc_OK

pfcOK_in

CCFF mode

(including SKIP function)

are inhibited whenever

pfcOK_in is low

VBUV

NCP1612A2 and NCP1612B2

BUVcomp1

−

VBUV

BUVcomp2

BUVcomp1

BUVcomp2

fastOVP

NCP1612A2 and

NCP1612B2

NCP1612A

NCP1612A1

NCP1612A3

and NCP1612B

NCP1612A

NCP1612A1

NCP1612A3

and NCP1612B

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 5. Start-up Threshold, VCC Increasing

(VCC(on)) vs. Temperature (A, A1, A2 and A3

Versions)

Figure 6. Start-up Threshold, VCC Increasing

(VCC(on)) vs. Temperature (B and B2 Versions)

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

11090703010−10−30−50

9.0

9.5

10.0

10.5

11.0

11.5

12.0

11090703010−10−30−50

16.0

16.2

16.6

16.8

17.0

17.2

17.4

17.6

Figure 7. VCC Minimum Operating Voltage, VCC

Falling (VCC(off)) vs. Temperature Figure 8. Hysteresis (VCC(on) − VCC(off)) vs.

Temperature (A, A1, A2 and A3 Versions)

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

8.00

8.25

8.50

8.75

9.00

9.50

9.75

10.00

0.50

0.75

1.00

1.25

1.50

1.75

2.00

Figure 9. Start-up Current @ VCC = 9.4 V vs.

Temperature Figure 10. Operating Current, No Switching

(VSENSE Grounded) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

0.25

0.50

0.75

1.00

1.25

1.50

VCC(on) (V)

VCC(off) (V)

VCC(hysr) (V)

ICC(start) (mA)

ICC(0p)1 (mA)

50 130 50 130

16.4

11090703010−10−30−50 50 130

9.25

11090703010−10−30−50 50 130

11090703010−10−30−50 50 130 11090703010−10−30−50 50 130

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 11. FFcontrol Pin Current, VSENSE =

1.4 V and VCONTROL Maximum vs. Temperature Figure 12. FFcontrol Pin Current, VSENSE =

2.8 V and VCONTROL Maximum vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

100

125

150

175

225

250

275

300

100

125

150

175

200

Figure 13. Dead-time, VFFcontrol = 1.75 V vs.

Temperature Figure 14. Dead-time, VFFcontrol = 1.00 V vs.

Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

12.5

14.5

16.5

18.5

20.5

22.5

Figure 15. FFcontrol Pin Skip Level (VFFcontrol

Rising) vs. Temperature Figure 16. FFcontrol Pin Skip Level (VFFcontrol

Falling) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

0.45

0.55

0.65

0.75

0.85

IDT1 (mA)

IDT2 (mA)

TDT2 (ms)

TDT3 (ms)

VSKIP−H (V)

11090703010−10−30−50 50 130

200

11090703010−10−30−50 50 130

11090703010−10−30−50 50 130 11090703010−10−30−50 50 130

11090703010−10−30−50 50 130 0.45

0.55

0.65

0.75

0.85

VSKIP−L (V)

11090703010−10−30−50 50 130

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 17. DRV Source Resistance vs.

Temperature Figure 18. DRV Voltage Rise-time (CL = 1 nF,

10−90% of Output Signal) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 19. DRV Sink Resistance vs.

Temperature Figure 20. DRV Voltage Fall-time (CL = 1 nF,

10−90% of Output Signal) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 21. DRV Pin Level @ VCC = 35 V (RL =

33 kW, CL = 1 nF) vs. Temperature Figure 22. Feedback Reference Voltage vs.

Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

2.35

2.40

2.45

2.50

2.55

2.60

2.65

ROH (W)

Trise (ns)

ROL (W)

Tfall (ns)

VDRVhigh (V)

VREF (V)

11090703010−10−30−50 50 130 0

11090703010−10−30−50 50 130

11090703010−10−30−50 50 130 0

11090703010−10−30−50 50 130

11090703010−10−30−50 50 130 11090703010−10−30−50 50 130

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 23. Error Amplifier Transconductance

Gain vs. Temperature Figure 24. Ratio (VOUT Low Detect Threshold /

VREF) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

150

175

200

225

250

Figure 25. Ratio (VOUT Low Detect Hysteresis /

VREF) vs. Temperature Figure 26. VCONTROL Source Current when

(VOUT Low Detect) is Activated for Dynamic

Response Enhancer (DRE) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

0.1

0.2

0.3

0.4

0.5

140

160

180

200

220

240

260

280

Figure 27. Current Sense Voltage Threshold

vs. Temperature Figure 28. Over-current Protection Leading

Edge Blanking vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

480

485

490

495

505

510

515

520

120

140

160

180

220

240

260

280

GEA (mS)

VOUTL / VREF (%)

HOUTL / VREF (%)

IBOOST (mA)

VBCS(th) (mV)

TLEB−OCP (ns)

11090703010−10−30−50 50 130 11090703010−10−30−50 50 130

11090703010−10−30−50 50 130

500

11090703010−10−30−50 50 130

200

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 29. “Overstress” Protection Leading

Edge Blanking vs. Temperature Figure 30. Over-current Protection Delay from

VCS/ZCD > VCS(th) to DRV Low (dVCS/ZCD / dt =

10 V/ms) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

100

110

120

130

140

100

Figure 31. Zero Current Detection, VCS/ZCD

Rising vs. Temperature Figure 32. Zero Current Detection, VCS/ZCD

Falling vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

650

700

750

800

850

230

235

240

245

255

260

265

270

Figure 33. Hysteresis of the Zero Current

Detection Comparator vs. Temperature Figure 34. VZCD(th) over VCS(th) Ratio vs.

Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

420

440

460

480

500

520

540

560

1.2

1.3

1.4

1.5

1.6

1.7

1.8

TLEB−OVS (ns)

TOCP (ns)

VZCD(th)H (mV)

VZCD(th)L (mV)

VZCD(hyst) (mV)

RZCD/CS (−)

11090703010−10−30−50 50 130

11090703010−10−30−50 50 130 11090703010−10−30−50 50 130

250

11090703010−10−30−50 50 130 11090703010−10−30−50 50 130

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 35. CS/ZCD Pin Bias Current @ VCS/ZCD

= 0.75 V vs. Temperature Figure 36. Watchdog Timer vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

0.5

0.6

0.8

0.9

1.1

1.2

1.4

1.5

160

170

180

190

210

220

230

240

Figure 37. Watchdog Timer in “Overstress”

Situation vs. Temperature Figure 38. Minimum ZCD Pulse Width for ZCD

Detection vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

640

680

720

760

840

880

920

960

100

110

120

130

140

Figure 39. ((VCS/ZCD < VZCD(th)) to DRV High)

Delay vs. Temperature Figure 40. Timeout Timer vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

100

110

IZCD/(bias) (mA)

TWTG (ms)

TWTG(OS) (ms)

TSYNC (ns)

TZCD (ns)

TTMO (ms)

11090703010−10−30−50 50 130

0.7

1.0

1.3

11090703010−10−30−50 50 130

200

11090703010−10−30−50 50 130

800

11090703010−10−30−50 50 130

11090703010−10−30−50 50 130 11090703010−10−30−50 50 130

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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TYPICAL CHARACTERISTICS

Figure 41. Maximum On Time @ VSENSE =

1.4 V vs. Temperature Figure 42. Maximum On Time @ VSENSE =

2.8 V vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

24.0

24.5

25.0

25.5

26.0

26.5

27.0

8.2

8.3

8.4

8.5

8.6

8.7

8.8

Figure 43. Minimum On Time @ VSENSE = 1.4 V

vs. Temperature Figure 44. Minimum On Time @ VSENSE = 2.8 V

vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

100

Figure 45. Ratio (Soft OVP Threshold, VFB

Rising) over VREF vs. Temperature Figure 46. Ratio (Soft OVP Hysteresis) over

VREF vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

104.6

104.7

104.8

104.9

105.0

105.2

105.3

105.4

1.8

1.9

2.0

2.1

2.2

TON(LL) (ms)

TON(HL) (ms)

TON(LL)(MIN) (ns)

TON(HL)(MIN) (ns)

RsoftOVP (%)

RsoftOVP(HYST) (%)

11090703010−10−30−50 50 130 11090703010−10−30−50 50 130

11090703010−10−30−50 50 130

100

11090703010−10−30−50 50 130

105.1

11090703010−10−30−50 50 130

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 47. Ratio (fastOVP Threshold, VFOVP

Rising) over VREF vs. Temperature Figure 48. Feedback Pin Bias Current @ VFB =

VOVP vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

106.6

106.7

106.8

106.9

107.1

107.2

107.3

107.4

150

170

190

210

230

250

270

290

Figure 49. Feedback Pin Bias Current @ VFB =

VUVP vs. Temperature Figure 50. Ratio (UVP Threshold, VFB Rising)

over VREF vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

150

170

190

210

230

250

270

290

Figure 51. Ratio (UVP Hysteresis) over VREF

vs. Temperature Figure 52. Brown-out Threshold, VSENSE

Rising vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.90

0.95

1.00

1.05

1.10

RfastOVP2 (%)

IB(FB) (nA)

IB(FB)2 (nA)

RfUVP (%)

RfUVP(HYST) (%)

VBOH (V)

11090703010−10−30−50 50 130

107.0

11090703010−10−30−50 50 130

11090703010−10−30−50 50 130 11090703010−10−30−50 50 130

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 53. Brown-out Threshold, VSENSE

Falling vs. Temperature Figure 54. Brown-out Comparator Hysteresis

vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

0.80

0.85

0.90

0.95

1.00

100

105

110

Figure 55. Brown-out Blanking Time vs.

Temperature Figure 56. VCONTROL Pin Sink Current when a

Brown-out Situation is Detected vs.

Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 57. Comparator Threshold for Line

Range Detection, VSENSE Rising vs.

Temperature

Figure 58. Comparator Threshold for Line

Range Detection, VSENSE Falling vs.

Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1.9

2.0

2.1

2.2

2.3

2.4

1.5

1.6

1.7

1.8

1.9

VBOL (V)

VBO(HYST) (mV)

TBO(blank) (ms)

ICONTROL(BO) (mA)

VHL (V)

VLL (V)

11090703010−10−30−50 50 130 11090703010−10−30−50 50 130

11090703010−10−30−50 50 13011090703010−10−30−50 50 130

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 59. Blanking Time for Line Range

Detection vs. Temperature Figure 60. Brown-out Pin Bias Current,

(VSENSE = VBOH) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

−4

−2

−1

THL(blank) (ms)

IBO(bias) (nA)

11090703010−10−30−50 50 130 11090703010−10−30−50 50 130

−3

DETAILED OPERATING DESCRIPTION

Introduction

The NCP1612 is designed to optimize the efficiency of

your PFC stage throughout the load range. In addition, it

incorporates protection features for rugged operation. More

generally, the NCP1612 is ideal in systems where

cost-effectiveness, reliability, low stand-by power and high

efficiency are the key requirements:

•Current Controlled Frequency Fold-back: the NCP1612 is

designed to drive PFC boost stages in so-called Current

Controlled Frequency Fold-back (CCFF). In this mode,

the circuit classically operates in Critical conduction

Mode (CrM) when the inductor current exceeds a

programmable value. When the current is below this

preset level, the NCP1612 linearly reduces the frequency

down to about 20 kHz when the current is zero. CCFF

maximizes the efficiency at both nominal and light load.

In particular, stand-by losses are reduced to a minimum.

Similarly to FCCrM controllers, an internal circuitry

allows near-unity power factor even when the switching

frequency is reduced.

•Skip Mode: to further optimize the efficiency, the

circuit skips cycles near the line zero crossing when the

current is very low. This is to avoid circuit operation

when the power transfer is particularly inefficient at the

cost of current distortion. When superior power factor

is required, this function can be inhibited by offsetting

the “FFcontrol” pin by 0.75 V.

•Low Start-up Current and large VCC range (B and B2

versions): The consumption of the circuit is minimized to

allow the use of high-impedance start-up resistors to

pre-charge the VCC capacitor. Also, the minimum value

of the UVLO hysteresis is 6 V to avoid the need for large

VCC capacitors and help shorten the start-up time without

the need for too dissipative start-up elements. The A, A1,

A2 and A3 versions are preferred in applications where

the circuit is fed by an external power source (from an

auxiliary power supply or from the downstream

converter). Their maximum start-up level (11.25 V) is set

low enough so that the circuit can be powered from

a 12 V rail. After start-up, the high VCC maximum rating

allows a large operating range from 9.5 V up to 35 V.

•pfcOK signal: the pfcOK pin is to disable/enable the

downstream converter. Grounded until the PFC output

has reached its nominal level and whenever the

NCP1612 detects a fault, it is in high-impedance when

the PFC stage outputs the nominal bulk voltage. In

addition, with the A, A1, A3 and B versions, the circuit

latches off if a voltage exceeding 7.5 V is applied to

pin 10.

•Fast Line/Load Transient Compensation (Dynamic

Response Enhancer): since PFC stages exhibit low loop

bandwidth, abrupt changes in the load or input voltage

(e.g., at start-up) may cause excessive over- or

under-shoot. This circuit limits possible deviations from

the regulation level as follows:

− The Soft Over-Voltage Protection contains the

output voltage when it tends to become excessive.

− The NCP1612 dramatically speeds-up the regulation

loop when the output voltage goes below 95.5 % of

its regulation level. In the versions targeting

applications where VCC is supplied by an external

power supply or the downstream converter (A, A1,

A2 and A3), this function is disabled until the PFC

stage having started-up, pfcOK is in high state. This

is to take benefit from the soft-start effect offered by

the VCONTROL pin gradual charge.

•Safety Protections: the NCP1612 permanently monitors

the input and output voltages, the MOSFET current and

the die temperature to protect the system from possible

over-stress making the PFC stage extremely robust and

reliable. In addition to the OVP protection, these methods

of protection are provided:

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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− Maximum Current Limit: the circuit senses the

MOSFET current and turns off the power switch if

the set current limit is exceeded. In addition, the

circuit enters a low duty-cycle operation mode when

the current reaches 150% of the current limit as

a result of the inductor saturation or a short of the

bypass diode.

− Under-Voltage Protection: this circuit turns off when

it detects that the output voltage is below 12% of the

voltage reference (typically). This feature protects

the PFC stage if the ac line is too low or if there is

a failure in the feedback network (e.g., bad

connection).

− Fast Over-Voltage Detection (Fast OVP): the FOVP

pin provides a redundant protection in the case of an

excessive output voltage level. Note that with the

NCP1612A2 and NCP1612B2 versions, the fast

OVP latches off the circuit.

− Bulk Under-Voltage Detection (BUV): The BUV

function is implemented to prevent the downstream

converter from operating when the buck voltage is

too low. Practically, the BUV comparator monitors

the FOVP pin (NCP1612A, NCP1612A1,

NCP1612A3 and NCP1612B) or the FB pin

(NCP1612A2, NCP1612B2) to disable the driver,

gradually discharge the control pin and ground the

pfcOK pin when the sensed voltage drops below the

BUV threshold (40% of the 2.5 V reference voltage

with the A1/A3 version, 76% with the other

versions). The BUV function has no action

whenever the pfcOK pin is in low state.

− Brown-Out Detection: the circuit detects low ac line

conditions and stops operation thus protecting the

PFC stage from excessive stress.

− Thermal Shutdown: an internal thermal circuitry

disables the gate drive when the junction

temperature exceeds 150°C (typically). The circuit

resumes operation once the temperature drops below

approximately 100°C (50°C hysteresis).

•Output Stage Totem Pole: the NCP1612 incorporates

a −0.5 A/+0.8 A gate driver to efficiently drive most

TO220 or TO247 power MOSFETs.

NCP1612 Operation Modes

As mentioned, the NCP1612 PFC controller implements

a Current Controlled Frequency Fold-back (CCFF) where:

•The circuit operates in classical Critical conduction

Mode (CrM) when the inductor current exceeds

a programmable value.

•When the current is below this preset level,

the NCP1612 linearly reduces the operating frequency

down to about 20 kHz when the current is zero.

Figure 61. CCFF Operation

High Current

No Delay →CrM

Low Current

The Next Cycle is

Delayed

Lower Current

Longer Dead-time

Timer Delay

As illustrated i n F igure 61, under high l oad c onditions, t he

boost s tage i s o perating i n C rM b ut a s t he l oad i s re duced, t he

controller enters controlled frequency discontinuous

operation.

Figure 62 d etails the o peration. A v oltage r epresentative of

the input current (“current information”) is generated. If this

signal is higher than a 2.5 V internal reference (named

“Dead-time Ramp Threshold” in Figure 62), there is no

dead-time and the circuit operates in CrM. If the current

information is lower than t he 2.5 V threshold, a d ead-time i s

inserted that l asts f or the t ime n ecessary f or t he i nternal r amp

to reach 2.5 V from the c urrent information f loor. Hence, the

lower t he c urrent information i s, t he l onger t he d ead-time. F or

all versions except NCP1612A3, the maximum dead-time is

approximately 48.5 ms when the current information is

0.65 V typically. The NCP1612A3 limits the maximum

dead-time to 41.5 ms typically when the current information

is 0.90 V typically. In both cases, if the current information

further decreases, the circuit enters skip mode (see next

section).

To further reduce the losses, the MOSFET turns on is

stretched until its drain-source voltage is at its valley. As

illustrated in Figure 62, the ramp is synchronized to the

drain-source ringing. I f t he r amp e xceeds the 2.5 V t hreshold

while the drain-source voltage is below Vin, the ramp is

extended u ntil it o scillates a bove Vin s o that the d rive w ill turn

on at the next valley.

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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Top: CrM operation when the current information exceeds the preset level during the demagnetization phase

Middle: the circuit re-starts at the next valley if the sum (ramp + current information) exceeds the preset level during the dead-time, while

the drain-source voltage is high

Bottom: the sum (ramp + current information) exceeds the preset level while during the dead-time, the drain-source voltage is low. The

circuit skips the current valley and re-starts at the following one.

Figure 62. Dead-Time generation

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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Current Information Generation

The “FFcontrol” pin sources a current that is

representative of the input current. In practice, Ipin5 is built

by multiplying the internal control signal (VREGUL, i.e., the

internal signal that controls the on-time) by the sense voltage

(pin 4) that is proportional to the input voltage. The

multiplier gain (Km of Figure 63) is three times less in

high-line conditions (that is when the “LLine” signal from

the brown-out block is in low state) so that Ipin5 provides a

voltage representative of the input current across resistor

RFF placed between pin 5 and ground. Pin 5 voltage is the

current information.

BO pin

V to I

converter

Vcontrol pin

V to I

converter

Multiplier

FFcontrol pin

SUM

RAMP

skip2

pfcOK

LLine

SKIP

RAMP

SUM

pfcOK

Figure 63. Generation of the Current Information

VSKIP_H / VSKIP_L

VSENSE Pin

VCONTROL Pin

FFCONTROL Pin

IBO IBO

IREGUL

IREGUL = K • VREGUL

Km • IREGUL • IBO

RFF

Skip Mode

As illustrated in Figure 63, the circuit also skips cycles

near the line zero crossing where the current is very low.

A comparator monitors the pin 5 voltage (“FFcontrol”

voltage) and inhibits the switching operation when Vpin5 is

lower than VSKIP_L (0.90 V typically for the NCP1612A3,

0.65 V for the other versions). Switching resumes when

Vpin5 exceeds VSKIP_H (1 V typically for the NCP1612A3,

0.75 V for the other versions). This function prevents circuit

operation when the power transfer is particularly inefficient

at the expense of slightly increased current distortion. When

superior power factor is needed, this function can be

inhibited of fsetting the “FFcontrol” pin by a voltage higher

than VSKIP_H. The skip mode capability is disabled

whenever the PFC stage is not in nominal operation (as

dictated by the “pfcOK” signal − see block diagram and

“pfcOK Internal Signal” Section).

The circuit does not abruptly interrupt the switching when

Vpin5 goes below VSKIP_L. Instead, the signal VTON that

controls the on-time is gradually decreased by grounding the

VREGUL signal applied to the VTON processing block (see

Figure 68). Doing so, the on-time smoothly decays to zero

in 3 to 4 switching periods typically. Figure 64 shows the

practical implementation.

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

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Figure 64. CCFF Practical Implementation

CCFF maximizes the efficiency at both nominal and light

load. In particular, the stand-by losses are reduced to

a minimum. Also, this method avoids that the system stalls

between valleys. Instead, the circuit acts so that the PFC

stage transitions from the n valley to (n + 1) valley or vice

versa from the n valley to (n − 1) cleanly as illustrated by

Figure 65.

Figure 65. Clean Transition Without Hesitation Between Valleys

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NCP1612 On-time Modulation

Let’s analyze the ac line current absorbed by the PFC

boost stage. The initial inductor current at the beginning of

each switching cycle is always zero. The coil current ramps

up when the MOSFET is on. The slope is (VIN/L) where L

is the coil inductance. At the end of the on-time (t1), the

inductor starts to demagnetize. The inductor current ramps

down until it reaches zero. The duration of this phase is (t2).

In some cases, the system enters then the dead-time (t3) that

lasts until the next clock is generated.

One can show that the ac line current is given by:

Iin +Vinƪt1ǒt1)t2Ǔ

2TL ƫ(eq. 1)

Where T = (t1 + t2 + t3) is the switching period and Vin is the

ac line rectified voltage.

In light of this equation, we immediately note that Iin is

proportional to Vin if [t1 (t1 + t2) / T] is a constant.

Figure 66. PFC Boost Converter (left) and Inductor Current in DCM (right)

The NCP1612 operates in voltage mode. As portrayed by

Figure 67, the MOSFET on-time t1 is controlled by the

signal V ton generated by the regulation block and an internal

ramp as follows:

t1+Cramp @Vton

Ich (eq. 2)

The charge current is constant at a given input voltage (as

mentioned, it is three times higher at high line compared to

its value at low line). Cramp is an internal capacitor.

The output of the regulation block (VCONTROL) is linearly

transformed into a signal (VREGUL) varying between 0 and

1 V. (VREGUL) is the voltage that is injected into the PWM

section t o modulate the MOSFET duty-cycle. The NCP1612

includes some circuitry that processes (VREGUL) to form the

signal (Vton) that is used in the PWM section (see

Figure 68). (Vton) is modulated in response to the dead-time

sensed during the precedent current cycles, that is, for

a proper shaping of the ac line current. This modulation

leads to:

Vton +T@VREGUL

t1)t2(eq. 3)

Vton @t1)t2

T+VREGUL

Given the low regulation bandwidth of the PFC systems,

(VCONTROL) and then (VREGUL) are slow varying signals.

Hence, the (Vton × (t1 + t2)/T) term is substantially constant.

Provided that in addition, (t1) is proportional to (Vton),

Equation 1 leads to: , where k is a constant. More exactly:

Iin +k@Vin

where:

k+constant +ƪ1

2L @VREGUL

ǒVREGULǓmax

@ton,maxƫ

Where ton,max is the maximum on-time obtained when

VREGUL is at its (VREGUL)max maximum level. The

parametric table shows that ton,max is equal to 25 ms

(TON(LL)) at low line and to 8.5 ms (TON(HL)) at high line

(when pin4 happens to exceeds 1.8 V with a pace higher than

40 Hz − see BO 25 ms blanking time).

Hence, we can re-write the above equation as follows:

Iin +Vin @TON(LL)

2@L@VREGUL

ǒVREGULǓmax

at low line.

Iin +Vin @TON(HL)

2@L@VREGUL

ǒVREGULǓmax

at high line.

From these equations, we can deduce the expression of the

average input power:

Pin,avg +ǒVin,rmsǓ2@VREGUL @TON(LL)

2@L@ǒVREGULǓmax

at low line.

Pin,avg +ǒVin,rmsǓ2@VREGUL @TON(HL)

2@L@ǒVREGULǓmax

at high line.

Where (VREGUL)max is the VREGUL maximum value.

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Hence, the maximum power that can be delivered by the

PFC stage is:

ǒPin,avgǓmax +ǒVin,rmsǓ2@TON(LL)

2@L

at low line.

ǒPin,avgǓmax +ǒVin,rmsǓ2@TON(HL)

2@L

at high line.

The input current is then proportional to the input voltage.

Hence, the ac line current is properly shaped.

One can note that this analysis is also valid in the CrM

case. This condition is just a particular case of this

functioning where (t3 = 0), which leads to (t1 + t2 = T) and

(VTON = VREGUL). That is why the NCP1612 automatically

adapts to the conditions and transitions from DCM and CrM

(and vice versa) without power factor degradation and

without discontinuity in the power delivery.

Figure 67. PWM circuit and timing diagram.

Figure 68. VTON Processing Circuit. The integrator OA1 amplifies the error between VREGUL and IN1

so that on average, (VTON * (t1+t2)/T) equates VREGUL.

Remark:

The “Vton processing circuit” is “informed” when a

condition possibly leading to a long interruption of the drive

activity (functions generating the STOP signal that disables

the drive − see block diagram − except OCP, i.e., BUV_fault,

OVP, OverStress, SKIP, staticOVP and OFF). Otherwise,

such situations would be viewed as a normal dead-time

phase and Vton would inappropriately over-dimension Vton

to compensate it. Instead, as illustrated in Figure 68, the Vton

signal is grounded leading to a short soft-start when the

circuit recovers.

Regulation Block and Low Output Voltage Detection

A trans-conductance error amplifier (OTA) with access to

the inverting input and output is provided. It features

a typical trans-conductance gain of 200 mS and a maximum

capability of ±20 mA. The output voltage of the PFC stage

is typically scaled down by a resistors divider and monitored

by the inverting input (pin 2). Bias current is minimized

(less than 500 nA) to allow the use of a high impedance

feed-back network. However, it is high enough so that the

pin remains in low state if the pin is not connected.

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The output of the error amplifier is brought to pin 3 for

external loop compensation. Typically a type−2 network is

applied between pin 3 and ground, to set the regulation

bandwidth below about 20 Hz and to provide a decent phase

boost.

The swing of the error amplifier output is limited within

an accurate range:

•It is forced above a voltage drop (VF) by some circuitry.

•It is clamped not to exceed 4.0 V + the same VF voltage

drop.

Hence, Vpin3 features a 4 V voltage swing. Vpin3 is then

offset down by (VF) and scaled down by a resistors divider

before it connects to the “VTON processing block” and the

PWM section. Finally, the output of the regulation block is

a signal (“VREGUL” of the block diagram) that varies

between 0 and a top value corresponding to the maximum

on-time.

The VF value is 0.5 V typically.

(VREGUL)max

VREGUL

VCONTROL

Figure 69. a) Regulation Block Figure (left), b) Correspondence between VCONTROL and VREGUL (right)

Given the low bandwidth of the regulation loop, abrupt

variations of the load, may result in excessive over or

under -shoots. Over-shoot is limited by the soft Over-voltage

Protection (OVP) connected to the feedback pin or the fast

OVP of pin1.

The NCP1612 embeds a “dynamic response enhancer”

circuitry (DRE) that contains under-shoots. An internal

comparator monitors the feed-back (Vpin1) and when Vpin2

is lower than 95.5% of its nominal value, it connects

a 200 mA current source to speed-up the charge of the

compensation network. Effectively this appears as a 10x

increase in the loop gain.

In the A, A1, A2 and A3 versions, DRE is disabled during

the start-up sequence until the PFC stage has stabilized (that

is when the “pfcOK” signal of the block diagram, is high). The

resulting slow and gradual charge of the pin 3 voltage

(VCONTROL) softens the soft start-up sequence. In the B and

B2 versions, DRE is enabled during start-up to speed-up this

phase and allow for the use of smaller VCC capacitors.

The circuit also detects overshoot and immediately

reduces the power delivery when the output voltage exceeds

105% of its desired level. The NCP1612 does not abruptly

interrupt the switching. Instead, the signal VTON that

controls the on-time is gradually decreased by grounding the

VREGUL signal applied to the VTON processing block (see

Figure 68). Doing so, the on-time smoothly decays to zero

in 4 to 5 switching periods typically. If the output voltage

still increases, the fast OVP comparator immediately

disables the driver if the output voltage exceeds 108.5% of

its desired level.

The error amplifier OTA and the soft OVP, UVP and DRE

comparators share the same input information. Based on the

typical value of their parameters and if (Vout,nom) is the

output voltage nominal value (e.g., 390 V), we can deduce:

•Output Regulation Level: Vout,nom

•Output Soft OVP Level: Vout,sovp = 105% × Vout,nom

•Output UVP Level: Vout,uvp = 12% × Vout,nom

•Output DRE Level: Vout,dre = 95.5% × Vout,nom

Fast OVP and Bulk Under-Voltage (BUV)

These functions check that the output voltage is within th e

proper window:

•The fast Over-Voltage Protection trips if the bulk

voltage reaches abnormal levels. When the feedback

network is properly designed and correctly connected,

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the bulk voltage cannot exceed the level set by the soft

OVP function (Vout,sovp = 105% × Vout,nom, see

precedent section). This second protection offers some

redundancy for a higher safety level. The FOVP

threshold is set 2% higher than the soft OVP

comparator reference so that the same portion of the

output voltage can be applied to both the FOVP/BUV

and feedback input pins (pins 1 and 2). Note that the

versions A, A1, A3 and B only interrupt the DRV

activity until the FOVP pin voltage drops below the fast

OVP threshold (1% hysteresis). Versions A2 and B2

latch off the circuit when the fast OVP trips.

•The BUV comparator trips when the bulk voltage drops

below a value which may be incompatible with the

downstream converter proper operation. With versions

A, A1, A3 and B, a BUV fault is detected if the FOVP

pin voltage drops below the VBUV threshold ((VBUV =

76% × VREF) in NCP1612A and NCP1612B, (VBUV =

40% × VREF) in NCP1612A1 and NCP1612A3, where

VREF is the 2.5-V reference voltage). With the

NCP1612A2 and NCP1612B2, the BUV comparator

monitors the feedback signal and trips when it drops

below (VBUV = 76% × VREF). In all versions, a BUV

fault leads the circuit to ground the pfcOK pin (to

disable the downstream converter) and gradually

discharge the VCONTROL signal. The drive output is

disabled for the VCONTROL discharge time. When the

VCONTROL discharge is complete, the circuit can

attempt to recover operation.

However, the BUV function is disabled whenever the

pfcOK pin is in low state, not to inappropriately interrupt

start-up phases.

Figure 70. Bulk Under-voltage Detection

FOVP

Vbulk

Rovp2

Rovp1

BUV

pfcOK

−

107%*Vref

fastOVP

−

BUVcomp

−

0.3 V

UVP2

250 nA

VBUV

FOVP

BUV

pfcOK

−

107%*Vref

fastOVP

−

BUVcomp

REGULATION, UVP, softOVP, DRE blocks

250 nA

Vbulk

RFB2

RFB1

250 nA

VBUV

N*Vbulk

a) Fast OVP and BUV Functions in NCP1612A, NCP1612A1, NCP1612A3 and

NCP1612B b) Fast OVP and BUV Functions in NCP1612A2 and NCP1612B2

As a matter of fact, the FOVP and BUV functions monitor

the output voltage and check if it is within the window for

proper operation. Assuming that the same portion of the

output voltage is applied to the FOVP and feedback pins, we

have:

•Output fast OVP Level: Vout,FOVP = 107% × Vout,nom

•Output BUV Level:

− NCP1612A, NCP1612B, NCP1612A2, NCP1612B2:

Vout,BUV = 76% × Vout,nom

− NCP1612A1/A3: Vout,BUV = 40% × Vout,nom

Hence, if the output regulation voltage is 390 V, the output

voltage for fastOVP triggering is 417 V and the BUV output

voltage level is 156 V with the NCP1612A1/NCP1612A3

and 296 V with the other circuit options.

A 250-nA sink current is built-in to ground the pin if the

FOVP pin is accidentally open. With the A, A1, A3 and B

versions, the UVP2 protection that disables the drive as long

as the pin voltage is below 300 mV (typically), protects the

circuit if the FOVP pin is floating.

W ith the NCP1612A2 and NCP1612B2, there is no UVP2

protection. Also, the BUV comparator does not monitor the

FOVP but the feedback pin. Hence, these circuits can

operate in the absence of a minimum voltage on the FOVP

pin. This helps use another FOVP input signal instead of the

output voltage portion traditionally provided by a resistors

divider. The resistors divider losses (due to the bias current

drawn from the high-voltage rail) may be incompatible with

the most stringent standby specifications. Tens of milliwatts

can be saved by as shown by Figure 70b, providing the

FOVP pin with a voltage representative of the output voltage

obtained using the auxiliary winding of the PFC boost

inductor.

Current Sense and Zero Current Detection

The NCP1612 is designed to monitor the current flowing

through the power switch. A current sense resistor (Rsense)

is inserted between the MOSFET source and ground to

generate a positive voltage proportional to the MOSFET

current (VCS). The VCS voltage is compared to a 500 mV

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internally reference. When VCS exceeds this threshold, the

OCP signal turns high to reset the PWM latch and forces the

driver low. A 200 ns blanking time prevents the OCP

comparator from tripping because of the switching spikes

that occur when the MOSFET turns on.

The CS pin is also designed to receive a signal from an

auxiliary winding for Zero Current Detection. As illustrated

in Figure 71, an internal ZCD comparator monitors the pin6

voltage and if this voltage exceeds 750 mV,

a demagnetization phase is detected (signal ZCD is high).

The auxiliary winding voltage is applied thought a diode to

prevent this signal from distorting the current sense

information during the on-time. Thus, the OCP protection is

not impacted by the ZCD sensing circuitry. This comparator

incorporates a 500 mV hysteresis and is able to detect ZCD

pulses longer than 200 ns. When pin 6 voltage drops below

the lower ZCD threshold, the driver can turn high within

200 ns.

It may happen that the MOSFET turns on while a huge

current flows through the inductor. As an example such a

situation can occur at start-up when large in-rush currents

charge the bulk capacitor to the line peak voltage.

T raditionally, a bypass diode is generally placed between the

input and output high-voltage rails to divert this inrush

current. If this diode is accidentally shorted, the MOSFET

will also see a high current when it turns on. In both cases,

the current can be large enough to trigger the ZCD

comparator. An AND gate detects that this event occurs

while the drive signal is high. In this case, a latch is set and

the “OverStress” signal goes high and disables the driver for

a 800 ms delay. This long delay leads to a very low

duty-cycle operation in case of “OverStress” fault in order

to limit the risk of overheating.

Figure 71. Current Sense and Zero Current Detection Blocks

When no signal is received that triggers the ZCD

comparator during the off-time, an internal 200 ms watchdog

timer initiates the next drive pulse. At the end of this delay,

the circuit senses the CS/ZCD pin impedance to detect

a possible grounding of this pin and prevent operation. The

CS/ZCD external components must be selected to avoid

false fault detection. 3.9 kW is the recommended minimum

impedance to be applied to the CS/ZCD pin when

considering the NCP1612 parameters tolerance over the

−40°C to 125°C temperature range. Practically, R cs must be

higher than 3.9 kW in the application of Figure 71.

pfcOK Signal

The pfcOK pin is in high-impedance state when the PFC

stage operates nominally and is grounded in the following

cases:

•During the PFC stage start-up, that is, until the output

voltage has stabilized at the right level.

•If the output voltage is too low for proper operation of

the downstream converter, more specifically, when the

“BUV_fault” signal (see Figure 4) is in high state.

•In the case of a condition preventing the circuit from

operating properly like in a Brown-out situation or

when one of the following faults turns off the circuit:

− Incorrect feeding of the circuit (“UVLO” high when

VCC < VCC(off), VCC(off) equating 9 V typically).

− Excessive die temperature detected by the thermal

shutdown.

− Under-voltage Protection

− Latched-off of the part

− Regulation loop failure (UVP)

− Brown-out Situation (BO_fault high − see Figure 4)

The pfcOK signal is controlled as illustrated by Figure 72.

The circuit monitors the current sourced by the O TA. If there

is no current, we can deduce that the output voltage has

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reached its nominal level. The start-up phase is then

complete and pfcOK remains high-impedance until a fault

is detected. Upon startup, the internal signals and the

internal supply rails need some time to stabilize. The

pfcOK latch cannot be set during this time and until a

sufficient blanking time has elapsed. For the sake of

simplicity, this blanking delay is not represented in

Figure 72.

Another ma n d a t ory condition to set pfcOK high i s the low

state of the “BUVcomp” signal. This second necessary

condition ensures that the voltage applied to pin 1 is high

enough not to immediately trigger the BUV protection.

The pfcOK pin is to be used to enable the downstream

converter.

Figure 72. pfcOK Detection

Vcc

OFF

OVLflag1

LpfcOK

BUV_fault

pfcOK

2.5 V

BUVcomp

−STDWN

Lstdwn

Vcc(reset)

BONOK

Vcc_OK

Latching−off circuitry

NCP1612A, NCP1612A1, NCP1612A3, NCP1612B only

With the NCP1612A, NCP1612A1, NCP1612A3 and

NCP1612B, the circuit also incorporates a comparator to

a 7.5 V threshold so that the part latches off if the pfcOK pin

voltage exceeds 7.5 V. This pin is to protect the part in case

of major fault like an over heating. To recover operation,

VCC must drop below VCC(reset).

Brown-out Detection

The VSENSE pin (pin4) receives a portion of the

instantaneous input voltage (Vin). As Vin is a rectified

sinusoid, the monitored signal varies between zero or a small

voltage and a peak value.

For the brown-out block, we need to ensure that the line

magnitude is high enough for operation. This is done as

follows:

•The VSENSE pin voltage is compared to a 1 V reference.

•If Vpin4 exceeds 1 V, the input voltage is considered

sufficient

•If Vpin4 remains below 0.9 V for 50 ms, the circuit

detects a brown-out situation (100 mV hysteresis).

By default, when the circuit starts operation, the circuit is

in a fault state (“BO_NOK” high) until Vpin4 exceeds 1 V.

When “BO_NOK” is high, the drive is not disabled.

Instead, a 50 mA current source is applied to pin3 to

gradually reduce VCONTROL. As a result, the circuit only

stops pulsing when the SKIP function is activated

(VCONTROL reaches the skip detection threshold). At that

moment, the circuit turns off (see Figure 4). This method

limits any risk of false triggering. The input of the PFC stage

has some impedance that leads to some sag of the input

voltage when the drawn current is large. If the PFC stage

stops while a high current is absorbed from the mains, the

abrupt decay of the current may make the input voltage rise

and the circuit detect a correct line level. Instead, the gradual

decrease of VCONTROL avoids a line current discontinuity

and limits risk of false triggering.

Pin 4 is also used to sense the line for feed-forward.

A similar method is used:

•The VSENSE pin voltage is compared to a 2.2 V

reference.

•If Vpin4 exceeds 2.2 V, the circuit detects a high−line

condition and the loop gain is divided by three (the

internal PWM ramp slope is three times steeper)

•Once this occurs, if Vpin4 remains below 1.7 V for

25 ms, the circuit detects a low-line situation (500 mV

hysteresis).

At startup, the circuit is in low-line state (“LLine” high”)

until Vpin4 exceeds 2.2 V.

The line range detection circuit allows more optimal loop

gain control for universal (wide input mains) applications.

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As portrayed in Figure 73, the pin 4 voltage is also utilized

to generate the current information required for the

frequency fold-back function.

Figure 73. Input Line Sense Monitoring

Thermal Shutdown (TSD)

An internal thermal circuitry disables the circuit gate drive

and keeps the power switch off when the junction

temperature exceeds 150°C. The output stage is then

enabled once the temperature drops below about 100°C

(50°C hysteresis).

Output Drive Section

The output stage contains a totem pole optimized to

minimize the cross conduction current during high

frequency operation. The gate drive is kept in a sinking

mode whenever the Under-voltage Lockout is active or

more generally whenever the circuit is off. Its high current

capability (−500 mA/+800 mA) allows it to effectively

drive high gate charge power MOSFET. As the circuit

exhibits a l a rge VCC range (up to 35 V), the drive pin voltage

is clamped not to provide the MOSFET gate with more than

14 V.

Reference Section

The circuit features an accurate internal 2.5 V reference

voltage (VREF) optimized to be ±2.4% accurate over the

temperature range.

OFF Mode

As previously mentioned, the circuit turns off when one

of the following faults is detected:

•Incorrect feeding of the circuit (“UVLO” high when

VCC < VCC(off), VCC(off) equating 9 V typically).

•Excessive die temperature detected by the thermal

shutdown.

•Brown-out Fault and SKIP (see block diagram)

•Output Under-voltage situation (when Vpin2 is lower

than 12% of VREF)

•UVP2 when Vpin1 is lower than 12% of VREF

(NCP1612A, NCP1612A1, NCP1612A3 and

NCP1612B only)

•Circuit latching-off produced either by pulling the

pfcOK pin above 7.5 V (NCP1612A, NCP1612A1,

NCP1612A3 and NCP1612B) or by triggering the fast

OVP comparator (NCP1612A2, NCP1612B2).

Generally speaking, the circuit turns off when the

conditions are not proper for desired operation. In this mode,

the controller stops operating. The major part of the circuit

sleeps and its consumption is minimized.

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Failure Detection

When manufacturing a power supply, elements can be

accidentally shorted or improperly soldered. Such failures

can also happen to occur later on because of the components

fatigue or excessive stress, soldering defaults or external

interactions. I n particular, adjacent pins of controllers can be

shorted, a pin can be grounded or badly connected. Such

open/short situations are generally required not to cause fire,

smoke nor big noise. The NCP1612 integrates functions that

ease meeting this requirement. Among them, we can list:

•Floating feedback pins

A 250 nA sink current source pulls down the voltage on

the feedback pin so that the UVP protection trips and

prevents the circuit from operating if this pin is

floating. This current source is small (450 nA

maximum) so that its impact on the output regulation

and OVP levels remain negligible with the resistor

dividers typically used to sense the bulk voltage.

•Fault of the GND connection

If the GND pin is properly connected, the supply

current drawn from the positive terminal of the VCC

capacitor, flows out of the GND pin to return to the

negative terminal of the VCC capacitor. If the GND pin

is not connected, the circuit ESD diodes offer another

return path. The accidental non connection of the GND

pin can hence be detected by detecting that one of this

ESD diode is conducting. Practically, the CS/ZCD ESD

diode is monitored. If such a fault is detected for

200 ms, the circuit stops operating.

•Detection the CS/ZCD pin improper connection

The CS/ZCD pin sources a 1 mA current to pull up the

pin voltage and hence disable the part if the pin is

floating. If the CS/ZCD pin is grounded, the circuit

cannot monitor the ZCD signal and the 200 ms

watchdog timer is activated. When the watchdog time

has elapsed, the circuit sources a 250 mA current source

to pull-up the CS/ZCD pin voltage. No drive pulse is

initiated until the CS/ZCD pin voltage exceeds the ZCD

0.75 V threshold. Hence, if the pin is grounded, the

circuit stops operating. Circuit operation requires the

pin impedance to be 3.9 kW or more, the tolerance of

the NCP1612 impedance testing function being

considered over the −40°C to 125°C temperature range.

•Boost or bypass diode short

The NCP1612 addresses the short situations of the

boost and bypass diodes (a bypass diode is generally

placed between the input and output high-voltage rails

to divert this inrush current). Practically, the overstress

protection is implemented to detect such conditions and

forces a low duty-cycle operation until the fault is gone.

Refer to application note AND9079/D for more details.

Table 5. ORDERING INFORMATION

Device Circuit Version Marking Package Shipping†

NCP1612ADR2G NCP1612A 1612A SOIC−10

(Pb−Free) 2500 / Tape & Reel

NCP1612A1DR2G NCP1612A1 1612A1 SOIC−10

(Pb−Free) 2500 / Tape & Reel

NCP1612A2DR2G NCP1612A2 1612A2 SOIC−10

(Pb−Free) 2500 / Tape & Reel

NCP1612A3DR2G NCP1612A3 1612A3 SOIC−10

(Pb−Free) 2500 / Tape & Reel

NCP1612BDR2G NCP1612B 1612B SOIC−10

(Pb−Free) 2500 / Tape & Reel

NCP1612B2DR2G* NCP1612B2 1612B2 SOIC−10

(Pb−Free) 2500 / Tape & Reel

*Please contact local sales representative for availability.

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS

SOIC−10 NB

CASE 751BQ

ISSUE B

SEATING

PLANE

610

X 45_

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’

AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15mm

PER SIDE. DIMENSIONS D AND E ARE DE-

TERMINED AT DATUM F.

5. DIMENSIONS A AND B ARE TO BE DETERM-

INED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

DIM

MIN MAX

4.80 5.00

MILLIMETERS

E3.80 4.00

A1.25 1.75

b0.31 0.51

e1.00 BSC

A1 0.10 0.25

A3 0.17 0.25

L0.40 0.80

M0 8

H5.80 6.20

0.25

DIMENSION: MILLIMETERS

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

h0.37 REF

L2 0.25 BSC

TOP VIEW

C0.20

2X 5 TIPS A-B D

C0.10 A-B

C0.10

b10X

C0.10

10X

SIDE VIEW END VIEW

DET AIL A

6.50

10X 1.18

10X 0.58 1.00

PITCH

RECOMMENDED

SEATING

PLANE

L2 A3

DETAIL A

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