© Semiconductor Components Industries, LLC, 2016
June, 2019 − Rev. 5
1Publication Order Number:
ESD7104/D
ESD7104
ESD Protection Diode
Low Capacitance ESD Protection Diode
for High Speed Data Line
The ESD7104 surge protection is designed to protect high speed
data lines from ESD. Ultra−low capacitance and low ESD clamping
voltage make this device an ideal solution for protecting voltage
sensitive high speed data lines. The flow−through style package
allows for easy PCB layout and matched trace lengths necessary to
maintain consistent impedance between high speed differential lines
such as USB 3.0 and HDMI.
Features
•Low Capacitance (0.3 pF Typical, I/O to GND)
•Low ESD Clamping Voltage
•Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
•UL Flammability Rating of 94 V−0
•SZESD7104MTWTAG − Wettable Flank Package for optimal
Automated Optical Inspection (AOI)
•SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•USB 3.0
•eSATA 3.0
•Thunderbolt (Light Peak)
•HDMI 1.3/1.4
•Display Port
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Operating Junction Temperature Range TJ−55 to +125 °C
Storage Temperature Range Tstg −55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15
±15
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
MARKING
DIAGRAM
UDFN10
CASE 517BB
PIN CONFIGURATION
AND SCHEMATIC
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7M MG
G
7M = Specific Device Code (tbd)
M = Date Code
G= Pb−Free Package
I/O I/O I/OI/O GND
N/C N/C N/C N/CGND
14523
10 7 698
(Note: Microdot may be in either location)
GND
Pin 2 Pin 4 Pin 5Pin 1
=
I/O I/O I/OI/O
Pin 3
See detailed ordering, marking and shipping information in the
package dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
WDFNW10
CASE 515AH XXX M
XX = Specific Device Code
M = Date Code
ESD7104
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2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM I/O Pin to GND 5.0 V
Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.5 V
Reverse Leakage Current IRVRWM = 5 V, I/O Pin to GND 1.0 mA
Clamping Voltage (Note 1) VCIPP = 1 A, I/O Pin to GND (8 x 20 ms pulse) 10 V
Clamping Voltage (Note 2) VCIEC61000−4−2, ±8 KV Contact See Figures 1 and 2 V
Clamping Voltage (Note 3) VCIPP = ±8 A
IPP = ±16 A
14.1
19.5
V
Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins 0.2 0.3 pF
Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins and GND 0.3 0.35 pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Surge current waveform per Figure 5.
2. For test procedure see Figures 3 and 4 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 − 2008 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
Figure 1. IEC61000−4−2 +8 KV Contact
Clamping Voltage
Figure 2. IEC61000−4−2 −8 KV Contact
Clamping Voltage
TIME (ns)
120100806040200−20
−10
0
10
20
30
40
50
60
VOLTAGE (V)
140
70
80
TIME (ns)
120100806040200−20
−80
−70
−60
−50
−40
−30
−20
−10
VOLTAGE (V)
140
0
10
ESD7104
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3
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Figure 4. Diagram of ESD Clamping Voltage Test Setup
50 W
Cable
Device
Under
Test Oscilloscope
ESD Gun
50 W
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 5. 8 x 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
tP
tr
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE IRSM @ 8 ms
HALF VALUE IRSM/2 @ 20 ms
ESD7104
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4
Figure 6. Positive TLP I−V Curve Figure 7. Negative TLP I−V Curve
CURRENT (A)
VOLTAGE (V)
CURRENT (A)
VOLTAGE (V)
14121086420
0
2
4
6
8
10
12
14
16
16
18
20
22
18 20
0
−2
−4
−6
−8
−10
−12
−14
−16
−18
−20
−22
22 24 −14−12−10−8−6−4−20 −16 −18 −20 −22 −2
4
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
Figure 8. Simplified Schematic of a Typical TLP
System
DUT
LS
÷
Oscilloscope
Attenuator
10 MW
VC
VM
IM
50 W Coax
Cable
50 W Coax
Cable
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ESD7104
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5
With ESD7104Without ESD
Figure 10. USB3.0 Eye Diagram with and without ESD7104. 5.0 Gb/s, 400 mVPP
With ESD7104Without ESD
Figure 11. HDMI1.4 Eye Diagram with and without ESD7104. 3.4 Gb/s, 400 mVPP
With ESD7104Without ESD
Figure 12. ESATA3.0 Eye Diagram with and without ESD7104. 6 Gb/s, 400 mVPP
ESD7104
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7
Figure 14. USB3.0 Standard A Connector Layout Diagram
Vbus
StdA_SSTX+
D−
StdA_SSTX−
D+
GND_DRAIN
GND
StdA_SSRX+
StdA_SSRX−
USB 3.0 Type A
Connector
ESD7104
ESD7L5.0
Figure 15. USB3.0 Micro B Connector Layout Diagram
D−
Vbus
ID
D+
MicB_SSTX−
GND
GND_DRAIN
MicB_SSTX+
MicB_SSRX−
USB 3.0 Micro B
Connector
MicB_SSRX+
ESD7104
ESD7104
ESD7104
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9
DEVICE ORDERING INFORMATION
Device Marking Package Shipping†
ESD7104MUTAG 7M UDFN10
(Pb−Free)
3000 / Tape & Reel
SZESD7104MUTAG 7M UDFN10
(Pb−Free)
3000 / Tape & Reel
SZESD7104MTWTAG
(In Development)
TBD WDFNW10
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ESD7104
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10
PACKAGE DIMENSIONS
UDFN10 2.5 x 1, 0.5P
CASE 517BB
ISSUE O
ÍÍÍ
ÍÍÍ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
CSEATING
PLANE
DB
E
0.10 C
A3 A
A1
2X
2X 0.10 C
DIM
A
MIN
MILLIMETERS
0.45
A1 0.00
A3 0.13 REF
b0.15
D2.50 BSC
b2 0.35
E1.00 BSC
e0.50 BSC
PIN ONE
REFERENCE
0.08 C
0.10 C
10X
A0.10 C
NOTE 3
L
e
b2
b
B
5
6
8X
1
10
10X
0.05 C
0.30
L
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
0.45
0.50
DIMENSIONS: MILLIMETERS
1.30
PITCH
0.25
10X
0.55
0.05
0.25
0.45
0.40
MAX
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÉÉÉ
A1
A3
DETAIL B
MOLD CMPD
EXPOSED Cu
OPTIONAL
CONSTRUCTION
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
---
L1 0.05
TOP VIEW
SIDE VIEW
BOTTOM VIEW
DETAIL B
DETAIL A
OUTLINE
PACKAGE
A
2X
RECOMMENDED
2X
8X
ESD7104
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11
PACKAGE DIMENSIONS
WDFNW10 2.5x1.0, 0.5P
CASE 515AH
ISSUE O
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Phone: 421 33 790 2910
ESD7104/D
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