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    
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February 2003 1394 Host Controller Solutions
Data Manual
SLLS450A
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
iii
Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Related Documents 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Trademarks 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Ordering Information 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 TSB43AB23 1394 OHCI Controller Programming Model 3–1. . . . . . . . . . . . . .
3.1 PCI Configuration Registers 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Vendor ID Register 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Device ID Register 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Command Register 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Status Register 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Class Code and Revision ID Register 36. . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Latency Timer and Class Cache Line Size Register 36. . . . . . . . . . . . . .
3.8 Header Type and BIST Register 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 OHCI Base Address Register 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 TI Extension Base Address Register 38. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Subsystem Identification Register 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Power Management Capabilities Pointer Register 39. . . . . . . . . . . . . . .
3.13 Interrupt Line and Pin Register 310. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 MIN_GNT and MAX_LAT Register 310. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15 OHCI Control Register 311. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16 Capability ID and Next Item Pointer Registers 311. . . . . . . . . . . . . . . . . . .
3.17 Power Management Capabilities Register 312. . . . . . . . . . . . . . . . . . . . . .
3.18 Power Management Control and Status Register 313. . . . . . . . . . . . . . . .
3.19 Power Management Extension Registers 313. . . . . . . . . . . . . . . . . . . . . . .
3.20 PCI PHY Control Register 314. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.21 Miscellaneous Configuration Register 315. . . . . . . . . . . . . . . . . . . . . . . . . .
3.22 Link Enhancement Control Register 316. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.23 Subsystem Access Register 317. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.24 GPIO Control Register 318. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 OHCI Registers 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 OHCI Version Register 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 GUID ROM Register 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Asynchronous Transmit Retries Register 46. . . . . . . . . . . . . . . . . . . . . . .
4.4 CSR Data Register 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
4.5 CSR Compare Register 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 CSR Control Register 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Configuration ROM Header Register 48. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Bus Identification Register 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Bus Options Register 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 GUID High Register 410. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 GUID Low Register 410. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 Configuration ROM Mapping Register 411. . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Posted Write Address Low Register 411. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Posted Write Address High Register 412. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 Vendor ID Register 412. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 Host Controller Control Register 413. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Self-ID Buffer Pointer Register 414. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 Self-ID Count Register 415. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Isochronous Receive Channel Mask High Register 416. . . . . . . . . . . . . .
4.20 Isochronous Receive Channel Mask Low Register 417. . . . . . . . . . . . . . .
4.21 Interrupt Event Register 418. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 Interrupt Mask Register 420. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Isochronous Transmit Interrupt Event Register 422. . . . . . . . . . . . . . . . . .
4.24 Isochronous Transmit Interrupt Mask Register 423. . . . . . . . . . . . . . . . . . .
4.25 Isochronous Receive Interrupt Event Register 423. . . . . . . . . . . . . . . . . . .
4.26 Isochronous Receive Interrupt Mask Register 424. . . . . . . . . . . . . . . . . . .
4.27 Initial Bandwidth Available Register 424. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 Initial Channels Available High Register 425. . . . . . . . . . . . . . . . . . . . . . . .
4.29 Initial Channels Available Low Register 425. . . . . . . . . . . . . . . . . . . . . . . . .
4.30 Fairness Control Register 426. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 Link Control Register 427. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 Node Identification Register 428. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.33 PHY Layer Control Register 429. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.34 Isochronous Cycle Timer Register 430. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.35 Asynchronous Request Filter High Register 431. . . . . . . . . . . . . . . . . . . . .
4.36 Asynchronous Request Filter Low Register 433. . . . . . . . . . . . . . . . . . . . .
4.37 Physical Request Filter High Register 434. . . . . . . . . . . . . . . . . . . . . . . . . .
4.38 Physical Request Filter Low Register 436. . . . . . . . . . . . . . . . . . . . . . . . . .
4.39 Physical Upper Bound Register (Optional Register) 436. . . . . . . . . . . . . .
4.40 Asynchronous Context Control Register 437. . . . . . . . . . . . . . . . . . . . . . . .
4.41 Asynchronous Context Command Pointer Register 438. . . . . . . . . . . . . .
4.42 Isochronous Transmit Context Control Register 439. . . . . . . . . . . . . . . . . .
4.43 Isochronous Transmit Context Command Pointer Register 440. . . . . . . .
4.44 Isochronous Receive Context Control Register 440. . . . . . . . . . . . . . . . . .
4.45 Isochronous Receive Context Command Pointer Register 442. . . . . . . .
4.46 Isochronous Receive Context Match Register 443. . . . . . . . . . . . . . . . . . .
5 TI Extension Registers 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 DV and MPEG2 Timestamp Enhancements 51. . . . . . . . . . . . . . . . . . . . .
v
5.2 Isochronous Receive Digital Video Enhancements 52. . . . . . . . . . . . . . .
5.3 Isochronous Receive Digital Video Enhancements Register 52. . . . . . .
5.4 Link Enhancement Register 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Timestamp Offset Register 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Serial EEPROM Interface 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 PHY Register Configuration 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Base Registers 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Port Status Register 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Vendor Identification Register 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Vendor-Dependent Register 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Power-Class Programming 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Application Information 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 PHY Port Cable Connection 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Crystal Selection 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Bus Reset 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 EMI Guidelines 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Electrical Characteristics 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 Absolute Maximum Ratings Over Operating Temperature Ranges 91.
9.2 Recommended Operating Conditions 92. . . . . . . . . . . . . . . . . . . . . . . . . .
9.3 Electrical Characteristics Over Recommended
Operating Conditions 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4 Electrical Characteristics Over Recommended Ranges of
Operating Conditions 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1 Device 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2 Driver 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.3 Receiver 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5 Thermal Characteristics 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6 Switching Characteristics for PHY Port Interface 95. . . . . . . . . . . . . . . . .
9.7 Operating, Timing, and Switching Characteristics of XI 95. . . . . . . . . . .
9.8 Switching Characteristics for PCI Interface 95. . . . . . . . . . . . . . . . . . . . . .
10 Mechanical Information 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
List of Illustrations
Figure Title Page
21 PDT Package Terminal Assignments 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22 PGE Package Terminal Assignments 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31 TSB43AB23 Block Diagram 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81 TP Cable Connections 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82 Typical Compliant DC Isolated Outer Shield Termination 82. . . . . . . . . . . . .
83 Non-DC Isolated Outer Shield Termination 82. . . . . . . . . . . . . . . . . . . . . . . . .
84 Load Capacitance for the TSB43AB23 PHY 83. . . . . . . . . . . . . . . . . . . . . . . .
85 Recommended Crystal and Capacitor Layout 83. . . . . . . . . . . . . . . . . . . . . . .
91 Test Load Diagram 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
List of Tables
Table Title Page
21 PDT Package Signals Sorted by Terminal Number 24. . . . . . . . . . . . . . . . . .
22 PGE Package Signals Sorted by Terminal Number 25. . . . . . . . . . . . . . . . . .
23 Signal Names Sorted Alphanumerically to Terminal Number 26. . . . . . . . . .
24 PCI System Terminals 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25 PCI Address and Data Terminals 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26 PCI Interface Control Terminals 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27 Miscellaneous Terminals 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 Physical Layer Terminals 210. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29 Power Supply Terminals 211. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31 Bit Field Access Tag Descriptions 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32 PCI Configuration Register Map 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33 Command Register Description 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34 Status Register Description 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35 Class Code and Revision ID Register Description 36. . . . . . . . . . . . . . . . . . .
36 Latency Timer and Class Cache Line Size Register Description 36. . . . . . .
37 Header Type and BIST Register Description 37. . . . . . . . . . . . . . . . . . . . . . . .
38 OHCI Base Address Register Description 37. . . . . . . . . . . . . . . . . . . . . . . . . .
39 TI Base Address Register Description 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
310 Subsystem Identification Register Description 39. . . . . . . . . . . . . . . . . . . . . .
311 Interrupt Line and Pin Registers Description 310. . . . . . . . . . . . . . . . . . . . . . . .
312 MIN_GNT and MAX_LAT Register Description 310. . . . . . . . . . . . . . . . . . . . .
313 OHCI Control Register Description 311. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
314 Capability ID and Next Item Pointer Registers Description 311. . . . . . . . . . . .
315 Power Management Capabilities Register Description 312. . . . . . . . . . . . . . .
316 Power Management Control and Status Register Description 313. . . . . . . . .
317 Power Management Extension Registers Description 313. . . . . . . . . . . . . . . .
318 PCI PHY Control Register 314. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
319 Miscellaneous Configuration Register 315. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
320 Link Enhancement Control Register Description 316. . . . . . . . . . . . . . . . . . . .
321 Subsystem Access Register Description 317. . . . . . . . . . . . . . . . . . . . . . . . . . .
322 General-Purpose Input/Output Control Register Description 318. . . . . . . . . .
41 OHCI Register Map 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42 OHCI Version Register Description 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43 GUID ROM Register Description 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44 Asynchronous Transmit Retries Register Description 46. . . . . . . . . . . . . . . .
45 CSR Control Register Description 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46 Configuration ROM Header Register Description 48. . . . . . . . . . . . . . . . . . . .
viii
47 Bus Options Register Description 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48 Configuration ROM Mapping Register Description 411. . . . . . . . . . . . . . . . . . .
49 Posted Write Address Low Register Description 411. . . . . . . . . . . . . . . . . . . .
410 Posted Write Address High Register Description 412. . . . . . . . . . . . . . . . . . . .
411 Host Controller Control Register Description 413. . . . . . . . . . . . . . . . . . . . . . . .
412 Self-ID Count Register Description 415. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
413 Isochronous Receive Channel Mask High Register Description 416. . . . . . .
414 Isochronous Receive Channel Mask Low Register Description 417. . . . . . . .
415 Interrupt Event Register Description 418. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
416 Interrupt Mask Register Description 420. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
417 Isochronous Transmit Interrupt Event Register Description 422. . . . . . . . . . .
418 Isochronous Receive Interrupt Event Register Description 423. . . . . . . . . . .
419 Initial Bandwidth Available Register Description 424. . . . . . . . . . . . . . . . . . . . .
420 Initial Channels Available High Register Description 425. . . . . . . . . . . . . . . . .
421 Initial Channels Available Low Register Description 425. . . . . . . . . . . . . . . . .
422 Fairness Control Register Description 426. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
423 Link Control Register Description 427. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
424 Node Identification Register Description 428. . . . . . . . . . . . . . . . . . . . . . . . . . .
425 PHY Control Register Description 429. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
426 Isochronous Cycle Timer Register Description 430. . . . . . . . . . . . . . . . . . . . . .
427 Asynchronous Request Filter High Register Description 431. . . . . . . . . . . . .
428 Asynchronous Request Filter Low Register Description 433. . . . . . . . . . . . . .
429 Physical Request Filter High Register Description 434. . . . . . . . . . . . . . . . . . .
430 Physical Request Filter Low Register Description 436. . . . . . . . . . . . . . . . . . .
431 Asynchronous Context Control Register Description 437. . . . . . . . . . . . . . . . .
432 Asynchronous Context Command Pointer Register Description 438. . . . . . .
433 Isochronous Transmit Context Control Register Description 439. . . . . . . . . .
434 Isochronous Receive Context Control Register Description 440. . . . . . . . . . .
435 Isochronous Receive Context Match Register Description 443. . . . . . . . . . . .
51 TI Extension Register Map 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52 Isochronous Receive Digital Video Enhancements Register Description 52
53 Link Enhancement Register Description 54. . . . . . . . . . . . . . . . . . . . . . . . . . .
54 Timestamp Offset Register Description 55. . . . . . . . . . . . . . . . . . . . . . . . . . . .
61 Registers and Bits Loadable Through Serial EEPROM 61. . . . . . . . . . . . . . .
62 Serial EEPROM Map 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71 Base Register Configuration 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72 Base Register Field Descriptions 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73 Page 0 (Port Status) Register Configuration 74. . . . . . . . . . . . . . . . . . . . . . . .
74 Page 0 (Port Status) Register Field Descriptions 74. . . . . . . . . . . . . . . . . . . .
75 Page 1 (Vendor ID) Register Configuration 75. . . . . . . . . . . . . . . . . . . . . . . . .
76 Page 1 (Vendor ID) Register Field Descriptions 75. . . . . . . . . . . . . . . . . . . . .
77 Page 7 (Vendor-Dependent) Register Configuration 76. . . . . . . . . . . . . . . . .
78 Page 7 (Vendor-Dependent) Register Field Descriptions 76. . . . . . . . . . . . .
79 Power Class Descriptions 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
1 Introduction
This chapter provides an overview of the Texas Instruments TSB43AB23 device and its features.
1.1 Description
The T exas Instruments TSB43AB23 device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device
that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification
(Revision 1.1), IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface
Specification (Release 1.1). It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at
100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB23 device provides three 1394 ports that have separate
cable bias (TPBIAS). The TSB43AB23 device also supports the IEEE Std 1394a-2000 power-down features for
battery-operated applications and arbitration enhancements.
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal
control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through
configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the
TSB43AB23 device is compliant with the PCI Bus Power Management Interface Specification as specified by the
PC 2001 Design Guide requirements. The TSB43AB23 device supports the D0, D1, D2, and D3 power states.
The TSB43AB23 design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at
132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided
to buffer the 1394 data.
The TSB43AB23 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2
performance. The TSB43AB23 device also provides multiple isochronous contexts, multiple cacheline burst
transfers, and advanced internal arbitration.
An advanced CMOS process achieves low power consumption and allows the TSB43AB23 device to operate at PCI
clock rates up to 33 MHz.
The TSB43AB23 PHY-layer provides the digital and analog transceiver functions needed to implement a three-port
node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers
include circuitry to monitor the line conditions as needed for determining connection status, for initialization and
arbitration, and for packet reception and transmission.
The TSB43AB23 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An
external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL),
which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the
clock signals that control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock
signal is supplied to the integrated LLC for synchronization and is used for resynchronization of the received data.
Data bits to be transmitted through the cable ports are received from the integrated LLC and are latched internally
in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted
at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or S400 speeds, respectively) as the outbound
data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the
twisted-pair B (TPB) cable pair(s), and the encoded strobe information is transmitted differentially on the twisted-pair
A (TPA) cable pair(s).
During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe
information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive
clock signal and the serial data bits. The serial data bits are resynchronized to the local 49.152-MHz system clock
and sent to the integrated LLC. The received data is also transmitted (repeated) on the other active (connected) cable
ports.
12
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the
TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely
supplied twisted-pair bias voltage.
The TSB43AB23 device provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY
layer contains two independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver ,
indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter
capacitor of 1.0 µF.
The line drivers in the TSB43AB23 device operate in a high-impedance current mode and are designed to work with
external 112- line-termination resistor networks in order to match the 110- cable impedance. One network is
provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56- resistors.
The midpoint of the pair of resistors that is directly connected to the TP A terminals is connected to its corresponding
TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the TPB terminals is
coupled to ground through a parallel R-C network with recommended values of 5 k and 220 pF. The values of the
external line-termination resistors are designed to meet the standard specifications when connected in parallel with
the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output
current and other internal operating currents. This current-setting resistor has a value of 6.34 k ±1%.
When the power supply of the TSB43AB23 device is off and the twisted-pair cables are connected, the TSB43AB23
transmitter and receiver circuitry present a high impedance to the cable and do not load the TPBIAS voltage at the
other end of the cable.
When the device is in a low-power state (for example, D2 or D3) the TSB43AB23 device automatically enters a
low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB43AB23 device disables its internal clock generators and also disables various voltage and current reference
circuits, depending on the state of the ports (some reference circuitry must remain active in order to detect new cable
connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the ultralow-power
sleep mode) is attained when all ports are either disconnected or disabled with the port interrupt enable bit cleared.
The TSB43AB23 device exits the low-power mode when bit 19 (LPS) in the host controller control register at OHCI
offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1 or when a port event occurs which
requires that the TSB43AB23 device to become active in order to respond to the event or to notify the LLC of the event
(for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, or
a new connection is detected on a nondisabled port). When the TSB43AB23 device is in the low-power mode, the
internal 49.153-MHz clock becomes active (and the integrated PHY layer becomes operative) within 2 ms after bit 19
(LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control
Register) is set to 1.
The TSB43AB23 device supports hardware enhancements to better support digital video (DV) and MPEG data
stream reception and transmission. These enhancements are enabled through the isochronous receive digital video
enhancements register at OHCI offset A88h (see Chapter 5, TI Extension Registers). The enhancements include
automatic timestamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet
(CIP) header stripping for received DV streams.
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data
contexts are implemented as hardware support for the synchronization timestamp for both DV and MPEG CIP
formats. The TSB43AB23 device supports modification of the synchronization timestamp field to ensure that the
value inserted via software is not stalethat is, the value is less than the current cycle timer when the packet is
transmitted.
13
1.2 Features
The TSB43AB23 device supports the following features:
Fully compliant with 1394 Open Host Controller Interface Specification (Release 1.1)
Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std
1394a-2000
Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394
Compliant with Intel Mobile Power Guideline 2000
Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed
concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
Power-down features to conserve energy in battery-powered applications include: automatic device power
down during suspend, PCI power management for link-layer, and inactive ports powered down
Ultralow-power sleep mode
Three IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
Cable ports monitor line conditions for active connection to remote node
Cable power presence monitoring
Separate cable bias (TPBIAS) for each port
1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
Physical write posting of up to three outstanding transactions
PCI burst transfers and deep FIFOs to tolerate large host latency
PCI_CLKRUN protocol
External cycle timer control for customized synchronization
Extended resume signaling for compatibility with legacy DV components
PHY-link logic performs system initialization and arbitration functions
PHY-link encode and decode functions included for data-strobe bit level encoding
PHY-link incoming data resynchronized to local clock
Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and
400M bits/s
Node power class information signaling for system power management
Serial ROM interface supports 2-wire serial EEPROM devices
Two general-purpose I/Os
Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std
1394a-2000 features
Fabricated in advanced low-power CMOS process
Isochronous receive dual-buffer mode
Out-of-order pipelining for asynchronous transmit requests
Register access fail interrupt when the PHY SCLK is not active
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
14
PCI power-management D0, D1, D2, and D3 power states
Initial bandwidth available and initial channels available registers
PME support per 1394 Open Host Controller Interface Specification
1.3 Related Documents
1394 Open Host Controller Interface Specification (Release 1.1)
IEEE Standard for a High Performance Serial Bus (IEEE Std 1394-1995)
IEEE Standard for a High Performance Serial Bus—Amendment 1 (IEEE Std 1394a-2000)
PC Card Standard—Electrical Specification
PC 2001 Design Guide
PCI Bus Power Management Interface Specification (Revision 1.1)
PCI Local Bus Specification (Revision 2.2)
Mobile Power Guideline 2000
Serial Bus Protocol 2 (SBP-2)
IEC 61883-1:1998 Consumer Audio/Video Equipment Digital Interface Part 1: General
1.4 Trademarks
iOHCI-Lynx and TI are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
1.5 Ordering Information
ORDERING NUMBER NAME VOLTAGE PACKAGE
TSB43AB23PDT iOHCI-Lynx 3.3 V PDT
TSB43AB23PGE iOHCI-Lynx 3.3 V PGE
21
2 Terminal Descriptions
This section provides the terminal descriptions for the TSB43AB23 device. Figure 22 shows the signal assigned to
each terminal in the package. T able 21 and Table 23 provide a cross-reference between each terminal number and
the signal name on that terminal. Table 21 is arranged in terminal number order, and Table 23 lists signals in
alphabetical order.
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
101
102
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
99
100
62
30 67
TSB43AB23
32
31
63
64 97
98
66
65
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
TPBIAS2
TPA2+
TPA2
AVDD
TPB2+
TPB2
AVDD
AGND
TPBIAS1
TPA1+
TPA1
AVDD
AGND
TPB1+
TPB1
AVDD
AGND
TPBIAS0
TPA0+
TPA0
AGND
TPB0+
TPB0
AGND
AVDD
AGND
AVDD
CPS
PHY_TEST_MA
CNA
DGND
DVDD
DGND
PCI_C/BE3
VDDP
PCI_IDSEL
PCI_AD23
PCI_AD22
DVDD
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
DGND
PCI_AD17
PCI_AD16
PCI_C/BE2
VDDP
PCI_FRAME
PCI_IRDY
DVDD
PCI_TRDY
PCI_DEVSEL
PCI_STOP
DGND
PCI_PERR
PCI_SERR
PCI_PAR
DVDD
PCI_C/BE1
PCI_AD15
VDDP
PCI_AD14
DGND
PCI_AD24
PCI_AD25
REG18
PCI_AD26
PCI_AD27
DVDD
PCI_AD28
PCI_AD29
PCI_AD30
DGND
PCI_AD31
PCI_PME
VDDP
PCI_REQ
PCI_GNT
DGND
PCI_PCLK
DVDD
G_RST
PCI_INTA
PCI_CLKRUN
REG_EN
XO
XI
PLLGND
PLLVDD
FILTER1
FILTER0
R0
R1
AVDD
AGND
PCI_AD13
PCI_AD12
PCI_AD11
DGND
PCI_AD10
PCI_AD9
PCI_AD8
DVDD
PCI_C/BE0
PCI_AD7
DGND
PCI_AD6
PCI_AD5
VDDP
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
DGND
PCI_AD0
PCI_RST
CYCLEOUT
CYCLEIN
DVDD
GPIO3/TEST1
GPIO2/TEST0
SCL
SDA
REG18
PC2
PC1
PC0
PDT PACKAGE
(TOP VIEW)
Figure 21. PDT Package Terminal Assignments
23
NC
NC
AGND
AVDD
R1
R0
FILTER0
FILTER1
PLLVDD
PLLGND
XI
XO
REG_EN
PCI_CLKRUN
PCI_INTA
G_RST
DVDD
PCI_PCLK
DGND
PCI_GNT
PCI_REQ
VDDP
PCI_PME
PCI_AD31
DGND
PCI_AD30
PCI_AD29
PCI_AD28
DVDD
PCI_AD27
PCI_AD26
REG18
PCI_AD25
PCI_AD24
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
PGE PACKAGE
(TOP VIEW)
NC
NC
TPBIAS2
TPA2+
TPA2
AVDD
TPB2+
TPB2
AVDD
AGND
TPBIAS1
TPA1+
TPA1
AVDD
AGND
TPB1+
TPB1
AVDD
AGND
TPBIAS0
TPA0+
TPA0
AGND
TPB0+
TPB0
AGND
AVDD
AGND
AVDD
CPS
PHY_TEST_MA
CNA
DGND
DVDD
NC
NC
NC
NC
PC0
PC1
PC2
REG18
SDA
SCL
GPIO2/TEST0
GPIO3/TEST1
DVDD
CYCLEIN
CYCLEOUT
PCI_RST
PCI_AD0
DGND
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
VDDP
PCI_AD5
PCI_AD6
DGND
PCI_AD7
PCI_C/BE0
DVDD
PCI_AD8
PCI_AD9
PCI_AD10
DGND
PCI_AD11
PCI_AD12
PCI_AD13
NC
NC
NC
NC
DGND
PCI_C/BE3
VDDP
PCI_IDSEL
PCI_AD23
PCI_AD22
DVDD
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
DGND
PCI_AD17
PCI_AD16
PCI_C/BE2
VDDP
PCI_FRAME
PCI_IRDY
DVDD
PCI_TRDY
PCI_DEVSEL
PCI_STOP
DGND
PCI_PERR
PCI_SERR
PCI_PAR
DVDD
PCI_C/BE1
PCI_AD15
VDDP
PCI_AD14
DGND
NC
NC
TSB43AB23
Figure 22. PGE Package Terminal Assignments
24
Table 21. PDT Package Signals Sorted by Terminal Number
NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME
1 DGND 33 PCI_AD13 65 DVDD 97 AGND
2 PCI_C/BE3 34 PCI_AD12 66 DGND 98 AVDD
3 VDDP 35 PCI_AD11 67 CNA 99 R1
4 PCI_IDSEL 36 DGND 68 PHY_TEST_MA 100 R0
5 PCI_AD23 37 PCI_AD10 69 CPS 101 FILTER0
6 PCI_AD22 38 PCI_AD9 70 AVDD 102 FILTER1
7 DVDD 39 PCI_AD8 71 AGND 103 PLLVDD
8 PCI_AD21 40 DVDD 72 AVDD 104 PLLGND
9 PCI_AD20 41 PCI_C/BE0 73 AGND 105 XI
10 PCI_AD19 42 PCI_AD7 74 TPB0106 XO
11 PCI_AD18 43 DGND 75 TPB0+ 107 REG_EN
12 DGND 44 PCI_AD6 76 AGND 108 PCI_CLKRUN
13 PCI_AD17 45 PCI_AD5 77 TPA0109 PCI_INTA
14 PCI_AD16 46 VDDP 78 TPA0+ 110 G_RST
15 PCI_C/BE2 47 PCI_AD4 79 TPBIAS0 111 DVDD
16 VDDP 48 PCI_AD3 80 AGND 112 PCI_PCLK
17 PCI_FRAME 49 PCI_AD2 81 AVDD 113 DGND
18 PCI_IRDY 50 PCI_AD1 82 TPB1114 PCI_GNT
19 DVDD 51 DGND 83 TPB1+ 115 PCI_REQ
20 PCI_TRDY 52 PCI_AD0 84 AGND 116 VDDP
21 PCI_DEVSEL 53 PCI_RST 85 AVDD 117 PCI_PME
22 PCI_STOP 54 CYCLEOUT 86 TPA1118 PCI_AD31
23 DGND 55 CYCLEIN 87 TPA1+ 119 DGND
24 PCI_PERR 56 DVDD 88 TPBIAS1 120 PCI_AD30
25 PCI_SERR 57 GPIO3/TEST1 89 AGND 121 PCI_AD29
26 PCI_PAR 58 GPIO2/TEST0 90 AVDD 122 PCI_AD28
27 DVDD 59 SCL 91 TPB2123 DVDD
28 PCI_C/BE1 60 SDA 92 TPB2+ 124 PCI_AD27
29 PCI_AD15 61 REG18 93 AVDD 125 PCI_AD26
30 VDDP 62 PC2 94 TPA2126 REG18
31 PCI_AD14 63 PC1 95 TPA2+ 127 PCI_AD25
32 DGND 64 PC0 96 TPBIAS2 128 PCI_AD24
25
Table 22. PGE Package Signals Sorted by Terminal Number
NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME
1 NC 37 NC 73 NC 109 NC
2 NC 38 NC 74 NC 110 NC
3 DGND 39 PCI_AD13 75 DVDD 111 AGND
4 PCI_C/BE3 40 PCI_AD12 76 DGND 112 AVDD
5 VDDP 41 PCI_AD11 77 CNA 113 R1
6 PCI_IDSEL 42 DGND 78 PHY_TEST_MA 114 R0
7 PCI_AD23 43 PCI_AD10 79 CPS 115 FILTER0
8 PCI_AD22 44 PCI_AD9 80 AVDD 116 FILTER1
9 DVDD 45 PCI_AD8 81 AGND 117 PLLVDD
10 PCI_AD21 46 DVDD 82 AVDD 118 PLLGND
11 PCI_AD20 47 PCI_C/BE0 83 AGND 119 XI
12 PCI_AD19 48 PCI_AD7 84 TPB0120 XO
13 PCI_AD18 49 DGND 85 TPB0+ 121 REG_EN
14 DGND 50 PCI_AD6 86 AGND 122 PCI_CLKRUN
15 PCI_AD17 51 PCI_AD5 87 TPA0123 PCI_INTA
16 PCI_AD16 52 VDDP 88 TPA0+ 124 G_RST
17 PCI_C/BE2 53 PCI_AD4 89 TPBIAS0 125 DVDD
18 VDDP 54 PCI_AD3 90 AGND 126 PCI_PCLK
19 PCI_FRAME 55 PCI_AD2 91 AVDD 127 DGND
20 PCI_RDY 56 PCI_AD1 92 TPB1128 PCI_GNT
21 DVDD 57 DGND 93 TPB1+ 129 PCI_REQ
22 PCI_TRDY 58 PCI_AD0 94 AGND 130 VDDP
23 PCI_DEVSEL 59 PCI_RST 95 AVDD 131 PCI_PME
24 PCI_STOP 60 CYCLEOUT 96 TPA1132 PCI_AD31
25 DGND 61 CYCLEIN 97 TPA1+ 133 DGND
26 PCI_PERR 62 DVDD 98 TPBIAS1 134 PCI_AD30
27 PCI_SERR 63 GPIO3/TEST1 99 AGND 135 PCI_AD29
28 PCI_PAR 64 GPIO2/TEST0 100 AVDD 136 PCI_AD28
29 DVDD 65 SCL 101 TPB2137 DVDD
30 PCI_C/BE1 66 SDA 102 TPB2+ 138 PCI_AD27
31 PCI_AD15 67 REG18 103 AVDD 139 PCI_AD26
32 VDDP 68 PC2 104 TPA2140 REG18
33 PCI_AD14 69 PC1 105 TPA2+ 141 PCI_AD25
34 DGND 70 PC0 106 TPBIAS2 142 PCI_AD24
35 NC 71 NC 107 NC 143 NC
36 NC 72 NC 108 NC 144 NC
26
Table 23. Signal Names Sorted Alphanumerically to Terminal Number
TERMINAL
NAME PDT
NO. PGE
NO. TERMINAL
NAME PDT
NO. PGE-
NO. TERMINAL
NAME PDT
NO. PGE-
NO. TERMINAL
NAME PDT
NO. PGE-
NO.
AGND 71 81 DVDD 56 62 PCI_AD23 5 7 PHY_TEST_MA 68 78
AGND 73 83 DVDD 65 75 PCI_AD24 128 142 PLLGND 104 118
AGND 76 86 DVDD 111 125 PCI_AD25 127 141 PLLVDD 103 117
AGND 80 90 DVDD 123 137 PCI_AD26 125 139 REG18 61 67
AGND 84 94 FILTER0 101 115 PCI_AD27 124 138 REG18 126 140
AGND 89 99 FILTER1 102 116 PCI_AD28 122 136 REG_EN 107 121
AGND 97 111 GPIO2/TEST0 58 64 PCI_AD29 121 135 R1 99 113
AVDD 70 80 GPIO3/TEST1 57 63 PCI_AD30 120 134 R0 100 114
AVDD 72 82 G_RST 110 124 PCI_AD31 118 132 SCL 59 65
AVDD 81 91 PCI_AD0 52 58 PCI_C/BE0 41 47 SDA 60 66
AVDD 85 95 PCI_AD1 50 56 PCI_C/BE1 28 30 TPA077 87
AVDD 90 100 PCI_AD2 49 55 PCI_C/BE2 15 17 TPA0+ 78 88
AVDD 93 103 PCI_AD3 48 54 PCI_C/BE3 2 4 TPA186 96
AVDD 98 112 PCI_AD4 47 53 PCI_CLKRUN 108 122 TPA1+ 87 97
CNA 67 77 PCI_AD5 45 51 PCI_DEVSEL 21 23 TPA294 104
CPS 69 79 PCI_AD6 44 50 PCI_FRAME 17 19 TPA2+ 95 105
CYCLEIN 55 61 PCI_AD7 42 48 PCI_GNT 114 128 TPBIAS0 79 89
CYCLEOUT 54 60 PCI_AD8 39 45 PCI_IDSEL 4 6 TPBIAS1 88 98
DGND 1 3 PCI_AD9 38 44 PCI_INTA 109 123 TPBIAS2 96 106
DGND 12 14 PCI_AD10 37 43 PCI_IRDY 18 20 TPB074 84
DGND 23 25 PCI_AD11 35 41 PCI_PAR 26 28 TPB0+ 75 85
DGND 32 34 PCI_AD12 34 40 PCI_PCLK 112 126 TPB182 92
DGND 36 42 PCI_AD13 33 39 PCI_PERR 24 26 TPB1+ 83 93
DGND 43 49 PCI_AD14 31 33 PCI_PME 117 131 TPB291 101
DGND 51 57 PCI_AD15 29 31 PCI_REQ 115 129 TPB2+ 92 102
DGND 66 76 PCI_AD16 14 16 PCI_RST 53 59 VDDP 3 5
DGND 113 127 PCI_AD17 13 15 PCI_SERR 25 27 VDDP 16 18
DGND 119 133 PCI_AD18 11 13 PCI_STOP 22 24 VDDP 30 32
DVDD 7 9 PCI_AD19 10 12 PCI_TRDY 20 22 VDDP 46 52
DVDD 19 21 PCI_AD20 9 11 PC0 64 70 VDDP 116 130
DVDD 27 29 PCI_AD21 8 10 PC1 63 69 XI 105 119
DVDD 40 46 PCI_AD22 6 8 PC2 62 68 XO 106 120
27
The terminals are grouped in tables by functionality, such as PCI system function and power supply function (see
Table 24 through Table 29). The terminal numbers are also listed for convenient reference.
Table 24. PCI System Terminals
TERMINAL
NAME PDT
NO. PGE
NO. I/O DESCRIPTION
G_RST 110 124 I
Global power reset. This reset brings all of the TSB43AB23 internal registers to their default states,
including those registers not reset by PCI_RST. When G_RST is asserted, the device is completely
nonfunctional, placing all output buf fers in a high impedance state.
When implementing wake capabilities from the 1394 host controller , it is necessary to implement two
resets to the TSB43AB23 device. G_RST is designed to be a one-time power-on reset, and PCI_RST
must be connected to the PCI bus RST. G_RST must be asserted for a minimum of 2 ms.
PCI_PCLK 112 126 I PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at the
rising edge of PCI_CLK.
PCI_INTA 109 123 O Interrupt signal. This output indicates interrupts from the TSB43AB23 device to the host. This terminal
is implemented as open-drain.
PCI_RST 53 59 I
PCI reset. When this bus reset is asserted, the TSB43AB23 device places all output buffers in a
high-impedance state and resets all internal registers except device power management context- and
vendor-specific bits initialized by host power-on software. When PCI_RST is asserted, the device is
completely nonfunctional. Connect this terminal to PCI bus RST.
Table 25. PCI Address and Data Terminals
TERMINAL
NAME PDT
NO. PGE
NO. I/O DESCRIPTION
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
118
120
121
122
124
125
127
128
5
6
8
9
10
11
13
14
29
31
33
34
35
37
38
39
42
44
45
47
48
49
50
52
132
134
135
136
138
139
141
142
7
8
10
11
12
13
15
16
31
33
39
40
41
43
44
45
48
50
51
53
54
55
56
58
I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI
interface. During the address phase of a PCI cycle, AD31AD0 contain a 32-bit address or other
destination information. During the data phase, AD31AD0 contain data.
28
Table 26. PCI Interface Control Terminals
TERMINAL
NAME PDT
NO. PGE
NO. I/O DESCRIPTION
PCI_CLKRUN 108 122 I/O
Clock run. This terminal provides clock control through the CLKRUN protocol. This terminal is
implemented as open-drain and must be pulled low through a 10-k nominal resistor for designs where
CLKRUN is not implemented. For mobile applications where CLKRUN is implemented, the pullup
resistor is typically provided by the system central resource.
PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3
41
28
15
2
47
30
17
4
I/O PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the
same PCI terminals. During the address phase of a bus cycle, PCI_C/BE3PCI_C/BE0 define the bus
command. During the data phase, this 4-bit bus is used for byte enables.
PCI_DEVSEL 21 23 I/O PCI device select. The TSB43AB23 device asserts this signal to claim a PCI cycle as the target device.
As a PCI initiator, the TSB43AB23 device monitors this signal until a target responds. If no target
responds before time-out occurs, the TSB43AB23 device terminates the cycle with an initiator abort.
PCI_FRAME 17 19 I/O PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. PCI_FRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When PCI_FRAME is deasserted, the PCI bus transaction is in the final data phase.
PCI_GNT 114 128 I PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB43AB23 device access to
the PCI bus after the current data transaction has completed. This signal may or may not follow a PCI
bus request, depending upon the PCI bus parking algorithm.
PCI_IDSEL 4 6 I Initialization device select. PCI_IDSEL selects the TSB43AB23 device during configuration space
accesses. PCI_IDSEL can be connected to 1 of the upper 21 PCI address lines on the PCI bus.
PCI_IRDY 18 20 I/O PCI initiator ready. PCI_IRDY indicates the ability of the PCI bus initiator to complete the current data
phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both
PCI_IRDY and PCI_TRDY are asserted.
PCI_PAR 26 28 I/O
PCI parity. In all PCI bus read and write cycles, the TSB43AB23 device calculates even parity across
the PCI_AD and PCI_C/BE buses. As an initiator during PCI cycles, the TSB43AB23 device outputs
this parity indicator with a one-PCI_CLK delay. As a target during PCI cycles, the calculated parity is
compared to the initiator parity indicator; a miscompare can result in a parity error assertion
(PCI_PERR).
PCI_PERR 24 26 I/O PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does
not match PCI_PAR when bit 6 (PERR_ENB) is set to 1 in the command register at offset 04h in the
PCI configuration space (see Section 3.4, Command Register).
PCI_PME 117 131 O Power management event. This terminal indicates wake events to the host and is implemented as an
open-drain output.
PCI_REQ 115 129 O PCI bus request. Asserted by the TSB43AB23 device to request access to the bus as an initiator . The
host arbiter asserts PCI_GNT when the TSB43AB23 device has been granted access to the bus.
PCI_SERR 25 27 O
PCI system error. When bit 8 (SERR_ENB) in the command register at offset 04h in the PCI
configuration space (see Section 3.4, Command Register) is set to 1, the output is pulsed, indicating
an address parity error has occurred. The TSB43AB23 device need not be the target of the PCI cycle
to assert this signal. This terminal is implemented as open-drain.
PCI_STOP 22 24 I/O PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI
bus transaction. This signal is used for target disconnects, and is commonly asserted by target devices
which do not support burst data transfers.
PCI_TRDY 20 22 I/O PCI target ready. PCI_TRDY indicates the ability of the PCI bus target to complete the current data
phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both
PCI_IRDY and PCI_TRDY are asserted.
29
Table 27. Miscellaneous Terminals
TERMINAL
NAME PDT
NO. PGE
NO. I/O DESCRIPTION
CYCLEIN 55 61 I/O The CYCLEIN terminal allows an external 8-kHz clock to be used as a cycle timer for synchronization
with other system devices.
If this terminal is not implemented, it must be pulled high to DVDD through a pullup resistor.
CYCLEOUT 54 60 I/O The CYCLEOUT terminal provides an 8-kHz cycle timer synchronization signal. If CYCLEOUT is not
implemented, this terminal must be pulled down to ground through a pulldown resistor.
REG_EN 107 121 I
Regulator enable. This terminal must be tied to ground to enable the internal voltage regulator. When
using a single 3.3-V supply , this terminal must be tied to ground to enable the internal voltage regulator .
When using a dual 1.8-V/3.3-V supply to provide power to the device, REG_EN must be pulled to DVDD
to disable the internal voltage regulator.
GPIO2/TEST0 58 64 I/O General-purpose I/O [2]. This terminal defaults as an input and if it is not implemented, it is
recommended that it be pulled low to ground with a 220- resistor.
GPIO3/TEST1 57 63 I/O General-purpose I/O [3]. This terminal defaults as an input and if it is not implemented, it is
recommended that it be pulled low to ground with a 220- resistor.
SCL 59 65 I/O Serial clock. This terminal provides the serial clock signaling and is implemented as open-drain. For
normal operation (a ROM is implemented in the design), this terminal must be pulled high to the ROM
DVDD with a 2.7-k resistor. Otherwise, it must be pulled low to ground with a 220- resistor.
SDA 60 66 I/O
Serial data. At PCI_RST, the SDA signal is sampled to determine if a two-wire serial ROM is present.
If the serial ROM is detected, this terminal provides the serial data signaling.
This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the
design), this terminal must be pulled high to the ROM DVDD with a 2.7-k resistor . Otherwise, it must
be pulled low to ground with a 220- resistor.
210
Table 28. Physical Layer Terminals
TERMINAL
NAME PDT
NO. PGE
NO. TYPE I/O DESCRIPTION
CNA 67 77 CMOS I/O
Cable not active. This terminal is asserted high when there are no ports receiving incoming
bias voltage. If not used, this terminal must be strapped either to DVDD or to GND through
a resistor . To enable the CNA terminal, the BIOS must set bit 7 (CNAOUT) of the PCI PHY
control register at offset ECh in the PCI configuration space (see Section 3.20, PCI PHY
Control Register). If an EEPROM is implemented and CNA functionality is needed, bit 7 of
byte offset 16h in the serial EEPROM must be set. This sets the bit in the PCI configuration
space at power up via the EEPROM.
CPS 69 79 CMOS I Cable power status input. This terminal is normally connected to cable power through a
400-k resistor. This circuit drives an internal comparator that detects the presence of cable
power. If CPS does not detect cable power, this terminal must be pulled to AVDD.
FILTER0
FILTER1 101
102 115
116 CMOS I/O
PLL filter terminals. These terminals are connected to an external capacitance to form a
lag-lead filter required for stable operation of the internal frequency multiplier PLL running
off of the crystal oscillator . A 0.1-µF ±10% capacitor is the only external component required
to complete this filter.
PC0
PC1
PC2
64
63
62
70
69
68 CMOS I Power class programming inputs. On hardware reset, these inputs set the default value of
the power class indicated during self-ID. Programming is done by tying these terminals high
or low.
R0
R1 100
99 114
113 Bias Current-setting resistor terminals. These terminals are connected to an external resistance
to set the internal operating currents and cable driver output currents. A resistance of
6.34 kΩ ±1% is required to meet the IEEE Std 1394-1995 output voltage limits.
TPA0+
TPA078
77 88
87 Cable I/O
TPA1+
TPA187
86 97
96 Cable I/O Twisted-pair cable A differential signal terminals. Board trace lengths from each pair of
positive and negative differential signal pins must be matched and as short as possible to
the external load resistors and to the cable connector
TPA2+
TPA295
94 105
104 Cable I/O
th
e ex
t
erna
l
l
oa
d
res
i
s
t
ors an
d
t
o
th
e ca
bl
e connec
t
or.
TPB0+
TPB075
74 85
84 Cable I/O
TPB1+
TPB183
82 93
92 Cable I/O Twisted-pair cable B differential signal terminals. Board trace lengths from each pair of
positive and negative differential signal pins must be matched and as short as possible to
the external load resistors and to the cable connector
TPB2+
TPB292
91 102
101 Cable I/O
th
e ex
t
erna
l
l
oa
d
res
i
s
t
ors an
d
t
o
th
e ca
bl
e connec
t
or.
TPBIAS0
TPBIAS1
TPBIAS2
79
88
96
89
98
106 Cable I/O
Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper
operation of the twisted-pair cable drivers and receivers and for signaling to the remote
nodes that there is an active cable connection. Each of these pins must be decoupled with
a 1.0-µF capacitor to ground.
XI
XO 105
106 119
120 Crystal
Crystal oscillator inputs. These pins connect to a 24.576-MHz parallel resonant fundamental
mode crystal. The optimum values for the external shunt capacitors are dependent on the
specifications of the crystal used (see Section 8.2, Crystal Selection). Terminal 5 has an
internal 10-k (nominal value) pulldown resistor . An external clock input can be connected
to the XI terminal. When using an external clock input, the XO terminal must be left
unconnected. Refer to Section 9.7 for the operating characteristics of the XI terminal.
211
Table 29. Power Supply Terminals
TERMINAL
NAME PDT
NO. PGE
NO. TYPE I/O DESCRIPTION
AGND 71, 73, 76, 80,
84, 89, 97 81, 83, 86, 90,
94, 99, 111 Supply Analog circuit ground terminals. These terminals must be tied together
to the low-impedance circuit board ground plane.
AVDD 70, 72, 81, 85,
90, 93, 98 80, 82, 91, 95,
100, 103, 112 Supply
Analog circuit power terminals. A parallel combination of high
frequency decoupling capacitors near each terminal is suggested,
such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and DVDD internal to the device to provide
noise isolation. They must be tied at a low-impedance point on the
circuit board.
DGND 1, 12, 23, 32,
36, 43, 51, 66,
113, 119
3, 14, 25, 34,
42, 49, 57, 76,
127, 133 Supply Digital circuit ground terminals. These terminals must be tied together
to the low-impedance circuit board ground plane.
DVDD 7, 19, 27, 40,
56, 65, 111,
123
9, 21, 29, 46,
62, 75, 125,
137 Supply
Digital circuit power terminals. A parallel combination of high frequency
decoupling capacitors near each DVDD terminal is suggested, such as
0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are
also recommended. These supply terminals are separated from
PLLVDD and AVDD internal to the device to provide noise isolation. They
must be tied at a low-impedance point on the circuit board.
PHY_TEST_MA 68 78 Test control input. This input is used in the manufacturing test of the
TSB43AB23 device. For normal use, the terminal must be tied to DVDD.
PLLGND 104 118 Supply PLL circuit ground terminal. This terminal must be tied to the
low-impedance circuit board ground plane.
PLLVDD 103 117 Supply
PLL circuit power terminal. A parallel combination of high frequency
decoupling capacitors near the terminal is suggested, such as 0.1 µF
and 0.001 µF. Lower frequency 10-µF filtering capacitors are also
recommended. This supply terminal is separated from DVDD and AVDD
internal to the device to provide noise isolation. It must be tied to a
low-impedance point on the circuit board.
REG18 61, 126 67, 140 Supply
REG18. 1.8-V power supply for the device core. The internal voltage
regulator provides 1.8 V from DVDD. When the internal regulator is
disabled (REG_EN is high), the REG18 terminals can be used to supply
an external 1.8-V supply to the TSB43AB23 core. It is recommended
that 0.1-µF bypass capacitors be used and placed close to these
terminals.
VDDP 3, 16, 30, 46,
116 5, 18, 32, 52,
130 Supply PCI signaling clamp voltage power input. PCI signals are clamped per
the PCI Local Bus Specification. In addition, if a 5-V ROM is used, the
VDDP must be connected to 5 V.
31
3 TSB43AB23 1394 OHCI Controller Programming Model
This section describes the internal PCI configuration registers used to program the TSB43AB23 1394 open host
controller interface. All registers are detailed in the same format: a brief description for each register is followed by
the register offset and a bit table describing the reset state for each register.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 31
describes the field access tags.
Table 31. Bit Field Access Tag Descriptions
ACCESS TAG NAME MEANING
R Read Field can be read by software.
W Write Field can be written by software to any value.
S Set Field can be set by a write of 1. Writes of 0 have no effect.
C Clear Field can be cleared by a write of 1. Writes of 0 have no effect.
U Update Field can be autonomously updated by the TSB43AB23 device.
Figure 31 shows a simplified block diagram of the TSB43AB23 device.
32
Received Data
Decoder/Retimer
Arbitration
and Control
State Machine
Logic
Bias Voltage
and
Current Generator
T ransmit Data
Encoder
Cable Port 1
Crystal
Oscillator,
PLL System,
and Clock
Generator
Cable Port 2
Internal
Registers
Isochronous
Transmit
Contexts
Asynchronous
Transmit
Contexts
Physical DMA
and Response
PCI
Target
SM
PHY
Register
Access
and
Status
Monitor
Central
Arbiter
and
PCI
Initiator
SM
Cycle Start
Generator and
Cycle Monitor
Synthesized
Bus Reset
Receive
FIFO
Link
Transmit
Link
Receive
PCI
Host
Bus
Interface
Resp
Time-out
Request
Filters
General
Request Receive
Asynchronous
Response
Receive
Isochronous
Receive
Contexts
OHCI PCI Power
Mgmt and CLKRUN
Transmit
FIFO
Receive
Acknowledge
Serial
ROM
GPIOs
CRC
Misc
Interface
PHY/
Link
Interface
Cable Port 0
Figure 31. TSB43AB23 Block Diagram
33
3.1 PCI Configuration Registers
The TSB43AB23 device is a single-function PCI device. The configuration header is compliant with the PCI Local Bus
Specification as a standard header. Table 32 illustrates the PCI configuration header that includes both the
predefined portion of the configuration space and the user-definable registers.
Table 32. PCI Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 00h
Status Command 04h
Class code Revision ID 08h
BIST Header type Latency timer Cache line size 0Ch
OHCI base address 10h
TI extension base address 14h
Reserved 18h2Bh
Subsystem ID Subsystem vendor ID 2Ch
Reserved 30h
Reserved PCI power
management
capabilities pointer
34h
Reserved 38h
Maximum latency Minimum grant Interrupt pin Interrupt line 3Ch
OHCI control 40h
Power management capabilities Next item pointer Capability ID 44h
PM data PMCSR_BSE Power management control and status 48h
Reserved 4ChEBh
PCI PHY control ECh
Miscellaneous configuration F0h
Link enhancement control F4h
Subsystem device ID alias Subsystem vendor ID alias F8h
GPIO3 GPIO2 Reserved FCh
3.2 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.
Bit 15 14 13 12 11 109876543210
Name Vendor ID
Type RRRRRRRRRRRRRRRR
Default 0001000001001100
Register: Vendor ID
Offset: 00h
Type: Read-only
Default: 104Ch