128Mb: x4, x8, x16 DDR SDRA M
Features
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128Mb_DDR_x4x8x16_D1.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 1©2004 Micron Technology, Inc. All rights reserved.
Double Data Rate (DDR) SDRAM
MT46V32M4 – 8 Meg x 4 x 4 Banks
MT46V16M8 – 4 Meg x 8 x 4 Banks
MT46V8M16 – 2 Meg x 16 x 4 Banks
Features
•VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
•V
DD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400)
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands enter ed on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per by te)
• Programmable burst lengths: 2, 4, or 8
• Auto refres h and self refresh modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
•tRAS lockout supported (tRAP = tRCD)
Notes: 1. Not recommended for new designs
Options Marking
• Configuration
–32 Meg x 4 (8 Meg x 4 x 4 banks) 32M4
–16 Meg x 8 (4 Meg x 8 x 4 banks) 16M8
–8 Meg x 16 (2 Meg x 16 x 4 banks) 8M16
•Plastic package – OCPL
–66 -p in TSO P TG
–66-pin TSOP (Pb-free) P
• Timi n g – cycle time
–5ns @ CL = 3 (DDR400) -5B
–6ns @ CL = 2.5 (DDR333)
(TSOP only) -6T
–7.5ns @ CL = 2 (DDR266)1-75E
–7.5ns @ CL = 2 (DDR266A) -75Z
–7.5ns @ CL = 2.5 (DDR266B) -75
• Self refresh
–Standard None
–Low-power self refresh L
• Temperatu re rating
–Commercial (0°C to 70°C) None
–Industrial (–40°C to +85°C) IT
• Revision :D
Table 1: Key Timing Parameters
CL = CAS (READ) latency; MIN clock rate with 50% duty cycle at CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and
CL = 3 (-5B)
Speed Grade
Clock Rate (MHz) Data Out
Window Access
Window DQS–DQ
SkewCL = 2 CL = 2.5 CL = 3
-5B 133 167 200 1.6ns ±0.70ns +0.40ns
-6T 133 167 n/a 2.0ns ±0.70ns +0.45ns
-75E/-75Z 133 133 n/a 2.5ns ±0.75ns +0.50ns
-75 100 133 n/a 2.5ns ±0.75ns +0.50ns
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128Mb_DDR_x4x8x16_D1.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 2©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Features
Figure 1: 128Mb DDR SDRAM Part Numbers
Note: Not all speeds and configurations are available in all packages.
Table 2: Addressing
Parameter 32 Meg x 4 16 Meg x 8 8 Meg x 16
Configuration 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
Refresh count 4K 4K 4K
Row address 4K (A0–A11) 4K (A0–A11) 4K (A0–A11)
Bank address 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Column address 2K (A0–A9, A11) 1K (A0–A9) 512 (A0–A8)
Table 3: Speed Grade Compatibility
Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2)
-5B Yes Yes Yes Yes Yes Yes
-6T – Yes Yes Yes Yes Yes
-75E – – Yes Yes Yes Yes
-75Z –––YesYesYes
-75 ––––YesYes
-5B -6T -75E -75Z -75 -75
Example Part Number: MT46V8M16P-6T:D
L
Special Options
Standard
Low power
ConfigurationMT46V Package Speed Revision
Special
Options
Temperature
Configuration
32 Meg x 4
16 Meg x 8
8 Meg x 16
32M4
16M8
8M16
Package
400-mil TSOP
400-mil TSOP (Pb-free)
TG
P
Speed Grade
tCK = 5ns, CL = 3
tCK = 6ns, CL = 2.5
tCK = 7.5ns, CL = 2
tCK = 7.5ns, CL = 2
tCK = 7.5ns, CL = 2.5
-5B
-6T
-75E
-75Z
-75
IT
Operating Temp
Commercial
Industrial
:D Revision
x4, x8, x16
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128Mb_DDRTOC.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 3©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Table of Contents
Table of Contents
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Electrical Specifications – IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Electrical Specifications – DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
ACTIVE (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
PRECHARGE (PRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
BURST TERMINATE (BST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
AUTO REFRESH (AR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
REGISTER DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
POWER-DOWN (CKE Not Active). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
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DDR_x4x8x16_Core1.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 4©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
State Diagram
State Diagram
Figure 2: Simplified State Diagram
Note: This diagram represents operations within a single bank only and does not capture concur-
rent operations in other banks.
Power
on
Power
applied
REFS
LMR REFA
REFSX
ACT
CKE LOW
CKEL
CKE HIGH
CKEH
PRE
Precharge
all banks
MR
EMR
Self
refresh
Idle
all banks
precharged
Row
active Burst
stop
Read
Read A
Automatic sequence
Command sequence
Write
WRITE
WRITE
Write A
WRITE A
Precharge
PREALL
Active
power-
down
Precharge
power-
down
Auto
refresh
PRE
WRITE A READ A
READ A
PRE
PRE
READ A
READ
READ
READ BST
ACT = ACTIVE
BST = BURST TERMINATE
CKEH = Exit power down
CKEL = Enter power down
EMR = Extended mode register
LMR = LOAD MODE REGISTER
MR = Mode register
PRE = PRECHARGE
PREALL = PRECHARGE all banks
READ A = READ with auto precharge
REFA = AUTO REFRESH
REFS = Enter self refresh
REFSX = Exit self refresh
WRITE A = WRITE with auto precharge
PRE
LMR
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DDR_x4x8x16_Core1.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 5©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Functional Description
Functional Description
The DDR SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n-prefetch architecture with an inter-
face designed to transfer two data words per clock cycle at the I/O pins. A single read or
write acce ss for th e DD R SD RA M effe c ti vel y cons is ts of a sing le 2 n-bi t w id e, one-clock-
cycle data transfer at the internal DRAM core and two corr esponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The x16 offering has two data strobes,
one for the lower byte and one for the upper byte.
The DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (addre ss and control signals) are registered at every positive edge of CK.
Input data is registered on both edge s of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; acce sses start at a
selected location and continue for a pr ogramme d number of locations in a progr ammed
sequence . A ccesses be gin with the r egi strati on of an ACTIVE command, which may then
be followed by a REA D or WRITE command. The address bits register ed coincident with
the ACTIVE command are used to select the bank and r ow to be accessed. The address
bits re gistere d coincident with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8
locations. An AUTO PRECHARGE function may be enabled to provide a self-tim ed row
precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high effective bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a power-saving power-down mode. All
inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs
are SSTL_2, Class II compatible.
General Notes • The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated
otherwise. Additionally, the x16 is divided into two bytes, the lower byte and upper
byte. For the lower byte (DQ0–DQ7) DM refers to LDM and DQS refers to LDQS. For
the upper by te (DQ8–DQ15) DM refers to UDM and DQS refers to UDQS.
• Complete functionality is described throughout the document and any page or
diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.
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128Mb_DDR_x4x8x16_D2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 6©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Functional Block Diagrams
Functional Block Diagrams
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory
containing 134,217,728 bits. It is internally configured as a 4-bank DRAM.
Figure 3: 32 Meg x 4 Functional Block Diagram
12
RAS#
CAS#
ROW-
ADDRESS
MUX
CK
CS#
WE#
CK#
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTERS
11
COMMAND
DECODE
A0–A11,
BA0, BA1
CKE
12
ADDRESS
REGISTER
14
1024
(x8)
8192
I/O GATING
DM MASK LOGIC
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(4,096 x 1,024 x 8)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
14
BANK1 BANK2 BANK3
12
10
1
2
2
REFRESH
COUNTER
4
4
4
1
INPUT
REGISTERS
1
1
1
1
RCVRS
1
8
8
2
8
CK
Out
DATA
DQS
MASK
DATA
CK
CK
COL0
COL0
CK
In
DRVRS
DLL
MUX
DQS
GENERATOR
4
4
4
4 4
8
DQ0–DQ3
DQS
1
READ
LATCH
WRITE
FIFO
&
DRIVERS DM
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128Mb_DDR_x4x8x16_D2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 7©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Functional Block Diagrams
Figure 4: 16 Meg x 8 Functional Block Diagram
Figure 5: 8 Meg x 16 Functional Block Diagram
12
RAS#
CAS#
ROW-
ADDRESS
MUX
CK
CS#
WE#
CK#
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTERS
10
COMMAND
DECODE
A0–A11,
BA0, BA1
CKE
12
ADDRESS
REGISTER
14
512
(x16)
8192
I/O GATING
DM MASK LOGIC
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(4,096 x 512 x 16)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
14
BANK1 BANK2 BANK3
12
9
2
2
REFRESH
COUNTER
8
8
8
1
INPUT
REGISTERS
1
1
1
1
RCVRS
1
16
16
2
16
CK
Out
DATA
DQS
MASK
DATA
CK
CK
CK
In
DRVRS
DLL
MUX
DQS
GENERATOR
8
8
8
8 8
16
DQ0–DQ7
DQS
1
READ
LATCH
WRITE
FIFO
&
DRIVERS
1
COL0
COL0
DM
12
RAS#
CAS#
ROW-
ADDRESS
MUX
CK
CS#
WE#
CK#
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTERS
9
COMMAND
DECODE
A0–A11,
BA0, BA1
CKE
12
ADDRESS
REGISTER
14
256
(x32)
8192
I/O GATING
DM MASK LOGIC
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(4,096 x 256 x 32)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
14
BANK1 BANK2 BANK3
12
8
2
2
REFRESH
COUNTER
16
16
16
2
INPUT
REGISTERS
2
2
2
2
RCVRS
2
32
32
4
32
CK
Out
DATA
DQS
MASK
DATA
CK
CK
CK
In
DRVRS
DLL
MUX
DQS
GENERATOR
16
16
16
16 16
32
DQ0–DQ15
LDQS
UDQS
2
READ
LATCH
WRITE
FIFO
&
DRIVERS
1
COL0
COL0
LDM,
UDM
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128Mb_DDR_x4x8x16_D2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 8©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Pin Assignments and De scriptio ns
Pin Assignments and Descriptions
Figure 6: 66-Pin TSOP Pin Assignment (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
DNU
VREF
VSS
UDM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
x16
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
DNU
LDM
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
x16 VSS
DQ7
VSSQ
NF
DQ6
VDDQ
NF
DQ5
VSSQ
NF
DQ4
VDDQ
NF
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
x
8
x4
VSS
NF
VSSQ
NF
DQ3
VDDQ
NF
NF
VSSQ
NF
DQ2
VDDQ
NF
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
NF
DQ1
VSSQ
NF
DQ2
VDDQ
NF
DQ3
VSSQ
NF
NC
VDDQ
NC
NC
VDD
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
x8 x4
VDD
NF
VDDQ
NF
DQ0
VSSQ
NF
NF
VDDQ
NF
DQ1
VSSQ
NF
NC
VDDQ
NC
NC
VDD
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
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128Mb_DDR_x4x8x16_D2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 9©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Pin Assignments and De scriptio ns
Table 4: Pin Descriptions
TSOP
Numbers Symbol Type Description
29, 30, 31
32, 35, 36,
37, 38, 39,
40, 28, 41
A0, A1, A2,
A3, A4, A5,
A6, A7, A8,
A9, A10, A11
Input Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the
PRECHARGE appl ies to one bank (A10 LOW, bank selected by BA0, BA1) or
all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
26, 27 BA0, BA1 Input Bank addr ess inputs: BA0 and BA1 define to which bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0 and BA1 also define
which mode register (mode register or extende d mode register) is loaded
during the LOAD MODE REGISTER command.
45, 46 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK and
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
44 CKE Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal
clock, input buffers, and output drivers. Taking CKE LOW provides
PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or
ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the ou tput s. C KE mu st
be maintained HIGH throughout read and write accesses. Input buffers
(excluding CK, CK#, and CKE) are disabled during POWER-DOWN. Input
buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2
input but will detect an LVCMOS LOW level after VDD is applied and until
CKE is first brought HIGH, after which it becomes an SSTL_2 input only.
24 CS# Input Chip select: CS# enables (regis tered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
47
20
47
DM
LDM
UDM
Input Input data mask: DM is an input mask sig nal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a write
access. DM is sampled on both edges of DQS. Although DM pins are input-
only, the DM loading is designed to match that of DQ and DQS pins. For the
x16, LDM is DM for DQ0–DQ7 and UDM is DM for DQ8–DQ15. Pin 20 is a NC
on x4 and x8.
23, 22, 21 RAS#, CAS#,
WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
2, 4, 5, 7,
8, 10, 11, 13,
54, 56, 57, 59,
60, 62, 63, 65
DQ0–DQ3
DQ4–DQ7
DQ8–DQ11
DQ12–DQ15
I/O Data input/output: Data bu s for x16.
2, 5, 8, 11,
56, 59, 62, 65 DQ0–DQ3
DQ4–DQ7 I/O Data input/output: Data bus for x8.
5, 11, 56, 62 DQ0–DQ3 I/O Data input/output: Data bus for x4.
51
16
51
DQS
LDQS
UDQS
I/O Data strobe: Output with read data, input with write data. DQS is edge-
aligned with read data, cent ered in write data. It is used to capture data. For
the x16, LDQS is DQS for DQ0–DQ7 and UDQS is DQS for DQ8–DQ15. Pin 16 is
NC on x4 and x8.
1, 18, 33 VDD Supply Power supply.
3, 9, 15, 55, 61 VDDQSupply DQ power supply: Isolated on the die for improved noise immunity.
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128Mb_DDR_x4x8x16_D2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 10 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Pin Assignments and De scriptio ns
34, 48, 66 VSS Supply Ground.
6, 12, 52, 58,
64 VSSQ Supply DQ ground: Isolated on the die for improved noise immunity.
49 VREF Supply SSTL_2 reference voltage.
14, 17, 25, 42,
43, 53 NC – No connect for x16: These pins should be left unconnected.
14, 16, 17, 20,
25, 42, 43, 53 NC – No connect for x8: These pins should be left unconnected.
14, 16, 17, 20,
25, 42, 43, 53 NC – No connect for x4: These pins should be left unconnected.
4, 7, 10, 13, 54,
57, 60, 63 NF – No function for x8: These pins should be left unconnected.
2, 4, 7, 8, 10,
13, 54, 57, 59,
60, 63, 65
NF – No function for x4: These pins should be left unconnected.
19, 50 DNU –Do not use: Must float to minimize noise on VREF.
Table 5: Reserved NC Pin Descriptions
NC pins not listed may also be reserved for other uses; this table defines NC pins of importance
TSOP
Numbers Symbol Type Description
42, 17 A12, A13 Input Address inputs A12 and A13 for 256Mb, 512Mb, and 1Gb devices.
Table 4: Pin Descriptions (continued)
TSOP
Numbers Symbol Type Description
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128Mb_DDR_x4x8x16_D2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 11 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Package Dimensions
Package Dimensions
Figure 7: 66-Pin Plastic TSOP (400 mil)
Notes: 1. All di mensions are in millimeters.
2. Package width an d leng th do not inclu de mold protrusio n; allowable mol d protru sion is
0.25mm per side.
SEE DETAIL A
0.10
0.65 TYP 0.71
10.16 ±0.08
0.15
0.50 ±0.10
PIN #1 ID
DETAIL A
22.22 ± 0.08
0.32 ± .075 TYP
+0.03
–0.02
+0.10
–0.05
1.20 MAX 0.10
0.25
11.76 ±0.20
0.80 TYP
0.10 (2X)
GAGE PLANE
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128Mb_DDR_x4x8x16_D2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 12 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – I
DD
Electrical Specifications – IDD
Table 6: IDD Specifications and Conditions (x4, x8; -5B, -6T, -75E, -75Z, -75)
VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V (-5B); VDDQ = +2.5V ±0.2V, V DD = +2.5V ±0.2V (-6T, -75E, -75Z, -75);
0°C ≤ TA ≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 26–31; See also Table 8 on page 14
Parameter/Condition Symbol -5B -6T -75E -75Z/-75 Units Notes
Operating one-bank active -precharge current:
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cycle; Address an d co ntrol inputs
changing once every two clock cycles
IDD0 115 125 110 105 mA 23, 48
Operating one-bank active-read-precharge current:
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address
and control inputs changing once per clock cycle
IDD1 135 135 120 120 mA 23, 48
Precharge power-down standby current: All banks idle;
Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2P 3 3 3 3 mA 24, 33
Idle standby current: CS# = HIGH; All banks are idle;
tCK = tCK (MIN); CKE = HIGH; Address an d other control inp uts
changing once per clock cycle. VIN = VREF for DQ, DQS, and DM
IDD2F 50 45 45 40 mA 51
Active power-down standby current: On e bank acti ve; Power-
down mode; tCK = tCK (MIN); CKE = LOW IDD3P 30 25 25 25 mA 24, 33
Active standby current: CS# = HIGH; CKE = HIGH; One bank
active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice pe r clock cycle; Address and other cont rol inputs
changing once per clock cycle
IDD3N 50 50 50 45 mA 23
Operating burst r ead current: Burst = 2; Continuous burst
reads; One bank active; Address and control inputs changing once
per clock cycle; tCK = tCK (MIN); IOUT =0mA
IDD4R 165 145 130 130 mA 23, 48
Operating burst write current: Burst = 2; Continuous burst
writes; One bank active; Address and control inputs changing
once per clock cyc l e ; tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice pe r clock cycle
IDD4W 165 145 130 130 mA 23
Auto refresh burst current: tRFC = tRFC (MIN) IDD5 240 265 220 220 mA 50
tRFC = 15.6µs IDD5A 6 5 5 5 mA 28, 50
Self re fresh current: CKE ≤ 0.2V Standard IDD644 4 4 mA12
Low power (L) IDD6A 1.3 1.3 1.3 1.3 mA 12
Operating bank interleave read current: Four bank
interleaving READs (Burst = 4) with auto precharge;
tRC = minimum tRC allo wed; tCK = tC K (MIN); Address and control
inputs change only during ACTIVE, READ, or WRITE commands
IDD7 355 355 330 325 mA 23, 49
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128Mb_DDR_x4x8x16_D2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 13 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – I
DD
Table 7: IDD Specifications and Conditions (x16; -5B, -6T, -75E -75Z -75)
VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V (-5B); VDDQ = +2.5V ±0.2V, V DD = +2.5V ±0.2V (-6T, -75E, -75Z, -75);
0°C ≤ TA ≤ +70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 26–31; See also Table 8 on page 14
Parameter/Condition Symbol -5B -6T -75E -75Z/-75 Units Notes
Operating one-bank active -precharge current:
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cycle; Address an d co ntrol inputs
changing once every two clock cycles
IDD0 125 125 115 110 mA 23, 48
Operating one-bank active-read-precharge current:
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT =0mA;
Address and control inputs changing once per cl ock cycle
IDD1 135 135 135 125 mA 23, 48
Precharge power-down standby current: All banks idle;
Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2P 3 3 3 3 mA 24, 33
Idle standby current: CS# = HIGH; All banks are idle;
tCK = tCK (MIN); CKE = HIGH; Address an d other control inp uts
changing once per clock cycle. VIN = VREF for DQ, DQS, and DM
IDD2F 50 45 45 40 mA 51
Active power-down standby current: One bank active; Power-
down mode; tCK = tCK (MIN); CKE = LOW IDD3P 30 25 25 25 mA 24, 33
Active standby current: CS# = HIGH; CKE = HIGH; One bank
active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS
inputs changing tw ic e per cloc k cyc le; Ad dress an d other control
inputs changing once per clock cycle
IDD3N 50 50 50 45 mA 23
Operating burst r ead current: Burst = 2; Continuous burst
reads; One bank active; Address and control inputs changing once
per clock cycle; tCK = tCK (MIN); IOUT =0mA
IDD4R 185 165 140 140 mA 23, 48
Operating burst write current: Burst = 2; Continuous burst
writes; One bank active; Address and control inputs changing
once per clock cyc l e ; tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice pe r clock cycle
IDD4W 185 165 140 140 mA 23
Auto refresh burst current: tRFC = tRFC (MIN) IDD5 265 265 250 250 mA 50
tRFC = 15.6µs IDD5A 10 5 5 5 mA 28, 50
Self re fresh current: CKE ≤ 0.2V Standard IDD6444 4 mA 12
Low power (L) IDD6A 1.3 1.3 1.3 1.3 mA 12
Operating bank interleave read current: Four bank
interleaving READs (Burst = 4) with auto precharge;
tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control
inputs change only during ACTIVE, READ, or WRITE commands
IDD7 385 385 375 375 mA 23, 49
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128Mb_DDR_x4x8x16_D2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 14 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – I
DD
Table 8: IDD Test Cycle Times
Values reflect number of clock cyc les for each test
IDD Test Speed
Grade Clock Cycle
Time tRRD tRCD tRAS tRP tRC tRFC tREFI CL
IDD0–75/75Z 7.5ns n/a n/a 6 3 9 n/a n/a n/a
–75E 7.5ns n/a n/a 6 2 8 n/a n/a n/a
–6T 6ns n/a n/a 7 3 10 n/a n/a n/a
–5B 5ns n/a n/a 8 3 11 n/a n/a n/a
IDD1–75 7.5ns n/a n/a 6 3 9 n/a n/a 2.5
–75Z 7.5ns n/a n/a 6 3 9 n/a n/a 2
–75E 7.5ns n/a n/a 6 2 8 n/a n/a 2
–6T 6ns n/a n/a 7 3 10 n/a n/a 2.5
–5B 5ns n/a n/a n/a n/a n/a n/a n/a 3
IDD4R –75 7.5ns n/a n/a n/a n/a n/a n/a n/a 2.5
–75Z 7.5ns n/a n/a n/a n/a n/a n/a n/a 2
–75E 7.5ns n/a n/a n/a n/a n/a n/a n/a 2
–6T 6ns n/a n/a n/a n/a n/a n/a n/a 2.5
–5B 5ns n/a n/a n/a n/a n/a n/a n/a 3
IDD4W –75 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a
–75Z 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a
–75E 7.5ns n/a n/a n/a n/a n/a n/a n/a n/a
–6T 6ns n/a n/a n/a n/a n/a n/a n/a n/a
–5B 5ns n/a n/a n/a n/a n/a n/a n/a n/a
IDD5–75/75Z 7.5ns n/a n/a n/a n/a n/a 10 10 n/a
–75E 7.5ns n/a n/a n/a n/a n/a 9 9 n/a
–6T 6ns n/a n/a n/a n/a n/a 12 12 n/a
–5B 5ns n/a n/a n/a n/a n/a 14 14 n/a
IDD5A –75/75Z 7.5ns n/a n/a n/a n/a n/a 10 1,030 n/a
–75E 7.5ns n/a n/a n/a n/a n/a 9 1,031 n/a
–6T 6ns n/a n/a n/a n/a n/a 12 1,288 n/a
–5B 5ns n/a n/a n/a n/a n/a 14 1,564 n/a
IDD7–75 7.5ns 2 3 n/a 3 10 n/a n/a 2.5
–75Z 7.5ns 2 3 n/a 3 10 n/a n/a 2
–75E 7.5ns 2 3 n/a 2 8 n/a n/a 2
–6T 6ns 2 3 n/a 3 10 n/a n/a 2.5
–5B 5ns 2 3 n/a 3 11 n/a n/a 3
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 15 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
Electrical Specifications – DC and AC
S tresses greater than those li sted in Table 9 may cause permanent damage to the devi ce.
This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this spe c ifi cat ion is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reli ability.
Table 9: Absolute Maximum Rating s
Parameter Absolute Maximum Value
VDD supply voltage relative to VSS –1V to +3.6V
VDDQ supply voltage relative to VSS –1V to +3.6V
VREF and inputs voltage relative to VSS –1V to +3.6V
I/O pins voltage relative to VSS –0.5V to VDDQ +0.5V
Storage temperature (plastic) –55°C to +150°C
Short circuit output current 50mA
Table 10: DC Electrical Characteristics and Operating Conditions (-5B)
Notes: 1–5 and 17 apply to entire table; Notes appear on pages 26–32;
VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
Parameter/Condition Symbol Min Max Units Notes
Supply voltage VDD +2.5 +2.7 V 37, 42
I/O supply voltage VDDQ +2.5 +2.7 V 37, 42, 45
I/O reference voltage VREF 0.49 × VDDQ 0.51 × VDDQV 7, 45
I/O termination voltage (system) VTT VREF - 0.04 VREF + 0.04 V 8, 45
Input high (logi c 1) vol tag e VIH(DC)VREF + 0.15 VDD + 0.3 V 29
Input low (logic 0) voltage VIL(DC)–0.3VREF - 0.15 V 29
Input leakage current :
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V
(All other pins not under test = 0V)
II–2 +2 µA
Output leakage current:
(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)IOZ –5 +5 µA
Full-drive option output
levels: (x4, x8, x16) High current (VOUT =
VDDQ - 0.373V, minimum
VREF, minimum VTT)
IOH –16.8 – mA 38, 40
Low current (VOUT =
0.373V, maximum VREF,
maximum VTT)
IOL +16.8 – mA
Reduced-drive option
output levels: (x16 only) High current (VOUT =
VDDQ - 0.373V, minimum
VREF, minimum VTT)
IOHR –9 – mA 39, 40
Low current (VOUT =
0.763V, maximum VREF,
maximum VTT)
IOLR +9 – mA
Ambient operating
temperatures Commercial TA0+70°C
Industrial TA–40 +85 °C
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 16 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
Table 11: DC Electrical Characteristics and Operating Conditions (-6, -6T, -75E, -75Z, -75)
Notes: 1–5, 17 apply to entire table; Notes appear on pages 26–32; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Parameter/Condition Symbol Min Max Units Notes
Supply voltage VDD +2.3 +2.7 V 37, 42
I/O supply voltage VDDQ +2.3 +2.7 V 37, 42, 45
I/O reference voltage VREF 0.49 x VDDQ 0.51 x VDDQV 7, 45
I/O termination voltage (system) VTT VREF - 0.04 VREF + 0.04 V 8, 45
Input high (logi c 1) vol tag e VIH(DC)VREF + 0.15 VDD + 0.3 V 29
Input low (logic 0) voltage VIL(DC)–0.3VREF - 0.15 V 29
Input leakage current :
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V
(All other pins not under test = 0V)
II–2 +2 µA
Output leakage current:
(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)IOZ –5 +5 µA
Full-drive option output
levels: (x4, x8, x16) High current (VOUT =
VDDQ - 0.373V , minimum
VREF, minimum VTT)
IOH –16.8 – mA 38, 40
Low current (VOUT =
0.373V, maximum VREF,
maximum VTT)
IOL +16.8 – mA
Reduced-drive option
output levels: (x16 only) High current (VOUT =
VDDQ - 0.763V , minimum
VREF, minimum VTT)
IOHR –9 – mA 39, 40
Low current (VOUT =
0.763V, maximum VREF,
maximum VTT)
IOLR +9 – mA
Ambient operating
temperatures Commercial TA0+70°C
Industrial TA–40 +85 °C
Table 12: AC Input Operating Conditions
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
(VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V for -5B)
Notes: 1–5 , 15 , 17 apply to entire table; No te s appear on pages 26–32
Parameter/Condition Symbol Min Max Units Notes
Input high (logi c 1) vol tag e VIH(AC)VREF + 0.310 – V 15, 29, 41
Input low (logic 0) voltage VIL(AC)–VREF - 0.310 V 15, 29, 41
I/O reference voltage VREF(AC) 0.49 × VDDQ 0.51 × VDDQV 7
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 17 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
Figure 8: Input Voltage Waveform
Notes: 1. VOH (MIN) with test load is 1.927V.
2. VOL (MAX) with test load is 0.373V.
3. Numbers in diagram reflect nominal values utilizing circui t belo w for all devi ces oth er than
-5B.
0.940V
1.100V
1.200V
1.225V
1.250V
1.275V
1.300V
1.400V
1.560V
VIL(AC)
VIL(DC)
VREF - AC noise
VREF - DC error
VREF + DC error
VREF + AC noise
Receiver
Tr
a
n
s
mi
tte
r
VIH(DC)
VIH(AC)
VOH (MIN) (1.670V1 for SSTL_2 termination)
VIN(AC) - provides margin
between VOL (MAX)
and VIL(AC)
VssQ
VDDQ (2.3V MIN)
VOL (MAX) (0.83V2 for SSTL_2
termination)
System noise margin (power/ground,
crosstalk, signal integrity attenuation)
Reference
point
25Ω
25Ω
VTT
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 18 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
Figure 9: SSTL_2 Clock Input
Notes: 1. CK or CK# may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
2. This provides a minimum of 1.1 5V to a maxim u m of 1.3 5 V an d is al wa ys ha l f of VDDQ.
3. CK and CK# must cross in this region.
4. CK and CK# must meet at least VID(DC) MIN when static and is centered around VMP(DC).
5. CK and CK# must have a minimum 700mV peak-to-peak swing.
6. For AC operation, all DC clock re quirements must also be satisfied.
7. Numbers in diagram reflect nominal values for all devices other than -5B.
Table 13: Clock Input Operating Conditions
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
(VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V for -5B)
Notes: 1–5 , 16 , 17 , 31 apply to entire tab le; Notes appear on pages 26–32
Parameter/Condition Symbol Min Max Units Notes
Clock input mi d-p oi nt voltage: CK and CK# VMP(DC) 1.15 1.35 V 7, 10
Clock input vol tage level: CK and CK# VIN(DC)–0.3VDDQ + 0.3 V 7
Clock input differential voltage: CK and CK# VID(DC)0.36VDDQ + 0.6 V 7, 9
Clock input differential voltage: CK and CK# VID(AC)0.7VDDQ + 0.6 V 9
Clock input crossing point voltage: CK and CK# VIX(AC) 0.5 × VDDQ - 0.2 0.5 × VDDQ + 0.2 V 10
CK
CK#
2.80V
Maximum clock level1
Minimum clock level1
–0.30V
1.25V
1.45V
1.05V VID(AC)5
VID(DC)4
X
X
VMP(DC)2VIX(AC)3
X
X
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 19 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
Table 14: Capacitance (x4, x8 TSOP – 128Mb, 256Mb, 512Mb, 1Gb)
Note: 14 applies to entire table; Notes appear on pages 26–32
Parameter Symbol Min Max Units Notes
Delta input/output capacitance: DQ0–DQ3 (x4), DQ0–DQ7 (x8) DCIO –0.50pF 25
Delta input cap a citance: Command and address DCI1–0.50pF 30
Delta input capacitance: CK, CK# DCI2–0.25pF 30
Input/output capacitance: DQs, DQS, DM CIO 4.0 5.0 pF
Input capacitance: Command and address CI12.0 3.0 pF
Input capacitance: CK, CK# CI22.0 3.0 pF
Input capacitance: CKE CI32.0 3.0 pF
Table 15: Capacitance (x4, x8 FBGA – 256Mb and 512Mb only)
Note: 14 applies to entire table; Notes appear on pages 26–32
Parameter Symbol Min Max Units Notes
Delta input/output capacitance: DQs, DQS, DM DCIO –0.50pF 25
Delta input cap a citance: Command and address DCI1–0.50pF 30
Delta input capacitance: CK, CK# DCI2–0.25pF 30
Input/output capacitance: DQs, DQS, DM CIO 3.5 4.5 pF
Input capacitance: Command and address CI11.5 2.5 pF
Input capacitance: CK, CK# CI21.5 2.5 pF
Input capacitance: CKE CI31.5 2.5 pF
Table 16: Capacitance (x16 TSOP – 128Mb, 256Mb, 512Mb, 1Gb)
Note: 14 applies to entire table; Notes appear on pages 26–32
Parameter Symbol Min Max Units Notes
Delta input/output capacitance: DQ0–DQ7, LDQS, LDM DCIOL –0.50pF 25
Delta input/output capacitance: DQ8–DQ15, UDQS, UDM DCIOU –0.50pF 25
Delta input cap a citance: Command and address DCI1–0.50pF 30
Delta input capacitance: CK, CK# DCI2–0.25pF 30
Input/outp ut ca paci tan ce: DQ , LDQS, UDQS, LDM, UDM CIO 4.0 5.0 pF
Input capacitance: Command and address CI12.0 3.0 pF
Input capacitance: CK, CK# CI22.0 3.0 pF
Input capacitance: CKE CI32.0 3.0 pF
Table 17: Capacitance (x16 FBGA – 256Mb and 512Mb only)
Note: 14 applies to entire table; Notes appear on pages 26–32
Parameter Symbol Min Max Units Notes
Delta input/output capacitance: DQ0–DQ7, LDQS, LDM DCIOL –0.50pF 25
Delta input/output capacitance: DQ8–DQ15, UDQS, UDM DCIOU –0.50pF 25
Delta input cap a citance: Command and address DCI1–0.50pF 30
Delta input capacitance: CK, CK# DCI2–0.25pF 30
Input/outp ut ca paci tan ce: DQ , LDQS, UDQS, LDM, UDM CIO 3.5 4.5 pF
Input capacitance: Command and address CI11.5 2.5 pF
Input capacitance: CK, CK# CI21.5 2.5 pF
Input capacitance: CKE CI31.5 2.5 pF
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 20 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
Table 18: Electrical Characteristics & Recommended AC Operating Conditions (-5B)
Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 26–32;
0°C ≤ TA ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
AC Characteristics -5B
Units NotesParameter Symbol Min Max
Access window of DQ from CK/CK# tAC –0.70 +0.70 ns
CK high-level width tCH 0.45 0.55 tCK 31
Clock cycle time CL = 3 tCK (3) 5 7.5 ns 52
CL = 2.5 tCK (2.5) 6 13 ns 46, 52
CL = 2 tCK (2) 7.5 13 ns 46, 52
CK low-level width tCL 0.45 0.55 tCK 31
DQ and DM input hold time relative to DQS tDH 0.40 – ns 27, 32
DQ and DM input pu lse width (for each input) tDIPW 1.75 – ns 32
Access window of DQS from CK/CK# tDQSCK –0.60 +0.60 ns
DQS input high pulse width tDQSH 0.35 – tCK
DQS input low pulse width tDQSL 0.35 – tCK
DQS–DQ skew, DQS to last DQ valid, per group, per access tDQSQ – 0.40 ns 26, 27
WRITE command to first DQS latching transition tDQSS 0.72 1.28 tCK
DQ and DM input setup time relative to DQS tDS 0.40 – ns 27, 32
DQS falling edge from CK rising – hold time tDSH 0.2 – tCK
DQS falling edge to CK rising – setup time tDSS 0.2 – tCK
Half-clock period tHP tCH,tCL – ns 35
Data-out High-Z window from CK/CK# tHZ – +0.70 ns 19, 43
Address and control input hold time (slew rate ≥0.5 V/n s) tIHF0.60 – ns 15
Address and control input pulse width (for each input) tIPW 2.2 – ns
Address and control input setup time (slew rate ≥0.5 V/ns) tISF0.60 – ns 15
Data-out Low-Z window from CK/CK# tLZ –0.70 – ns 19, 43
LOAD MODE REGISTER command cycle time tMRD 10 – ns
DQ–DQS hold, DQS to first DQ to go non-valid, per access tQH tHP -
tQHS – ns 26, 27
Data hold skew factor tQHS – 0.50 ns
ACTIVE-to-READ with auto precharge command tRAP 15 – ns
ACTIVE-to-PRECHARGE command tRAS 40 70,000 ns 36
ACTIVE-to-ACTIVE/AUTO REFRESH command period tRC 55 – ns
ACTIVE-to-READ or WRITE delay tRCD 15 – ns
REFRESH-to-REFRESH command
interval 128Mb tREFC – 140.6 µs 24
256Mb, 512Mb, 1Gb tREFC – 70.3 µs 24
AUTO REFRESH command period 128Mb, 256Mb, 512Mb tRFC 70 – ns 50
1Gb tRFC 120 – ns 50
Average periodic refresh interval 128Mb tREFI – 15.6 µs 24
256Mb, 512Mb, 1Gb tREFI – 7.8 µs 24
PRECHARGE command period tRP 15 – ns
DQS read preamble tRPRE 0.9 1.1 tCK 44
DQS read postamble tRPST 0.4 0.6 tCK 44
ACTIVE bank a to ACTIVE bank b command tRRD 10 – ns
Terminating voltage delay to VDD tVTD 0 – ns
DQS write preamble tWPRE 0.25 – tCK
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 21 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
DQS write preamble setup time tWPRES 0 – ns 21, 22
DQS write postamble tWPST 0.4 0.6 tCK 20
Write recovery time tWR 15 – ns
Internal WRITE-to-READ command delay tWTR 2 – tCK
Exit SELF REFRESH-to-non-READ
command 128Mb, 256Mb, 512 Mb tXSNR 70 – ns
1Gb tXSNR 126 – ns
Exit SELF REFRESH-to-READ command tXSRD 200 – tCK
Data valid output window (DVW) n/a tQH - tDQSQ ns 26
Table 18: Electrical Characteristics & Recommended AC Operating Conditions (-5B) (continued)
Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 26–32;
0°C ≤ TA ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
AC Characteristics -5B
Units NotesParameter Symbol Min Max
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 22 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6, -6T, -75E)
Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 26–32;
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
AC Characteristics -6 (FBGA)1-6T (TSOP) -75E
Units NotesParameter Symbol Min Max Min Max Min Max
Access window of DQ from CK/CK# tAC –0.70 +0.70 –0.70 +0.70 –0.75 +0.75 ns
CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK 31
Clock cycle time CL = 2.5 tCK (2.5) 6 13 6 13 7.5 13 ns 46, 52
CL = 2 tCK (2) 7.5 13 7.5 13 7.5 13 ns 46, 52
CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 31
DQ and DM input hold time relative to DQS tDH 0.45 – 0.45 – 0.5 – ns 27, 32
DQ and DM input pu lse width (for each input) tDIPW 1.75 – 1.75 – 1.75 – ns 32
Access window of DQS from CK/CK# tDQSCK –0.6 +0.6 –0.6 +0.6 –0.75 +0.75 ns
DQS input high pulse width tDQSH 0.35 – 0.35 – 0.35 – tCK
DQS input low pulse width tDQSL 0.35 – 0.35 – 0.35 – tCK
DQS–DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ – 0.4 – 0.45 – 0.5 ns 26, 27
WRITE command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQ and DM input setup time relative to DQS tDS 0.45 – 0.45 – 0.5 – ns 27, 32
DQS falling edge from CK rising - hold time tDSH 0.2 – 0.2 – 0.2 – tCK
DQS falling edge to CK rising - setup time tDSS 0.2 – 0.2 – 0.2 – tCK
Half-clock period tHP tCH,
tCL –tCH,
tCL –tCH,
tCL –ns35
Data-out High-Z window from CK/CK# tHZ – +0.7 – +0.7 – +0.75 ns 19, 43
Address and control input hold time (fast slew rate) tIHF0.75 – 0.75 – 0.90 – ns
Address and control input hold time (slow slew rate) tIHS0.8 – 0.8 – 1 – ns 15
Address and control input pulse width (for each
input)
tIPW 2.2 – 2.2 – 2.2 – ns
Address and control input setup time (fast slew rate) tISF0.75 – 0.75 – 0.90 – ns
Address and control input setup time (slow slew rate) tISS0.8 – 0.8 – 1 – ns 15
Data-out Low-Z window from CK/CK# tLZ –0.7 – –0.7 – –0.75 – ns 19, 43
LOAD MODE REGISTER command cycle time tMRD12–12–15–ns
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH tHP -
tQHS –tHP -
tQHS –tHP -
tQHS – ns 26, 27
Data hold skew factor tQHS – 0.50 – 0.55 – 0.75 ns
ACTIVE-to-READ with auto precharge command tRAP15–15–15–ns
ACTIVE-to-PRECHARGE command tRAS 42 70,00
042 70,00
040 120,0
00 ns 36, 54
ACTIVE-to-ACTIVE/AUTO REFRESH command period tRC 60 – 60 – 60 – ns
ACTIVE-to-READ or WRITE delay tRCD15–15–15–ns
REFRESH-to-REFRESH
command interval 128Mb tREFC – 140.6 – 140.6 – 140.6 µs 24
256Mb, 512Mb, 1Gb tREFC –70.3–70.3–70.3µs 24
Average periodic refresh
interval 128Mb tREFI –15.6–15.6–15.6µs 24
256Mb, 512Mb, 1Gb tREFI–7.8–7.8–7.8µs24
AUTO REFRESH command
period 128Mb, 256Mb, 512Mb tRFC72–72–75–ns50
1Gb tRFC – – 120 – – – ns 50
PRECHARGE command period tRP 15 – 15 – 15 – ns
DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 44
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 23 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
Notes: 1. -6 (FBGA) available in 256Mb and 512Mb densities only.
DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 44
ACTIVE bank a to ACTIVE bank b command tRRD12–12–15–ns
Terminating voltage delay to VSS tVTD0–0–0–ns
DQS write preamble tWPRE 0.25 – 0.25 – 0.25 – tCK
DQS write preamble setup time tWPRES 0 – 0 – 0 – ns 21, 22
DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 20
Write recovery time tWR 15 – 15 – 15 – ns
Internal WRITE-to-READ command delay tWTR1–1–1–
tCK
Exit SELF REFRESH-to-non-
READ command 128Mb, 256Mb, 512Mb tXSNR 75 – 75 – 75 – ns
1Gb tXSNR––126–––ns
Exit SELF REFRESH-to-READ command tXSRD 200 – 200 – 200 – tCK
Data valid output window (DVW) n/a tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns 26
Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6, -6T, -75E)
(continued)
Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 26–32;
AC Characteristics -6 (FBGA)1-6T (TSOP) -75E
Units NotesParameter Symbol Min Max Min Max Min Max
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 24 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-75Z, -75)
Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 26–32;
0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
AC Characteristics -75Z -75
Units NotesParameter Symbol Min Max Min Max
Access window of DQ from CK/CK# tAC –0.75 +0.75 –0.75 +0.75 ns
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 31
Clock cycle time CL = 2.5 tCK (2.5) 7.5 13 7.5 13 ns 46
CL = 2 tCK (2) 7.5 13 10 13 ns 46
CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 31
DQ and DM input hold time relative to DQS tDH 0.5 – 0.5 – ns 27, 32
DQ and DM input pu lse width (for each input) tDIPW 1.75 – 1.75 – ns 32
Access window of DQS from CK/CK# tDQSCK –0.75 +0.75 –0.75 +0.75 ns
DQS input high pulse width tDQSH 0.35 – 0.35 – tCK
DQS input low pulse width tDQSL 0.35 – 0.35 – tCK
DQS–DQ skew, DQS to last DQ valid, per group, per access tDQSQ – 0.5 – 0.5 ns 26, 27
WRITE command-to-first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK
DQ and DM input setup time relative to DQS tDS 0.5 – 0.5 – ns 27, 32
DQS falling edge from CK rising – hold time tDSH 0.2 – 0.2 – tCK
DQS falling edge to CK rising – setup time tDSS 0.2 – 0.2 – tCK
Half-clock period tHP tCH,tCL – tCH,tCL – ns 35
Data-out High-Z window from CK/CK# tHZ – +0.75 – + 0.75 ns 19, 43
Address and control input hold time (fast slew rate) tIHF0.90 – 0.90 – ns
Address and control input hold time (slow slew rate) tIHS1–1–ns15
Address and control input pulse width (for each input) tIPW 2.2 – 2.2 – ns
Address and control input setup time (fast slew rate) tISF0.90 – 0.90 – ns
Address and control input setup time (slow slew rate) tISS1–1–ns15
Data-out Low-Z window from CK/CK# tLZ –0.75 – –0.75 – ns 19, 43
LOAD MODE REGISTER command cycle time tMRD 15 – 15 – ns
DQ–DQS hold, DQS to first DQ to go non-valid, per access tQH tHP -
tQHS –tHP -
tQHS – ns 26, 27
Data hold skew factor tQHS – 0.75 – 0.75 ns
ACTIVE-to-READ with auto precharge command tRAP 20 – 20 – ns
ACTIVE-to-PRECHARGE command tRAS 40 120,000 40 120,000 ns 36
ACTIVE-to-ACTIVE/AUTO REFRESH command period tRC 65 – 65 – ns
ACTIVE-to-READ or WRITE delay tRCD 20 – 20 – ns
REFRESH-to-REFRESH command interval 128Mb tREFC – 140.6 – 140.6 µs 24
256Mb,
512Mb,
1Gb
tREFC – 70.3 – 70.3 µs 24
Average periodic refresh interval 128Mb tREFI – 15.6 – 15.6 µs 24
256Mb,
512Mb,
1Gb
tREFI – 7.8 – 7.8 µs 24
AUTO REFRESH command period 128Mb,
256Mb,
512Mb
tRFC 75 – 75 – ns 50
1Gb tRFC – – 120 – ns 50
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 25 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
PRECHARGE command period tRP 20 – 20 – ns
DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 44
DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK 44
ACTIVE bank a to ACTIVE bank b command tRRD 15 – 15 – ns
Terminating voltage delay to VDD tVTD 0 – 0 – ns
DQS write preamble tWPRE 0.25 – 0.25 – tCK
DQS write preamble setup time tWPRES 0 – 0 – ns 21, 22
DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK 20
Write recovery time tWR 15 – 15 – ns
Internal WRITE-to-READ command delay tWTR 1 – 1 – tCK
Exit SELF REFRESH-to-non-READ command 128Mb,
256Mb,
512Mb
tXSNR 75 – 75 – ns
1Gb tXSNR – – 127.5 – ns
Exit SELF REFRESH-to-READ command tXSRD 200 – 200 – tCK
Data valid output window (DVW) n/a tQH - tDQSQ tQH - tDQSQ ns 26
Table 21: Input Slew Rate Derating Values for Addresses and Commands
Note: 15 applies to entire table; 0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Speed Slew Rate tIS tIH Units
-75/-75Z/-75E 0.500 V/ns 1.00 1 ns
-75/-75Z/-75E 0.400 V/ns 1.05 1 ns
-75/-75Z/-75E 0.300 V/ns 1.10 1 ns
Table 22: Input Slew Rate Derating Va lues for DQ, DQS, and DM
Note: 32 apply to entire table; 0°C ≤ TA ≤ +70° C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Speed Slew Rate tDS tDH Units
-75/-75Z/-75E 0.500 V/ns 0.50 0.50 ns
-75/-75Z/-75E 0.400 V/ns 0.55 0.55 ns
-75/-75Z/-75E 0.300 V/ns 0.60 0.60 ns
Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-75Z, -75)
(continued)
Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 26–32;
AC Characteristics -75Z -75
Units NotesParameter Symbol Min Max Min Max
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128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
Notes 1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal re ference/supply volt age levels, but the related specifications and the
device operation are guaranteed for the full voltage ra nge specified.
3. Outputs (except for IDD measurements) measured with equivalent load:
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environ-
ment, but input timing is still r efer enced to VREF (or to the crossing point for CK/CK#),
and parameter specifications are guarante ed for the specified AC input lev els under
normal use conditions. The minimum slew rate for the input signals used to test the
device is 1 V/ns in th e range be twe e n VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 standard (i.e.,
the receiver will effectively switch as a r esult of the signal crossing the AC input level
and will remain in that state as long as the signal does not ring back above [belo w] the
DC input LOW [HIGH] level).
6. All speed grades ar e not offered on all densities. Refer to page 1 for availability.
7. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in
the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not
exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC
error and an additional ±25mV for AC noise. This measurement is to be taken at the
nearest VREF bypass capacitor.
8. VTT is not applied directly to the device. VTT is a system supply for signal termination
resistors, it is expected to be set equal to VREF, and it must track variations in the DC
level of VREF.
9. VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
10. The value of VIX and VMP is expected to equal VDDQ/2 of the transmitting device and
must track variations in the DC leve l of th e sam e.
11. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle times at CL = 3 for -5B; CL = 2.5, -6/-6T/-75; and CL = 2,
-75E/-75Z speeds with the outputs open.
12. Enables on-chip refresh and address counters.
13. IDD specifications are tested after the device is properly initialized and is averaged at
the defined cycle rate.
14. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF =VSS,
f=100MHz, T
A=25°C, VOUT(DC)=VDDQ/2, VOUT (peak-to-p eak) = 0.2V. DM input is
grouped with I/O pins, reflecting the fact that they are matched in loading.
15. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If the slew rate is
less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each
100 mV/ns reduction in slew rate from the 500 mV/ns. tIH has 0ps added, that is, it
remai ns constant. If the slew rate ex ceeds 4.5 V/ns , functionality is uncertain. F or -5B ,
-6, and -6T, slew rates must be greater than or equal to 0.5 V/ns.
Output
(VOUT)Reference
point
50Ω
VTT
30pF
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128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
16. The CK/CK# input referenc e level (for timing refere nced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
VREF.
17. Inputs ar e not recognized as valid until VREF stabilizes . O nce i nitial iz ed, inc luding self
refresh mode, VREF must be powered within specified range. Exception: during the
period before VREF stabilizes, CKE < 0.3 × VDD is recognized as LOW.
18. The output timing reference level, as measured at the timing reference point (indi-
cated in Note 3), is VTT.
19. tHZ and tLZ transitions occur in the same access time windows as data valid transi-
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (High-Z) or begins driving (Low-Z).
20. The intent of the “Don’t Care” state after completion of the postamble is the DQS-
driven signal should either be HIGH, LOW, or High-Z, and that any signal transition
within the input switch ing region must follow valid input requirements. That is, if
DQS transitions HIGH (above VIH[DC] MIN) then it must not transition LOW (below
VIH[DC] prior to tDQSH [MIN]).
21. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
22. It is recommended that DQS be valid (HIGH or LO W) on or before the WRITE com-
mand. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on tDQSS.
23. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the
minimum absolute value for the respective parameter. tRAS (MAX) for IDD me as ure-
ments is the largest multiple of tCK that meets the maximum absolute value for tRAS.
24. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs
(15.625µs for 128Mb DDR). H owever, an AUTO REFRESH command must be asserted
at least once every 70.3µs (140.6µs for 128Mb DDR); burst refr eshing or posting b y the
DRAM controller greater than 8 REFRESH cycles is not allowed.
25. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
26. The data valid window is derived by achieving other specifications: tHP (tCK/2),
tDQSQ, and tQH (tQH = tHP- tQHS). The data valid window derates in di rect propor-
tion to the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55, because functionality is
uncertain when operating beyond a 45/55 ratio. The data valid window derating
curves are provided in Figure 10 on page 28 for duty cy cles ranging between 50/50
and 45/55.
27. Refer enced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;
x16 = LDQS with DQ0–DQ7 and UDQS with DQ8–DQ15.
28. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
during the REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
29. To m aintain a valid level, the transitioni ng e dg e of the input mus t:
29a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
29b. Rea ch at least the target AC level.
29c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
30. The input capacitance per pin group will not differ by more than this maximum
amount for any given device.
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Electrical Specifications – DC and AC
31. CK and CK# input slew rate must be ≥1V/ns (≥2 V/ns if measured differentially).
Figure 10: Derating Data Va lid Window (tQH – tDQSQ)
32. DQ and DM input slew rates m u st not deviate from DQS by more than 10 percent. If
the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must
be added to tDS and tDH for each 100 mV/ns reduction in slew rate. For -5B, -6, and
-6T speed grades, the slew rate must be ≥0.5 V/ns. If t he slew rate exceeds 4 V/ns,
functionality is uncertain.
33. VDD must not vary more than 4 percent if CKE is not active while any bank is active.
34. The clock is allowed up to ±150ps of jitter . Each timing parameter is allowed to vary by
the same amount.
35. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the device CK
and CK# inputs, collectively, during bank active.
36. READs and WRITEs with auto pr ec harge ar e not allo w ed to be iss ued until tRAS (MIN)
can be satisfied prior to the internal PRECHARGE command being issued.
37. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV
or 2.9V (+300mV or 2.9V maximum for -5B), whichever is less. Any nega tive glitch
must be less than 1/3 of the clock cycl e and not excee d either –300mV or 2.2V (2.4V for
-5B), whichever is more positive. The average cannot be below the +2.5V (2.6V for -5B)
minimum.
38. Normal output drive curves:
38a. The full driver pull-down current variation from MIN to MAX process; tempera-
ture and voltage will lie within the outer bounding lines of the V-I curve of
Figure 11 on page29.
38b. The driver pull -down current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I cur ve of Figure11 on page29.
38c. The full driver pull-up current variation from MIN to MAX process; temperature
and voltage will lie within the outer bounding lines of the V -I curve of Figure 12 on
page 29.
3.0ns
2.5ns
2.0ns
1.5ns
1.0ns 50/50 49/51 48/53 46/54 47/53 45/55
-6T @ tCK = 7.5ns
-75E / -75 @ tCK = 7.5ns
-6 @ tCK = 6ns
-6T @ tCK = 6ns
-5B @ tCK = 5ns
1.48 1.45 1.43 1.40 1.38 1.35
2.75
2.60 2.56 2.53 2.45 2.41 2.38
2.68
2.35 2.31 2.28
2.13
2.20 2.16
2.43
2.10 2.07 2.04
1.89 1.86 1.83 1.80
1.98 1.95
2.00 1.97 1.94 1.91 1.88
1.73 1.70
1.82 1.79
1.58 1.55
Clock Dut
y
C
y
cle
Data Valid Window
2.71
2.46
1.53
2.64
2.39
1.92
1.76
1.85
1.60
1.50
2.49
2.50
2.24
2.01
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128Mb: x4, x8, x16 DDR SDRA M
Electrical Specifications – DC and AC
38d. The driver pull-u p current variation within nominal limits of voltage and temper-
ature is expected, but not guaranteed, to lie within the inner bounding lines of the
V-I curve of Figure 12 on page 29.
38e. The full ratio variation of MAX to MIN pull-up and pull-down current should be
between 0.71 and 1.4 for drain-to-source voltages from 0.1V to 1.0V at the same
voltage and temperature.
38f. The full ratio variation of the nominal pull-up to pull-down current should be
unity ±10 percent for device drain-to-source voltages from 0.1V to 1.0V.
Figure 11: Full Drive Pull-Down Characteristics
Figure 12: Full Drive Pull-Up Characteristics
39. Reduced output drive curves:
39a. The full driver pull-down current variation from MIN to MAX process; tempera-
ture and voltage will lie within the outer bounding lines of the V-I curve of
Figure 13 on page30.
39b. The driver pull -down current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I cur ve of Figure13 on page30.
39c. The full driver pull-up current variation from MIN to MAX process; temperature
and voltage will lie within the outer bounding lines of the V-I curve of Figure 14.
0
20
40
60
80
100
120
140
160
0.0 0.5 1.0 1.5 2.0 2.5
IOUT (mA)
VOUT (V)
-200
-180
-160
-140
-120
-100
-8 0
-6 0
-4 0
-2 0
0
0. 0 0 . 5 1. 0 1 . 5 2. 0 2 . 5
I
OUT
(mA)
V
DD
Q - V
OUT
(V)
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Electrical Specifications – DC and AC
39d. The driver pull-up current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I cur ve of Figure14 on page30.
39e. The full ratio variation of the MAX-t o-MIN pull- up and pull-d own current sh ould
be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V at
the same voltage and temperature.
39f. The full ratio variation of the nominal pull-up to pull-down current should be
unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
Figure 13: Reduced Drive Pull-Down Characteristics
Figure 14: Reduced Drive Pull-Up Characteristics
40. The voltage levels used are derived from a minimum VDD level and the referenced test
load. In practice, the voltage levels obtained from a properly terminated bus will pro-
vide significantly different voltage values.
41. VIH overshoot: VIH (MAX) = VDDQ +1.5V for a pulse width ≤ 3ns, and the pulse
width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = –1.5V
for a pulse width ≤ 3ns, and the pulse width can not be greater than 1/3 of th e c ycle
rate.
42. VDD and VDDQ must track each other.
43. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
0
10
20
30
40
50
60
70
80
0 . 00 . 5 1 . 01 . 5
2.0 2.5
IOUT (mA)
VOUT (V)
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.5 1.0 1.5 2.0 2.5
IOUT (mA)
VDDQ - VOUT (V)
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Electrical Specifications – DC and AC
44. tRPST end point and tRPRE begin point ar e not referenced to a specific voltage level
but specify when the device output is no longer driving (tRPST) or begins driving
(tRPRE).
45. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V.
Alternatively, VTT may be 1.35V maximum during po w er up, even if VDD/VDDQ are 0V,
provided a minimum of 42Ω of series resistance is used between the VTT supply and
the input pin.
46. The current Micron part operates below 83 MHz (slowest sp ecified JEDEC operating
frequency). As such, future die may not reflect this option.
47. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
48. Random address is changing; 50 perc ent of data is changing at every transfer.
49. Random address is changing; 100 perc ent of data is changing at every transfer.
50. CKE must be active (HIGH) during the entire time a REFRESH command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satisfied.
51. IDD2N spec ifies the DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level.
IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
52. Whenever the operating frequency is altere d, not including jitter, the DLL is required
to be reset followed by 200 clock cycles before any READ command.
53. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz.
Any noise above 20 MHz at the DRAM generated from any source other than that of
the DRAM itself may not exceed the DC voltage range of 2.6V ±100mV.
54. The -6/-6T speed grades will operate with tRAS (MIN) = 40ns and
tRAS (MAX) = 120,000ns at any slower frequency.
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Electrical Specifications – DC and AC
Table 23: Normal Output Drive Ch aracteristics
Characteristics are specified under best, worst, and nominal process variation/con di tion s
Voltage
(V)
Pull-Down Current (mA) Pull-Up Current (mA)
Nominal
Low Nominal
High Min Max Nominal
Low Nominal
High Min Max
0.1 6.0 6.8 4.6 9.6 –6.1 –7.6 –4.6 –10.0
0.2 12.2 13.5 9.2 18.2 –12.2 –14.5 –9.2 –20.0
0.3 18.1 20.1 13.8 26.0 –18.1 –21.2 –13.8 –29.8
0.4 24.1 26.6 18.4 33.9 –24.0 –27.7 –18.4 –38.8
0.5 29.8 33.0 23.0 41.8 –29.8 –34.1 –23.0 –46.8
0.6 34.6 39.1 27.7 49.4 –34.3 –40.5 –27.7 –54.4
0.7 39.4 44.2 32.2 56.8 –38.1 –46.9 –32.2 –61.8
0.8 43.7 49.8 36.8 63.2 –41.1 –53.1 –36.0 –69.5
0.9 47.5 55.2 39.6 69.9 –43.8 –59.4 –38.2 –77.3
1.0 51.3 60.3 42.6 76.3 –46.0 –65.5 –38.7 –85.2
1.1 54.1 65.2 44.8 82.5 –47.8 –71.6 –39.0 –93.0
1.2 56.2 69.9 46.2 88.3 –49.2 –77.6 –39.2 –100.6
1.3 57.9 74.2 47.1 93.8 –50.0 –83.6 –39.4 –108.1
1.4 59.3 78.4 47.4 99.1 –50.5 –89.7 –39.6 –115.5
1.5 60.1 82.3 47.7 103.8 –50.7 –95.5 –39.9 –123.0
1.6 60.5 85.9 48.0 108.4 –51.0 –101.3 –40.1 –130.4
1.7 61.0 89.1 48.4 112.1 –51.1 –107.1 –40.2 –136.7
1.8 61.5 92.2 48.9 115.9 –51.3 –112.4 –40.3 –144.2
1.9 62.0 95.3 49.1 119.6 –51.5 –118.7 –40.4 –150.5
2.0 62.5 97.2 49.4 123.3 –51.6 –124.0 –40.5 –156.9
2.1 62.8 99.1 49.6 126.5 –51.8 –129.3 –40.6 –163.2
2.2 63.3 100.9 49.8 129.5 –52.0 –134.6 –40.7 –169.6
2.3 63.8 101.9 49.9 132.4 –52.2 –139.9 –40.8 –176.0
2.4 64.1 102.8 50.0 135.0 –52.3 –145.2 –40.9 –181.3
2.5 64.6 103.8 50.2 137.3 –52.5 –150.5 –41.0 –187.6
2.6 64.8 104.6 50.4 139.2 –52.7 –155.3 –41.1 –192.9
2.7 65.0 105.4 50.5 140.8 –52.8 –160.1 –41.2 –198.2
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Electrical Specifications – DC and AC
Table 24: Reduced Output Drive Characteristics
Characteristics are specified under best, worst, and nominal process variation/con di tion s
Voltage
(V)
Pull-Down Current (mA) Pull-Up Current (mA)
Nominal
Low Nominal
High Min Max Nominal
Low Nominal
High Min Max
0.1 3.4 3.8 2.6 5.0 –3.5 –4.3 –2.6 –5.0
0.2 6.9 7.6 5.2 9.9 –6.9 –7.8 –5.2 –9.9
0.3 10.3 11.4 7.8 14.6 –10.3 –12.0 –7.8 –14.6
0.4 13.6 15.1 10.4 19.2 –13.6 –15.7 –10.4 –19.2
0.5 16.9 18.7 13.0 23.6 –16.9 –19.3 –13.0 –23.6
0.6 19.9 22.1 15.7 28.0 –19.4 –22.9 –15.7 –28.0
0.7 22.3 25.0 18.2 32.2 –21.5 –26.5 –18.2 –32.2
0.8 24.7 28.2 20.8 35.8 –23.3 –30.1 –20.4 –35.8
0.9 26.9 31.3 22.4 39.5 –24.8 –33.6 –21.6 –39.5
1.0 29.0 34.1 24.1 43.2 –26.0 –37.1 –21.9 –43.2
1.1 30.6 36.9 25.4 46.7 –27.1 –40.3 –22.1 –46.7
1.2 31.8 39.5 26.2 50.0 –27.8 –43.1 –22.2 –50.0
1.3 32.8 42.0 26.6 53.1 –28.3 –45.8 –22.3 –53.1
1.4 33.5 44.4 26.8 56.1 –28.6 –48.4 –22.4 –56.1
1.5 34.0 46.6 27.0 58.7 –28.7 –50.7 –22.6 –58.7
1.6 34.3 48.6 27.2 61.4 –28.9 –52.9 –22.7 –61.4
1.7 34.5 50.5 27.4 63.5 –28.9 –55.0 –22.7 –63.5
1.8 34.8 52.2 27.7 65.6 –29.0 –56.8 –22.8 –65.6
1.9 35.1 53.9 27.8 67.7 –29.2 –58.7 –22.9 –67.7
2.0 35.4 55.0 28.0 69.8 –29.2 –60.0 –22.9 –69.8
2.1 35.6 56.1 28.1 71.6 –29.3 –61.2 –23.0 –71.6
2.2 35.8 57.1 28.2 73.3 –29.5 –62.4 –23.0 –73.3
2.3 36.1 57.7 28.3 74.9 –29.5 –63.1 –23.1 –74.9
2.4 36.3 58.2 28.3 76.4 –29.6 –63.8 –23.2 –76.4
2.5 36.5 58.7 28.4 77.7 –29.7 –64.4 –23.2 –77.7
2.6 36.7 59.2 28.5 78.8 –29.8 –65.1 –23.3 –78.8
2.7 36.8 59.6 28.6 79.7 –29.9 –65.8 –23.3 –79.7
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Commands
Commands Tables 25 and 26 provide a quick refer ence of available commands . Two additional Truth
Tables—Table 27 on page 35, and Table28 on page 36— provide current state/next state
information.
Notes: 1. DESELECT and NOP are functionally interch a ngeabl e.
2. BA0–BA1 provide bank address and A0–An (128Mb: n = 11; 256Mb and 512Mb: n = 12; 1Gb:
n = 13) provide row address.
3. BA0–BA1 provide bank address; A0–Ai provide column address, (where Ai is the most signif-
icant column address bit for a given density and configuration, see Table 2 on page 2) A10
HIGH enables the auto precharge feature (non persistent), and A10 LOW disables the auto
precharge feature.
4. Applies only to READ bursts with auto pr echa rge disab led; th is c ommand is u ndefi ned (an d
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are pre-
charged and BA0–BA1 are “Don’t Care.”
6. This comm and is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing while in self refresh mode, all inputs and
I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0
select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combina-
tions of BA0–BA1 are reserved). A0–An provide the op-code to be written to the selected
mode register.
Table 25: Truth Ta ble 1 – Commands
CKE is HIGH for all commands shown except SELF REFRESH; All states and sequences not shown are illegal or
reserved
Name (Function) CS# RAS# CAS# WE# Address Notes
DESELECT (NOP) HXXX X 1
NO OPERATION (NOP) LHHH X 1
ACTIVE (select bank and activate row) L L H H Bank/row 2
READ (select bank and column and start READ burst) LHLHBank/col3
WRITE (select bank and column and start WRITE burst) L H L L Bank/col 3
BURST TERMINATE LHHL X 4
PRECHARGE (deactivate row in bank or banks) L L H L Code 5
AUTO REFRESH or SELF REFRESH
(enter self refresh mode) LLLH X6, 7
LOAD MODE REGISTER LLLLOp-code8
Table 26: Truth Table 2 – DM Operation
Used to mask write data, provided coincident wit h the corresponding data
Name (Function) DM DQ
Write enable L Valid
Write inhibit H X
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Commands
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 30 on page 38) and
after tXSNR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that state).
Exceptions ar e covered in the notes below.
3. Current state definitions:
• Idle: The bank has been precharged, and tRP has been met.
• Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
• Read: A READ burst has been initiated, with auto precharge disabled , and has not yet
terminated or been terminated.
• Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COM-
MAND INHIBIT or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determi ned by its current state and Table 27 and according to Table 28 on
page 36.
• Precharging: Starts with registration of a PR ECHARGE command and ends when tRP is
met. Once tRP is met, the bank will be in the idle state.
• Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. Once tRCD is met, the bank will be in the “row active” state.
• Read with auto-precharge enabled: Starts with registration of a READ command with
auto precharge enabled an d ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
• Write with auto-precharge enabled: Starts with registration of a WRITE command with
auto precharge enabled an d ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
5. The following states mus t not be interrupt ed by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Table 27: Truth Ta ble 3 – Current State Bank n – Command to Bank n
Notes: 1–6 apply to entire table; Notes appear below
Current
State CS# RAS# CAS# WE# Command/Action Notes
Any HXX X
DESELECT (NOP/continue previous operation)
LHH H
NO OPERATION (NOP/con tinue previous operation)
Idle LLHH
ACTIVE (select and activate row)
LLL H
AUTO REFRESH 7
LLL L
LOAD MODE REGISTER 7
Row active LHL H
READ (select column and start READ burst) 10
LHL L
WRITE (select column and start WRITE burst) 10
LLH L
PRECHARGE (deactivate row in bank or banks) 8
Read (auto-
precharge
disabled)
LHL H
READ (select column and start new READ burst) 10
LHL L
WRITE (select column and start WRITE burst) 10, 12
LLH L
PRECHARGE (truncate READ burst, start PRECHARGE) 8
LHH L
BURST TERMINATE 9
Write (auto-
precharge
disabled)
LHL H
READ (select column and start READ burst) 10, 11
LHL L
WRITE (select column and start new WRITE burst) 10
LLH L
PRECHARGE (truncate WRITE burst, start PRECHARGE) 8, 11
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128Mb: x4, x8, x16 DDR SDRA M
Commands
• Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC
is met. Once tRFC is met, the DDR SDRAM will be in the all banks idle state.
• Accessing mode register: Starts with registration of a LOAD MODE REG ISTE R comma nd
and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM will be in the
all banks idle state.
• Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. Once tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all ba nks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
bank.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied aft er the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Ta ble 30 on page 38) and
after tXSNR has been met (if the previous state was self refresh).
Table 28: Truth Ta ble 4 – Current State Bank n – Command to Bank m
Notes: 1–6 apply to entire table; Notes appear below
Current State CS# RAS# CAS# WE# Command/Action Notes
Any HX X X
DESELECT (NOP/c ontinue previous operatio n)
LHHH
NO OPERATION (NOP/continue previous operation)
Idle XXX X
Any command otherwise allowed to bank m
Row activating,
active, or
precharging
LLHH
ACTIVE (select and activate row)
LHL H
READ (select column and start READ burst) 7
LHL L
WRITE (select column and start WRITE burst) 7
LLHL
PRECHARGE
Read (auto-
precharge
disabled)
LLHH
ACTIVE (select and activate row)
LHL H
READ (select column and start new READ burst) 7
LHL L
WRITE (select column and start WRITE burst) 7, 9
LLHL
PRECHARGE
Write (auto-
precharge
disabled)
LLHH
ACTIVE (select and activate row)
LHL H
READ (select column and start READ burst) 7, 8
LHL L
WRITE (select column and start new WRITE burst) 7
LLHL
PRECHARGE
Read
(with auto-
precharge)
LLHH
ACTIVE (select and activate row)
LHL H
READ (select column and start new READ burst) 7
LHL L
WRITE (select column and start WRITE burst) 7, 9
LLHL
PRECHARGE
Write
(with auto-
precharge)
LLHH
ACTIVE (select and activate row)
LHL H
READ (select column and start READ burst) 7
LHL L
WRITE (select column and start new WRITE burst) 7
LLHL
PRECHARGE
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128Mb: x4, x8, x16 DDR SDRA M
Commands
2. This table describes alternate bank operation, except where noted (i.e., the current state is
for bank n, and the commands shown are those allowed to be issued to bank m, assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
• Idle: The bank has been precharged, and tRP has been met.
• Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
• Read: A READ burst has been initiated, with auto precharge disabled , and has not yet
terminated or been terminated.
• Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
• Read with auto precharge enabled: See note 3a below.
• Write with auto precharge enabled: See note 3a below.
a. The read with auto precharge enabled or write with auto precharge enabled states
can each be broken into two parts: the access period and the precharge period. For
read with auto precharge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all of the data in the burst. For write with
auto precharge, the precharge period begins when tWR ends, with tWR measured as
if auto precharge was disabled. The access period starts with registration of the com-
mand and ends where the precharge period (or tRP) beg ins. This device supports
concurrent auto precharge such that when a read with auto precharge is enabled or
a write with auto precharge is enabled, any command to other banks is allowed, as
long as that command does not interrupt the read or write data transfer already in
process. In either case, all other related limitations apply (e.g., contention be tween
read data and write data must be avoided).
b. The minimum delay from a READ or WRITE command with auto precharge enabled,
to a command to a different bank is summarized in Table 29.
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks
are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the “Command/Action” column include READ s or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
Table 29: Command Delays
CLRU = CL rounded up to the next integer
From
Command To Command Minimum Delay
(with Concurrent Auto Precharge)
WRITE with auto
precharge READ or READ with auto precharge [1 + (BL/2)] × tCK + tWTR
WRITE or WRITE with auto precharge (BL/2) × tCK
PRECHARGE 1 tCK
ACTIVE 1 tCK
READ with auto
precharge READ or READ with auto precharge (BL/2) × tCK
WRITE or WRITE with auto precharge [CLRU + (BL/2)] × tCK
PRECHARGE 1 tCK
ACTIVE 1 tCK
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128Mb: x4, x8, x16 DDR SDRA M
Commands
9. A WRITE command may be applied after the completion of the READ burst; otherwise , a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COM-
MANDn.
4. All states and sequences not shown are illegal or reserved.
5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay
HIGH until after the read postamble time (tRPST); for a WRITE, CKE must stay HIGH until the
write recovery time (tWR) has been met.
6. Once initialized, including during self refresh mode, VREF must be powered within the spec-
ified range.
7. Upon exit of the self refresh mode, the DLL is automatically enabled. A minimum of 200
clock cycles is needed before applying a READ command for the DLL to lock. DESELECT or
NOP commands should be issued on any clock edges occurr ing during the tXSNR period.
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to
perform a NOP (CS# is LOW with RAS#, CAS#, and WE# are HIGH). This prevents
unwanted commands from be ing registered during id le or wait states. Operations
already in progress are not affected.
LOAD MODE REGISTER (LMR)
The mode registers are loaded via inputs A0–An (see "REGISTER DEFINITION" on page
45). The LOAD MODE REGISTER command can only be issued when all banks are idle,
and a subsequent executable command cannot be issued until tMRD is met.
Table 30: Truth Table 5 – CKE
Notes 1–6 apply to entire table; Notes appear below
CKEn-1 CKEnCurrent State CommandnActionnNotes
L L Power-down X Maintain power-down
Self refresh X Maintain self refresh
L H Power-down DESELECT or NOP Exit power-down
Self refresh DESELECT or NOP Exit self refresh 7
H L All banks idle DESELECT or NOP Precharge power-down entry
Bank(s) active DESELECT or NOP Active power-down entry
All banks idle AUTO REFRESH Self refresh entry
H H See Table 25 on page 34
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128Mb: x4, x8, x16 DDR SDRA M
Commands
ACTIVE (ACT)
The AC TIVE command is used to open (or activate) a row in a particular bank for a
subsequent access, like a read or a write, as shown in Figure15. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0–An selects the row.
Figure 15: Activating a Specific Row in a Specific Bank
READ
The READ command is used to initiate a burst read access to an active row, as shown in
Figur e16 on page40. The v alue on the BA0, BA1 inputs sel ects the bank, and the addr ess
pro vided on inputs A0–Ai (where Ai is the most significant column add ress bit for a given
density and config uration, se e Table 2 on page 2) selects the starting column location.
CS#
WE#
CAS#
RAS#
CKE
ADDRESS
Row
HIGH
BA0, BA1
Bank
CK
CK#
DON’T CARE
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128Mb: x4, x8, x16 DDR SDRA M
Commands
Figure 16: READ Command
Note: EN AP = enable auto precharge; DISAP=disableautoprecharge.
WRITE
The WRITE command is used to initiate a burst write access to an active ro w as sho wn in
Figure 17. The value on the BA0, BA1 inputs selects the ba nk, and the address provided
on inputs A0–Ai (where Ai is the most significant column address bit for a given density
and configuration, see Table 2 on page2) selects the starting colum n lo cation.
Figure 17: WRITE Command
Note: EN AP = enable auto precharge; and DIS AP = disable auto precharge.
CS#
WE#
CAS#
RAS#
CKE
Col
ADDRESS
A10
BA0, BA1
HIGH
EN AP
DIS AP
Bank
CK
CK#
DON’T CARE
CS#
WE#
CAS#
RAS#
CKE
Col
A10
BA0, BA1
HIGH
EN AP
DIS AP
Bank
CK
CK#
DON’T CARE
ADDRESS
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128Mb: x4, x8, x16 DDR SDRA M
Commands
PRECHARGE (PRE)
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open ro w in all b anks as sho wn in F igure18. The value on the BA0, BA1 inputs selects
the bank, and the A10 input selects whether a single bank is precharged or whether all
banks are precharged.
Figure 18: PRECHARGE Command
Notes: 1. If A10 is HIGH, bank address becomes “Don’t Care”.
BURST TERMINATE (BST)
The BURST TERMINATE command is used to truncate READ bursts (with auto
precharge disabled). The most recently registered READ command pr ior to the BURST
TERMINATE command will be truncated, as shown in “Operations” on page 42. The
open page from which the READ burst was terminated r emains open.
AUTO REFRESH (AR)
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous
to CAS#-before-RAS# (CBR) re fresh in FPM/EDO DRAMs. This command is nonpersis-
tent, so it must be issued each time a refresh is required. All banks must be idle before an
AU TO REFRESH command is issued.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the
rest of the system is powered down. The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled (LOW).
CS#
WE#
CAS#
RAS#
CKE
A10
BA0, BA1
HIGH
ALL BANKS
ONE BANK
Bank1
ADDRESS
CK
CK#
DON’T CARE
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Operations
INITIALIZATION
Prior to normal operation, DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures, other than those specified, may result in
undefined operation.
To ensure device operation, the DRAM must be initialized as des c ribed in the following
steps:
1. S i multaneously apply power to VDD and VDDQ.
2. Apply VREF and then VTT power. VTT must be applied after VDDQ to avoid device latch-
up, which may cause permanent damage to the device. Exept for CKE, inputs are not
recognized as valid until after VREF is applied.
3. Assert and hold CKE at a LVCMOS logic LOW. Maintaining an LVCMOS LOW level on
CKE during power-up is required to ensure that the DQ and DQS outputs will be in
the High-Z state, where they will remain until driven in norm al operation (by a read
access).
4. Provide stab le cloc k si gnals.
5. Wait at least 200µs.
6. Bring CKE HIGH, and provide at least one NOP or DESELECT command. At this
point, the CKE input changes from a LVCMOS input to a SSTL_2 input only and will
remain a SSTL_2 input unless a power cycle occurs.
7. Perform a PRECHARGE ALL command.
8. Wait at least tRP time; during this time NOPs or DESELECT commands must be given.
9. Usin g the LMR command, program the extended mode register (E0 = 0 to enable the
DLL and E1 = 0 for normal drive; or E1 = 1 for reduced drive and E2–En must be set to
0 [where n = most significant bit]).
10. Wait at least tMRD time; only NOPs or DESELECT commands are allo wed.
11. Using the LMR command, program the mode register to set operating para meters
and to reset the DLL. At least 200 clock cycles are requir ed between a DLL reset and
any READ command.
12. Wait at least tMRD time; only NOPs or DESELECT commands are allowed.
13. Issue a PRECHARGE ALL command.
14. Wait at least tRP time; only NOPs or DESELECT commands are allowed.
15. Issue an AUTO REFRESH command. This may be moved prior to step 13.
16. Wait at least tRFC time; only NOPs or DESELECT commands are allowed.
17. Issue an AUTO REFRESH command. This may be moved prior to step 13.
18. Wait at least tRFC time; only NOPs or DESELECT commands are allowed.
19. Although not required by the Micron device, JEDEC requires an LMR command to
clear the DLL bit (set M8 = 0). If an LMR command is issued, the same operating
parameters should be utilized as in step 11.
20. Wait at least tMRD time; only NOPs or DESELECT commands are allo wed.
21. At this point the DRAM is ready for any valid command. At least 200 clock cycles with
CKE HIGH are required between step 11 (DLL RESET) and any READ command.
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 19: INITIALIZ ATION Flow Diagram
V
DD
and V
DD
Q ramp
Apply V
REF
and V
TT
CKE must be LVCMOS LOW
Apply stable CLOCKs
Bring CKE HIGH with a NOP command
Wait at least 200µs
PRECHARGE ALL
Assert NOP or DESELECT for tRP time
Configure extended mode register
Configure load mode register and reset DLL
Assert NOP or DESELECT for tMRD time
Assert NOP or DESELECT for tMRD time
PRECHARGE ALL
Issue AUTO REFRESH command
Assert NOP or DESELECT for tRFC time
Optional LMR command to clear DLL bit
Assert NOP or DESELECT for tMRD time
DRAM is ready for any valid command
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Assert NOP or DESELECT commands for tRFC
Issue AUTO REFRESH command
Assert NOP or DESELECT for tRP time
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 20: INITIALIZATION Timing Diagram
Notes: 1. VTT is not applied directly to the device; however, tVTD ≥ 0 to avoid device latch-up. VDDQ,
VTT, and V REF ≤ VDD + 0.3V. Alternatively, VTT may be 1.35V maximum du ring power up,
even if VDD/VDDQ are 0V, provided a minimum of 42 ohms of series resistance is used
between the VTT supply and the input pin. Once initialized, VREF must always be powered
within the specified range.
2. Although not required by the Micron device, JEDEC specifies issuing another LMR command
(A8 = 0) prior to activating any bank. If another LMR command is issued, the same, previ-
ously issued operating parameters must be used.
3. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LOAD
MODE REGISTER (LMR) command at Ta0.
4. tMRD is required before any command can be applied (during MRD time only NOPs or
DESELECTs are allowed), and 200 cycles of CK are required before a READ command can be
issued.
5. While programming the operating parameters, reset the DLL with A8 = 1.
t
VTD1
CKE LVCMOS
LOW LEVEL
DQ
BA0, BA1
200 cycles of CK4
Load extended
mode register Load mode
register5
tMRD tMRD tRP tRFC tRFC
t
IS
Power-up: V
DD
and CK stable
T = 200µs
High-Z
t
IH
DM
DQS High-Z
ADDRESS
RA
A10 ALL BANKS
CK
CK#
t
CH
t
CL
t
CK
V
TT
1
dc
V
REF
V
DD
V
DD
Q
COMMAND LMRNOP PRELMR AR AR ACT2
t
IS t
IH
BA0 = 1
BA1 = 0
t
IS t
IH
t
IS
t
IH
BA0 = 0
BA1 = 0
t
IS t
IH
(
) (
)
(
) (
)
(
) (
)
(
) (
)
CODE CODE
t
IS t
IH
CODE CODE3
PRE
ALL BANKS
t
IS t
IH
T0 T1 Ta0 Tb0 Tc0 Td0 Te0 Tf0
(
) (
)
DON’T CARE
BA
(
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(
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RA
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 45 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Operations
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific DDR SDRAM mode of operation. This
definition includes the selection of a burst length, a burst type, a CAS latency, and an
operating mode, as shown in Figure 21. The mode register is programmed via the LMR
command (with BA0=0 and BA1=0) and will retain the stored information until it is
programmed again or until the device loses power (except for bit A8, which is self-
clearing).
Repr og r ammi ng the mode r e gister wil l not alter the contents of the memory, provided it
is performed correctly. The mode register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller m ust wai t the specifi ed tim e before
initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length , A3 specifies the type of burst (sequen-
tial or interleaved), A4–A6 specify the CAS latency, and A7–An specify the operating
mode.
Figure 21: Mode Register Definition
Notes: 1. n is the most significant row address bit from Table 2 on page 2.
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3 (-5B only)
Reserved
Reserved
2.5
Reserved
Burst lengthCAS La t e n c y BT0
A9 A7 A6 A5 A4 A3A8 A2 A1 A0
Mode Register
(Mx)
Address Bus
976543
8210
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
Operating mode
...AnBA0BA1
...
n1
n+1
0
n+2
Operating Mode
Normal operation
Normal operation/reset DLL
All other states reserved
0
1
–
0
0
–
0
0
–
0
0
–
0
0
–
Valid
Valid
–
M6–M0
M8 M7
M9...Mn
Burst Length
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M0
0
1
0
1
0
1
0
1
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
Mn+1
0
1
0
1
Mode Register Definition
Base mode register
Extended mode register
Reserved
Reserved
Mn+2
0
0
1
1
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Burst Length (BL)
Read and write accesses to the DDR SDRAM are burst oriented , with the burst length
being programmable for both READ and WRITE bursts, as shown in Figure21 on
page 45. The burst length determines the maximum number of column locations that
can be accessed for a given READ or WRITE command. BL = 2, BL = 4, or BL = 8 locations
are available for both the sequential and the interleaved burst types. Reserved states
should not be used, as unknown operation or incompatibility with future versions may
result.
When a READ or WRITE comm and is issu ed , a block of col u m n s eq ual to the bu rst
length is effectively se lected. All accesses for that burst take place within this block—
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–Ai when BL = 2, by A2–Ai when BL = 4, and by A3–Ai when
BL = 8 (where Ai is the most significant column address bit for a given configuration).
The remai ning (least significant) addr ess bit(s) i s (are ) used to select t he starting location
within the block. For example: for BL = 8, A3–Ai select the eight-data-el em ent block; A0–
A2 select the first access within the block.
Burst Type
Accesse s within a given b urst may be progr ammed to be eithe r sequential or interleaved;
this is referred to as the burst typ e and is selected via bit M3.
The ordering of accesses within a burst is determined b y the burst lengt h, the burst t ype ,
and the starting column address, as shown in Table 31.
Table 31: Burst Definition
Burst Length Starting Column Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
2––A0 ––
––0 0-1 0-1
––1 1-0 1-0
4–A1 A0 ––
– 0 0 0-1-2-3 0-1-2-3
– 0 1 1-2-3-0 1-0-3-2
– 1 0 2-3-0-1 2-3-0-1
– 1 1 3-0-1-2 3-2-1-0
8A2 A1 A0 ––
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
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128Mb: x4, x8, x16 DDR SDRA M
Operations
CAS Latency (CL)
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (-5B
only) clocks, as shown in Figure 22. Reserved states should not be used, as unknown
operation or incompatibilit y with future versions may result.
If a READ command is registered at clock edge n, and the latency is m clock s, the da ta
will be available nomina ll y co i nci dent with clock edge n + m. Table 32 on page 48 indi-
cates the operating frequencies at which each CL setting can be used.
Figure 22: CAS Latency
Note: BL = 4 in the cases shown; shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND
DQ
DQS
CL = 2
READ NOP NOP NOP
READ NOP NOP NOP
CK
CK#
COMMAND
DQ
DQS
CL = 2.5
T
0
T1 T
2
T
2
n T
3
T
3
n
T0 T1 T2 T2n T3 T3n
DON’T CARE TRANSITIONING DATA
READ NOP NOP NOP
CK
CK#
COMMAND
DQ
DQS
CL = 3
T0 T1 T2 T3 T3n
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 48 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Operations
Operating Mode
The normal operating mode is selected by issuing a LOAD MO DE REGISTER command
with bits A7–An each set to zero and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing an LMR command with bits A 7 and A9–An each set to zero, bit A8 set
to one, and bit s A0–A6 set to the desired values. Although not required by the Micron
device, JEDEC specifications reco mmend that a LOAD MODE REGISTER command
resetting the DLL should always be followed by a LOAD MODE REGISTER command
selecting normal operating mode.
All other combinations of values for A7–An are reserved for future use and/or test
modes . Test modes and reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
Extended Mode Register
The extended mode register controls functions beyond those controlled by the mode
r egister; these additional fu nctions are DLL enable/disable and output drive strength.
These functions ar e controlled via the bits shown in Fi gure 23 on page 49. The extended
mode register is programmed via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the stored informat ion unti l it is
programmed again or until the device loses power. The enabling of the DLL should
always be followed by an LMR command to the mode register (BA0/BA1 = 0) to reset the
DLL. The extended mode register must be loaded when all banks are idle and no bursts
are in progre ss, and the cont roll er mus t w ait the specified time before initiating any
subsequent operation . V iol ati ng either requirement could result in an unspecified oper-
ation.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. The x16
supports a programmable option for reduced drive. This option is intended for the
support of the lighter load and/or point-to-point environments. The sele ction of the
reduced drive strength will alter the DQ and DQS pins from SSTL_2, Class II drive
strength to a reduced drive strength, which is approximately 54 percent of the SSTL_2,
Class II drive strength.
DLL Enable/Disable
When the part is running without the DLL enabled, device functionality may be altered.
The DLL must be enabled for normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation after having disabled the DLL
for the purpose of debug or evaluati on (when the devi ce exits sel f refresh mode , the DLL
is enabled automatically). Anytime the DLL is enabled, 200 clock cycles with CKE HIGH
must occur befor e a READ command can be issued.
Table 32: CAS La tency
Speed
Allowable Operating Clock Frequency (MHz)
CL = 2 CL = 2.5 CL = 3
-5B 75 ≤ f ≤ 133 75 ≤ f ≤ 167 133 ≤ f ≤ 200
-6/-6T 75 ≤ f ≤ 133 75 ≤ f ≤ 167 –
-75E 75 ≤ f ≤ 133 75 ≤ f ≤ 133 –
-75Z 75 ≤ f ≤ 133 75 ≤ f ≤ 133 –
-75 75 ≤ f ≤ 100 75 ≤ f ≤ 133 –
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 23: Extended Mode Register Definition
Notes: 1. n is the most significant row address bit from Table 2 on page 2.
2. The reduced drive strength option is available only on the x16 version. The reduced drive
strength option is not supported on the x4 and x8 versions; contact Micron for future sup-
port of this feature.
3. The QFC# option is not supported.
ACTIVE
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For e xample, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period)
results in 2.7 clocks rounded to 3. This is reflected in Figure 24 on page 50 , which c overs
any case wher e 2 < tR CD (MIN)/tCK ≤ 3 (Figure24 also s ho ws the same case for tRRD; the
same procedure is used to convert other specification limits from time units to clock
cycles).
A row remains active (or open) for accesses until a PRECHARGE command is issued to
that bank. A PRECHARGE command must be issued before opening a different row in
the same bank.
A subsequent ACTIVE command to a differ ent row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which resul ts in a r eduction of total r o w-access o verhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
tRRD.
Operating Mode
Reserved
Reserved
0
–
0
–
V alid
–
DLL
Enable
Disable
10
A9 A7 A6 A5 A4 A3 A8 A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
976543821
0
1
E0
0
1
Drive Strength
Normal
Reduced
E12
E23E0
E1,
Operating Mode
...AnBA1 BA0
...n1
n+1n+2
E3 E4
0
–
0
–
0
–
0
–
0
–
E6 E5
E7 E8 E9
0
–
0
–
...En
DS
0
–
Mn+1
0
1
0
1
Mode Register Definition
Base mode register
Extended mode register
Reserved
Reserved
Mn+2
0
0
1
1
DLL
0
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 24: Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK ≤ 3
READ
During the READ command, the value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the READ burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
Note: For the READ com mands used in th e fol lowing illustrations, auto precharge is dis-
abled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid nominally at the next positive or negative clock edge (i.e., at the
next crossing of CK and CK#). Figure 25 on page 52 shows the general timing for each
possible CL setting. DQS is driven by the DDR SDRAM along with output data. The
initial LOW state on DQS is known as the read preamble; the LOW state coincident with
the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. Detailed explanations of tDQSQ (valid data-out skew), tQH (data-out
window hold), and the valid data window are depicted in Figure33 on page 60 and
Figure 34 on page 61. Detailed explanations of tDQSCK (DQS transition skew to CK) and
tAC (data- out transition skew to CK) are depicted in Figure35 on page 62.
Data from any READ burst may be concatenated or truncated with data from a subse-
quent READ command. In either case , a continuous flo w of data can be maintained. The
first data element from the new burst follows either the last element of a completed
burst or the last desire d data element of a longer burst which is being truncated. The
new READ command should be issued x cycl es afte r the firs t RE AD com mand, where x
equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 26 on page 53. A READ command can be initiated
on any clock cycle following a previous READ command. Nonconsecutive read data is
illustrated in Figure 27 on page 54. Full-speed random read accesses within a page (or
pages) can be performed, as shown in Figure 28 on page 55.
t
COMMAND
BA0, BA1
ACT ACT
NOP
RRD tRCD
CK
CK#
Bank xBank y
ADDRESS Row Row
NOP RD/WR
NOP
Bank y
Col
NOP
T
0
T1 T
2
T
3
T4 T5 T
6
T7
DON’T CARE
NOP
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure29 on page 56. The BURST TERMINATE latency is equal to the CL, that
is, the BURST TERMINATE command should be issued x cy cles after the READ
command where x equals the number of desired data element pairs (pairs are required
by the 2n-p refetch arc hitecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure30 on pag e57. The tDQSS (NOM) case is shown; the
tDQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and tDQSS [MAX] are
defined in the section on WRITEs.) A READ burst may be followed by, or truncated with,
a PRECHARGE command to the same bank prov ided that auto precharge was not acti-
vated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desir ed data element pairs (pairs are requir ed by the 2n-prefetch
architecture). This is shown in Figure31 on page58. Following the PRECHARGE
command, a subsequent command to the same bank cannot be issued until both tRAS
and tRP hav e been met. Part of the ro w pre charge time is hidden during the access of the
last data elements.
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 25: READ Burst
Notes: 1. DO n = data-out from column n.
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND READ NOP NOP NOP NOP NOP
ADDRESS
READ NOP NOP NOP NOP NOP
CL = 2
CK
CK#
COMMAND
ADDRESS
DQ
DQS
CL = 2.5
DQ
DQS
DO
n
DO
n
T0 T1 T2 T3T2n T3n T4 T5
T0 T1 T2 T3T2n T3n T4 T5
DON’T CARE TRANSITIONING DATA
READ NOP NOP NOP NOP NOP
CK
CK#
COMMAND
ADDRESS
DQ
DQS
CL = 3
DO
n
T0 T1 T2 T3 T4nT3n T4 T5
Bank a,
Col n
Bank a,
Col n
Bank a,
Col n
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 26: Consecutive READ Bursts
Notes: 1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts
the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent ele m ents of data-out appear in the programmed order follow-
ing DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. Example applies only when READ commands are issued to same device.
CK
CK#
COMMAND READ NOP READ NOP NOP NOP
ADDRESS
COMMAND READ NOP READ NOP NOP NOP
ADDRESS
CL = 2
CK
CK#
DQ
DQS
CL = 2.5
DQ
DQS
DO
nDO
b
DO
nDO
b
T0 T1 T2 T3T2n T3n T4 T5T4n T5n
T0 T1 T2 T3T2n T3n T4 T5T4n T5n
DON’T CARE TRANSITIONING DATA
COMMAND READ NOP READ NOP NOP NOP
ADDRESS
CK
CK#
DQ
DQS
CL = 3
DO
nDO
b
T0 T1 T2 T3 T3n T4 T5T4n T5n
Bank,
Col nBank,
Col b
Bank,
Col nBank,
Col b
Bank,
Col nBank,
Col b
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 27: Nonconsecutive READ Bursts
Notes: 1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts
the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent ele m ents of data-out appear in the programmed order follow-
ing DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND READ NOP NOP NOP NOP NOP
ADDRESS
READ
COMMAND
ADDRESS
CL = 2
CK
CK#
DQ
DQS
CL = 2.5
DQ
DQS
DO
n
T0 T1 T2 T3T2n T3n T4 T5 T5n T6
READ NOP NOP NOP NOP NOPREAD
T0 T1 T2 T3T2n T3n T4 T5 T5n T6
DO
b
DO
nDO
b
DON’T CARE TRANSITIONING DATA
COMMAND
ADDRESS
CK
CK#
DQ
DQS
CL = 3
READ NOP NOP NOP NOP NOPREAD
T0 T1 T2 T3 T3n T4 T5 T6
DO
nDO
b
T4n
Bank,
Col nBank,
Col b
Bank,
Col nBank,
Col b
Bank,
Col nBank,
Col b
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 55 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 28: Random READ Accesses
Notes: 1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
2. BL = 2, BL = 4, or BL = 8 (if BL = 4 or BL = 8, the following burst interrupts the previous).
3. n', x', b', or g' indicate the next data-out following DO n, DO x, DO b, or DO g, respectively.
4. READs are to an active row in any bank.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND READ READ READ NOP NOP
ADDRESS
READ
COMMAND
ADDRESS
CL = 2
CK
CK#
DQ
DQS
CL = 2.5
DQ
DQS
DO
nDO
x' DO
g
DO
n' DO
b
DO
xDO
b'
DO
nDO
x'
DO
n' DO
b
DO
xDO
b'
T0 T1 T2 T3T2n T3n T4 T5T4n T5n
READ READ READ NOP NOPREAD
T0 T1 T2 T3T2n T3n T4 T5T4n T5n
DON’T CARE TRANSITIONING DATA
COMMAND
ADDRESS
CK
CK#
DQ
DQS
CL = 3
DO
nDO
x'
DO
n' DO
b
DO
xDO
b'
READ READ READ NOP NOPREAD
T0 T1 T2 T3 T3n T4 T5T4n T5n
Bank,
Col nBank,
Col b
Bank,
Col xBank,
Col g
Bank,
Col nBank,
Col b
Bank,
Col xBank,
Col g
Bank,
Col nBank,
Col b
Bank,
Col xBank,
Col g
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 29: Terminating a READ Burst
Notes: 1. Page remains open.
2. DO n = data-out from column n.
3. BL = 4.
4. Subsequent element of data-out appears in the programmed order follow ing DO n.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND READ NOP NOP NOP NOP
ADDRESS Bank a,
Col n
READ NOP NOP NOP NOP
Bank a,
Col n
CL = 2
CK
CK#
COMMAND
ADDRESS
DQ
DQS
CL = 2.5
DQ
DQS
DO
n
DO
n
T0 T1 T2 T3T2n T4 T5
T0 T1 T2 T3T2n T4 T5
DON’T CARE TRANSITIONING DATA
READ NOP NOP NOP NOP
Bank a,
Col n
CK
CK#
COMMAND
ADDRESS
DQ
DQS
CL = 3
DO
n
T0 T1 T2 T3 T3n T4 T5
BST1
BST1
BST1
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 30: READ-to-WRITE
Notes: 1. Page remains open.
2. DO n = data-out from column n; DI b = data-in from column b.
3. BL = 4 (applies for bursts of 8 as well ; if BL = 2, the BURST command shown can be NOP).
4. One subse quent element of data-out appears in the programmed order following DO n.
5. Data-in ele ments are applied following DI b in the programmed order.
6. Shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND READ BST1NOP NOP NOP
ADDRESS Bank,
Col n
WRITE
Bank,
Col b
T0 T1 T2 T3T2n T4 T5T4n T5n
DQ
DQS
DM
t
(NOM)
DQSS
DI
b
CK
CK#
COMMAND READ BST1NOP WRITE NOP
ADDRESS Bank a,
Col n
NOP
T0 T1 T2 T3 T3n T4 T5 T5n
DQ
DQS
DO
n
DM
DON’T CARE TRANSITIONING DATA
DO
n
t
(NOM)
DQSS
CK
CK#
COMMAND READ NOP NOP
ADDRESS Bank,
Col n
WRITE
Bank,
Col b
T0 T1 T2 T3T2n T4 T5 T5n
DQ
DQS
DM
t
(NOM)
DQSS
DI
b
DO
n
NOP
CL = 2.5
CL = 2
T3n
CL = 3
DI
b
BST1
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 58 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 31: READ-to-PRECHARGE
Notes: 1. Provided tRAS (MIN) is met, a READ command with auto precharge enabled would cause a
precharge to be performed at x number of clock cycles after the READ command, where
x=BL/2.
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
assumed that tRAS (MIN) is met.
7. An ACTIVE command to the same bank is only allowed if tRC (MIN) is met.
CK
CK#
COMMAND READ NOP PRE NOP NOP ACT
ADDRESS Bank a,
Col nBank a,
(a or all)Bank a,
Row
READ NOP PRE NOP NOP ACT
Bank a,
Col n
CL = 2 tRP
tRP
CK
CK#
COMMAND
ADDRESS
DQ
DQS
CL = 2.5
DQ
DQS
DO
n
DO
n
T0 T1 T2 T3T2n T3n T4 T5
T0 T1 T2 T3T2n T3n T4 T5
Bank a,
(a or all)Bank a,
Row
READ NOP PRE NOP NOP ACT
Bank a,
Col n
tRP
CK
CK#
COMMAND
ADDRESS
DQ
DQS
CL = 3
DO
n
T0 T1 T2 T3 T4nT3n T4 T5
Bank a,
(a or all)Bank a,
Row
DON’T CARE TRANSITIONING DATA
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 32: Bank READ – Without Auto Precharge
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. The PRECHARGE command can only be applied at T5 if tRAS (MIN) is met.
4. Disable aut o pr echarge.
5. “Don’t Care” if A10 is HIGH at T5.
6. DO n (or b) = data-out from column n (or column b); subsequent elements are provided in
the programmed order.
7. Refer to Figure 33 on page 60, Figure 34 on page 61, and Figure 35 on page 62 for detailed
DQS and DQ timing.
CK
CK#
CKE
A10
BA0, BA1
tCK tCH tCL
tIS
tIS
tIH
tIS
tIS
tIH
tIH
tIH
tIS tIH
tRCD
tRC
tRP
CL = 2
DM
T0 T1 T2 T3 T4 T5 T5n T6nT6 T7 T8
DQS
Case 1: tAC
(
MIN)
and tDQSCK
(
MIN)
Case 2: tAC
(
MAX)
and tDQSCK
(
MAX)
DQS
t
RPRE
tRPRE
tRPST
tRPST
t
DQSCK
(
MIN)
t
LZ
(
MIN)
t
AC
(
MIN)
t
LZ
(
MIN)
DO
n
t
HZ
(
MAX)
t
AC
(
MAX)
DO
n
ACT
Col n
Bank xBank x
ACT
Bank x
ONE BANK
ALL BANKS
DON’T CARE TRANSITIONING DATA
t
DQSCK (MAX)
C
OMMAND NOP1NOP1NOP1NOP1NOP1
READ2PRE3
4
Bank x5
tRAS3
ADDRESS Row
Row
Row
Row
DQ
DQ
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Operations
Figure 33: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window
Notes: 1. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
2. tDQSQ is derive d at each DQS clock edge, is not cumulative over time, begins with DQS
transition, and ends w ith the last valid DQ transition.
3. DQs transitioning after DQS transition define the tDQSQ window . DQS transitions at T2 and
T2n are an “early DQS”; at T3, a “nominal DQS”; and at T3n, a “late DQS”.
4. For a x4, only two DQs apply.
5. tQH is derived from tHP: tQH = tHP - tQHS.
6. The data valid window is derived for each DQS transitions and is defined as tQH - tDQSQ.
DQ (last data valid)
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQS3
DQ (last data valid)
DQ (first data no longer valid)
DQ (first data no longer valid)
All DQ and DQS, collectively6
Earliest signal transition
Latest signal transition
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
CK
CK#
T1 T
2
T
3
T4 T
2
n T
3
n
tQH5
tHP
1
tHP
1
tHP
1
tQH5tQH5
tHP
1
tHP
1
tHP
1
tQH5
tDQSQ
2
tDQSQ
2
tDQSQ
2
tDQSQ
2
Data
valid
window
Data
valid
window
Data
valid
window
Data
valid
window
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 34: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window
Notes: 1. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
2. tDQSQ is derive d at each DQS clock edge, is not cumulative over time, begins with DQS
transition, and ends w ith the last valid DQ transition.
3. DQs transitioning after DQS transition define the tDQSQ window. LDQS defines the lower
byte, and UDQS defines the upper byte.
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5. tQH is derived from tHP: tQH = tHP - tQHS.
6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.
7. DQ8, DQ9, DQ10, D11 , DQ12, DQ13, DQ14, or DQ15.
DQ (last data valid)4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
LDQS3
DQ (last data valid)4
DQ (first data no longer valid)4
DQ (first data no longer valid)4
DQ0–DQ7 and LDQS, collectively6
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
CK
CK#
T1 T
2
T
3
T4 T
2
n T
3
n
tQH5tQH5
tDQSQ
2
tDQSQ
2
tDQSQ
2
tDQSQ
2
Data valid
window Data valid
window
DQ (last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
UDQS3
DQ (last data valid)7
DQ (first data no longer valid)7
DQ (first data no longer valid)7
DQ8–DQ15 and UDQS, collectively6
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
tQH5tQH5tQH5tQH5
tDQSQ2tDQSQ2tDQSQ2
tDQSQ2
tHP
1
tHP
1
tHP
1
tHP
1
tHP
1
tHP
1
tQH5
tQH5
Data valid
window
Data valid
window Data valid
window Data valid
window Data valid
window
Upper Byte
Lower Byte
Data valid
window
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 35: Data Output Timing – tAC and tDQSCK
Notes: 1. READ command with CL = 2 issued at T0.
2. tDQSCK is the DQS output window relative to CK and is the “long term” component of the
DQS skew.
3. DQs transitioning after DQS transition define the tDQSQ window.
4. All DQs mus t transition by tDQSQ after DQS transitions, regardless of tAC.
5. tAC is the DQ output window relative to CK and is the “long term” component of DQ skew.
6. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.
7. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.
WRITE
During a WRITE command, the value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst (after tWR time); if auto precharge is not
selected, the row will remain open for subseq uent accesses.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM sig nal is r egi ster ed LO W, the
corresponding data will be written to memory. If the DM signal is registered HIGH, the
corresponding data inputs will be igno red, and a WRITE will not be executed to that
byte/column location.
Note: Fo r the WRITE commands used in the following illustrations, auto precharge is dis-
abled.
During WRITE bursts, the first valid data-in element will be registered on the first risi ng
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamb le; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time betwe en the WRIT E command and the first corresponding rising ed ge of DQS
(tDQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one
clock cycle). All of the WRITE diagrams show the nominal case, and where the two
extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intuitive; they have
CK
CK#
DQS or LDQS/UDQS3
T1 T2 T3 T4 T5
T2n T3n T4n T5n T6
tRPST
tLZ (MIN)
tDQSCK2 (MAX)
tDQSCK2 (MIN) tDQSCK2 (MAX)
tDQSCK2 (MIN)
tHZ (MAX)
tRPRE
All DQ values collectively4
tAC5
(MIN) tAC5
(MAX)
tLZ (MIN) tHZ (MAX)
T2
T2
T2n T3n T4n T5n
T2n
T2n
T3n
T3n
T4n
T4n
T5n
T5n
T3
T4
T4
T5
T5
T2 T3 T4 T5
T3
DQ (last data valid)
DQ (first data valid)
T01
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Operations
also been included. Figure 36 on page 64 shows the nominal case and the extremes of
tDQSS for BL = 4. Upon completion of a burst, assuming no other commands have been
initiated, the DQ will remain High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can b e maintai n e d.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst which is being truncated. The new WRITE command should be issued x cycles
after the first WRITE command, where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architecture).
Figure 37 on page 65 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure38 on page 66. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 39 on page 66.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst, tWTR should be met, as shown in Figure 40
on page 67.
Data for any WRITE burst may be truncated b y a subsequent READ command, as shown
in Figure 41 on page 68.
Note that only the data-in pairs that are registered prior to the tWTR period are written
to the internal array, and any subsequent data-in should be masked with DM, as shown
in Figure 42 on page 69.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst, tWR should be met, as shown in
Figure 43 on page70.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 44 on page 71 and Figure 45 on page 72. Only the data-in pairs regis-
tered prior to the tWR per io d are written to the internal array; any subsequent data-in
should be masked with DM, as shown in Figures 44 and 45. After the PRECHARGE
command, a subsequent command to the same bank cannot be issued until tRP is met.
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Operations
Figure 36: WRITE Burst
Notes: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
DQS
tDQSS (MAX)
tDQSS (NOM)
tDQSS (MIN)
tDQSS
DM
DQ
CK
CK#
COMMAND WRITE NOP NOP
ADDRESS Bank a,
Col b
NOP
T0 T1 T2 T3T2n
DQS
tDQSS
DM
DQ
DQS
tDQSS
DM
DQ DI
b
DI
b
DI
b
DON’T CARE TRANSITIONING DATA
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Operations
Figure 37: Consecutive WRITE-to-WRITE
Notes: 1. DI b (or n) = data-in from column b (or column n).
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
CK
CK#
COMMAND
WRITE NOP WRITE NOP NOP
Bank,
Col b
NOP
Bank,
Col n
T0 T1 T2 T3T2n T4 T5T4nT3nT1n
DQ
DQS
DM
DI
n
DI
b
DON’T CARE TRANSITIONING DATA
t
DQSS
ADDRESS
t
DQSS (NOM)
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Operations
Figure 38: Nonconsecutive WRITE-to -WRITE
Notes: 1. DI b (or n) = data-in from column b (or column n).
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
Figure 39: Random WRITE Cycles
Notes: 1. DI b (or x or n or a or g) = data-in from column b (or colu mn x, or column n, or column a, or
column g).
2. b', x', n', a' or g' indicate the next data-in following DO b, DO x, DO n, DO a, or DO g,
respectively.
3. Programmed BL = 2, BL = 4, or BL = 8 in cases shown.
4. Each WRITE command may be to any bank.
CK
CK#
COMMAND
WRITE NOP NOP NOP NOP
ADDRESS
Bank,
Col b
WRITE
Bank,
Col n
T0 T1 T2 T3T2n T4 T5T4nT1n T5n
DQ
DQS
DM
DI
n
DI
b
tDQSS (NOM) tDQSS
DON’T CARE TRANSITIONING DATA
t
DQSS (NOM)
CK
CK#
COMMAND
WRITE WRITE WRITE WRITE NOP
ADDRESS
Bank,
Col bBank,
Col xBank,
Col nBank,
Col g
WRITE
Bank,
Col a
T0 T1 T2 T3T2n T4 T5T4nT1n T3n T5n
DQ
DQS
DM
DI
bDI
b'DI
xDI
x'DI
nDI
n'DI
aDI
a'DI
gDI
g'
DON’T CARE TRANSITIONING DATA
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Operations
Figure 40: WRITE-to-READ – Uninterrupting
Notes: 1. DI b = data-in for column b; DO n = data-out for column n.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to the same device. However, the READ and WRITE
commands may be to different devices, in which case tWTR is not required, and the READ
command could be applied earl ier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
tDQSS (NOM)
CK
CK#
COMMAND WRITE NOP NOP READ NOP NOP
ADDRESS Bank a,
Col bBank a,
Col n
NOP
T0 T1 T2 T3T2n T4 T5T1n T6 T6n
tWTR
CL = 2
DQ
DQS
DM
DI
bDO
n
tDQSS
tDQSS (MIN) CL = 2
DQ
DQS
DM
DI
bDO
n
tDQSS
tDQSS (MAX) CL = 2
DQ
DQS
DM
DI
bDO
n
tDQSS
DON’T CARE TRANSITIONING DATA
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Operations
Figure 41: WRITE-to-READ – Interrupting
Notes: 1. DI b = data-in for column b; DO n = data-out for column n.
2. An interrupted burst of 4 is shown; two data elements are written.
3. One subse quent element of data-in is applied in the programmed order following DI b.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to re gister DM.
7. If the burst of 8 is used, DM and DQS are required at T3 and T3n because the READ com-
mand will not mask these two data ele ments.
tDQSS (NOM)
CK
CK#
COMMAND WRITE NOP NOP NOP NOP NOP
ADDRESS Bank a,
Col bBank a,
Col n
READ
T0 T1 T2 T3T2n T4 T5 T5nT1n T6 T6n
tWTR
CL = 2
DQ
DQS
DM
DI
bDO
n
tDQSS (MIN) CL = 2
DQ
DQS
DM
DI
b
tDQSS (MAX) CL = 2
DQ
DQS
DM
DI
bDO
n
DO
n
DON’T CARE TRANSITIONING DATA
tDQSS
tDQSS
tDQSS
T3n
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Operations
Figure 42: WRITE-to-READ – Odd Number of Data, Interrupting
Notes: 1. DI b = data-in for column b; DO n = data-out for column n.
2. An interrupted burst of 4 is shown; one data element is written.
3. tWTR is refere n ced from the first positi ve CK edge after the last desired data-in pair (not
the last two data elements).
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 is used, DM and DQS are required at T3–T3n because the READ command
will not mask these data elements.
tDQSS (NOM)
CK
CK#
COMMAND WRITE NOP NOP NOP NOP NOP
ADDRESS Bank a,
Col bBank a,
Col n
READ
T0 T1 T2 T3T2n T4 T5T1n T6 T6nT5n
tWTR
CL = 2
DQ
DQS
DM
DI
bDO
n
tDQSS (MIN) CL = 2
DQ
DQS
DM
DI
bDO
n
tDQSS (MAX) CL = 2
DQ
DQS
DM
DI
bDO
n
DON’T CARE TRANSITIONING DATA
tDQSS
tDQSS
tDQSS
T3n
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Operations
Figure 43: WRITE-to-PRECHARGE – Uninterrupting
Notes: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE
and WRITE commands may be to different devices, in which case tWR is not required, and
the PRECHARGE command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
tDQSS (NOM)
CK
CK#
COMMAND WRITE NOP NOP NOP NOP
ADDRESS Bank a,
Col bBank,
(a or all)
NOP
T0 T1 T2 T3T2n T4 T5T1n T6
tWR tRP
DQ
DQS
DM
DI
b
tDQSS (MIN)
DQ
DQS
DM
DI
b
tDQSS (MAX)
DQ
DQS
DM
DI
b
DON’T CARE TRANSITIONING DATA
tDQSS
tDQSS
tDQSS
PRE
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Operations
Figure 44: WRITE-to-PRECHARGE – Interrupting
Notes: 1. DI b = data-in for column b.
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 8 is shown; two data elements are written.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T4 and T4n (nominal case) to re gister DM.
7. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
tDQSS
tDQSS (NOM)
CK
CK#
COMMAND WRITE NOP NOP NOP NOP
ADDRESS Bank a,
Col bBank,
(a or all)
NOP
T0 T1 T2 T3T2n T4 T5T1n T6
tWR tRP
DQ
DQS
DM
DI
b
tDQSS
tDQSS (MIN)
DQ
DQS
DM
DI
b
tDQSS
tDQSS (MAX)
DQ
DQS
DM
DI
b
DON’T CARE TRANSITIONING DATA
T3n T4n
PRE
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Operations
Figure 45: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
Notes: 1. DI b = data-in for column b.
2. An interrupted burst of 8 is shown; one data element is written.
3. tWR is referenced from the first positive CK edge after the last data-in pair.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T4 and T4n (nominal case) to re gister DM.
6. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
tDQSS
tDQSS (NOM)
CK
CK#
COMMAND
WRITE NOP NOP NOP NOP
ADDRESS
Bank a,
Col bBank,
(a or all)
NOP
T0 T1 T2 T3T2n T4 T5T1n T6
tWR tRP
DQ
DQS
DM
DI
b
tDQSS
tDQSS (MIN)
DQ
DQS
DM
tDQSS
tDQSS (MAX)
DQ
DQS
DM
DI
b
DI
b
DON’T CARE TRANSITIONING DATA
T3n T4n
PRE
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 46: Bank WRITE – Without Auto Precharge
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. Disable aut o pr echarge.
4. “Don’t Care” if A10 is HIGH at T8.
5. DI b = data-in from column b; subsequent elements are provided in the programmed order.
6. See Figure 48 on page 75 for detailed DQ timing.
CK
CK#
CKE
A10
BA0, BA1
t
CK
t
CH
t
CL
t
IS
t
IS
t
IH
t
IS
t
IS
t
IH
t
IH
t
IH
t
IS
t
IH
t
RCD
t
RAS
t
RP
t
WR
T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T4n
ACT
Col n
ONE BANK
ALL BANKS
Bank x
PRE
Bank x
t
DQSL
t
DQSH
t
WPST
DQS
DM
DI
b
tDS tDH
DON’T CARE TRANSITIONING DATA
t
DQSS (NOM)
t
WPRE
t
WPRES
COMMAND
NOP1NOP1NOP1NOP1NOP1NOP1
WRITE2
3
Bank x4
DQ5
ADDRESS
Row
Row
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 47: WRITE – DM Operation
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. Disable aut o pr echarge.
4. “Don’t Care” if A10 is HIGH at T8.
5. DI b = data-in from column b; subsequent elements are provided in the programmed order.
6. See Figure 48 on page 75 for detailed DQ timing.
CK
CK#
CKE
A10
BA0, BA1
t
CK
t
CH
t
CL
t
IS
t
IS
t
IH
t
IS
t
IS
t
IH
t
IH
t
IH
t
IS
t
IH
t
RCD
t
RAS tRP
tWR
T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T4n
ACT
Col n
ONE BANK
ALL BANKS
Bank x
PRE
Bank x
t
DQSL
t
DQSH
t
WPST
DQS
DM
DI
b
t
DS
t
DH
DON’T CARE TRANSITIONING DATA
t
DQSS (NOM)
t
WPRES
t
WPRE
COMMAND
NOP1NOP1NOP1NOP1NOP1NOP1
3
Bank x4
DQ5
WRITE2
ADDRESS
Row
Row
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 75 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 48: Data Input Timing
Notes: 1. WRITE command issued at T0.
2. tDSH (MIN) generally oc curs during tDQSS (MIN).
3. tDSS (MIN) gener a lly occurs during tDQSS (MAX).
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
5. DI b = data-in from column b
PRECHARGE
The bank(s) will be available for a subsequent row access a specified time (tRP) after the
PRECHAR GE command is issued, except in the case of concurrent auto precharge. With
concurrent auto precharge, a READ or WRITE command to a different bank is allowed as
long as it does not interrupt the data transfer in the current bank and does not violate
any other timing parameters. I nput A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1
select the bank. When all banks are to be precharged, BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged , it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank. A PRECHARGE
command will be treated as a NOP if there is no open row in that bank (idle state), or if
the previously open row is already in the process of precharging.
Auto Precharge
Auto precharge is a feature which performs the same indivi dual-bank precharge func-
tion described above, but without requiring an explic it c o mm and . Thi s is a cco m plished
by using A10 to enable auto pr echarge in conjunction with a specific READ or WRITE
command. A precharge of the bank/ row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is either enabled or disabled for each individual READ or WRITE
command. This device supports concurrent auto precharge if the command to the other
bank does not interrupt the data transfer to the current bank.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating tRAS (MIN), as described for
each burst type in “Operations” on page 42. The user must not issue another command
to the same bank until the precharge time (tRP) is completed.
DQS
tDQSS
tDQSH tWPST
tDH
tDS
tDQSL
DM
DQ
CK
CK# T1 T1n T2 T2n T3
DON’T CARE
TRANSITIONING DATA
t
WPRE
t
WPRES
T01
tDSH2tDSH2
tDSS3tDSS3
DI
b
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Operations
Figure 49: Bank READ – with Auto Precharge
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. The REA D command can only be applied at T3 if tRAP is satisfied at T3.
4. Enable auto precharge.
5. tRP starts only after tRAS has been satisfied.
6. DO n = data-out from column n; subsequent elements are provided in the programmed
order.
7. Refer to Figure 33 on page 60, Figure 34 on page 61, and Figure 35 on page 62 for detailed
DQS and DQ timing.
CK
CK#
CKE
A10
BA0, BA1
t
CK
t
CH
t
CL
t
IS
t
IS
t
IH
t
IS
t
IS
t
IH
t
IH
t
IH
ISIH
t
RC
CL = 2
DM
T0 T1 T2 T3 T4 T5 T5n T6nT6T7 T8
DQS
Case 1:
t
AC (
MIN)
and
t
DQSCK (
MIN)
Case 2:
t
AC
(
MAX)
and
t
DQSCK
(
MAX)
DQS
t
RPRE
t
RPRE
t
RPST
t
RPST
t
DQSCK
(
MIN)
t
DQSCK
(
MAX)
t
AC
(
MIN)
t
LZ
(
MIN)
DO
n
t
HZ
(
MAX)
t
AC
(
MAX)
DO
n
ACT
Col n
Bank xBank x
ACT
Bank x
DON’T CARE TRANSITIONING DATA
tRAS
NOP1NOP1NOP1NOP1NOP1NOP1
READ2,3
4
tRCD, tRAP3
DQ6
DQ6
COMMAND
tRP5
ADDRESS
tLZ (MIN)
Row
Row
Row
Row
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Figure 50: Bank WRITE – with Auto Precharge
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. Enable auto precharge.
4. DI n = data-out from column n; subsequent elements are provided in the programmed
order.
5. See Figure 48 on page 75 for detailed DQ timing.
AUTO REFRESH
During au to refres h, the addressing is generated by the internal refresh controller. This
makes the address bits a “Don’t Care” during an AUTO REFRESH command. The DDR
SDRAM requires AUTO REFRESH cycles at an average interval of tREFI (MAX).
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provi ded. A maximum of eight AUTO REFRESH
commands can be posted to any giv en DDR SDRAM, meaning that the maximum abso-
lute interval betw een any AUTO REFRESH command and the next AUTO REFRESH
command is 9 x tREFI(= tREFC). JEDEC specifications only allow 8 x tREFI; Micron sp eci-
fications exceed the JEDEC requirement by one clock. This maximum absolute interval
is to allow future support for DLL updates, internal to the DDR SDRAM, to be restricted
to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates.
CK
CK#
CKE
A10
BA0, BA1
tCK tCH tCL
tIS
tIS
tIH
tIS
tIS
tIH
tIH
tIH
tIS tIH
tRCD
tRAS tRP
tWR
T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T4n
ACT
Col n
Bank xBank x
tDQSL tDQSH tWPST
DQS
DM
DI
b
t
DS
t
DH
tDQSS (NOM)
DON’T CARE TRANSITIONING DATA
t
WPRES
t
WPRE
COMMAND
NOP1NOP1NOP1NOP1NOP1NOP1NOP1
WRITE2
3
DQ4
ADDRESS
Row
Row
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128Mb: x4, x8, x16 DDR SDRA M
Operations
Although not a JEDEC r eq uirement, to provide for futur e fu nct ionality features, CKE
must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFR ESH command is registered and ends tRFC later.
Figure 51: Auto Refresh Mode
Notes: 1. NOP commands are shown for ease of illustration; other valid commands may be possible at
these times. CKE must be active during clock-positive transitions.
2. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time; CKE must
be active during clock-positive transitions.
3. The second AUTO REFRESH is not required and is only shown as an exampl e of two b ack- to-
back AUTO REFRESH commands.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
(i.e., must precharge all active banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for the operations shown.
SELF REFRESH
When in the self refresh mode, the DDR SDRAM retains data without external clocking.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled upon exiting SELF REFRESH (A DLL reset and 200 clock cycles must then occur
before a READ command can be issued). Input signals except CKE are “D on’t C are”
during SELF REFRESH. VREF voltage is also required for the full duration of SELF
REFRESH.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK
and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP comm ands issued for tXSNR because time is required for the
completion of any internal refresh in progress. A simple algorithm for meeting both
refresh an d D LL requirements is to apply NOPs for tXSRD time, then a DLL RESET (via
CK
CK#
COMMAND
NOP1
VALID VALID
NOP1NOP1
PRE
CKE
RA
ADDRESS
A10
BA0, BA1
Bank(s)4BA
AR NOP1,2 AR3NOP1,2 ACT NOP1
ONE BANK
ALL BANKS
CK
t
CH
t
CL
t
IS
t
IS
t
IH
t
IH
t
IS
t
IH
RA
DQ5
DM5
DQS5
t
RFC
t
RP t
RFC
T
0
T1 T2 T3 T4 Ta0 Tb0
Ta1 Tb1 Tb2
DON’T CARE
(
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(
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(
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(
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(
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(
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(
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DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN 79 ©2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRA M
Operations
the extended mode register) and NOPs for 200 additional clock cycles before applying a
READ. Any command other than a READ can be performed tXSNR (MIN) after the DLL
reset. NOP or DESELECT commands must be issued during the tXSNR (MIN) time.
Figure 52: Self Refresh Mode
Notes: 1. Clock must be stable until after the SELF REFRESH command has been registered. A change
in clock frequency is allowed before Ta0, provided it is within the specified tCK limits.
Regardless, the clock must be stable before exiting self refresh mode—that is, the clock
must be cycling within specifications by Ta0.
2. NOPs are interchangeable with DESELECT commands.
3. AUTO REFRESH is not required at this point but is highly recommended.
4. Device must be in the all banks idle state prior to enter ing se lf refresh mode.
5. tXSNR is required before any non-READ command can be applied; that is only NOP or DESE-
LECT commands are allowed until Tb1.
6. tXSRD (200 cycles of a valid clock with CKE = HIGH) is required before any READ comman d
can be applied.
7. As a general rule, any time self refresh mode is exited, the DRAM may not re-enter the self
refresh mode until all rows have been refreshed via the AUTO REFRESH command at the
distributed refresh rate, tREFI, or faster. However, the self refresh mode may be re-entered
anytime after exiting if each of the following conditions is met:
7a. The DRAM had been in the self refresh mode for a minimum of 200ms prior to exiting.
7b. tXSNR and tXSRD are not violated.
7c. At least two AUTO REFRESH commands are performed during each tREFI interval while
the DRAM remains out of self refresh mode.
8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.
9. Once the device is initialized, VREF must always be powered within specified range.
CK
1
CK#
COMMAND
2NOP AR
ADDRESS
CKE
DQ
DM
DQS
NOP
tRP
4
tCHtCLtCK
tIS
tIS
tIH
tIStIH tIS
Enter self refresh mode7Exit self refresh mode7
T0 T11Ta1
DON’T CARE
Ta0
1
tXSRD6
()()
()()
()()
()()
NOP
VALID3VALID
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
tXSNR5
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
Ta2 Tb1Tb2Tc1
VALID VALID
VALID
tIStIH
()()
()()
VALID
()()
()()
()()
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128Mb: x4, x8, x16 DDR SDRA M
Operations
POWER-DOWN (CKE Not Active)
Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in
progress, from the issuing of a READ or WRITE command, until completion of the
access. Thus a clock suspend is not supported. For READs, an access complet ion is
defined when the read postamble is satisfied; for WRITEs, when the wr ite recovery time
(tWR) is satisfied.
Powe r-down, as shown in Figure 53, is e ntered when CKE is regi stered L OW and all
criteria in Table 30 on page 38 are met. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when a row is
active in any bank, this mode is referred to as active power-down. Entering power-down
deactivates the input and output buffers, excluding CK, CK#, and CKE. For maximum
power savings, the DLL is frozen during precharge power-down mode. Exiting power-
down requir es the device to be at the same voltage and frequency as when it entered
power-down. However, power-down dura tion is limited by the refre s h requirements of
the device (tREFC).
While in power-down, CKE LOW and a stable clock signal must be maintained at the
inputs of the DDR SDRAM, while all other input signals are “Don’t Care.” The power-
down state is synchronously exited when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command). A valid executable command may be applied one clock
cycle later.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
128Mb: x4, x8, x16 DDR SDRA M
Operations
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Figure 53: Power-Down Mode
Notes: 1. Once initialized, VREF must always be powered within the specified range.
2. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at
least one row is already active), then the power-down mode shown is active power-down.
3. No column accesses are allowed to be in progress at the time power-down is entered.
CK
CK#
COMMAND VALID2 NOP
ADDRESS
CKE
DQ
DM
DQS
VALID
tCK tCH tCL
tIS
tIS
tIH
tIS
tIS tIH
tIH tIS
Enter 3
power-down
mode
Exit
power-down
mode
tREFC
(
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(
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(
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(
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(
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(
) (
)
(
) (
)
(
) (
)
(
) (
)
(
) (
)
(
) (
)
T
0
T1 Ta
0
Ta1 Ta
2
T
2
NOP
DON’T CARE
(
) (
)
(
) (
)
VALID VALID
1
