19-0878; Rev 1; 8/96 Generali Description The MX7545A and MAX7645, 12-bit CMOS multiplying digital-to-analog converters (DAC) with internal data latches, are improved versions of the industry stand- ard MX7545. The MX7545A features a 100ns max write pulse width (150ns for MAX7645) which allows inter- facing to a wide range of fast 8- and 16-bit microprocessors. The MX7545A/MAX7645 are loaded by a single 12-bit wide word when CS and WR are both low. The CS and WR inputs can be connected low making the input data latches transparent and allowing unbuffered operation of these DACs. The MX7545A is specified both with a single +5V and +15V power supply. With a +5V supply, the digital inputs are TTL and +5V-GMOS compatible while high voltage CMOS compatibility is maintained with a +15V supply. The MAX7645 is TTL and CMOS compatible with a +15V supply. Maxim MX7545A and MAX7645 use low tempco thin- film resistors laser trimmed to +%4LSB linearity and better than +1LSB gain accuracy. The digital inputs have improved protection against electrostatic dis- charge (ESD) damage and can typically withstand over 6,000V of ESD voltage. Both the MX7545A and the MAX7645 are supplied in 20-lead narrow DIP, surface mount Small Outline and PLCC packages. Applications Motion Control Systems Automatic Test Equipment uP Controlled Systems Programmable Gain Amplifiers Programmable Power Supplies Typical Operating Circuit Rre 20 MAXIM MX7545A 1 ourt Vrer 12 MAX7645 12-BIT y MULTIPLYING DAC 2 aGND wr 17) = Yoo cs 16 TJ > INPUT DATA LATCHES 3 panp ns 1 ot DB11-DB0 (PINS 4-15) MAXIMA MAA AL/VI CMOS 12-Bit Buffered Multiplying DACs ?-; + @ Ad # Small Footprint Packages # Improved ESD Protection Features Improved Versions of MX7545 Gain Accuracy to +1 LSB Max. Fast Interface Timing All Grades 12-Bit Accurate MX7545A TITL/CMOS Compatible for Vpp = 5V CMOS Compatible for Vpp = 15V MAX7645 TTL/CMOS Compatible for Vop = 15V Ordering Information GAIN PART TEMP. RANGE PACKAGE ERROR MX7545ALN OC to +70C = Plastic DIP, = +1 LSB MX7545AKN orc to+70C Plastic DIP +3 LSB MX7545ALCWP 0C to +70C = Wide SO +1L8$B MX7545AKCWP OC to+70C Wide SO +3 LSB MX7545AK/D oC to +70C Dice +3 LSB MX7545ALP Orc to+70C PLCC +1LSB MX7545AKP oC to +70C PLCC +3 LSB MX7545AKEWP -40C to +85C = Wide SO +3 LSB MX7545ACQ -40C to +85C = CERDIP +1LSB MX7545ABQ -40C to +85C = CERDIP +3 LSB MX7545AUQ -55C to +125C CERDIP +1L5B MX7545ATQ -5BC to +125C CERDIP +3 LSB Ordering information continued at end of data sheet. Maxim reserves the right to ship ceramic sidebraze packages In fieu of CERDIP packages. Pin Configuration TOP VIEW a, ourt [4 20] Fre AGND [2| 9] VREF DGND [3] 8} Voo oB11MSB) [41 AAAXLAA |17] WA osio[s] MX7545A [ie] tS ves [a] MAX7645 6 115] DBO(LSB) oes [7 +4] 081 DB7 [a] 3] DB2 bB6 [ 9 | 2] 083 oes [10] 11] 084 See page 11 for Plastic Chip Carrier Pin Configuration Maxim Integrated Products 1 For free samples & the latest literature: http:/;www.maxim-ic.com, or phone 1-800-998-8800 SPOLXVW/VSPSZLXWCMOS 12-Bit Buffered Multiplying DACs ABSOLUTE MAXIMUM RATINGS Vop to DGND oe ec eeee cre rerenereseeeeneseensacee -0.3V, +17V Operating Temperature Ranges Digital Input Voltage to DGND........ eee -0.3V, Vop + 0.3V MX7545AK/AL, MAX7645AC/BC ue OC to +70C VRFB, VREF tO DGND ooo. cccccscessetetesstenetecsessnersentenseees #25V MX7545AB/AC/AKE, MAX7645AE/BE ............. -40C to +85C QUT1 to DGND wee cecccssesecesessseeeenresasesnses -0.3V, Vop + 0.3V MX7545AT/AU, MAX7645AM/BM.................. -55C to +125C AGND to DGND........ ccc ccssesesserenssereceens -0.3V, Vop + 0.3V Storage Temperature oo... ccc ccessssersceersass -65C to +150C Power Dissipation (Any Package) to +75C 0... 450mWw Lead Temperature (Soldering, 10 sec)... +300C Derate Above +75C DY... cece sstecccscseeseteeerseene end 6mWPC Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ra tings only, and functional operation of the device at these or any other conditions beydhd those indicated in the operational sections of the specifications is not implied. Exposure to MX7545A/MAX7645 absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICSMX7545A (Vop . +5V, Vner = +10V, Vout = OV, AGND al DGND. Ty = Twin to Tax unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP = MAX | UNITS STATIC PERFORMANCE Resolution N 12 Bits Relative Accuracy INL Endpoint measurement 1/2 LSB . : 4 . All grades guaranteed Differential Non-Linearity ONL 12-bit monotonic over temperature range 4 LSB Measured using IK gt JA = *26C +3 : internal RFB; DAC | "| __Ta = Twin tO Twax +4 Gain Error FSE register loaded Ley A= 125C 7 LSB with all 1s. "Ta = Twin to Twax +2 Gain Tempco AGain/ATemp. (Note 1) TOFS +200 +5 [pom DC Supply Rejection _ Ty = +25C 0.002 AGAaiN/AVpp (Note 1) PSR | AVpp = +5% Ta = Twin to Twax 0.004 | %/% DYNAMIC PERFORMANCE . : To +1/2 LSB. OUT1 load is 100M in parallel woe Time ts with 13pF. CS = OV. DAC output measured 1 US ote from falling edge of WR. From digital inputs, DB11- DBO, change to Propagation Delay 90% of final _ (Notes 1, 2) ep analog output. Ta = 425C 200 ns OUT1 load is 100 in parallel with 13pF. Digital to Analog ore aan Glitch Impulse 1002 in parallel Ta = +25C 5 nv-s (Notes 1, 2} with 13pF. AC Feedthrough at OUT1 Vaer = 10V, 10kHz sine wave, (Notes 1, 3) FTE | DB11-DBo = ov. mVp-P REFERENCE INPUT Input Resistance Rrer Vaer pin to AGND 10 15 20 kQ Input Resistance Tempco TCR -300 ppm/*C MAXIMCMOS 12-Bit Buffered Multiplying DACs ELECTRICAL CHARACTERISTICSMX7545A (Continued) (Voo = +5V, Veer = +10V, Vouz = OV, AGND = DGND. Ty = Tyan to Tyax unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS ANALOG OUTPUTS OUT1 Capacitance DB11-DBO = OV, WR = CS = OV 40 70 (Note 1) Cour | DB11-DB0 = Vp. WA = CS = OV 100 = 50: |_:sPF ee All Ta = +25C 10 OUT Leakage Current hee | WRT Ceo uy [KIBLC Ta = Twn to Twax 50 | nA T,U Ta = Twin tO Tax 200 DIGITAL INPUTS Input High Voltage Vin 2.4 Vv Input Low Voltage Vit 0.8 V Input Current lin | Vin = OV or Vop " - 1, 5 Traax *0.001 bo uA Input Capacitance (Note 1)} Cin | Vin = OV; DB11-DBO, WR, CS 8 pF SWITCHING CHARACTERISTICS (Notes 1, 4) All Ta = +25C 100 Chip Select to tes K.B.L,C Ta= Twn to Twax | 130 ns Write Setup Time TU Ta = Twin to Twax 170 Chip Select to Write Hold Time ton 0 ns : All Ta = +25C 100 Write Pulse Width twa tcs = twr, toy 2 0] K,B,L,C Ta = Twin to Twax 130 ns TU Ta = Twin to Tax 170 . Ta = +25C 100 Data Setup Time tos Ta = Twin to Tuax 150 ns Data Hold Time tox ns POWER REQUIREMENTS Supply Voltage Vop +5% for specified performance +5 Vv eo Viv or Vin 2 mA Supply Current lop All digital inputs: OV oF Voo 5 100 yA Note 1: Sample tested to ensure compliance. Note 2: DB11-DBO changed from OV to Vop or Vpp to OV. Note 3; In ceramic packages the feedthrough can be further reduced by grounding the metal lid of the package. Note 4: See timing diagram for definitions of the switching times. MAXIM 3 SPOLXVN/VSPSZLXWMX7545A/MAX7645 CMOS 12-Bit Buffered Multiplying DACs ELECTRICAL CHARACTERISTICSMX7545A, MAX7645 (Vop = +15V, Vage = +10V, Vou = OV, AGND = DGND. T, = Ty to Tyax unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS STATIC PERFORMANCE Resolution N 12 Bits : MX7545A +2 Relative Accuracy INL encpont ent MAX7645A +12 | LSB , MAX7645B +1 . . di . All grades guaranteed Differential Non-Linearity ONL | 12-bit monotonic over temperature range #1 LSB Measured using |K.B,T Ta = +25C +3 : internat RFB; Ta = Twin to Twrax +4 Gain Error FSE DAC register LOU T= *25C wv LSB loaded with all 1s. Ta = Tain to Taax +2 Gain Tempco AGain/ATemp. (Note 1) TOFS +2005 [ppm/*C DC Supply Rejection - Ta = +25C 0.002 AGain/AVpp (Note 1) PSR | AVop = +5% Ta = Twn 10 Twax 0.004 | /% DYNAMIC PERFORMANCE : : To 1/2 LSB. OUT1 load is 1000 in parallel nae Settling Time ts with 13pF. CS = OV. DAC output measured 1 us {Note 1) from falling edge of WR. From digital inputs, DB11- DBO, change to Propagation Delay 90% of final - (Notes 1, 2) tep analog output. Ta = 425C 180 ns OQUT1 load is 1000 in parallel with 13pF. Veer = AGND OUT1 load is Digital to Analog 1000 in parallel Glitch Impulse Q with 13pF. Ta = +25C 5 nv-s (Notes 1, 2) Alternately loaded with all 0's and 1's. AC Feedthrough at OUT1 Vaer = 10V, 10kHz sine wave, (Notes 1, 3) FTE | DB11-DBO = ov. 8 mVPP REFERENCE INPUT : : MX7545A 10 15 20 input Resistance Rrer | Vper pin to AGND | wyayze4g 7 1 15 kQ Input Resistance Tempco TCR ~300 ppm/*C ANALOG OUTPUTS OUT1 Capacitance C DB11-DBO = OV, WR = CS = OV 40 70 pF (Note 1) OUT! | DB11-DBO = Vop, WR = CS = OV 100 150 pF ee All Ta = +25C 10 OUT1 Leakage Current like Ont 685 ov K,B,L.C Ta = Tin to Taax 50 nA TU Ta = Twin to Tmax 200 MAXIMCMOS 12-Bit Buffered Multiplying DACs ELECTRICAL CHARACTERISTICSMX7545A, MAX7645 (Continued) (Vop = +15V, Var = +10V, Vour = OV, AGND = DGND. Ty = Ty tO Tax unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS DIGITAL INPUTS Input High Voltage Vin UC bIS y V MX7545A 15 Input Low Voltage Vit V i MAX7645 0.8 = 0 Input Current ln [Vin = OV oF Vpo 7 ae Cc Tune +0.001 Ht uA Input Capacitance = av: _ we TS (Note 1) Cin Vin = OV; OB11-DBO, WR, CS 8 pF SWITCHING CHARACTERISTICSMX7545A (Notes 1, 4) All Ta = +25C 75 Chip Select to ~ Write Setup Time tes K,B,L,C Ta = Twin to Twax 85 ns TU Ta = Twin to Twax 95 Chip Select to Write Hold Time tox 0 ns All Ta = +25C 75 Write Pulse Width twr tes = twa, tcy 2 0 | K,B,L,C Ta = Twin to Tuax 85 ns TU Ta = Tain to Trax 95 + = + o Data Setup Time tos i : m C Tuax en ns Data Hold Time tou 5 ns SWITCHING CHARACTERISTICSMAX7645 (Notes 1, 4) Chip Select to t Ta = +25C 150 ns Write Setup Time cs Ta = Tun tO Twax | 210 Chip Select to Write Hold Time ton 0 ns = Write Pulse Width twa | tos > twa, ton > 0 hte to Tum | 20 ns = Data Setup Time tos us - Tuax aon ns Data Hold Time tox 10 ns POWER REQUIREMENTS Supply Voltage Vop +5% for specified performance +15 Vv Supply Current Ipp ~| All digital inputs: My or vis 5 no Wr Note 1: Sample tested to ensure compliance. Note 2: DB11-DB0 changed from OV to Vpp or Vpn to OV. Note 3: In ceramic packages the feedthrough can be further reduced by grounding the metal lid of the package. Note 4: See timing diagram for definitions of the switching times. MAXIMA 5 SPOLXVA/VSPSLXHMX7545A/MAX7645 CMOS 12-Bit Buffered Multiplying DACs FULL SCALE GAIN ERROR vs TEMPERATURE 05 04 03 02 of 0 or 0.2 03 0.4 0.5 -75-50 -25 0 25 50 75 100 125 = 15V FULL SCALE GAIN ERROR (LSB) TEMPERATURE (C) OUTPUT LEAKAGE CURRENT vs TEMPERATURE 10 iLxGOUTPUT LEAKAGE (nA) 8 1 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) Detailed Description D/A Gonverter The basic MX7545A/MAX7645 DAC circuit consists of a laser trimmed, thin-film R-2R resistor array with NMOS current switches as shown in Figure 1. Binarily weighted currents are switched to either OUT1 or AGND depending on the status of each input data bit. Although the current at OUT1 and AGND depends on the digital input code, the sum of the two output currents are always equal to the input current at Vper. Either current output can be converted into a voltage by adding an external output amplifier (Figure 3). The Vrer input accepts a wide range of signals including fixed and time varying voltage or current inputs. If a current source is used for the reference input, then a low tempco external resistor should be used for Rrg to minimize gain variation with temperature. Typical Performance Characteristics LOGIC THRESHOLD VOLTAGE vs SUPPLY VOLTAGE 5 wl : : 10 = Fos : anrsasa | F 0 5 10 15 Vop SUPPLY VOLTAGE SUPPLY CURRENT vs TEMPERATURE = 5V i 3 0.01 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) ? RFB OUT1 VA ONG LV ZP Ziy zie? Bl ] | I} tT | I ] 1 4, Sy T 1 O AG ND | 1 \ | DB11 DB10 OBS DB1 OBO (MSB) (LSB) Figure 1. Simplified DiA Circuit of MX7545A/MAX7@45 MAXIMCMOS 12-Bit Buffered Multiplying DACs TO LAODER ae TO OUT1 TO AGND Vin Do a neal INPUT BUFFERS CONTROL CONTROL Figure 2. Digital Input Structure The internal feedback resistor Reg is compensated with an NMOS switch that matches the NMOS switches used in the R-2R array. This results in excel- lent supply rejection and gain temperature coefficient. The OUT1 pin output capacitance, Coy; is code dependent and is typically 40pF with all switches to AGND and 100pF with all switches to OUT1. Digital Circuit The digital circuit for one bit is shown in Figure 2. The digital CONTROL signal is HIGH when and CS are both low. When WR and C5 are tied low, the digital input directly controls the DAC switches. The input buffer inverters act as level shifters convert- ing TTL levels into CMOS logic levels. These input buffers are TTL compatible (0.8V and 2.4V) at Von = +5V for MX7545A, and Vpp = +15V for MAX7645, The MX7545A also works with p = +15V where the input buffers are CMOS compatible (1.5V and 13.5V). When the digital input voltages are between 1V and 6V the input buffers operate in their linear regions drawing current from the power supply. Therefore to minimize an pr" Voo wa [_r | Vop a DATA IN VW paTA VALID x 0 {DB0-DB11) Vib MODE SELECTION HOLD MODE: Either CS or WA high, data bus (DBO-DB11) is locked out; DAC lagl data present when WR or CS assumed high state. WRITE MODE: CS and WR tow, DAC responds to data bus (DBO-0811) inputs. NOTES: Vop = +5V, t = t = 20ns Voo = +15V, t, = ty = 40ns All input signal rise and fall times measured from 10% to 90% of Vop. Timing measurement reference level is (Viy + Vq.)/2. high supply currents the digital input voltages should be kept as close to the supply and ground voltages (Vpp and DGND) as possible. Circuit Configurations Unipolar Operation The most common configuration for the MX7545A/ MAX7645 is shown in Figure 3. This circuit is used for unipolar operation or 2-quadrant multiplication. The code table for this mode is given in Tabie 1. Note that the polarity of the output is the inverse of the refer- ence voltage, Vrer- In many applications gain adjustment will not be necessary especially when using parts with maximum gain error of +1LSB. In these cases, and when the gain is trimmed at the reference source, resistors R14 and R2 in Figure 3 can be omitted. However, if the trims are desired and the DAC is operated over a wide temperature range, low tempco (<300ppm/C) resis- tors should be used for R1 and R2. The capacitor C7 provides phase compensation and helps reduce overshoot and ringing when fast ampli- fiers are used at the output of the DAC. R1* Figure 3. Unipolar Binary Operation Table 1. Uni Binary Code Table for Circuit of re 3 DIGITAL INPUT MSB LsB ANALOG OUTPUT 4095 111711111911 -Vmlapge| 1000 0000 0000 Ww ggg = -172 Vi 0000 0000 0001 Vin aaa] 0000 0000 0000 0 MAXIMA SPOLXVH/VSPSLXNMX7545A/MAX7645 CMOS 12-Bit Buffered Multiplying DACs Bipolar Operation Figure 4 shows the MX7545A/MAX7645 operating in the bipolar, or 4-quadrant multiplying mode. A second amplifier and three matched resistors (R3, R4 and R5) are required. These resistors must be of the same material (preferably metal film or wire-wound) for good temperature tracking characteristics, and should match to 0.01% for 12-bit performance. The output code is 2s complement and is listed in Table 2. In multiplying applications, the MSB determines output polarity while the other 11 bits control amplitude. The U1 inverter on the MSB line converts the 2s comple- ment input code to offset-binary code. If this inversion is done in software using an exclusive-OR instruction or the input code is in offset binary, the U1 inverter can be omitted. Table 3 shows the code relationships to output voltage for the offset binary operation. 49 Vin. AY acnn fs aD opt! DB10-0B0 /7 MAX#00_ Vout MAXIMA RE MX7545A 5k MAX400 " ANALOG 10% MAX7645 ANALOG: (SEE TEXT) DATA INPUT KBT LGU Ri 500 200 R2 270 6.80 Figure 4, Bipolar Operation (2's Complement Code} Table 2. 2's Complement Code Table for Circuit To adjust the circuit, load the DAC with a code of 1000 000 0000 and trim R1 for a OV output. With R1 and R2 omitted, an alternative zero trim is to adjust the ratio of R3 and R4 for OV out. Full scale can be trimmed by loading the DAC with all zeros or all ones and adjusting the amplitude of Vge_r or varying R5 until the desired positive or negative output is obtained. In many applications the gain adjustment will not be necessary, especially when using the parts with guaranteed maximum <+1LSB gain errors. In those cases, the gain can be trimmed at the reference source and resistors R1 and R2 in Figure 4 omitted. However, if the trims are desired and the DAC is operated over a wide temperature range, then low tempco G=s00ppm/C) resistors should be used for an . _____ (Voltage Mode) Singie Supply The MX7545A/MAX7645 can be conveniently used in single supply (voltage mode) operation with OUT1 and AGND biased at any voltage between DGND and Vpp-. This is possible since the ladder termination resistor is connected to AGND. OUT1 and AGND must not be allowed to go 0.3V lower than the DGND or 0.3V higher than Vpp. Otherwise, internal diodes would turn on causing a high current flow from the supply which could possibly destroying the device. Figure shows the MX7545A/MAX7645 connected as a voltage output DAC. OUT1 is connected to the reference input and AGND is grounded. Vper pin, now the DAC output, is a voltage source with a constant impedance equal to the reference input resistance. This output should be buffered with an op amp when a lower output impedance is required. Reg pin is not used in this mode. The input impedance of the reference input (OUT 1) for this mode is code dependent, and the response time of the circuit depends on the behavior of the reference source with changing load conditions. Table 3. Offset Binary Code Tabie of Figure 4 DIGITAL INPUT DIGITAL INPUT MSB LSB | ANALOG OUTPUT MSB LSB | ANALOG OUTPUT O11141111111 Vn 2042 ya4ddtd1 tid \Vper{ oe 0000 0000 0001 in| saul 1000 0000 0001 Vass (sa 00000000 0000 0 1000 0000 0000 0 4494.9911 1111 ye ar 011111111111 Vper( sou] 1000 0000 0000 vn Fog 0000 0000 0000 as 28 MAXIMCMOS 12-Bit Buffered Multiplying DACs Two advantages of the voltage mode operation are single supply operation and that a negative reference is not required for a positive output. It should also be noted that the reference input (the voltage at OUT1) must always be positive and limited to no more than 2.5V when Vpp is 15V. If the reference voltage is greater than oBy OF Vpp is reduced, resistance mis- matches in the DACs internal NMOS switches result in degraded linearity and differential nonlinearity (DNL). Figures 6 and 7 show the typical dependence of DNL on supply voltage, Vop, and the rference voltage, Vaer. If the DAC is offset from DGND by bias- ing OUT1 and AGND at a voltage above DGND, this will effect DNL and its effect will be the same as reducing Vpp by the amount of the offset. AVOLIAGE maxim Varta? Vo AGND MX7545A/ MAX7645 DGNO DB1i-DB0 + fs 15 VOLT CMOS DIGITAL INPUTS Figure 5. Single Supply Operation Using Voltage Switching Mode DNL 4 (88) +2.0 +1.0 +10 Vpp (VOLTS) The unipolar and bipolar circuits in Figures 3 and 4 can all be converted to voltage output mode. Figure 8 shows the 2's complement bipolar circuit of Figure 4 modified to work with an output range of +2V to +8V around an offset ground potential of +5V from a single supply, Vop. of +10V to +15V. The MAX673 reference is used to bias the AGND at +5V. Resistors R1 and R2 form a voltage divider together with the DAC reference ONL (LSB) +05 055 +5 "#10 Vrer (VOLTS) Figure 7. Differential Nonlinearity vs. Reference Voltage for Figure 4 Circuit. Vop = 15 Volts. Shaded Area Shows Range of Values of Ditferential Nonlinearity that Typically Occur for L, C, and U Grades. Figura 6. Differential Nonlinearity vs. Voo for Figure 4 Circuit. Reference Voltage = 2.5 Volts. Shaded Area Shows Range of Values of Differential Nonlinearity that Typically Occur for L, C and U Grades. MAXIM MAXIM MX7545A Vop = +10V TO +15V MAX7645 ~ a" rt 8 [20 ape L 20k 10kq 2 Voo Ars at R3 SMa veer UN Tatts | DB10- AGND Vo +2 [MSB_DBO OGND/* MAX400 MHAX400 4 3 wy +5V RE $2 6 Sk OS Pd > 2 &k < MAXIM R4 > &| || MAX673112 Yop 2* 4 LJ CMOS DATA BUS. Vop = +10V TO +15V Figure 8 Single Supply Bipolar 2's Complement D/A Converter SPOLXVWN/VSPSZLXNMX7545A/MAX7645 CMOS 12-Bit Buffered Multiplying DACs input resistor, supplying the DAC with +2V input volt- age. If the application requires a wide temperature range, the +2V should be generated with an op amp to avoid drifts due to tempco matching of the DAC resistors to the external resistors. Output voltage ranges can be produced by changing R4 to change the offset, and (R1 + R2) to change the gain (slope) of the DAC transfer function. To ensure good linearity, the supply voltage, Vpp, must be kept at least +5 above the OUT1 voltage. ____ _ Mileroprocessor Intertacing The MX7545A/MAX7645 directly interfaces to 8- and 16-bit microprocessors using standard WR and CS control signals and its 12-bit data latch. Figure 9 shows a typical interface circuit for an 8-bit processor. This application uses two memory ad- dresses for the lower 8-bits and the upper 4-bits of data to the DAC. A 4-bit externai latch is required to implement the interface. For processors with 16-bit wide address busses and 8-bit data busses, such as 6800, 8080 and Z80, the 12 lower address lines can be used to supply data to the DAC, as shown in Figure 10. The upper 4 bits contain the address of the DAC that is selected. This arrange- ment takes 4k bytes of address locations for each DAC and the data is written with a single instruction cycle. Als ADDRESS BUS 7 ADDRESS DECODE = Qo" Qa; * cPU 4 r WR ) O7 @-BIT DATA BUS Do = *Qo = DECODED ADDRESS FOR DAC G, = DECODED ADDRESS FOR LATCH 3 Figure 9. 8-Bit Processor to MX7545A/MAX7645 Interface Application information Output Amplifier Offeet For best linearity, OUT1 and AGND should be termi- nated at exactly OV. In most applications OUT1 is connected to the summing junction of an inverting op amp. The input offset voltage of the amplifier can degrade the linearity of the DAC by causing OUT1 to be terminated to a non-zero voltage. The resulting error is: Error Voltage = Vos (1 + Rep/R) 10 where Vos is the op amps offset voltage and Ro is the output resistance of the DAC. R is a function of the digital input code, and varies from approximately 1ikohms to 33kohms. The error voltage range is then typically 4/3 Vog to 2 Vos, a change of 2/3 Vos. An amplifier with 3mV of offset will therefore degrade the Ats 16-BIT ADDRESS BUS AO < AODRESS 12 DECODE Q <> Fd cPuU 3 o7 DATA BUS Figure 10. Connecting the MX7545A/MAX7645 to 8-Bit Processors via the Address Bus linearity by 2mV, almost a full LSB with a 10V refer- ence voltage. For best linearity, a low-offset amplifier such as the MAX400 should be used, or the amplifier offset must be trimmed to zero. A good rule of thumb is that Vog should be no more than 1/10 LSB. The output amplifier input bias current (Ig) can also limit performance since I, Reg generates an offset error. I, should therefore be much tess than the DAC output current for 1LSB, typically 250nA with Vre_r = 10V. One tenth of this value, 25nA, is recommended. Offset and linearity can also be impaired if the output amplifier noninverting input is grounded through a bias current compensation resistor. This resistor adds to the offset at this pin and should not be used. Best performance is obtained when the noninverting input is directly connected to ground. Dynamic Considerations In static or DC applications, the AC characteristics of the output amplifier are not critical. In higher speed applications, where either the reference input is an AC signal or the DAC output must quickly settle to a new programmed value, the AC parameters of the output op-amp must be considered. Another error source in dynamic applications is para- sitic coupling of signal from the Vaer pin to OUT1. This normally is a function of board. ayout and lead- to-lead capacitance. Noise signals can also be injected into the DAC outputs when the digital inputs are switched. This digital feedthrough is usually depen- dent on circuit board layout and on-chip capacitive coupling. Layout induced feedthrough can be mini- mized with guard traces between digital inputs, Vref. and OUT1 pins. The DAG_gutput follows the digital inputs when the WR and CS pins are low. In systems where the data is not valid for the full period when WR is low, invalid MAXIMCMOS 12-Bit Buffered Multiplying DACs outputs and voltage glitches can ar at the DAC output. Adjusting the timing of the WR signal so that it is low onty when data valid can eliminate this problem. Compensation A compensation capacitor, C1, may be required when the DAC is used with a high speed output amplifier. The purpose of the capacitor is to cancel the pole formed by the DAC output capacitance Coy; and the internal feedback resistor, Reg. Its value depends on the type of op amp used but typically ranges from 10pF to 33pF. Too small a value causes output ringing while excess capacitance overdamps the output. The size of C1 can be minimized and the output voltage settling time improved by keeping the circuit board trace and stray capacitance at OUT1 as low as possible. Grounding and Bypassing Since OUT1, AGND and noninverting input of the output amplifier are sensitive to offset voltages, nodes that are to be grounded should be connected directly to "single point ground through a separate, low resistance (less than 0.2 ohms) connection. The cur- rent at OUT1 and AGND varies with input code, creating a code dependent error if these terminals are connected to ground (or a virtual ground) through a resistive path. A 1yzF bypass capacitor, in parallel with a 0.01pF ceramic capacitor, should be connected across the DAC Vpp and DGND as close to the pins as possible. The MX7545A/MAX7645 has high-impedance digital inputs. To minimize noise pick-up, they should be tied to either Vpp or DGND when not used. It is good practice to connect active inputs to Vjp or DGND through high valued resistors (iMohms) to prevent static charge accumulation if the pins are left floating, such as when a circuit card is left unconnected. It is also recommended that two back-to-back diodes be connected between the DGND and AGND pins in systems where these pins tie on the backplane. ___ Ordering Information (continued) PART TEMP. RANGE PACKAGE = pcalh, MAX7645ACPP 0C to +70C Plastic DIP. +1 LSB MAX7645BCPP 0Cto+70C Plastic DIP +3 LSB MAXT645ACWP OC to +70C WideSO | +1LSB MAX7645BCWP 0C to +70C WideSO +3LSB MAX7645B/D __OC to +70C__Dice +3 LSB MAX7645ACQP _0C to +70C PLCC +1 LSB MAX7645BCQP 0C to +70C PLCC +3 LSB MAX7645AEJP -40C to 486C CERDIP +1 LSB MAX7645BEJP -40C 10 +85C CERDIP _+3LSB MAX7645AMJP -55C to +125C CERDIP +1LSB MAX7645BMJP -55C to +125C CERDIP +3 LSB Maxim reserves the right to ship ceramic packages in lieu of CERDIP packages. MAXIM _____. Pin Configuration (continued) Top View Rep B Ver GIF DB11 (MSB) | 4 | 118] Yoo DB10| 5 | wa MAXIM = 069 | S| MX7545A cs pps MAX7645 115] DB0 (LSB) pe7 | | 14] 0B 20 Lead Plastic Chip Carrier (Quad Pak) Chip Topography DGND AGND iout: Ree Vaee Vopo peat a @ tan A Fi 7" ey ea Ye cL poee DBS DBZ 0.100" [2.54mm] 11 SPOLXVN/VSPSZLXHMX7545A/MAX7645 CMOS 12-Bit Buffered Multiplying DACs Package Information INCHES MILLIMETERS E Dim MIN | MAX | MIN | MAX <_ D ~~ | ae A ~ 0.200 - 5.08 _ _ dq At | 0.015 | 0.38 _ A 4 wy AS A2 | 0.125 | 0.175 | a18 | 4.45 a A2 1 A3 | 0.055 | 0.080 | 1.40 | 2.03 TL B_| 0.016 | 0.022 | 0.41 | 0.56 Bi | 0.045 | 0.065 1.44 1.65 C | 0.008 | 0.012 | 0.20 9.30 D1 7] 0.005 | 0.080 | 0.13 2.03 Ei .0.300 | 0.325 | 7.62 6.26 t 4 o> E1 | 0.240 | 0.310 | 610 | 7.87 Bi <eA> e {| 0.100 ~ 2.54 = B eA {| 0.200 | 7.62 - eB _ eB] - 0.400 - 10.16 aa D1 L [os | 0150 | 292 | 3.81 Sey fo . INCHES | MILLIMETERS Plastic DIP lpka. DIM PINS! MIN | MAX | MIN | MAX PLASTIC P | D | 8 |0.348 [0.390 | 8.84 | 9.91 ) DUAL-IN-LINE = . < 0.735 | 0.765 | 18.67 | 19.43 0.745 | 0.765 | 18.92 | 19.43 PACKAGE P | D | 16 [0.895 | 0.915 | 22.48 | 23.24 ces AS (0.300 in.) P | D | 20 | 1.015 | 1.045 | 25.78 | 26.54 N | 0 | 24 | 1.14 [1.265 [28.06 | 32.13 | 21-D043A | pim |_INCHES MILLIMETERS MIN | MAX | MIN | MAX |t-- |) > A | 0.093 | 0.104 | 235 | 265 ! Al | 0.004 | 0.012 | 0.10 | 0.30 o-8 | 8 | 0.014 | 0.019 | 0.35 | 0.49 yA L i c | 0.009 | 0.013 | 023 | 0.32 7/ Tiormm E | 0.291 | 0.299 | 7.40 | 7.60 |e t-te} |~- B f A feces] + 8 0.050 1.27 Al c L H | 0.394 | 0.419 | 10.00 | 10.65 L | oo16 | 0.050] 040 | 1.27 BHa//Bean INCHES | MILLIMETERS . DIM |PINS ian | MAX | MIN | MAX Eu Wide SO D | 16 | 0.398 | 0.413 | 10.10 | 10.50 SMALL-OUTLINE p | 18 | 0.447 | 0.463 | 11.35 [11.75 PACKAGE D | 20 | 0.496 | 0.512 | 12.60 | 13.00 HEE) /ARESE _ : D | 24 | 0.598 | 0.614 | 15.20 | 15.60 (0.300 in.) D | 28 | 0.697 | 0.713 | 17.70 | 18.10 21-0042A Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied, Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1996 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products.