TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 2010, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
•High-Performance: fmax (w/o feedback)
TIBPAL20R’ -15C Series . . . 45 MHz
TIBPAL20R’ -20M Series . . . 41.6 MHz
•High-Performance . . . 45 MHz Min
•Reduced ICC of 180 mA Max
•Functionally Equivalent, but Faster Than
PAL20L8, PAL20R4, PAL20R6, PAL20R8
•Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
•Preload Capability on Output Registers
Simplifies Testing
•Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
DEVICE I
INPUTS
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
I/O
PORT
S
PAL20L8 14 2 0 6
PAL20R4 12 0 4 (3-state buffers) 4
PAL20R6 12 0 6 (3-state buffers) 2
PAL20R8 12 0 8 (3-state buffers) 0
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT™ circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for futher
reduction in board space.
Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low state.
This feature simplifies testing because the registers can be set to an initial state prior to executing the test
sequence.
The TIBPAL20’ C series is characterized from 0°C to 75°C. The TIBPAL20’ M series is characterized for
operation over the full military temperature range of −55°C to 125°C.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
I
I
I
I
I
I
I
I
I
I
I
GND
VCC
I
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
TIBPAL20L8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
(TOP VIEW)
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O
I/O
I/O
NC
I/O
I/O
I/O
I
I
I
NC
I
I
I
426
14 15 16 17 18
I
I
GND
NC
I
I
O
I
I
I
NC
I
O
TIBPAL20L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
NC −No internal connection
Pin assignments in operating mode
V
CC
TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
CLK
I
I
I
I
I
I
I
I
I
I
GND
I
I/O
I/O
Q
Q
Q
Q
I/O
I/O
I
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
OE
TIBPAL20R4’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
(TOP VIEW)
I
I
GND
NC
I
I/O
I
I
CLK
NC
I
I/O
(TOP VIEW)
VCC
11 19
12 13 14 15 16 17 18
4
10
9
8
7
6
5 I/O
20
21
22
23
24
25
3 2 1 282726
I
I
I
NC
I
I
I
Q
Q
NC
Q
Q
I/O
TIBPAL20R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
NC −No internal connection
OE
CLK
I
I
I
I
I
I
I
I
I
I
GND
I
I/O
Q
Q
Q
Q
Q
Q
I/O
I
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13 OE
I
I
GND
NC
I
I/O
I
I
CLK
NC
I
I/O
VCC
11 19
12 13 14 15 16 17 18
4
10
9
8
7
6
5Q
20
21
22
23
24
25
3 2 1 282726
I
I
I
NC
I
I
I
Q
Q
NC
Q
Q
Q
OE
VCC
(TOP VIEW)
TIBPAL20R6’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
(TOP VIEW)
TIBPAL20R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
CLK
I
I
I
I
I
I
I
I
I
I
GND
I
Q
Q
Q
Q
Q
Q
Q
Q
I
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13 OE
I
I
GND
NC
I
Q
I
I
CLK
NC
I
Q
VCC
11 19
12 13 14 15 16 17 18
4
10
9
8
7
6
5Q
20
21
22
23
24
25
3 2 1 282726
I
I
I
NC
I
I
I
Q
Q
NC
Q
Q
Q
OE
VCC
(TOP VIEW)
TIBPAL20R8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
(TOP VIEW)
TIBPAL20R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
Pin assignments in operating mode
TIBPAL20L8-15C, TIBPAL20R4-15C
TIBPAL20L8-20M, TIBPAL20R4-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
functional block diagrams (positive logic)
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I
EN ≥1
&
40 X 64
14 20
206
7
7
7
7
7
7
7
7
6
20 x
denotes fused inputs
Q
I/O
I/O
I/O
I/O
I
EN
12 20
204
7
7
7
8
8
8
7
4
20 x
≥1
&
40 X 64
≥1
8
Q
Q
Q
4
1D
I = 0 2
CLK C1
EN 2
OE
4
TIBPAL20L8’
TIBPAL20R4’
TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
functional block diagrams (positive logic)
denotes fused inputs
TIBPAL20R6’
TIBPAL20R8’
Q
I/O
I/O
I
EN
12 20
202
7
8
8
8
7
2
20 x
≥1
&
40 X 64
≥1
8
Q
Q
Q
6
1D
I = 0 2
CLK C1
EN 2
OE
6
8Q
8Q
Q
I12 20
208
8
8
8
8
20 x
8
Q
Q
Q
1D
I = 0 2
CLK C1
EN 2
8Q
8Q
&
40 X 64
≥1
OE
8Q
8Q
4 8 12 16 20 24 28 32
I3
I4
I5
I6
I7
I8
I9
I10
O
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
O
15
I
14
Increment
I1
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
0
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
2520
First Fuse
Numbers
36 390
I2I
23
I11 I
13
TIBPAL20L8-15C
TIBPAL20L8-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
logic diagram (positive logic)
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
4 8 12 16 20 24 28 32
I3
I4
I5
I6
I7
I8
I9
I10
I/O
22
I/O
21
I/O
16
I/O
15
Increment
0
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
2520
First Fuse
Numbers
36 390
I2I
23
I11 I
14
Q
20
Q
19
Q
18
Q
17
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
13 OE
CLK 1
TIBPAL20R4-15C
TIBPAL20R4-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
logic diagram (positive logic)
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
4 8 12 16 20 24 28 32
I3
I4
I5
I6
I7
I8
I9
I10
I/O
22
I/O
15
Increment
0
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
2520
First Fuse
Numbers
36 390
I2I
23
I11 I
14
Q
20
Q
19
Q
18
Q
17
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
13 OE
CLK 1
Q
21
C1
1D
I = 0
Q
16
C1
1D
I = 0
TIBPAL20R6-15C
TIBPAL20R6-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
logic diagram (positive logic)
Fuse number = First fuse number + Increment
Pin numbers shown are for JT, NT, and W packages.
4 8 12 16 20 24 28 32
I3
I4
I5
I6
I7
I8
I9
I10
Increment
0
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
2520
First Fuse
Numbers
36 390
I2I
23
I11 I
14
Q
20
Q
19
Q
18
Q
17
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
13 OE
CLK 1
Q
21
C1
1D
I = 0
Q
16
C1
1D
I = 0
Q
22
C1
1D
I = 0
Q
15
C1
1D
I = 0
TIBPAL20R8-15C
TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
logic diagram (positive logic)
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IOH High-level output current −3.2 mA
IOL Low-level output current 24 mA
fclock†Clock frequency 0 45 MHz
High 10
Low 12
tsu†Setup time, input or feedback before clock↑15 ns
th†Hold time, input or feedback after clock↑0 ns
TAOperating free-air temperature 0 25 75 °C
†fclock, tw, tsu, and th do not apply for TIBPAL20L8’.
ns
Pulse duration, clock tw†
VO = 0.4 V
IOZL VCC = 5.25 V, μA
VO = 2.7 V
IOZH VCC = 5.25 V, μA
fmax¶MHz
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.75 V, II = −18 mA −0.8 −1.5 V
VOH VCC = 4.75 V, IOH = −3.2 mA 2.4 V
VOL VCC = 4.75 V, IOL = 24 mA 0.3 0.5 V
O, Q outputs 20
I/O ports 100
O, Q outputs −20
I/O ports −250
IIVCC = 5.25 V, VI = 5.5 V 0.1 mA
IIH‡VCC = 5.25 V, VI = 2.7 V 25 μA
IIL‡VCC = 5.25 V, VI = 0.4 V −0.25 mA
IOS§VCC = 5.25 V, VO = 0.5 V −30 −70 −130 mA
ICC
VCC = 5.25 V,
Outputs open,
VI = 0,
OE at VIH
120 180 mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITION MIN TYP†MAX UNIT
With feedback 37 40
Without feedback 45 50
tpd I, I/O O, I/O R1 = 200 Ω, 12 15 ns
tpd CLK↑QR2 = 390 Ω, 8 12 ns
ten OE Q See Figure 3 10 15 ns
tdis OE↑Q 8 12 ns
ten I, I/O O, I/O 12 18 ns
tdis I, I/O O, I/O 12 15 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡For I/O ports, the parameters IIH and IIL include the off-state output current.
§Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
¶fmax(with feedback) +1
tsu )tpd (CLK to Q)
, fmax(without feedback) +1
twhigh )twlow
,
fmax does not apply for TIBPAL20L8,.
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IOH High-level output current −2 mA
IOL Low-level output current 12 mA
fclock†Clock frequency 0 41.6 MHz
High 12
Low 12
tsu†Setup time, input or feedback before clock↑20 ns
th†Hold time, input or feedback after clock↑0 ns
TAOperating free-air temperature −55 25 125 °C
†fclock, tw, tsu, and th do not apply for TIBPAL20L8’.
ns
Pulse duration, clock tw†
μAVI = 2.7 V
VO = 0.4 V
VCC = 5.5 V,
IIH‡
IOZL‡VCC = 5.5 V, μA
fmax¶MHz
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = −18 mA −0.8 −1.5 V
VOH VCC = 4.5 V, IOH = −2 mA 2.4 3.2 V
VOL VCC = 4.5 V, IOL = 12 mA 0.3 0.5 V
IOZH VCC = 5.5 V, VO = 2.7 V 100 μA
O, Q outputs −20
I/O ports −250
IIVCC = 5.5 V, VI = 5.5 V 1 mA
I/O ports 100
All others 25
IIL‡VCC = 5.5 V, VI = 0.4 V −0.25 mA
IOS§VCC = 5.5 V, VO = 0.5 V −30 −70 −250 mA
ICC
VCC = 5.5 V,
Outputs open,
VI = 0,
OE = VIH
120 180 mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITION MIN TYP†MAX UNIT
With feedback 28.5 40
Without feedback 41.6 50
tpd I, I/O O, I/O R1 = 390 Ω, 12 20 ns
tpd CLK↑QR2 = 750 Ω, 8 15 ns
ten OE Q See Figure 3 10 20 ns
tdis OE↑Q 8 20 ns
ten I, I/O O, I/O 12 25 ns
tdis I, I/O O, I/O 12 20 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡For I/O ports, the parameters IIH and IIL include the off-state output current.
§Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. Set VO at 0.5 V to
avoid test equipment ground degradation.
¶fmax(with feedback) +1
tsu )tpd (CLK to Q)
, fmax(without feedback) +1
twhigh )twlow
,
fmax does not apply for TIBPAL20L8,.
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Notes 2 and 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1. With VCC at 5 volts and Pin 1 at VIL, raise Pin 13 to VIHH.
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse Pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower Pin 13 to VIL. Preload can be verified by observing the
voltage level at the output pin.
td
tsu
tw
td
VIHH
VIL
VIL
VOL
VOH
VIH
Pin 13
Pin 1
Registered I/O Input Output
VIH
VIL
Figure 1. Preload Waveforms
NOTES: 2. Pin numbers shown are for JT, NT, and W packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 v
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021 D− D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
14
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
1.5 V
tsu‡
tpd†
tw
VIL
VIH
5 V
VCC
Active Low
Registered Output
CLK
4 V
VOH
VOL
1.5 V
(600 ns TYP, 1000 ns MAX)
1.5 V
†This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M
HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS021A − D2920, JUNE 1986 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15
PARAMETER MEASUREMENT INFORMATION
tsu
S1
R2
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V
1.5 V
th
1.5 V
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
1.5 V 1.5 V
1.5 V 1.5 V
tw
1.5 V 1.5 V
≈ 3.3 V
VOL
VOH
VOH −0.5 V
≈ 0 V
ten
ten
tdis
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
R1
VOL +0.5 V
5 V
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
From Output
Under Test
Test
Point
Input
Out-of-Phase
Output
(see Note D)
Timing
Input
Data
Input
In-Phase
Output
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ). PRR ≤ 1 MHz,
tr = tf ≤ 2 ns, duty cycle = 50%. For M suffix, use the voltage levels indicated in brackets [ ]. PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty cycle
= 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 3. Load Circuit and Voltage Waveforms
D0892
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©1992 Texas Instruments Incorporated
SRPS021
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PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-87671013A ACTIVE LCCC FD 28 1 TBD POST-PLATE N / A for Pkg Type
5962-8767101KA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
5962-8767101LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
5962-87671023A ACTIVE LCCC FD 28 1 TBD POST-PLATE N / A for Pkg Type
5962-8767102KA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
5962-8767102LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
5962-87671033A ACTIVE LCCC FD 28 1 TBD POST-PLATE N / A for Pkg Type
5962-8767103KA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
5962-8767103LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
5962-87671043A ACTIVE LCCC FD 28 1 TBD POST-PLATE N / A for Pkg Type
5962-8767104KA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
5962-8767104LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
8412901LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
8412901XA ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
8412902KA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
8412902LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
8412902XA ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
8412903KA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
8412903LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
8412903XA ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
8412904KA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
8412904LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
8412904XA ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
JM38510/50501BLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
JM38510/50502BLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
JM38510/50503BLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
JM38510/50504BLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
M38510/50501BLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
M38510/50502BLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
M38510/50503BLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
M38510/50504BLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
TIBPAL20L8-15CFN ACTIVE PLCC FN 28 37 TBD CU Level-1-220C-UNLIM
TIBPAL20L8-15CNT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TIBPAL20L8-20MFKB ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
TIBPAL20L8-20MJT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
TIBPAL20L8-20MJTB ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
TIBPAL20L8-20MWB ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
TIBPAL20R4-15CFN ACTIVE PLCC FN 28 37 TBD CU Level-1-220C-UNLIM
TIBPAL20R4-15CNT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TIBPAL20R4-20MFKB ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
TIBPAL20R4-20MJT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
TIBPAL20R4-20MJTB ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
TIBPAL20R4-20MWB ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
TIBPAL20R6-15CFN ACTIVE PLCC FN 28 37 TBD CU Level-1-220C-UNLIM
TIBPAL20R6-15CNT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TIBPAL20R6-20MFKB ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
TIBPAL20R6-20MJTB ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
TIBPAL20R6-20MWB ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
TIBPAL20R8-15CFN ACTIVE PLCC FN 28 37 TBD CU Level-1-220C-UNLIM
TIBPAL20R8-15CNT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TIBPAL20R8-20MFKB ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
TIBPAL20R8-20MJTB ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
TIBPAL20R8-20MWB ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 3
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
4040110/C 08/96
B
0.200 (5,08) MAX
0.320 (8,13)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
13
12
0.030 (0,76)
0.070 (1,78)
0.015 (0,38) MIN
A
24
1
0.100 (2,54) MAX
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0°–15°
1.440
(37,08)
1.460
0.285
(7,39)
0.291
(36,58)
(7,24)
28
PINS **
1.280
1.240
0.300
0.245
(7,62)
DIM
B MAX
A MAX
A MIN
B MIN (6,22)
24
(32,51)
(31,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
MECHANICAL DATA
MCFP007 – OCTOBER 1994
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W (R-GDFP-F24) CERAMIC DUAL FLATPACK
4040180-5/B 03/95
1.115 (28,32)
0.090 (2,29)
0.375 (9,53)
0.019 (0,48)
0.030 (0,76)
0.045 (1,14)
0.006 (0,15)
0.045 (1,14)
0.015 (0,38)
0.015 (0,38)
0.026 (0,66)
0.004 (0,10)
0.340 (8,64)
0.840 (21,34)
124
0.360 (9,14)
0.240 (6,10)
1312
Base and Seating Plane
30° TYP
0.360 (9,14)
0.240 (6,10)
0.395 (10,03)
0.360 (9,14)
0.640 (16,26)
0.490 (12,45)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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