| FAIRCHILD eer pepe SEMICONDUCTOR 74AC08 - 74ACT08 Quad 2-Input AND Gate General Description The AC/ACTO8 contains four, 2-input AND gates. November 1988 Revised December 1998 Features lB loc reduced by 50% on 74AC only Hi Outputs source/sink 24 mA Ordering Code: Order Number | Package Number Package Description 74ACO08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Body 74AC08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.8mm Wide 74ACO8MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACO8PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACTO8SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Body 74ACTO8MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACTO8PG N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. (PC not available in Tape and Reel.) Logic Symbol Connection Diagram IEEE/EC Pin Assignment for DIP, SOIC and TSSOP Aa & r %o 9 Voc A L 0, Ap yb B 2 Aa 2 i 0, Og Bo hs Aa 3 i 05 Bs a3 05 Pin Descriptions Pin Names Description An, Bn Inputs On Outputs FACT is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS009914.prf www.fairchildsemi.com 9185 GNV Indul-Z peno g0LOVrZ * 800VrZ74AC08 - 74ACT08 Absolute Maximum Ratingsinote 1) Supply Voltage (Vcc) DC Input Diode Current (I)x) Vv, =-0.5V Vi =Vec + 0.5V DC Input Voltage (V)) DC Output Diode Current (lox) Vo =-0.5V Vo =Voc + 0.5V DC Output Voltage (Vo) DC Output Source or Sink Current (lo) DC Voc or Ground Current per Output Pin (l or Ienp) Storage Temperature (Tstq) Junction Temperature (Ty) PDIP 0.5V to +7.0V -20 mA +20 mA -0.5V to Vec +0.5V -20 mA +20 mA -0.5V to Vec +0.5V +50 mA +50 mA -65C to +150C 140C DC Electrical Characteristics for AC Supply Voltage (Vcc) AC ACT Input Voltage (V)) Output Voltage (Vo) Operating Temperature (Ta) Minimum Input Edge Rate (AV/At) AC Devices Vin from 30% to 70% of Veco Voc @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (AV/At) ACT Devices Vin from 0.8V to 2.0V Voc @ 4.5V, 5.5V Recommended Operating Conditions 2.0V to 6.0V 4.5V to 5.5V OV to Voc OV to Voc 40C to +85C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. Voc Ty =+25C | Ta =40C to +85C - _ Symbol Parameter Units Conditions (V) Typ Guaranteed Limits Vin Minimum HIGH Level 3.0 1.5 2.1 21 Vout =0.1V Input Voltage 4.5 2.25 3.15 3.15 v or Veg 0.1V 5.5 2.75 3.85 3.85 VIL Maximum LOW Level 3.0 1.5 0.9 0.9 Vout =0.1V Input Voltage 4.5 2.25 1.35 1.35 Vv or Veg 0.1V 5.5 2.75 1.65 1.65 Vou Minimum HIGH Level 3.0 2.99 29 29 lout =50 pA Output Voltage 45 4.49 44 44 Vv 5.5 5.49 5.4 5.4 Vin = Vit or Vin 3.0 2.56 2.46 loy=12 mA 45 3.86 3.76 Vv lon =24 mA 5.5 4.86 4.76 lon =24 mA (Note 2) Vo. Maximum LOW Level 3.0 0.002 0.1 0.1 lout = 50 pA Output Voltage 45 0.001 0.1 01 Vv 5.5 0.001 0.1 0.1 Vin = Vir or Vin 3.0 0.36 0.44 lol =12 mA 45 0.36 0.44 Vv lo =24 mA 5.5 0.36 0.44 lo = 24 mA (Note 2) In Maximum Input 5.5 +0.1 +H1.0 BA 1Vi=Vec, GND (Note 4) Leakage Current lot Minimum Dynamic 5.5 75 mA | Vo_p = 1.65V Max Output Current (Note 3) loup 5.5 75 mA | Voup = 3-85V Min loc Maximum Quiescent 5.5 2.0 20.0 HA |Vin=Veco (Note 4) Supply Current or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: |), and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vc. www.fairchildsemi.com NoDC Electrical Characteristics for ACT 80LOVPZ * 8090VPZ Vee Ta =+285C Ta =40C to +85C Symbol Parameter Units Conditions (V) Typ Guaranteed Limits Vin Minimum HIGH Level 45 1.5 2.0 2.0 Vv Vout = 0.1V Input Voltage 5.5 1.5 2.0 2.0 or Veg 0.1V Vit Maximum LOW Level 45 1.5 0.8 0.8 Vv Vout =0.1V Input Voltage 5.5 1.5 0.8 0.8 or Veg 0.1V Vou Minimum HIGH Level 45 4.49 44 44 Vv lout =50 pA Output Voltage 5.5 5.49 5.4 5.4 Vin= Vit or Vin 45 3.86 3.76 Vv lon =-24 mA 5.5 4.86 4.76 lon =-24 mA (Note 5) VoL Maximum LOW Level 45 0.001 0.1 0.1 Vv lout = 50 pA Output Voltage 5.5 0.001 01 0.1 Vin= Vit or Vin 45 0.36 0.44 Vv lol =24 mA 5.5 0.36 0.44 lol =24 mA (Note 5) lI Maximum Input 5.5 +0.1 +1.0 BA |Vi=Vec, GND Leakage Current leet Maximum 5.5 0.6 1.5 mA |Vi=Veco-2.1V Io/Input lotp Minimum Dynamic Output Current 5.5 75 mA | Vo_p = 1.65V Max loup (Note 6) 5.5 -75 mA | Vonp = 3.85V Min loc Maximum Quiescent 5.5 4.0 40.0 BPA |Vin=Veco Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Vee Ta =+285C Ta = 40C to +85C Symbol Parameter (V) C_ =50 pF C, = 50 pF Units (Note 7) Min Typ Max Min Max teLH Propagation Delay 3.3 1.5 7.5 9.5 1.0 10.0 ns 5.0 1.5 5.5 75 1.0 8.5 tPHL Propagation Delay 3.3 1.5 7.0 8.5 1.0 9.0 ns 5.0 1.5 5.5 7.0 1.0 7.5 Note 7: All outputs loaded; thresholds on input associated with output under test. Note 8: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for ACT Vee Ta =+285C Ta = 40C to +85C Symbol Parameter (V) C_ =50 pF C, = 50 pF Units (Note 9) Min Typ Max Min Max teLH Propagation Delay 5.0 1.0 6.5 9.0 1.0 10.0 ns teu Propagation Delay 5.0 1.0 6.5 9.0 1.0 10.0 ns Note 9: Voltage Range 5.0 is 5.0V +0.5V Capacitance Symbol Parameter Typ Units Conditions Cn Input Capacitance 45 pF Voce = OPEN Cpp Power Dissipation Capacitance 20.0 pF Voc = 5.0V 3 www.fairchildsemi.com74AC08 - 74ACT08 Physical DimensiONS inches (millimeters) unless otherwise noted -~ (8.509 8 738 1. 130 12 211=10 t 0.335 0.344 - | ) Af 14-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.3mm Wide Package Number M14D 0 228-0 244 (5.791 6.198) | [ow LEAD ND. 1 77 IDENT yr JO U U 0 G U U- 1 2 3 4 58 6 0.010 max (0.254) 0.150 -0.157 | (3.810 3.988) 0,053 ~0.069 0.010-0.020 0.053 - 0.069 (0.254~-0.508) * >| [* (0.345 1.753) 8 MAX TYP 0.004 -0.010 ALL LEADS (0.102 0.254) + sh cme SSS i =- PLANE } 0.008 0.010 t oot 9.050 | | | | 0.014-0.020 fyp (0.203 0.254) 0.016 0.050 (0.386) i270) ? (0.356 0.508) TYP ALL LEADS 0.004 (0.406 1.270) TYP 0.008 (0.102) TYP ALL LEADS >I i903) ALL LEAD TIPS pana EY 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Body Package Number M14A 14 8 0.295-0.319 (7.5-8.1) 0.205-0.213 (5.2-5.4) 1 7 0.394-0.402 0.71 _ Seo es __+1 . 0.006-0.010 (10.0-10.2) (ray) (0.15-0.25) TYP [ \ 0.067-0.083 " r/ U7-2.4)~ 0-8 TYP + Ol0.006 (0.15) s 0.050 0.049 +| |. SEATING PLANE 9.050 typ 0.000-0.010 ( TYP) (1.27) a (1.25) (0-0.25) _, 0.016-0.031 1p 9.014-0.020 5, _ ~(0.4-0.8) (0.35-0.50) M14D (REV B) www.fairchildsemi.comPhysical DimensiONS inches (millimeters) unless otherwise noted (Continued) I4L0, TOLOP, JEDEC MO-lSs, 44MM WIDE nas Tre TAT ALL LEAD TIF? PIN #1 IDENT, se ALL LEAD TIF - ous Le MAX ayn fe] Weal ag i 1] L | i" a, LOE0,05 - LS a, NOTE: A. CONFORMS TO JEDEC PEGIZTRATION MO-153 VARIATION ABU REF NOTE &, DATED 75 B. DIMENSION: ARE IN MILLIMETER: C, DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAP EXTRUSION? oes Fk fu de i a LAND PATTERN RECOMMENDATION TEE DETAIL A PO Loa ceo, SET I i >. O.08-et) \ oP + dent TOF 8 BOTTO SEATING PLANE [ae DETAIL A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 80LOVPZ * 8090VPZ74AC08 - 74ACT08 Quad 2-Input AND Gate Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) 0.740 0.770 18.80 19.56) |< -2.090 (2.286) | [ial] fra] (2) fa) fio] fs) fia) cy a.2s04 o.o10 p/ O at (6.350 + 0.254) PINNO. 1% IDENT WITT G8! 7 4 0.092 0.030 MAX oo (2.337) (0.762) DEPTH OPTION 1 OPTION 02 0.135 0.005 0.300 0.320 (3.429 0.127) A306 00 0.445 0.200 0060. typ \ ae Tye (7.620 8.128) _0.085_ 736845 080) P| 41.524) ae [ae (1.651) (3-684 5.080) ( ) am\ OPTIONAL A f f 1 , 4 a F f a 95 45 0.0080.016 yyp 0.020 Y go 44 TYP lee" "(0.203 0,408) (0.508) ~ <4 MIN 0.125 0.150_ |! 0.075 +0.015 8.175 3.810) | ~~ 1 905 .10.381) 0.280 0.0140.023 (7112) | jos6casea PO II 0.100 +0.010 MIN {0.356 0.584) > .100 0.010 yyp 0.050 10.010 (2.540 + 0.254) |= a: : YP +0.040 | (1-270 0.254) 0 328 o o15 +1.016 (6.255 raga) Naa REV F) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Fairchild coes not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairctild reserves the right at any time without notice to change said circuitry and spedifications.