Clock Synthesizer with Differential CPU Outputs
CY28346
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07331 Rev. *A Revised March 7, 2002
Features
• Compliant with Intel® CK 408 Mobile Clock Synthesizer
specifications
• 3.3V power supply
• Three differential CPU clocks
• Ten copies of PCI clocks
• 5/6 copies of 3V66 clocks
• SMBus support with read-back capabilities
• Spread Spectrum electromagnetic interference (EMI)
reduction
• Dial-a-Frequency™ features
• Dial-a-dB™ featu res
• 56-pin TSSOP and SSOP packages
Table 1. Frequency Table[1]
S2 S1 S0 CPU (0:2) 3V66 66BUFF(0:2)/
3V66(0:4) 66IN/3V66–5 PCI_FPCI REF USB/ DOT
1 0 0 66M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M
1 0 1 100M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M
1 1 0 200M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M
1 1 1 133M 66M 66IN 66-MHZ clock input 66IN/2 14.318M 48M
0 0 0 66M 66M 66M 66M 33 M 14.318M 48M
0 0 1 100M 66M 66M 66M 33 M 14.318M 48M
0 1 0 200M 66M 66M 66M 33 M 14.318M 48M
0 1 1 133M 66M 66M 66M 33 M 14.318M 48M
M 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
M 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2
Note:
1. TCLK is a test clock driven on the XT AL_IN input during test mode. M= driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a
0 state will be latched into the device’s internal state register.
PLL1
PLL2
/2
WD
Logic
Power
Up Logic
XIN
XOUT
CPU_STP#
IREF
VSSIREF
S(0:2)
MULT0
VTT_PG#
PCI_STP#
PD#
SDATA
SCLK
VDDA 66B[0:2]/3V66[2:4]
48M DOT
48M USB
PCI_F(0:2)
PCI(0:6)
3V66_1/VCH
3V66_0
CPUC(0:2)
CPUT(0:2)
REF
66IN/3V66-5
I2C
Logic
VDD
XIN
XOUT
VSS
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
PCI1
PCI2
PCI3
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
66B0/3V66_2
66B1/3V66_3
66B2/3V66_4
66IN/3V66_5
PD#
VDDA
VSSA
VTT_PG#
REF
S1
S0
CPU_STP#
CPUT0
CPUC0
VDD
CPUT1
CPUC1
VSS
VDD
CPUT2
CPUC2
MULT0
IREF
VSSIREF
S2
48MUSB
48MDOT
VDD
VSS
3V66_1/VCH
PCI_STP#
3V66_0
VDD
VSS
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CY28346
Pin ConfigurationBlock Diagram
CY28346
Document #: 38-07331 Rev. *A Page 2 of 20
Pin Description
Pin Name PWR I/O Description
2XIN IOscillator Bu ffer Input. Connect to a crystal or to an external clock.
3XOUTV
DD OOscillator Buffer Output. Connect to a crystal. Do not connect when an external
clock is applied at XIN.
52, 51, 49, 48,
45, 44 CPUT(0:2),
CPUC(0:2) VDD ODifferential Host Output Clock Pairs. See Table 1 for frequency/functionality.
10, 11, 12, 13,
16, 17, 18 PCI(0:6) VDDP OPCI Clock Outputs. Are synchronous to 66IN or 3V66 clock. See Table 1.
5, 6, 7 PCIF (0:2) VDD O33-MHz PCI Clocks. ÷2 c opies of 66IN o r 3V66 clocks th at may be free running
(not stopped when PCI_STP# is asserted LOW) or may be stoppable depending
on the programming of SMBus register Byte3,Bits (3:5).
56 REF VDD OBuffered Output Copy of the Device’s XIN Clock.
42 IREF VDD ICurrent Reference Programming Input for CPU Buffers. A resistor is
connected between this pin and VSSIREF.
28 VTT_PG# VDD IQuali fying Input that Latches S(0: 2) and MUL T0. Wh en this input is at a logic
LOW, the S(0:2) and MULT0 are latched.
39 48MUSB VDD48 OFixed 48-MHz USB Clock Outputs.
38 48MDOT VDD48 OFixed 48-MHZ DOT Clock Outputs.
33 3V66_0 VDD O3.3V 66-MHz Fixed-frequency Clock.
35 3V66_1/VCH VDD O3.3V Clock Selectable with SMBus Byte0,Bit5, When Byte5,Bit5. When Byte
0,Bit 5 is at a logic 1, then this pin is a 48M output clock. When Byte0,Bit5 is a
logic 0, this is a 66M output clock (default).
25 PD# VDD I
PU Power-down Mode Pin. A logic LOW level causes the device to enter a
power-do wn state. All interna l logic is turn ed of f exce pt for the SMBu s logic . All
output buffers are stopped.
43 MULT0 I
PU Programming Input Selection for CPU Clock Current Multiplier.
55, 54 S(0,1) I I Frequency Select Inputs. See Table 1.
29 SDATA I I Serial Data Input. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.
30 SCLK I I Serial Clock Input. Conforms to the SMBus specification.
40 S2 VDD I
TFrequency Select Input. See Table 1. This is a Tri-level input which is driven
HIGH, LOW or driven to a intermediate level.
34 PCI_STP# VDD I
PU PCI Clock Disable Input. When asserted LOW, PCI (0:6) clocks are synchro-
nously disabled in a LOW state. This pin does not effect PCIF (0:2) clocks’
outputs if they are programmed to be PCIF clocks via the device’s SMBus
interface.
53 CPU_STP# VDD I
PU CPU Clock Disable Input. When asserted LOW, CPUT (0:2) clocks are synchro-
nously disabled in a HIGH state and CPUC(0:2) clocks are synchronously
disabled in a LOW state.
24 66IN/3V66_5 VDD I/O Input Connection for 66CLK(0:2) Output Clock Buffers if S2 = 1, or output
clock for fixed 66-MHz clock if S2 = 0. See Table 1.
21, 22, 23 66B(0:2)/
3V66(2:4) VDD O3.3V Clock Outputs. These clocks are buffered copies of the 66IN clock or fixed
at 66 MHz. See Table 1.
1, 8, 14, 19, 32,
37, 46, 50 VDD PWR 3.3V Power Supply.
4, 9, 15, 20, 27,
31, 36, 47 VSS PWR Common Grou nd.
41 VSSIREF PWR Current Reference Programming Input for CPU Buffers. A resistor is
connected between this pin and IREF. This pin should also be returned to device
VSS.
26 VDDA –PWR Analog Power Input . Us ed for p has e-l oc ked lo ops (PLL s) a nd i nte rnal an alo g
circuits . It is al so sp ecific ally used to detect a nd dete rmine wh en pow er is at a n
acceptable level to enable the device to operate.
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Two-Wire SMBus Contr ol Interface
The t wo-wire co ntro l interf ace im plements a Re ad/W rite s lave
only interface according to SMBus specification.
The d evice will acc ept data written to th e D2 address a nd data
may read back from address D3. It will not respond to any other
addresses, and previously set control regis ters are retained a s
long as power in maintained on the device.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
1. “Command code“ byte
2. “Byte count” byte.
Although the data (bits) in the command is considered “don’t
care,” it must be sent and will be acknowledged. After the
Command Code and the Byte Count have been acknowl-
edged, the sequence (Byte 0, Byte 1, and Byte 2) described
below will be valid an d acknowledged.
Byte 0: CPU Clock Register[2,3]
Bit @Pup Pin# Description
7 0 Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On
This is a Read and Write control bit.
6 0 CPU Clock Power-down Mode Select. 0 = Drive CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2)
LOW when PD # is asserte d LOW. 1 = T ri-stat e all CPU ou tputs. Thi s is only ap plicable when
PD# is LOW. It is not applicable to CPU_STP#.
5 0 35 3V66_1/VCH Frequency Select, 0 = 66M selected, 1 = 48M selected
This is a Read and Write control bit.
4 Pin 53 44,45,48,49,5
1,52 CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is
Read-only.
3 Pin 34 10,11,12,13,1
6,17,18 Reflects the current va lue of the internal PCI _STP# function when read. In ternally PCI_STP#
is a logical AND function of the internal SMBus register bit and the external PCI_STP# pin.
2 Pin 40 Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read-only.
1 Pin 55 Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read-only.
0 Pin 54 Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read-only.
Byte 1: CPU Clock Register
Bit @Pup Pin# Description
7 Pin 43 43 MULT0 (Pin 43) Value. This bit is Read-only.
6 0 53 CPUT/C(0:2) Output Functionality Control When CPU_STP# is Asserted. 0 = Drive
CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) LOW when CPU_STP# asserted LOW.
1 = three-state all CPU outputs. This bit will override Byte0,Bit6 such that even if it is 0,
when PD# goes LOW the CPU outputs will be three-stated.
5 0 44,45 CPU2 Functionality Control When CPU_STP# is Asserted LOW. 1 = Fr ee Running, 0 =
Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.
4 0 48,49 CPU1 Functionality Control When CPU_STP# is Asserted LOW. 1 = Fr ee Running, 0 =
Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.
3 0 51,52 CPUT0 Fun ctiona lity Cont rol When CPU_ STP# is Asse rted LOW. 1 = Free Runnin g, 0 =
Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.
2 1 44,45 CPUT/C2 Output Control. 1 = e nabled, 0 = di sable HIGH and CPUC2 dis ables LOW . T his
is a Read and Write control bit.
1 1 48,49 CPUT/C1 Output Control. 1 = e nabled, 0 = di sable HIGH and CPUC1 dis ables LOW . T his
is a Read and Write control bit.
0 1 51,52 CPUT/C0 Output Control. 1 = e nabled, 0 = di sable HIGH and CPUC0 dis ables LOW . T his
is a Read and Write control bit.
Notes:
2. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 – 1.8V and HIGH = > 2.0V.
3. The “Pin#” column lists the relevant pin number where applicable. The “@Pup” column gives the default state at power-up.
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Byte 2: PCI Clock Control Register (all bits are Read and Write functional)
Bit @Pup Pin# Description
7 0 53 REF Output Control. 0 = high strength, 1 = low strength.
6 1 18 PCI6 Output Control. 1 = enabled, 0 = forced LOW.
5 1 17 PCI5 Output Control. 1 = enabled, 0 = forced LOW.
4 1 16 PCI4 Output Control. 1 = enabled, 0 = forced LOW.
3 1 13 PCI3 Output Control. 1 = enabled, 0 = forced LOW.
2 1 12 PCI2 Output Control. 1 = enabled, 0 = forced LOW.
1 1 11 PCI1 Output Control. 1 = enabled, 0 = forced LOW.
0 1 10 PCI0 Output Control. 1 = enabled, 0 = forced LOW.
Byte 3: PCI_F Clock and 48M Control Register (all bits are Read and Write functional)
Bit @Pup Pin# Description
7 1 38 48MDOT Output Control. 1 = enabled, 0 = forced LOW.
6 1 39 48MUSB Output Control. 1 = enabled, 0 = forced LOW.
5 0 7 PCI_STP#, Control of PCI_F2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
4 0 6 PCI_STP#, Control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
3 0 5 PCI_STP#, Control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
2 1 7 PCI_F2 Output Control. 1 = running, 0 = forced LOW.
1 1 6 PCI_F1 Output Control. 1 = running, 0 = forced LOW.
0 1 5 PCI_F0 Output Control. 1 = running, 0 = forced LOW.
Byte 4: DRCG Control Register (all bits are Read and Write functional)
Bit @Pup Pin# Description
7 0 SS2 Spread Spectrum Control Bit (0 = down spread, 1 = center spread).
6 0 Reserved. Set = 0.
5 1 33 3V66_0 Output Enabled. 1 = enabled, 0 = disable.
4 1 35 3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled.
3 1 24 3V66_5 Output Enable. 1 = enabled, 0 = disabled.
2 1 23 66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled.
1 1 22 66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled.
0 1 21 66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled.
Byte 5: Clock Control Register (all bits are Read and Write functional)
Bit @Pup Pin# Description
7 0 SS1 Spread Spectrum Control Bit.
6 1 SS0 Spread Spectrum Control Bit.
5 0 66IN to 66M delay Control MSB.
4 0 66IN to 66M delay Control LSB.
3 0 Reserved. Set = 0.
2 0 48MDOT Edge Rate Control. When set to 1, the edge is slowed by 15%.
1 0 Reserved. Set = 0.
0 0 USB edge rate control. When set to 1, the edge is slowed by 15%.
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Byte 6: Silicon Signature Register[4] (all bits are Read-only)
Bit @Pup Pin# Description
7 0 Revision = 0001
60
50
41
3 0 Vendor Code = 0011
20
11
01
Byte 7: Rese rved Register
Bit @Pup Pin# Description
70 Reserved. Set = 0.
60 Reserved. Set = 0.
50 Reserved. Set = 0.
40 Reserved. Set = 0.
30 Reserved. Set = 0.
20 Reserved. Set = 0.
10 Reserved. Set = 0.
00 Reserved. Set = 0.
Byte 8: Dial-a-Frequency Control Register N
Bit @Pup Name Description
7 0 Reserved. Set = 0.
6 0 N6, MSB These bits are for programming the PLL’s int erna l N reg is ter. This ac ce ss a llo w s the us er to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
50N5
40N4
30N3
20N2
10N3
00N0, LSB
Byte 9: Dial-a-Frequency Control Register R
Bit @Pup Name Description
7 0 Reserved. Set = 0.
6 0 R5, MSB These bits are for pro gramm ing the PLL’s internal R regi ste r. This access al lo ws the us er to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
50R4
40R3
30R2
20R1
10R0
00
DAF_ENB R and N reg ist er mux s el ec tion . 0 = R an d N va lue s com e from the R OM. 1 = data is loaded
from DAF (SMBus) registers.
Note:
4. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.
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Dial-a-Frequency Features
SMBus D ial-a-Frequenc y feature is availabl e in this device via
Byte8 and Byte9.
P is a large-v alue PLL constant that depends on the frequency
selec tion achieved t hrough the hard ware selectors (S1, S0). P
value may be determined from Table 2.
Dial-a-dB Features
SMBus Dial-a-dB feature is available in this device via Byte8
and Byte9.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to
minimizing EMI radiation generated by repetitive digital
signals. A clock presents the greatest EMI energy at the center
frequency it is generating. Spread Spectrum distributes this
energy over a specific and controlled frequency bandwidth
therefore causing the average energy at
any o ne point in this band to dec rease in v alue. This technique
is achieved by modulating the clock away from its resting
frequ ency by a c ertain perce ntage (whi ch a lso d etermi nes t he
amount of EMI reduction). In this device, Spread Spectrum is
enabled by setting specific register bits in the SMBus control
bytes. Table 3 is a listing of the modes and percentages of
Spread Spectrum modulation that this device incorporates.
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the di fferential Host Clock Outputs.
Table 2. P V alu e
S(1:0) P
0 0 32005333
0 1 48008000
1 0 96016000
1 1 64010667
Table 3. Spread Spectrum
SS2 SS1 SS0 Spread Mode Spread%
0 0 0 Down +0.00, –0.25
0 0 1 Down +0.00, –0.50
0 1 0 Down +0.00, –0.75
0 1 1 Down +0.00, –1.00
1 0 0 Center +0.13, –0.13
1 0 1 Center +0.25, –0.25
1 1 0 Center +0.37, –0.37
1 1 1 Center +0.50, –1.50
M easurem ent Poin t
2pF
CPUT
MULTSEL
TPCB
TPCB
CPUC
220Ω
63.4Ω 63.4Ω
475Ω
33.2Ω
33.2Ω Measu rem en t Point
2pF
Figure 1. 1.0V Test Load Termination
CPUT
MULTSEL
TPCB
TPCB
CPUC
33Ω
33Ω M easurement Point
49.9Ω
49.9Ω 2pF
Me asurement Point
2pF
475Ω
VDD
Figure 2. 0.7V Test Load Termination
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Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference
circuit details are contained in the previous table of this data
sheet. The following parameters are used to specify output
buffer characteristic s:
1. Output impedance of the current mode buffer circuit – Ro
(see Figure 4).
2. Minimum and maximum required voltage operation range
of the circuit – Vop (see Figure 4).
3. Series res is tan ce i n the bu f f er ci rcuit – Ros (see Figure 4).
4. Current accuracy at given configuration into nominal test
load for given configuration.
2.4V
0.4V
3.3V
0V
Tr Tf
1.5V
3.3V signals
tDC
Probe
Output unde r Test
Load Cap
--
Figure 3. For Single-ended Output Signals
1.2V0V
Iout
Iout
Ros
Ro
VDD3 (3.3V +/- 5%)
Vout = 1.2V max Vout
Slope ~ 1/R
0
Figure 4. Buffer Characteris tics
Table 4. Host Clock (HCSL) Buffer Characteristics
Characteristic Min. Max.
Ro 3000Ω (recommended) N/A
Ros
Vout N/A 1.2V
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Document #: 38-07331 Rev. *A Page 8 of 20
Iout is selectable depending on implementation. The param-
eters above apply to all configurations. Vout is the voltage at
the pin of the device.
The various output current configurations are shown in the
host swing select functions table. For all configurations, the
deviat ion from the expected outp ut current is ±7% as sh own in
the current accuracy table.
USB and DOT 48M Phase Relationship
The 48MUSB and 48MDOT clocks are in phase. It is under-
stood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for
VCH (48-MHz) operation it is also in phase with the USB and
DOT outputs . See Figure 5.
66IN to 66 B ( 0 :2 ) B u ffered P ro p D e lay
The 66IN to 66B(0:2) output delay is shown in Figure 6.
The Tpd is the prop delay from the input pin (66IN) to the
output pins (66B[0:2]). The outputs’ variation of Tpd is
described in the AC parameters section of this data sheet. The
measurement taken at 1.5V.
66B(0:2) to PCI Buffered Clock Skew
Fig ure 7 shows the difference (skew) between the 3V33(0:5)
outputs when the 66M clocks are connected to 66IN. This
offset is described in the Group T iming Relationship and Toler-
ances section of this data sheet. The measurements were
taken at 1.5V.
3V66 to P C I U n -B u ffer e d Cl o ck Ske w
Figure 8 shows the timing relati onship betwee n 3V66(0:5) and
PCI(0:6) and PCI _F(0 :2) whe n co nfi gured to run in the unbuf-
fered mode.
Table 5. CPU Clock Current Select Function
Mult0 Board Target Trace/Term Z Reference R, Iref – Vdd (3*Rr) Output Current Voh @ Z
0 50ΩRr = 221 1%, Iref = 5.00mA Ioh = 4*Iref 1.0V @ 50
1 50ΩRr = 475 1%, Iref = 2.32mA Ioh = 6*Iref 0.7V @ 50
Table 6. Group T i min g Relations hip and Tolerances
Description Offset Tolerance Conditions
3V66 to PCI 2.5 ns ±1.0 ns 3V66 Leads PCI (unbuffered mode)
48MUSB to 48MDOT Skew 0.0 ns ±1.0 ns 0 degrees phase shift
66B(0:2) to PCI offset 2.5 ns ±1.0 ns 66B Leads PCI (buffered mode)
48MUSB
48MDOT
Figure 5. 48MUSB and 48MDOT Phase Relationship
66IN
66B(0:2)
Tpd
Figure 6. 66IN to 66B(0:2) Output Delay Figure
66B(0:2)
PCI(0:6)
PCIF(0:2)
1.5-
3.5ns
Figure 7. Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship
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Special Functions
PCI_F and IOAPIC Clock Outputs
The PCIF clock outputs are intended to be used, if required,
for systems IOAPIC clock functionality. Any two of the PCI_F
clock outputs can be used as IOAPIC 33 Mhz clock outputs.
They are 3.3V outputs will be divided down via a simple
resistive voltage divider to meet specific system IOAPIC clock
voltage requirements. In the event that these clocks are not
required, they can be used as general PCI clocks or disabled
via the assertion of the PC I_STP# pin.
3V66_1/VCH Clock Output
The 3V66_1/VCH pin has a dual functionality that is selectab le
via SMBus.
Configured as DRCG (66M), SMBus Byte0, Bit 5 = “0”
The default condition for this pin is to power-up in a 66M
operation. In 66M operation this output is SSCG-capable and
when spreading is turned on, this clock will be modulated.
Configured as VCH (48M), SMBus Byte0, Bit 5 = “1”
In this mode, output is configured as a 48-Mhz non-spread
spectrum output that is phase-aligned with other 48M outputs
(USB and DOT) to within 1 ns pin-to-pin skew. The switching
of 3V66_1/VCH into VCH mode occurs at system power-on.
When the SMBus Bit 5 of Byte 0 is programmed from a “0” to
a “1,” the 3 V66_1/VCH outp ut may glit ch whil e tr ansition ing to
48M output mode.
CPU_STP# Clarification
The CPU_STP# signal is an active LOW input used to
synch ron ous ly sto p an d start the CPU output c lo cks w hi le the
rest of the clock generator continues to function.
CPU_STP# – Assertion
When CPU_STP# pin is asserted, all CPUT/C outpu ts that are
set wit h the SMBus configurati on to be s toppable via assertion
of CPU_STP# will be stopped after being sampled by two
falling CPUT/C clock edges. The final state of the stopped
CPU signals is CPUT = HIGH and CPU0C = LOW . There is no
change to the output drive current values during the stopped
state. The CPUT is driven HIGH with a current value equal to
(Mult 0 “select”) × (Iref), and the CPUC signal will not be
driven. Due to external pull-down circuitry CPUC will be LOW
during this stopped state.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all
CPUT/C outputs that were stopped to resume normal
oper atio n in a sy nc hro nou s m an ner (m ea nin g that no sho rt or
stretched clock pulses will be produces when the clock
resumes). The maximum latency from the deassertion to
active outputs is no more than two CPUC clock cycles.
Three-state Control of CPU Clocks Clarification
During CPU_STP# and PD# modes, CPU clock outputs may
be set to driven or undriven (tri-state) by setting the corre-
sponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.
PCI(0:6)
PCI_F(0:2)
Tpci
3V66(0:5)
Figure 8. Unbuffered Mode – 3V66(0:5) to PCI (0:6) and PCI_F(0:2) Phase Relationship
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 9. CPU_STP# Assertion W aveform
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PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for c ap turi ng PCI_ STP# g oin g LO W is 10 ns (tsetup) (see
Fig u re 14.) The PCI_F (0:2) clocks will not be affected by this
pin if their control bits in the SMBus register are set to allow
them to be free running.
Table 7. Cypress Clock Power Management Truth Table
B0b6 B1b6 PD# CPU_STP# Stoppable
CPUT Stoppable
CPUC Non-Stop CPUT Non-Stop CPUC
0 0 1 1 Running Running Running Running
0 0 1 0 Iref x6 Iref x6 Running Running
0 0 0 1 Iref x2 LOW Iref x2 LOW
0 0 0 0 Iref x2 LOW Iref x2 LOW
0 1 1 1 Running Running Running Running
0 1 1 0 Hi-Z Hi-Z Running Running
0 1 0 1 Hi-Z Hi-Z Hi-Z Hi-Z
0 1 0 0 Hi-Z Hi-Z Hi-Z Hi-Z
1 0 1 1 Running Running Running Running
1 0 1 0 Iref x6 Iref x6 Running Running
1 0 0 1 Hi-Z Hi-Z Hi-Z Hi-Z
1 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z
1 1 1 1 Running Running Running Running
1 1 1 0 Hi-Z Hi-Z Running Running
1 1 0 1 Hi-Z Hi-Z Hi-Z Hi-Z
1 1 0 0 Hi-Z Hi-Z Hi-Z Hi-Z
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 10. CPU_STP# Deassertion Waveform
CY28346
Document #: 38-07331 Rev. *A Page 11 of 20
PCI_STP# – Deassertion (transition from logic “0”
to logic “1”)
The deassertion of the PCI_STP# signal will cause all PCI(0:6)
and stoppable PCI_F(0:2) clocks to resume running in a
synchronous manner within two PCI clock periods after
PCI_STP# transitions to a HIGH level.
Note. The PCI ST OP functi on is controll ed by two inputs . One
is the device PCI_STP# pin number 34 and the other is SMBus
Byte 0,Bit 3. These two inputs to the function are logically
AND’ed. If either the external pin or the internal SMBus
register bit is set LOW, the stoppable PCI clocks will be
stoppe d in a logic LOW state. Re ading SMBus By te 0,Bit 3 will
return a 0 value if either of these control bits are set LOW
(whic h indica tes that th e devices stoppable PCI clock s are not
running).
PD# (Power-down) Clarification
The PD# (power-down) pin is used to shut off all clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW in put . Th is si gn al is synchroniz ed in tern all y to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is LOW, all clocks are driven to a LOW value and held there
and the VCO an d PLLs are al so pow ered down. Al l clo cks are
shut down in a synchronous manner so has not to cause
glitches while transitioning to the LOW “stopped” state.
PD# – Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock, then on the next HIGH-to-LOW transition
of PCIF, the PCIF clock is stopped LOW. On the next
HIGH-to -LOW trans ition of 66Buff, the 66 Buff c lock is st opped
LOW. From this time, each clock will stop LOW on its next
HIGH-to-LOW transition, except the CPUT clock. The CPU
clocks are held with the CPUT clock pin driven HIGH with a
value of 2 × Iref, and CPUC undriven. After the last clock has
stopped, the rest of the generator will be shut down.
PD# – Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 3.0 ms.
PCI_STP#
PCI_F(0:2) 33M
PCI(0:6) 33M
setup
t
Figure 11. PCI_STP# Assertion Waveform
PCI_STP#
PCI_F(0:2)
PCI(0:6)
setup
t
Figure 12. PCI_STP# Deassertion Waveform
CY28346
Document #: 38-07331 Rev. *A Page 12 of 20
66Buff[0..2]
PCIF
PWRDWN#
C PU 133M H z
CP U# 133M H z
3V66
66In
R EF 14.318MH z
USB 48MH z
Figure 13. power-down Assertion Timing Waveforms Figure – Buffered Mode
PC I 33M Hz
PWRDWN#
C PU T (0:2) 133M H z
C PU C (0:2) 133M Hz
R EF 14.318M H z
USB 48M Hz
3V66
Figure 14. Power-down Assertion Timing Waveforms –Unbuffered Mode
CY28346
Document #: 38-07331 Rev. *A Page 13 of 20
Table 8. PD# Functionality
PD# DRCG 66CLK (0:2) PCI_F/PCI PCI USB/DOT
1 66M 66Input 66Input/2 66Input/2 48M
0 LOW LOW LOW LOW LOW
CPU 13 3M Hz
3V66
CPU# 133MHz
REF 14.318MHz
USB 48MHz
PC IF / AP IC
33MHz
66In
66Buff[0,2]
PWRDWN#
66 B uff1 / GMC H
400uS max<1.8mS
PCI 33M Hz
30uS min
Figure 15. Power-down D eas sertio n Timing Wa vefo rms – Buffered Mode
CY28346
Document #: 38-07331 Rev. *A Page 14 of 20
Maximum Ratings
Input Voltage Relative to VSS:.............................. VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: .............VDD + 0.3V
Storage Temperature:................................ –65°C to + 150°C
Operating Temperature:.................................... 0°C to +85°C
Maximum Power Supply:................................................3.5V
Current Accuracy[5]
Parameter Conditions Configuration Load Min. Max.
Iout VDD = nominal (3.30V) M0 = 0 or 1 and Rr (see Table 1) Nominal test load for given
configuration –7%
Inom + 7%
Inom
Iout VDD = 3.30 ± 5% All combinations of M0 or 1 and Rr
(see Table 1)Nominal test load for given
configuration –12%
Inom + 12%
Inom
DC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C)
Parameter Description Conditions Min. Typ. Max. Unit
IDD3.3V Dynamic Supply Current All frequencies at maximum values[6] 280 mA
IPD3.3V Power-down Supply Current PD# asserted Note 7 mA
CIN Input Pin Capa cit anc e 5pF
COUT Output Pin Capacitance 6pF
LPIN Pin Inductance 7nH
CXTAL Crystal Pin Capacitance Measured from the XIN or XOUT pin to ground 30 36 42 pF
AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C)
Parameter Description 66 MHz 100 MH z 133 MHz 200 MHz Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.
Crystal
TDC XIN Duty Cycle 47.5 52.5 47.5 52.5 47.5 52.5 47.5 52.5 % 8, 9, 10
TPERIOD XIN period 69.84 71.0 69.84 71.0 69.84 71 .0 69 .84 71.0 ns 8, 11,
12, 9
VHIGH XIN HIGH Voltage 0.7VDD VDD 0.7VDD VDD 0.7VDD VDD 0.7VDD VDD V
VLOW XIN LOW Voltage 0 0.3VDD 00.3V
DD 00.3V
DD 00.3V
DD V
TR / TFXIN Rise and Fall Times 10.0 10.0 10.0 10.0 ns 13
TCCJ XIN Cycle to C ycle Ji tter 500 500 500 500 ps 11, 14 , 9
CPU at 0.7V Timing
TDC CPUT and CPUC Duty
Cycle 45 55 45 55 45 55 45 55 % 14, 15,
18
TPERIOD CPUT and CPUC
Period 14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 14, 15,
18
TSKEW Any CPU to CPU Clock
Skew 100 100 100 100 ps 11, 14,
15
Notes:
5. Inom refers to the expected current based on the configuration of the device.
6. All outputs loaded as per maximum capacitive load table.
7. Absolute value = ((Programmed CPU Iref) × (2)) + 10 mA.
8. This parameter is measured as an average over 1 µs duration, with a crystal center frequency of 14.31818 MHz.
9. When Xin is driven from an external clock source.
10. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
11. All outputs loaded as per Table 9 below.
12. Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet).
13. Measur ed bet w een 0.2V DD and 0.7VDD.
14. This measurement is applicable with Spread ON or Spread OFF.
15. Measured at crossing point (Vx) or where subtraction of CLK–CLK# crosses 0V Measured from VOL = 0.175V to VOH = 0.525V.
16. Measur ed fro m VOL = 0.175V to VOH = 0.525V.
17. Determined as a f raction of 2*(Trise–Tfall)/ (Trise+Tfall).
18. Test load is Rta = 33.2Ω, Rd = 49.9Ω .
CY28346
Document #: 38-07331 Rev. *A Page 15 of 20
TCCJ CPU Cycle to Cycle
Jitter 150 150 150 150 ps 14, 15,
18
TR/TFCPUT and CPUC Rise
and Fall Times 175 700 175 700 175 700 175 700 ps 14, 16,
19
Rise/Fall Matching 20% 20% 20% 20% 16, 17,
18
DeltaTRRise Time Variation 125 125 125 125 ps 16, 18
DeltaTFFall Time Variation 125 125 125 125 ps 16, 18
VCROSS Crossing Poin t Voltag e
at 0.7V Swing 280 430 280 430 280 430 280 430 mV 14, 18
CPU at 1.0V Timing
TDC CPUT and CPUC Duty
Cycle 45 55 45 55 45 55 45 55 % 14, 15
TPERIOD CPUT and CPUC
Period 14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 nS 14, 15
TSKEW Any CPU to Any CPU
Clock Skew 100 100 100 100 pS 11, 14,
15
TCCJ CPU Cycle to Cycle
Jitter 150 150 150 150 pS 11, 15
Differential
TR/TFCPUT and CPUC Rise
and Fall Times 175 467 175 467 175 467 175 467 ps 14, 19
SE–
DeltaSlew Abso lute Single- ended
Rise/Fall Waveform
Symmetry
325 325 325 325 ps 20, 21
VCROSS Cross Point at 1.0V
swing 510 760 510 760 510 760 510 760 mV 21
3V66
TDC 3V66 Duty Cycle 45 55 45 55 45 5 5 45 55 % 11, 12
TPERIOD 3V66 Perio d 15.0 15.3 15.0 15.3 15.0 15.3 15.0 15.3 ns 8, 11, 12
THIGH 3V66 HIGH Time 4.95 4.95 4.95 4.95 ns 22
TLOW 3V66 LOW Time 4.55 4.55 4.55 4.55 ns 23
TR/TF3V66 Rise and Fall
Times 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 24
TSKEW
Unbuffered 3V66 to 3V66 Clock
Skew 500 500 500 500 ps 11, 12
TSKEW
Buffered 3V66 to 3V 66 Cloc k
Skew 250 250 250 250 ps 11, 12
TCCJ DRCG Cycle to Cycle
Jitter 250 250 250 250 ps 11, 12
Notes:
19. Measurement taken from differential waveform, from –0.35V to +0.35V.
20. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as “the instantaneous
difference between maximum CLK rise (fall) and minimum CLK# fall (rise) time or minimum CLK rise (fall) and maximum CLK# fall (rise) time.” This pa ram ete r
is designed form waveform symmetry.
21. Measured in absolute voltage, i.e., single-ended measurement.
22. THIGH is measured at 2.4V for non-host outputs.
23. TLOW is measured at 0.4V for all outputs.
24. Pro bes ar e plac ed on t he pins , and measur ement s are a cquir ed bet ween 0.4V an d 2.4V for 3. 3V si gnals ( see t est and measu remen t set-up section of this data
sheet).
AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C) (continued)
Parameter Description 66 MHz 100 MH z 133 MHz 200 MHz Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.
CY28346
Document #: 38-07331 Rev. *A Page 16 of 20
66B
TDC 66B(0:2) Duty Cycle 45 55 45 55 45 55 45 55 % 11, 12
TR/TF66B(0:2) Rise and Fall
Times 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 11, 24
TSKEW Any 66B to Any 66B
Skew 175 175 175 175 ps 11, 12
TPD 66IN to 66B(0:2 ) Propa-
gation Delay 2.5 4.5 2.5 4.5 2.5 4.5 2.5 4.5 ns 11, 12
TCCJ 66B(0:2) Cycle to Cycle
Jitter 100 100 100 100 ps 11, 12,
25
PCI
TDC PCI_F(0:2) PCI (0:6)
Duty Cycle 45 55 45 55 45 55 45 55 % 11, 12
TPERIOD PCI_F(0:2) PCI (0:6)
Period 30.0 30.0 30.0 30 nS 8, 1 1, 12
THIGH PCI_F(0:2) PCI (0:6)
HIGH Time 12.0 12.0 12.0 12.0 nS 22
TLOW PCI_F(0:2) PCI (0:6)
LOW Time 12.0 12.0 12.0 12.0 nS 23
TR/TFPCI_F(0:2) PCI (0 :6)
Rise and Fall Times 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 nS 24
TSKEW Any PCI Clock to Any
PCI Clock Skew 500 500 500 500 pS 11, 12
TCCJ PCI_F(0:2) PCI (0:6)
Cycle to Cycle Jitter 250 250 250 250 ps 11, 12
48MUSB
TDC 48MUSB Duty Cycle 45 55 45 55 45 55 45 55 % 11, 12
TPERIOD 48M USB Period 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 11, 12
TR/TF48MUSB Rise and Fall
Times 1.0 2.0 1.0 2.0 1.0 2.0 1.0 2.10 ns 11, 24
TCCJ 48MUSB Cycle to Cycle
Jitter 350 350 350 350 ps 8, 1 1, 12
48MDOT
TDC 48MDOT Duty Cycle 45 55 45 55 45 55 45 55 % 11, 12
TPERIOD 48MDOT Perio d 20.837 20.837 20.837 20.837 ns 11, 12
TR/TF48MDOT Rise and Fall
Times 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 ns 11, 12
TCCJ 48MDOT Cycle to Cycle
Jitter 350 350 350 350 ps 11, 12
REF
TDC REF Duty Cycle 4 5 55 45 55 45 55 45 55 % 11, 12
TPERIOD REF Period 69.84 71.0 69.84 71.0 69.84 71.0 69.84 71.0 ns 11, 12
TR/TFREF Rise and Fall
Times 1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns 11, 24
TCCJ REF Cycle to Cycle
Jitter 1000 1000 1000 1000 ps 11, 12
Note:
25. This figure is in addition to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500-ps jitter figure is specified .
AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C) (continued)
Parameter Description 66 MHz 100 MH z 133 MHz 200 MHz Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.
CY28346
Document #: 38-07331 Rev. *A Page 17 of 20
TPZL/TPZH Outp ut Enab le Dela y
(All Outputs) 1.0 10.0 1.0 10.0 1.0 10.0 1.0 10.0 ns 9
TPZL/TPZH Output disable delay (all
outputs) 1.0 10.0 1.0 10.0 1.0 10.0 1.0 10.0 ns 9
TSTABLE All Clock Stabilization
from Power-up 3333ms9
TSS Stopclock Set-up Time 10.0 10.0 10.0 10.0 ns 26
TSH Stopclock Hold Time 0 0 0 0 ns 26
TSU Oscillator Start-up Ti me X X X X ms 27
AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C) (continued)
Parameter Description 66 MHz 100 MH z 133 MHz 200 MHz Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.
Table 9. Maximum Lumped Capacitive Output Loads
Clock Max Load Units
PCI Clocks 30 pF
3V66 (0,1) 30 pF
66B(0:2) 30 pF
48MUSB Cloc k 20 pF
48MDOT 10 pF
REF Clock 50 pF
Notes:
26. CPU_STP# and PCI _STP# set-up time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock’s rising edge
27. When crystal meets minimum 40Ω device series resistance specification.
28. Device is not affected, VTT_PWRGD# is ignored.
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
VDD Clock Gen
Clock S tate
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0 State 2 State 3
Wait for
VTT_GD# Sample Sels
Off
Off
On
On
State 1
(Note A)
Figure 16. VTT_PWRGD# Timin g
CY28346
Document #: 38-07331 Rev. *A Page 18 of 20
Package Drawing and Dimensions
Order in g In fo rmat io n
Part Number Package Type Product Flow
CY28346OC 56-pin SSOP – Tube Commerci al, 0° to 7 0 °C
CY28346OCT 56-pin SSOP – Tape and Reel Commercial, 0° to 70°C
CY28346ZC 56-pin TSSOP – Tube Commercial, 0° to 7 0 °C
CY28346ZCT 56-pin TSSOP – Tape and Reel Commercial, 0° to 70°C
VTTPWRGD#
= Low
Delay 0.25mS
S1
Power Off
S0
VDDA = 2.0V
Sample
Inputs (pins
54,55)
S2
VDD3.3 = Off Normal
Operation
S3
Enable Outputs
Figure 17. Clock Generator Power-up/Run State Diagram
56-lead Shrunk Small Outline Package O56
51-85062-C
CY28346
Document #: 38-07331 Rev. *A Page 19 of 20
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Intel is a registered trademark of Intel Corporation. Dial-a-Frequency and Dial-a-dB are trademarks of Cypress Semiconductor.
All product and company names mentioned in this document may be the trademarks of their respective holders.
51-85060-B
56-lead Thin Shrunk Small Outline Package, Type II (6 mm × 12 mm) Z56
