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FEATURES
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
VCC
4OE
4A
4Y
3OE
3A
3Y
D, DB, NS, OR PW PACKAGE
(TOP VIEW) RGY PACKAGE
(TOP VIEW)
1 14
7 8
2
3
4
5
6
13
12
11
10
9
4OE
4A
4Y
3OE
3A
1A
1Y
2OE
2A
2Y
1OE
3Y V
GND
CC
DESCRIPTION/ORDERING INFORMATION
SN74LV125ATQUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTS
SCES629A – MAY 2005 – REVISED AUGUST 2005
•Inputs Are TTL-Voltage Compatible •I
off
Supports Partial-Power-Down ModeOperation•4.5-V to 5.5-V V
CC
Operation
•Latch-Up Performance Exceeds 250 mA Per•Typical t
pd
of 3.8 ns at 5 V
JESD 17•Typical V
OLP
(Output Ground Bounce)
•ESD Protection Exceeds JESD 22<0.8 V at V
CC
= 5 V, T
A
= 25 °C
– 2000-V Human-Body Model (A114-A)•Typical V
OHV
(Output V
OH
Undershoot)>2.3 V at V
CC
= 5 V, T
A
= 25 °C – 200-V Machine Model (A115-A)•Support Mixed-Mode Voltage Operation on All – 1000-V Charged-Device Model (C101)Ports XXXX
XXXX
The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-stateoutputs. Each output is disabled when the associated output-enable ( OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGY Reel of 1000 SN74LV125ATRGYR VV125Tube of 50 SN74LV125ATDSOIC – D
Reel of 2500 SN74LV125ATDRTube of 50 SN74LV125ATNSSOP – NS
Reel of 2000 SN74LV125ATNSR–40 °C to 85 °C
Tube of 80 SN74LV125ATDB LV125ATSSOP – DB
Reel of 2000 SN74LV125ATDBRTube of 90 SN74LV125ATPWTSSOP – PW Reel of 2000 SN74LV125ATPWRReel of 250 SN74LV125ATPWT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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2A 2Y
2OE
1A 1Y
1OE 1
2
4
5
3
64A 4Y
4OE
3A 3Y
3OE 10
9
13
12
8
11
Absolute Maximum Ratings
(1)
SN74LV125AT
QUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTS
SCES629A – MAY 2005 – REVISED AUGUST 2005
FUNCTION TABLE(EACH BUFFER)
INPUTS
OUTPUT
YOE A
L H HLLLH X Z
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 7 VV
I
Input voltage range
(2)
–0.5 7 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 7 VV
O
Output voltage range
(2) (3)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –20 mAI
OK
Output clamp current V
O
< 0 or V
O
> V
CC
±50 mAI
O
Continuous output current V
O
= 0 to V
CC
±35 mAContinuous current through V
CC
or GND ±70 mAD package
(4)
86DB package
(4)
96θ
JA
Package thermal impedance NS package
(4)
76 °C/WPW package
(4)
113RGY package
(5)
47T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) This value is limited to 5.5 V maximum.(4) The package thermal impedance is calculated in accordance with JESD 51-7.(5) The package thermal impedance is calculated in accordance with JESD 51-5.
2
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Recommended Operating Conditions
(1)
Electrical Characteristics
Switching Characteristics
SN74LV125ATQUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTS
SCES629A – MAY 2005 – REVISED AUGUST 2005
MIN MAX UNIT
V
CC
Supply voltage 4.5 5.5 VV
IH
High-level input voltage V
CC
= 4.5 V to 5.5 V 2 VV
IL
Low-level input voltage V
CC
= 4.5 V to 5.5 V 0.8 VV
I
Input voltage 0 5.5 VHigh or low state 0 V
CCV
O
Output voltage V3-state 0 5.5I
OH
High-level output current V
CC
= 4.5 V to 5.5 V –16 mAI
OL
Low-level output current V
CC
= 4.5 V to 5.5 V 16 mA∆t/ ∆v Input transition rise or fall rate V
CC
= 4.5 V to 5.5 V 20 ns/VT
A
Operating free-air temperature –40 125 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
over recommended operating free-air temperature range (unless otherwise noted)
T
A
= –40 °C T
A
= –40 °CT
A
= 25 °C
to 85 °C to 125 °CPARAMETER TEST CONDITIONS V
CC
UNITMIN TYP MAX MIN MAX MIN MAX
I
OH
= –50 µA 4.5 V 4.4 4.5 4.4 4.4V
OH
VI
OH
= –16 mA 4.5 V 3.8 3.8 3.8I
OL
= 50 µA 4.5 V 0 0.1 0.1 0.1V
OL
VI
OL
= 16 mA 4.5 V 0.55 0.55 0.55I
I
V
I
= 5.5 V or GND 0 to 5.5 V ±0.1 ±1±1µAI
OZ
V
O
= V
CC
or GND 5.5 V ±0.25 ±2.5 ±2.5 µAI
CC
V
I
= V
CC
or GND, I
O
= 0 5.5 V 2 20 20 µAOne input at 3.4 V,∆I
CC
(1)
5.5 V 1.35 1.5 1.5 mAOther inputs at V
CC
or GNDI
off
V
I
or V
O
= 0 to 5.5 V 0 0.5 5 5 µAC
i
V
I
= V
CC
or GND 2 pF
(1) This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or V
CC
.
over recommended operating free-air temperature range, V
CC
= 5 V ±0.5 V (unless otherwise noted) (see Figure 1 )
T
A
= –40 °C T
A
= –40 °CT
A
= 25 °CFROM TO LOAD
to 85 °C to 125 °CPARAMETER UNIT(INPUT) (OUTPUT) CAPACITANCE
MIN TYP MAX MIN MAX MIN MAX
t
pd
A Y C
L
= 15 pF 1.9 3.8 5.5 1 6.5 1 8.5 nst
en
OE Y C
L
= 15 pF 2 3.6 5.1 1 6 1 7.5 nst
dis
OE Y C
L
= 15 pF 1.5 3.2 6.8 1 8 1 10 nst
pd
A Y C
L
= 50 pF 2.9 5.3 7.5 1 8.5 1 10.5 nst
en
OE Y C
L
= 50 pF 2.8 5.1 7.1 1 8 1 9.5 nst
dis
OE Y C
L
= 50 pF 2.8 6.1 8.8 1 10 1 10 nst
sk(o)
C
L
= 50 pF 1 1 1 ns
3
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Noise Characteristics
(1)
Operating Characteristics
SN74LV125AT
QUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTS
SCES629A – MAY 2005 – REVISED AUGUST 2005
V
CC
= 5 V, C
L
= 50 pF, T
A
= 25 °C
MIN TYP MAX UNIT
V
OL(P)
Quiet output, maximum dynamic V
OL
1.1 1.5 VV
OL(V)
Quiet output, minimum dynamic V
OL
–0.3 –0.8 VV
OH(V)
Quiet output, minimum dynamic V
OH
3 VV
IH(D)
High-level dynamic input voltage 2 VV
IL(D)
Low-level dynamic input voltage 0.8 V
(1) Characteristics are for surface-mount packages only.
V
CC
= 5 V, T
A
- 25 °C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance Outputs enabled C
L
= 50 pF, f = 10 MHz 16 pF
4
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PARAMETER MEASUREMENT INFORMATION
50% VCC
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
3 V
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
3 V
0 V
tw
VOLTAGE WA VEFORMS
PULSE DURATION
Input
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1 VCC
RL = 1 kΩGND
From Output
Under Test CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH − 0.3 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V1.5 V 1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
SN74LV125ATQUADRUPLE BUS BUFFER GATEWITH 3-STATE OUTPUTS
SCES629A – MAY 2005 – REVISED AUGUST 2005
Figure 1. Load Circuits and Voltage Waveforms
5
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LV125ATD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATDB ACTIVE SSOP DB 14 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATDBE4 ACTIVE SSOP DB 14 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATDBG4 ACTIVE SSOP DB 14 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATDBR ACTIVE SSOP DB 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATDBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATDBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATDE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATDRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATNS ACTIVE SO NS 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATNSE4 ACTIVE SO NS 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATNSG4 ACTIVE SO NS 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATNSR ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATNSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATNSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATPW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATPWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATPWT ACTIVE TSSOP PW 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LV125ATPWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATPWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV125ATRGYR ACTIVE VQFN RGY 14 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LV125ATRGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LV125ATDBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LV125ATDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LV125ATNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LV125ATPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV125ATPWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV125ATRGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV125ATDBR SSOP DB 14 2000 367.0 367.0 38.0
SN74LV125ATDR SOIC D 14 2500 367.0 367.0 38.0
SN74LV125ATNSR SO NS 14 2000 367.0 367.0 38.0
SN74LV125ATPWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74LV125ATPWT TSSOP PW 14 250 367.0 367.0 35.0
SN74LV125ATRGYR VQFN RGY 14 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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