○Product structure：Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays
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TSZ02201-0313AAF00660-1-2
© 2016 ROHM Co., Ltd. All rights reserved.
19.Feb.2016 Rev.001
TSZ22111・14・001
www.rohm.com
Power Supply IC Series for TFT-LCD Panels
Gamma voltage generated IC
with built-in DAC
BD81026MUV
General Description
The feature of gamma voltage generated IC
BD81026MUV provides a single-chip solution with a
high-precision 10-bit DAC setting controlled by I2C serial
communications interface and a buffer amp (12ch).
Features
Built in 10bit DAC (12ch)
Built in DAC Output Buffer Amplifier (12ch)
Double Register Switch Synchronously Function
(BKSEL)
DAC Output Latch Function (LD)
I2C Interface (SDA, SCL)
STANDARD-MODE, FAST-MODE changeable
Thermal Shut-Down Circuit
Under Voltage Lock-Out Function
Power ON Reset Circuit
Input Tolerant ( SDA, SCL, BKSEL, LD )
Applications
It may be used with TFT-LCD panels, such as big screen
and high resolution LCD televisions.
Key Specifications
Power Supply Voltage Range(VDD): 2.1V to 3.6V
Power Supply Voltage Range(VCC): 8.0V to 18.0V
Operating Temperature Range: -25°C to +85°C
Package W(Typ) x D(Typ) x H(Max)
VQFN024V4040
4.00mm x 4.00mm x 1.00mm
Datashee
t
Datashee
t
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TSZ02201-0313AAF00660-1-2
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19.Feb.2016 Rev.001
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TSZ22111・15・001
BD81026MUV
Block Diagram
LD
SCL
SDA
A0
BKSEL
PGND
6
DAC
OUT0
VCC
RESISTER
BANK A/B
×3.5
5
DAC
OUT1
VCC
RESISTER
BANK A/B
×3.5
4
DAC
OUT2
VCC
RESISTER
BANK A/B
×3.5
3
DAC
OUT3
VCC
RESISTER
BANK A/B
×3.5
2
DAC
OUT4
VCC
RESISTER
BANK A/B
×3.5
1
DAC
OUT5
VCC
RESISTER
BANK A/B
×3.5
24 DAC
VCC
RESISTER
BANK A/B
×3.5
23 DAC
VCC
RESISTER
BANK A/B
×3.5
22 DAC
VCC
RESISTER
BANK A/B
×3.5
21 DAC
VCC
RESISTER
BANK A/B
×3.5
20 DAC
VCC
RESISTER
BANK A/B
×3.5
19 DAC
VCC
RESISTER
BANK A/B
×3.5
7
8
9
10
11
12
13
14
15
161718
Power
ON
Reset
VREF
TSD
UVLO
VDD
VCC
AGND
VDD
MODE
N.C.
N.C.
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
Serial
I/F
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CTL
VCC
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
VDD
VDD
2.5R
R
REFIN
VCC
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TSZ02201-0313AAF00660-1-2
© 2016 ROHM Co., Ltd. All rights reserved.
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TSZ22111・15・001
BD81026MUV
Pin Configuration
Pin Description
PIN
No.
Pin name
Function
PIN
No.
Pin name
Function
1
OUT5
Gamma output pin 5
13
LD
Latch pin (Note 1)
2
OUT4
Gamma output pin 4
14
SCL
Serial clock input pin
3
OUT3
Gamma output pin 3
15
SDA
Serial data input pin
4
OUT2
Gamma output pin 2
16
A0
Device address switching pin
5
OUT1
Gamma output pin 1
17
BKSEL
BANK select pin (Note 2)
L : BANK A select
H : BANK B select
6
OUT0
Gamma output pin 0
18
PGND
DAC output buffer amplifier GND input
7
VCC
Buffer amplifier power supply input
for DAC output
19
OUT11
Gamma output pin 11
8
AGND
Logic, Analog GND input
20
OUT10
Gamma output pin 10
9
VDD
Logic, Analog power supply input
21
OUT9
Gamma output pin 9
10
MODE
BKSEL/LD mode switching pin
L : BKSEL writing mode select
H : LD writing mode select
22
OUT8
Gamma output pin 8
11
N.C.
-
23
OUT7
Gamma output pin 7
12
N.C.
-
24
OUT6
Gamma output pin 6
(Note 1) When Data writing function by LD pin control is not used, please connect LD pin to GND.
(Note 2) When Data writing function by BKSEL pin control is not used, please connect BKSEL pin to GND.
TOP VIEW
1 2 3 4 5 6
789101112
192021222324
131415161718
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TSZ22111・15・001
BD81026MUV
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Rating
Unit
Power Supply Voltage 1
VDD
4.5
V
Power Supply Voltage 2
VCC
19.0
V
Functional Pin Voltage
VBKSEL, VA0, VLD
VMODE
4.5
V
2 Lines Serial Pin Voltage
VSDA, VSCL
4.5
V
Junction Temperature
Tjmax
150
°C
Power Dissipation
Pd
3.56 (Note 1)
W
Operating Temperature Range
Topr
-25 to +85
°C
Storage Temperature Range
Tstg
-55 to +150
°C
(Note 1) To use the IC at temperatures over Ta25°C, derate power rating by 28.5mW/°C.
When mounted on a four-layer glass epoxy board measuring 74.2mm x 74.2mm x 1.6mm (All layer with copper foil: 5505mm2).
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions (Ta-25°C to +85°C)
Parameter
Symbol
Min
Max
Unit
Power Supply Voltage 1
VDD
2.1
3.6
V
Power Supply Voltage 2
VCC
8.0
18.0
V
Function Pin Voltage
VBKSEL, VA0, VLD
VMODE
-0.1
+3.6
V
2 Lines Serial Pin Voltage
VSDA, VSCL
-0.1
+3.6
V
2 Lines Serial Frequency
fCLK
-
400
kHz
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TSZ22111・15・001
BD81026MUV
Electrical Characteristics (Unless otherwise specified, Ta25°C, VDD=3.3V, VCC=12.6V)
Parameter
Symbol
Limit
Unit
Condition
MIN
TYP
MAX
【 Gamma Amplifier 】
Sink Current Capability
Nch Side (AMP0)
IooA
-
-
-10
mA
During REG0=3AFh (11.6V ) setting,
VOUT0=12.6V input
Sink Current Capability
Nch Side (AMP1 to AMP5,
AMP7 to AMP10)
IooB
-
-
-30
mA
During REG1 to REG5, REG7 to
REG10=1E8h (6.0V) setting, VOUT1
to VOUT5, VOUT7 to VOUT10=7V
Sink Current Capability
Nch Side (AMP6)
IooC
-
-
-60
mA
During REG6=1E8h (6.0V) setting,
VOUT6=7V
Sink Current Capability
Nch Side (AMP11)
IooD
-
-60
mA
During REG11=051h (1.0V) setting,
VOUT11=2V input
Source Current Capability
Pch Side (AMP0)
IoiA
60
-
-
mA
During REG0=3AFh (11.6V) setting,
VOUT0=10.6V input
Source Current Capability
Pch Side (AMP1 to AMP5,
AMP7 to AMP10)
IoiB
30
-
-
mA
During REG1 to REG5, REG7 to
REG10=1E8h (6.0V) setting, VOUT1
to VOUT5, VOUT7 to VOUT10=5V
Source Current Capability
Pch Side (AMP6)
IoiC
60
-
-
mA
During REG6=1E8h (6.0V) setting,
VOUT6=5V
Source Current Capability
Pch Side (AMP11)
IoiD
10
-
-
mA
During REG11=051h (1.0V) setting,
VOUT11=0V input
Load Stability (OUT0)
⊿VO-A
-
10
70
mV
During REG0=1E8h (6.0V) setting,
Io=0mA to -30mA
Load Stability (OUT1 to OUT5,
OUT7 to OUT10)
⊿VO-B
-
10
70
mV
During REG1 to REG5, REG7 to
REG10=1E8h
(6.0V) setting, IO=-15mA to +15mA
Load Stability (OUT6)
⊿VO-C
-
10
70
mV
During REG6=1E8h (6.0V) setting,
IO=-15mA to +15mA
Load Stability (OUT11)
⊿VO-D
-
10
70
mV
During REG11=1E8h (6.0V) setting,
IO=0mA to +30mA
MAX Output Voltage (OUT0)
VOH-A
VCC-0.2
VCC-0.1
-
V
IO=-30mA
MAX Output Voltage
(OUT1 to OUT5, OUT7 to
OUT10)
VOH-B
VCC-1.0
VCC-0.6
-
V
IO=-15mA
MAX Output Voltage (OUT6)
VOH-C
VCC-1.0
VCC-0.6
-
V
IO=-15mA
MAX Output Voltage (OUT11)
VOH-D
VCC-1.2
VCC-0.75
-
V
IO=-15mA
MIN Output Voltage (OUT0)
VOL-A
-
0.75
1.20
V
IO=+15mA
MIN Output Voltage
(OUT1 to OUT5, OUT7 to
OUT10)
VOL-B
-
0.6
1.0
V
IO=+15mA
MIN Output Voltage (OUT6)
VOL-C
-
0.6
1.0
V
IO=+15mA
MIN Output Voltage (OUT11)
VOL-D
-
0.1
0.2
V
IO=+30mA
Slew Rate (AMP0)
SR-A
1
4
-
V/µsec
OUT0=No load
Slew Rate (AMP1 to AMP5,
AMP7 to AMP10)
SR-B
1
4
-
V/µsec
OUT1 to OUT5,OUT7 to OUT10=No
load
Slew Rate (AMP6)
SR-C
1
4
-
V/µsec
OUT6=No load
Slew Rate (AMP11)
SR-D
1
4
-
V/µsec
OUT11=No load
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19.Feb.2016 Rev.001
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TSZ22111・15・001
BD81026MUV
Electrical Characteristics – Continued (Unless otherwise specified, Ta25°C, VDD=3.3V, VCC=12.6V)
Parameter
Symbol
Limit
Unit
Condition
MIN
TYP
MAX
【 10 Bit DAC 】
Resolution
RES
-
10
-
Bit
Integral Non-Linearity Error
(INL)
LE
-2
-
+2
LSB
005h to 3FAh is the allowable
margin of error against the ideal
linear.
Differential Non-Linearity Error
(DNL)
DLE
-2
-
+2
LSB
005h to 3FAh is the allowable
margin of error against the ideal
increase of 1LSB.
Output Voltage Precision
VO
5.945
6.005
6.065
V
During REG0 to REG11=1E8h
(6.0V) setting
Output Voltage
Thermal Characteristics
VT
-50
-
+50
mV
During REG0 to REG11=1E8h
(6.0V) setting, Ta=-25°C to +85°C
【 Control Signal 1 (BKSEL, A0, LD, MODE) 】
Threshold Voltage 1
Vth1A
0.8
-
1.7
V
VDD=3.3V
Threshold Voltage 2
Vth1B
0.6
-
1.7
V
VDD=2.5V
Pull-down Resistor
Rctl
21
30
39
kΩ
【 Control Signal 2 (SDA, SCL) 】
Threshold Voltage 1
Vth2A
0.8
-
1.7
V
VDD=3.3V
Threshold Voltage 2
Vth2B
0.6
-
1.7
V
VDD=2.5V
Minimum Output Voltage
VOCL
-
-
0.4
V
ISDA=3mA
【 Whole Device 】
VDD Power ON Reset
Start-up Voltage
Vdet1
1.75
1.9
2.05
V
VDD Rising voltage
VDD Under Voltage Lock-Out
Voltage
VDDUV
1.55
1.7
1.85
V
VDD Falling voltage
VDD Under Voltage Lock-Out
Hysteresis Voltage
VDDHY
-
200
-
mV
VCC Under Voltage Lock-Out
Release Voltage
Vdet2
3.2
3.4
3.6
V
VCC Rising voltage
VCC Under Voltage Lock-Out
Voltage
VCCUV
2.8
3.0
3.2
V
VCC Falling voltage
VCC Under Voltage Lock-Out
Hysteresis Voltage
VCCHY
-
400
-
mV
BKSEL Switching Time (Note 1)
tBKSEL
-
0.3
1.0
µsec
LD Switching Time (Note 2)
tLD
-
0.3
1.0
µsec
VDD Circuit Current
ICCL
0.16
0.25
0.34
mA
Output No-load ,
DAC initial value setting
VCC Circuit Current
ICCH
2
4
6
mA
Output No-load ,
DAC initial value setting
(Note 1) BKSEL switching time timing is shown below.
(Note 2) LD switching time timing is shown below.
OUT
BKSEL
tBKSEL tBKSEL
OUT
LD
tLD
Figure 1. BKSEL Switching time timing
Figure 2. LD Switching time timing
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19.Feb.2016 Rev.001
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TSZ22111・15・001
BD81026MUV
Operation of each block
(1) 10 Bit DAC block
■Serial data control block
The serial interface uses a 2-line serial data format (SCL, SDA).
The serial data control block consists of a register that stores data from the SDA and SCL pins, and a DAC circuit that
receives the output from this register and provides adjusted voltages to other IC blocks.
Figure 3. Serial block
・Register ( Ch0 to Ch11 )
A serial signal (consisting of 10-bit gamma correction voltage values) input using the serial interface or I2C bus interface is
held for each register address.
Data is initialized by the reset signal generated during a power-on reset.
Register is selectable by BKSEL pin. (For detail, refer to P.9.)
Also, it is selectable that either revises the DAC output setting voltage by LD pin to the data, read to register.
(For detail, refer to P.10. )
・Data writing mode selector
Switching MODE pin High/Low enables changing data switching mode.
During MODE=Low, a data is rewrote by Double Register switching function of BKSEL control.
During MODE=High, a data is rewrote by DAC output latch function of LD control.
MODE pin is pulled down inside so that at open state, it is Low.
If it is set to High, connect to VDD.
・DAC
The DAC LOGIC converts the 10-bit digital signal read to the register to a voltage.
・AMP ( Ch0 to Ch11 )
The Amp amplifies the voltage output from the DAC LOGIC.
While Under Voltage Lock-Out (UVLO) circuit or Thermal Shut Down (TSD) circuit is operating, output goes into Hi-z.
In case connecting high capacity capacitor with low ESR, damping is needed with a resistor to keep phase margin.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
Acknowledge
SDA
SCL Shift Register DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
BKSEL
LD
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
Register11 BANK B
Register11 BANK A
Register10 BANK B
Register10 BANK A
Register9 BANK B
Register9 BANK A
Register8 BANK B
Register8 BANK A
Register7 BANK B
Register7 BANK A
Register6 BANK B
Register6 BANK A
Register5 BANK B
Register5 BANK A
Register4 BANK B
Register4 BANK A
Register3 BANK B
Register3 BANK A
Register2 BANK B
Register2 BANK A
Register1 BANK B
Register1 BANK A
Register0 BANK B
Register0 BANK A
CTL
MODE
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TSZ22111・15・001
BD81026MUV
■Output Voltage setting mode
Writes to a register address specified by I2C BUS.
Mode for writing from I2C BUS to register are ( i )Single mode and ( ii )Multi mode.
On single mode, write data to one designated register.
On multi mode, multi data write can be performed continuously from a start address register specified with the second byte
of data.
Single mode or multi mode can be configured by having or not having “stop bit”.
(i) Single mode timing chart
Figure 4. Output voltage setting (Single mode)
(ii) Multi mode timing chart
Figure 5. Output voltage setting (Multi mode)
■Device address
Device address A6 to A1 are specific to the IC and should be set as follows: （A6 to A0）=111010(A0).
A0 can be set by external. It is pulled-up inside so that in open state, it turns to”0”. If setting to ”1”, connect to VDD.
SCL
SDA_in
Device_Out
Write single DAC register. R3-R0 specify DAC address.
start Device Address Write Ackn Start DAC address pointer. R6-R5 have no meaning Ackn
A6 A5 A4 A3 A2 A1 A0 R/W Ackn WS R6 R5 R4 R3 R2 R1 R0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
DAC(pointer) MSbyte. D15-D10 have no meaning Ackn DAC(pointer) LSbyte. Ackn Stop
A6 A5 A4 A3 A2 A1 A0 R/W Ackn WS R6 R5 R4 R3 R2 R1 R0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
The whole DAC Register D9-D0 is
update in this moment.
SCL
SDA_in
Device_Out
Write multiple DAC registers. R3-R0 specify start DAC
address
start Device Address Write Ackn Start DAC address pointer. R6-R5 have no meaning Ackn
A6 A5 A4 A3 A2 A1 A0 R/W Ackn WS R6 R5 R4 R3 R2 R1 R0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
DAC(pointer) MSbyte. D15-D10 have no meaning Ackn DAC(pointer) LSbyte. Ackn
A6 A5 A4 A3 A2 A1 A0 R/W Ackn WS R6 R5 R4 R3 R2 R1 R0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
・・・
・・・
・・・
D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
DAC(3) MSbyte. D15-D10 have no meaning Ackn DAC(3) LSbyte. Ackn
D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
Stop
・・・
・・・
・・・
The whole DAC Register D9-D0 is
update in this moment.
The whole DAC Register D9-D0 is
update in this moment.
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TSZ22111・15・001
BD81026MUV
■Command interface
Use I2C BUS for command interface with host. Writing or reading by specifying 1 byte select address, along with slave
address. I2C BUS Slave mode format is shown below.
MSB
LSB
MSB
LSB
MSB
LSB
S
Slave Address
A
Select Address
A
DATA
A
P
S : START condition
Slave Address : After slave address (7bit), send total 8bit data with either READ mode (H) or WRITE mode
(L). （MSB first）
A : Acknowledge
Added acknowledge bit per byte in sending and receiving data.
If the data is sent/ received properly, “L” is send/ received.
Sending or Receiving ”H” means lack of acknowledge.
Select Address : Use 1 byte select address.
DATA : Data byte. Sending/ Receiving data. （MSB first）
P : STOP condition
The case where writing 3FCh to DAC1（Single mode）
S
Slave Address
A
Select Address
A
Register1 DATA0
A
Register1 DATA1
A
P
(EX.)
E8h or EAh
01h
03h
FCh
The case where writing 3FCh from DAC0 to DAC3 (Multi mode)
S
Slave Address
A
Select
Address
A
Register0
DATA0
A
Register0
DATA1
A
Register1
DATA0
A
Register1 to 3
DATA0,DATA1
A
P
(EX.)E8h or EAh
00h
03h
FCh
03h
■Double Register switching function
When setting Low of MODE pin, it is able to switch BANK A or BANK B by changing High/Low of BKSEL pin.
During BKSEL=Low, connect BANK A to DAC.
During BKSEL=High, connect BANK B to DAC.
: Slave from master
: Master from slave
: Slave from master
: Master from slave
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TSZ22111・15・001
BD81026MUV
■DAC output switching function by LD pin
During MODE pin = High setting, depending on LD pin condition, DAC output is able to switch.
・In case LD=Low, write a data to a register of a specified address and DAC output outputs the data written to the
register.
(Refer to Figure 6: DAC output switching operation by LD pin (i).)
・In case LD=High, write a data to a register of a specified address and DAC output maintains the previous data setting.
In this condition, if LD pin switches from High to Low, all DAC output (OUT0 to OUT11) outputs synchronously a data,
written to a register.
(Refer to Figure 6: DAC output switching operation by LD pin (ii).)
Figure 6. DAC output switching operation by LD pin
(ⅰ) When LD = Low, DAC output switching operation
start ADevice Address ARegister Address ADAC(0) MLByte ADAC(0) LSByte ・・・ ADAC(11) MLByte ADAC(11) LSByte
・・・
ADAC(1) MLByte ADAC(1) LSByte STOP
LD
SDA
DAC OUT0
DAC OUT1
DAC OUT11
・・・
start ADevice Address ARegister Address ADAC(0) MLByte ADAC(0) LSByte ・・・ ADAC(11) MLByte ADAC(11) LSByte
・・・
ADAC(1) MLByte ADAC(1) LSByte STOP
LD
SDA
DAC OUT0
DAC OUT1
DAC OUT11
・・・
(ⅱ) When LD = High, DAC output switching operation
Outputs a written data
After switching LD = H→L,
all DAC output outputs a written data all together.
DAC(0) DATA DAC(1) DATA DAC(11) DATA
DAC(0) DATA DAC(1) DATA DAC(11) DATA
Outputs a written data
Outputs a written data
Outputs a written data
Outputs a written data
Outputs a written data
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TSZ22111・15・001
BD81026MUV
■Register address
BANK A and BANK B register addresses are configured by the chart below.
For Register address, lower 5bit (R4 to R0) at 2nd byte will be used. R6 to R5 is “Don’t Care.”
(2) Power On Reset
At VDD input, it generates Reset signal and initialize serial I/F and each register.
(3) UVLO (Under Voltage Lock Out)
When VDD and VCC falls under the setting value, Under Voltage Lock Out function is activated and output will be Hi-Z.
If VDD UVLO is operated, initialize a register.
If VCC UVLO is operated, NOT initialize a register.
(4) TSD(Thermal Shut Down)
The TSD circuit turns output Hi-z when the chip temperature reaches or exceeds approximately
175°C in order to prevent thermal destruction or thermal runaway. When the chip returns to a specified temperature,
the circuit resets.
The TSD circuit is designed only to protect the IC itself. Application thermal design should ensure operation of the
IC below the junction temperature of approximately 150°C.
Power supply sequence
Activate VDD before VCC to avoid a malfunction due to undefined logic in LOGIC circuit. Inputs serial data after canceling
Power on Reset.
In case power supply turns OFF, it is recommended after VCC OFF, VDD OFF ,or VCC and VDD OFF synchronously.
If VDD turns OFF before VCC OFF, output condition may not be stable because of LOGIC circuit instability.
Please demonstrate and test fully on an application board.
Figure 7. Power supply sequence
Power supply sequence typical value
Parameter
Symbol
Limit
Unit
Condition
Min
Typ
Max
Serial Input Timing
tDS
100
-
-
µs
VCC Input Timing
tSV
10
-
-
µs
VCC Rising Time
tVCC
１
-
-
ms
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
VCC
VDD
SCL
SDA
tDS tSV
tVCC
1.9V (TYP.)
10%
90%
R4 R3 R2 R1 R0 R4 R3 R2 R1 R0
Register 0 BANK A 0 0 0 0 0 000h Register 0 BANK B 1 0 0 0 0 000h
Register 1 BANK A 0 0 0 0 1 000h Register 1 BANK B 1 0 0 0 1 000h
Register 2 BANK A 0 0 0 1 0 000h Register 2 BANK B 1 0 0 1 0 000h
Register 3 BANK A 0 0 0 1 1 000h Register 3 BANK B 1 0 0 1 1 000h
Register 4 BANK A 0 0 1 0 0 000h Register 4 BANK B 1 0 1 0 0 000h
Register 5 BANK A 0 0 1 0 1 000h Register 5 BANK B 1 0 1 0 1 000h
Register 6 BANK A 0 0 1 1 0 000h Register 6 BANK B 1 0 1 1 0 000h
Register 7 BANK A 0 0 1 1 1 000h Register 7 BANK B 1 0 1 1 1 000h
Register 8 BANK A 0 1 0 0 0 000h Register 8 BANK B 1 1 0 0 0 000h
Register 9 BANK A 0 1 0 0 1 000h Register 9 BANK B 1 1 0 0 1 000h
Register 10 BANK A 0 1 0 1 0 000h Register 10 BANK B 1 1 0 1 0 000h
Register 11 BANK A 0 1 0 1 1 000h Register 11 BANK B 1 1 0 1 1 000h
Register name
BANK A
Initial
Value
BANK B
Initial
Value
Register name
12/18
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© 2016 ROHM Co., Ltd. All rights reserved.
19.Feb.2016 Rev.001
www.rohm.com
TSZ22111・15・001
BD81026MUV
I2C Timing
Figure 8. I2C timing
・Timing rule
PARAMETER
SYMBOL
NORMAL mode
FAST mode
Unit
MIN
TYP
MAX
MIN
TYP
MAX
SCL frequency
fSCL
-
-
100
-
-
400
kHz
SCL”H” time
tHIGH
4.0
-
-
0.6
-
-
µs
SCL”L” time
tLOW
4.7
-
-
1.2
-
-
µs
Rising time
tR
-
-
1.0
-
-
0.3
µs
Falling time
tF
-
-
0.3
-
-
0.3
µs
Start condition holding time
tHD；STA
4.0
-
-
0.6
-
-
µs
Start condition set-up time
tSU；STA
4.7
-
-
0.6
-
-
µs
SDA holding time
tHD；DAT
200
-
-
100
-
-
ns
SDA set-up time
tSU；DAT
200
-
-
100
-
-
ns
Acknowledge delay time
tPD
-
-
0.9
-
-
0.9
µs
Acknowledge hold time
tDH
-
0.1
-
-
0.1
-
µs
Stop condition set-up time
tSU；STO
4.7
-
-
0.6
-
-
µs
BUS open time
tBUF
4.7
-
-
1.2
-
-
µs
Noise spike width
tl
-
0.1
-
-
0.1
-
µs
Gamma output setting
Relation between gamma output voltage (OUT0 to OUT11) and DAC setting value is shown as below.
VCC
valuesettingDAC
OUTtoOUTvoltageOutput 1024
)110(
DAC setting value range is 0 to 1023.
Gamma output OUT0 to OUT11 is outputted after VCC UVLO release. During UVLO detection, output is Hi-Z.
tBUF
tHD:STA tSU;DAT
tR
tLOW
tHIGH
tHD;DAT
tDH
tPD
tF
SCL
SDA
(IN)
SDA
(OUT)
tSU;STA tHD;STA
tl
tSU;STO
SCL
SDA
S P S：START ビット
P：STOP ビット
80%
20%
80%
80%
20%
80%
20%
80%
20%
S:START bit
P:STOP bit
13/18
TSZ02201-0313AAF00660-1-2
© 2016 ROHM Co., Ltd. All rights reserved.
19.Feb.2016 Rev.001
www.rohm.com
TSZ22111・15・001
BD81026MUV
I/O Equivalent circuits
1.OUT5, 2.OUT4, 3.OUT3, 4.OUT2
5.OUT1, 6.OUT0, 19.OUT11, 20.OUT10
21.OUT9, 22.OUT8, 23.OUT7, 24.OUT6
7.VCC
9.VDD
VCCVCC
VCC
VDD
10.MODE, 13.LD,
16.A0, 17.BKSEL
14.SCL
15.SDA
VDD
30kΩ
VDD
VDD
14/18
TSZ02201-0313AAF00660-1-2
© 2016 ROHM Co., Ltd. All rights reserved.
19.Feb.2016 Rev.001
www.rohm.com
TSZ22111・15・001
BD81026MUV
Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Thermal Consideration
Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may
result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the
board size and copper area to prevent exceeding the maximum junction temperature rating.
6. Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
7. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
8. Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
15/18
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© 2016 ROHM Co., Ltd. All rights reserved.
19.Feb.2016 Rev.001
www.rohm.com
TSZ22111・15・001
BD81026MUV
Operational Notes – continued
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Figure 9. Example of monolithic IC structure
13. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below
the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
N N
P+PN N
P+
P Substrate
GND
NP+N N
P+
NP
P Substrate
GND GND
Parasitic
Elements
Pin A
Pin A
Pin B Pin B
B C
EParasitic
Elements
GND
Parasitic
Elements
CB
E
Transistor (NPN)Resistor
N Region
close-by
Parasitic
Elements
16/18
TSZ02201-0313AAF00660-1-2
© 2016 ROHM Co., Ltd. All rights reserved.
19.Feb.2016 Rev.001
www.rohm.com
TSZ22111・15・001
BD81026MUV
Ordering Information
B
D
8
1
0
2
6
M
U
V
-
E 2
Part number
Package
MUV: VQFN024V4040
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
VQFN024V4040 (TOP VIEW)
8 1 0 2 6
Part Number Marking
LOT Number
1PIN MARK
Notice-PGA-E Rev.003
© 2015 ROHM Co., Ltd. All rights reserved.
Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅣ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E Rev.003
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
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Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
DatasheetDatasheet
Notice – WE Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred by you or third parties resulting from inaccur acy or errors of or
concerning such information.
