ISL6443AIVZ-TK - Intersil Corporation

FN6600.2

ISL6443A

300kHz Dual, 180° Out-of-Phase, Step-Down

PWM and Single Linear Controller

The ISL6443A is a high-performance, triple-output controller

optimized for converting wall adapter, battery or network

intermediate bus DC input supplies into the system supply

voltages required for a wide variety of applications. Each

output is adjustable down to 0.8V. The two PWMs are

synchronized at 180° out-of-phase, thus reducing the RMS

input current and ripple voltage.

The ISL6443A incorporates several protection features. An

adjustable overcurrent pr ot ection circuit monitors the out pu t

current by sensing the voltage drop across the lower

MOSFET. Hiccup mode overcurrent operation protects the

DC/DC components from damage during output

overload/short circuit conditions. Each PWM has an

independent logic-level shutdown input (SD1 and SD2).

A single PGOOD signal is issued when soft-start is complete

on both PWM controllers and their outputs are within 10% of

the set point and the linear regulator output is greater than

75% of its setpoint. Thermal shutdown circuitry turns off the

device if the junction temperature exceeds +150 °C.

Features

• Wide Input Supply Voltage Range

- Variable 5.6V to 24V

- Fixed 4.5V to 5.6V

• Three Independently Programmable Output Voltages

• Switching Frequency . . . . . . . . . . . . . . . . . . . . . . .300kHz

• Out-of-Phase PWM Controller Operation

- Reduces Requ ired Input Capacitance and Power

Supply Induced Loads

• No External Current Sense Resistor

- Uses Lower MOSFET’s rDS(ON)

• Bidirectional Frequency Synchronization for

Synchronizing Multiple ISL6443As

• Programmable Soft-Start

• Extensive Circuit Protection Functions

- PGOOD

-UVLO

- Overcurrent

- Over-temperature

- Independent Shutdown for Both PWMs

• Excellent Dynamic Response

- Voltage Feed-Forward with Current Mode Control

• QFN Packages:

- QFN - Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package Footp r int, which Improves

PCB Efficiency and has a Thinner Profile

• Pb-Free (RoHS Compliant)

Applications

• Power Supplies with Multiple Outputs

• xDSL Modems/Routers

• DSP, ASIC, and FPGA Power Supplies

• Set-Top Boxes

• Dual Output Supplies for DSP, Memory, Logic, µP Core

and I/O

• Telecom Systems

Ordering Information

PART

NUMBER

(Note) PART

MARKING

TEMP.

RANGE

(°C) PACKAGE

(Pb-Free) PKG.

DWG. #

ISL6443AIRZ* 6443A IRZ -40 to +85 28 Ld 5x5 QFN L28.5x5

ISL6443AIVZ* 6443A IVZ -40 to +85 28 Ld TSSOP M28.173

Add “-TK” suffix for tape and reel. Please refer to TB347 for details

on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ

special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination

finish, which is RoHS compliant and compatible with both SnPb and

Pb-free soldering operations). Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

Data Sheet June 2, 2008

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN6600.2

June 2, 2008

Pinouts ISL6443A

(28 LD QFN)

TOP VIEW

ISL6443A

(28 LD TSSOP)

TOP VIEW

PHASE2

ISEN2

PGOOD

VCC_5V

SD2

SS2

OCSET2

ISEN1

PGND

SD1

SS1

SGND

OCSET1

FB1

FB2

SGND

VIN

SYNC

FB3

SGND

GATE3

UGATE2

BOOT2

LGATE2

LGATE1

BOOT1

PHASE1

UGATE1

28 27 26 25 24 23 22

8 9 10 11 12 13 14

LGATE2

BOOT2

UGATE2

PHASE2

ISEN2

PGOOD

VCC_5V

SD2

SS2

OCSET2

FB2

VIN

SYNC

LGATE1

UGATE1

PHASE1

ISEN1

PGND

SS1

OCSET1

FB1

SGND

GATE3

FB3

BOOT1

SD1

SGND

ISL6443A

3FN6600.2

June 2, 2008

Block Diagram

ERROR AMP 1

FB1 180kΩ

PWM1

+0.8V

ISEN1

SAMPLE

CURRENT

SAMPLE

CURRENT

PHASE1

VCC_5V

UGATE1

BOOT1

LGATE1

PGND

+1.7V REFERENCE

OCSET1

ERROR AMP 2

ADAPTIVE DEAD-TIME

VSEN2

18.5pF 1400kΩ

180kΩ

PWM2

+0.8V

ISEN2

SAMPLE

CURRENT SAMPLE

CURRENT

PHASE2

VCC_5V

UGATE2

BOOT2

LGATE2

PGND

V/I SAMPLE TIMING

1.7V REFERENCE

OCSET2

VIN VCC_5V

DUTY CYCLE RAMP GENERA TOR

PWM CHANNEL PHASE CONTROL

OC2

OC1

2 CLOCK CYCLES

SAME STATE FOR

REQUIRED TO LATCH

OVERCURRENT FAULT

2 CLOCK CYCLES

SAME STATE FOR

REQUIRED TO LATCH

OVERCURRENT FAULT

VIN

PGOOD

18.5pF

1400kΩ

PGOOD

ADAPTIVE DEAD-TIME

V/I SAMPLE TIMING

OC1

POR

FAULT LA TCH

BIAS SUPPLIES

REFERENCE

ENABLE

SOFT-START

SGNDSD1 SD2

SOFT2

OC2

REF

16kΩ16kΩ

VCC_5V

GATE3 +

0.8V REFERENCE

FB3

SYNC

SS1

ISL6443A

4FN6600.2

June 2, 2008

Typical Application Schematic

PGOOD

+12V

UGATE2

PHASE2

ISL6443A* +

C10

LGATE2

16 11

ISEN2 R4

BOOT2

VIN

GATE3

OCSET2

FB1

UGATE1

PHASE1

PGND

LGATE1

ISEN1

BOOT1

SYNC

OCSET1

VCC_5V

7R8

SD2

FB3

SS1 SS2

SGND

VOUT1

R1 Q2

FB2

SGND

VOUT2

R10

R11

C12

VOUT3

SD1

+2.5V, 500mA

+3.3V, 2A

+3.3V

C3 C6

+1.2V, 2A

R12

C11

SGND

VCC_5V

VOUT2

56µF

BAT54HT1

120k

6.4µH

FDS6990S FDS6990S

10k

31.6k

1.4k

10k

4.99k

0.1µF

1µF

0.1µF

4.7µF

0.1µF

21.5k

10k

10µF

IRF7404

330µF

PGOOD

1µF

0.1µF

0.01µF

100

330µF

*NOTE: Pin numbers correspond to the QFN pinout.

ISL6443A

5FN6600.2

June 2, 2008

Absolute Maximum Ratings Thermal Information

Supply Voltage (VCC_5V Pin) . . . . . . . . . . . . . . . . . . . .-0.3V to +7V

Input Voltage (VIN Pin). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+27V

BOOT1, 2 and UGATE1, 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .+35V

PHASE1, 2 and ISEN1, 2

. . . . . . . . . . . . . . . . . . . . .-5V (<100ns, 10µJ)/-0.3V (DC) to +27V

BOOT1, 2 with Respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . +6.5V

UGATE1, 2. . . . . . . . . . . .(PHASE1, 2 - 0.3V) to (BOOT1, 2 + 0.3V)

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

28 Lead QFN (Notes 1, 2) . . . . . . . . 36 4

28 Lead TSSOP (Note 1) . . . . . . . . . 75 NA

Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversel y impact product reliability and

result in failures not covered by warranty.

NOTES:

1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379

2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 3 and “Typical

Application Schematic” on page 4. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to +85°C (Note 7),

Typical values are at TA = +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless

otherwise specified. Temperature limits established by characterization and are not production tested.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VIN SUPPLY

Input Voltage Range 5.6 12 24 V

Input Voltage Range VIN = VCC (Note 4) 4.5 5.0 5.6 V

VCC_5V SUPPLY (Note 4)

Input Voltage 4.5 5.0 5.6 V

Output Voltage VIN > 5.6V, IL = 20mA 4.5 5.0 5.5 V

Maximum Output Current VIN = 12V 60 - - mA

SUPPLY CURR ENT

Shutdown Current (Note 5) SD1 = SD2 = GND - 50 375 µA

Operating Current (Note 6) - 2.0 4.0 mA

REFERENCE SECTION

Nominal Reference Voltage - 0.8 - V

Reference Voltage Tolerance -1.0 - 1.0 %

POWER-ON RESET

Rising VCC_5V Threshold 4.25 4.45 4.5 V

Falling VCC_5V Threshold 3.95 4.2 4.4 V

OSCILLATOR

Total Frequency Variation 260 300 340 kHz

Peak-to-Peak Sawtooth Amplitude (Note 7) VIN = 12V - 1.6 - V

VIN = 5V - 0.667 - V

Ramp Offset (Note 7) -1.0- V

SYNC Input Rise/Fall Time (Note 7) - 5.0 - ns

SYNC Frequency Range 4.16 4.8 5.44 MHz

SYNC Input HIGH Level 3.5 - - V

SYNC Input LOW Level --1.5V

ISL6443A

6FN6600.2

June 2, 2008

SYNC Input Minimum Pulse Width (Note 7) - 15.0 - ns

SYNC Output HIGH Level VCC - 0.6V - - V

SHUTDOWN1/SHUTDOWN2

HIGH Level (Converter Enabled) Internal Pull-up (3μA) 2.0 - - V

LOW Level (Converter Disabled) - - 0.8 V

PWM CONVERTERS

Output Voltage -0.8- V

FB Pin Bias Current --150nA

Maximum Duty Cycle COUT = 1000pF, TA = +25°C 93 - - %

Minimum Duty Cycle -4-%

PWM CONTROLLER ERROR AMPLIFIERS

DC Gain (Note 7) -88-dB

Gain-Bandwidth Product (Note 7) - 15 - MHz

Slew Rate (Note 7) - 2.0 - V/µs

PWM CONTROLLER GATE DRIVERS (Note 7)

Sink/Source Current - 400 - mA

Upper Drive Pull-Up Resistance VCC_5V = 4.5V - 8 - Ω

Upper Drive Pull-Down Resistance VCC_5V = 4.5V - 3.2 - Ω

Lower Drive Pull-Up Resistance VCC_5V = 4.5V - 8 - Ω

Lower Drive Pull-Down Resistance VCC_5V = 4.5V - 1.8 - Ω

Rise Time COUT = 1000pF - 18 - ns

Fall Time COUT = 1000pF - 18 - ns

LINEAR CONTROLLER

Drive Sink Current 50 - - mA

FB3 Feedback Threshold I = 21mA - 0.8 - V

Undervoltage Threshold VFB -75-%

FB3 Input Leakage Current - 45 150 nA

Amplifier Transconductance VFB = 0.8V, I = 21mA - 2 - A/V

POWER GOOD AND CONTROL FUNCTIONS

PGOOD LOW Level Voltage Pull-up = 100kΩ-0.10.5V

PGOOD Leakage Current - - ±1.0 µA

PGOOD Upper Threshold, PWM 1 and 2 Fraction of set point 105 - 120 %

PGOOD Lower Threshold, PWM 1 and 2 Fraction of set point 80 - 95 %

PGOOD for Linear Controller 70 75 80 %

ISEN AND CURRENT LIMIT

Full Scale Input Current (Note 8) - 32 - µA

Overcurrent Threshold (Note 8) ROCSET = 110kΩ-64-µA

OCSET (Current Limit) Voltage - 1.7 - V

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 3 and “Typical

Application Schematic” on page 4. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to +85°C (Note 7),

Typical values are at TA = +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless

otherwise specified. Temperature limits established by characterization and are not production tested.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ISL6443A

7FN6600.2

June 2, 2008

SOFT-START

Soft-Start Current -5-µA

PROTECTION

Thermal Shutdown Rising - 150 - °C

Hysteresis - 20 - °C

NOTES:

4. In normal operation, where the device is supplied with voltage on the VIN pin, the VCC_5V pin provides a 5V output capable of 60mA (min).

When the VCC_5V pin is used as a 5V supply input, the internal LDO regulator is disabled and the VIN input pin must be connected to the

VCC_5V pin. (Refer to “Pin Descriptions” on page 10 for more details.)

5. This is the total shutdown current with VIN = VCC_5V = PVCC = 5V.

6. Operating current is the supply current consumed when the device is active but not switching. It does not include g ate drive current.

7. Limits should be considered typical and are not production tested.

8. Established by characterization. The full scale current of 32µA is recommended for optimum current sample and hold operation. See “Feedback

Loop Compensation” on page 13.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 3 and “Typical

Application Schematic” on page 4. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to +85°C (Note 7),

Typical values are at TA = +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless

otherwise specified. Temperature limits established by characterization and are not production tested.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ISL6443A

8FN6600.2

June 2, 2008

Typical Performance Curves Oscilloscope Plots are Taken Using the ISL6443A EVAL Evaluation Board, VIN = 12V Unless

Otherwise Noted.

FIGURE 1. PWM1 LOAD REGULATION FIGURE 2. PWM2 LOAD REGULATION

FIGURE 3. REFERENCE VOL T AGE VARIA TION OVER

TEMPERATURE FIGURE 4. SOFT-START WAVEFORMS WITH PGOOD

FIGURE 5. PWM1 WAVEFORMS FIGURE 6. PWM2 WAVEFORMS

3.30

3.32

3.33

3.35

3.38

3.39

3.40

01.0 2.53.5

LOAD CURRENT (A)

PWM1 OUTPUT VOLTAGE (V)

4.50.5 1.5 2.0 3.0 4.0

3.37

3.36

3.34

3.31

3.30

3.32

3.33

3.35

3.38

3.39

3.40

0 1.0 2.5 3.5

LOAD CURRENT (A)

PWM2 OUTPUT VOLTAGE (V)

4.50.5 1.5 2.0 3.0 4.0

3.37

3.36

3.34

3.31

-40 -20 20 40 80

0.75

0.81

0.85

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

0.78

0.83

0.80

0.77

060

0.84

0.82

0.79

0.76

PGOOD 5V/DIV

VOUT3 2V/DIV

VOUT2 2V/DIV

VOUT1 2V/DIV

VOUT1 20mV/DIV, AC-COUPLED

IL1 0.5A/DIV, AC-COUPLED

PHASE1 10V/DIV

VOUT2 20mV/DIV, AC-COUPLED

IL2 0.5A/DIV, AC-COUPLED

PHASE2 10V/DIV

ISL6443A

9FN6600.2

June 2, 2008

FIGURE 7. LOAD TRANSIENT RESPONSE VOUT1 (3.3V) FIGURE 8. LOAD TRANSIENT RESPONSE VOUT2 (3.3V)

FIGURE 9. PWM SOFT-START WAVEFORM FIGURE 10. OVERCURRENT HICCUP MODE OPERATION

FIGURE 11. PWM1 EFFICIENCY vs LOAD (3 .3V), VIN = 12V FIGURE 12. PWM2 EFFICIENCY vs LOAD (3.3V), VIN = 12V

Typical Performance Curves Oscilloscope Plots are Taken Using the ISL6443A EVAL Evaluation Board, VIN = 12V Unless

Otherwise Noted. (Continued)

VOUT1 200mV/DIV

IOUT1 1A/DIV

AC-COUPLED

VOUT2 200mV/DIV

AC-COUPLED

IOUT2 1A/DIV

VCC_5V 1V/DIV

VOUT1 1V/DIV

VOUT1 2V/DIV

IL1 2A/DIV

SS1 2V/DIV

100

LOAD CURRENT (A)

PWM1 EFFICIENCY (%)

234 60

100

LOAD CURRENT (A)

PWM2 EFFICIENCY (%)

234

ISL6443A

10 FN6600.2

June 2, 2008

Pin Descriptions

BOOT2, BOOT1 - These pins power the upper MOSFET

drivers of each PWM converter. Connect these pins to the

junction of the bootstrap capacitor and the cathode of the

bootstrap diode. The anode of the bootstrap diode is

connected to the VCC_5V pin.

UGATE2, UGATE1 - These pins provide the gate drive for

the upper MOSFETs.

PHASE2, PHASE1 - These pins are connected to the junction

of the upper MOSFETs source, output filter inducto r and lower

MOSFETs drain.

LGATE2, LGATE1 - These pins provide the gate drive for

the lower MOSFETs.

PGND - This pin provides the power ground connection for

the lower gate drivers for both PWM1 and PWM2. This pin

should be connected to the sources of the lower MOSFETs

and the (-) terminals of the external input capacitors.

FB3, FB2, FB1 - These pins are connected to the feedback

resistor divider and provide the voltage feedback signals for

the respective controller. They set the output voltage of the

converter. In addition, the PGOOD circuit uses these inputs

to monitor the ou tput voltage status.

ISEN2, ISEN1 - These pins are used to monitor the voltage

drop across the lower MOSFET for current loop feedback

and overcurrent protection.

PGOOD - This is an open drain logic output used to indicate

the status of the output voltages. This pin is pulled low when

either of the two PWM outputs is not within 10% of the

respective nominal voltage, or if the linear controller output is

less than 75% of it’s nominal value.

Table 1 shows detailed status of PGOOD which can be

classified into 4 cases under different combinations of SD1

and SD2 inputs.

The first case is when both SD1 and SD2 are HIGH.

PGOOD will be HIGH if all FB pins from the 3 REQUIRED

outputs are within regulation AND soft-starts (SS1 AND SS2)

are complete.

The other two cases are when either of SD1 or SD2 is LOW

which means the system wants to shut down one of the

PWM outputs but still wants to keep another output working.

PGOOD will be HIGH if all the FB pins from the 2

REQUIRED outputs are within regulation AND soft-start

(SS1/SS2) is complete.

The last case is when both of the SD1 and SD2 are LOW.

PGOOD will be low.

SGND - (Pin 20 on the TSSOP; Pin 17 on the QFN)

This is the small-signal ground, common to all 3 controllers,

and must be routed separately from the high current ground

(PGND). All voltage levels are measured with respect to this

pin. A small ceramic capacitor should be connected right

next to this pin for noise decouplin g.

VIN - Use this pin to power the device with an external

supply voltage with a range of 5.6V to 24V. For 5V ±10%

operation, connect this pin to VCC_5V.

VCC_5V - This pin is the output of the internal 5V lin ear

regulator. This output supplies the bias for the IC, the low

side gate drivers, and the external boot circuitry for the high

side gate drivers. The IC may be powered directly from a

single 5V (±10%) supply at this pin. When used as a 5V

supply input, this pin must be externally conn ected to VIN.

The VCC_5V pin must be always de-coupled to power

ground with a minimum of 4.7µF ceramic capacitor, placed

very close to the pin.

SYNC - This pin may be used to synchronize two or more

ISL6443A controllers. This pin requires a 1k resistor to

ground if used; connect directly to VCC_5V if not used.

SS1, SS2 - These pins provide a soft-start function for their

respective PWM controllers. When the chip is enabled, the

regulated 5µA pull-up current source charges the capacitor

connected from this pin to ground. The error amplifier

reference voltage ramps from 0V to 0.8V while the voltage

on the soft-start pin ramps from 0V to 0.8V.

SD1, SD2 - These pins provide an enable/disable function

for their respective PWM output. The output is enabled when

this pin is floating or pulled HIGH, and disabled when the pin

is pulled LOW.

GATE3 - This pin is the open drain output of the linear

regulator controller.

OCSET2, OCSET1 - A resistor from this pin to ground sets

the overcurrent threshold for the respective PWM.

TABLE 1. DETAILED STATUS OF PGOOD

SD1 SD2 LDO > 75%? 90% < FB1 < 110%? 90% < FB2 < 110%? SS1 COMPLETED? SS2 COMPLETED? PGOOD

11 Y Y Y Y Y 1

10 Y Y x Y x 1

01 Y x Y x Y 1

00 x x x x x 0

“x” means “don’t care”.

ISL6443A

11 FN6600.2

June 2, 2008

Functional Description

General Description

The ISL6443A integrates control circuits for two synchronous

buck converters and one linear controller . The two synchronous

bucks operate out-of-phase to subst antially reduce the input

ripple and thus reduce the input filter requirements. The chip

has four control lines (SS1, SD1, SS2, and SD2), which provide

independent control for each of the synchronous buck outputs.

The buck PWM controllers employ a free-running frequency

of 300kHz. The current mode control scheme with an input

voltage feed-forward ramp input to the modulator provides

excellent rejection of input voltage variations and provides

simplified loop compensatio ns.

The linear controller can drive either a PNP or PFET to provide

ultra low-dropout regulation with programmable voltages.

Internal 5V Linear Regulator (VCC_5V)

All ISL6443A functions are internally power ed from an

on-chip, low dropout 5V regulator. The maximum regulator

input voltage is 24V. Bypass the regulator’s output

(VCC_5V) with a 4.7µF capacitor to ground. The dropout

voltage for this LDO is typically 600mV, so when VIN is

greater than 5.6V, VCC_5V is typicall y 5V. The ISL6443A

also employs an undervoltage lockout circuit that disables

both regulators when VCC_5V falls below 4.4V.

The internal LD O can source over 60mA to supply the IC,

power the low side gate drivers and charge the external boot

capacitor. When driving large FETs (especially at 300kHz

frequency), little or no regulator current may be available for

external loads.

For example, a single large FET with 15nC total ga te charge

requires 15nC x 300kHz = 4.5mA. Also, at high er input

voltages with larger FETs, the power dissipation across the

internal 5V will increase. Excessi ve dissip a tion across this

regulator must be avoided to prevent the junction temperature

from rising. Larger FETs can be used with 5V ±10% input

applications. The thermal overload protectio n circuit will be

triggered if the VCC_5V output is short circui ted. Connect

VCC_5V to VIN fo r 5V ±10% inpu t a pplications.

Soft-Start Operation

When soft-start is initiated, the voltage on the SS pin of the

enabled PWM channels starts to ramp gradually, due to the

5μA current sourced into the external capacitor. The output

voltage follows the soft-start voltage.

When the SS pin voltage reaches 0.8V, the output voltage of

the enabled PWM channel reaches the regulation point, and

the soft-start pin voltage continues to rise. At this point the

PGOOD and fault circuitry is enabled . This completes the

soft-sta rt sequence. Any further rise of SS pin voltage does

not affect the output voltage. By varying the values of the

soft-st art capacitors, it is possible to provide sequencin g of the

main outputs at start-up. The soft-start time can be obtained

from Equation 1:

The soft-start capacitors can be chosen to provide start-up

tracking for the two PWM outputs. This can be achieved by

choosing the soft-start capacitors such that the soft-start

capacitor ratio equals the respective PWM output voltage

ratio. For example, if one uses PWM1 = 1.2V and PWM2 =

3.3V, then the soft-start capacitor ratio should be,

CSS1/CSS2 = 1.2/3.3 = 0.364. Figure 14 shows that soft-start

waveform with CSS1 = 0.01µF and CSS2 = 0.027µF.

Output Voltage Programming

A resistive divider from the output to ground sets the output

voltage of either PWM channel. The center poin t of the

divider shall be connected to FBx pin. The output voltage

value is determined by Equation 2.

where R1 is the top resistor of the feedback divider network

and R2 is the resistor connect ed from FBx to ground.

tSOFT 0.8V CSS

5μA

-----------

⎝⎠

⎛⎞

=(EQ. 1)

FIGURE 13. SOFT-START OPERATION

VCC_5V 1V/DIV

SS1 1V/DIV

VOUT1 1V/DIV

FIGURE 14. PWM1 AND PWM2 OUTPUT TRACKING DURING

START-UP

VOUT2 1V/DIV

VOUT1 1V/DIV

VOUTx 0.8V R1R2

---------------------

⎝⎠

⎜⎟

⎛⎞

=(EQ. 2)

ISL6443A

12 FN6600.2

June 2, 2008

Out-of-Phase Operation

The two PWM controllers in the ISL6443A operate 180o

out-of-phase to reduce input ripple current. This reduces the

input capacitor ripple current requirements, reduces power

supply-induced noise and improves EMI. This effectively helps

to lower component cost, save board space and reduce EMI.

Dual PWMs typically operate in-phase and turn on both upper

FETs at the same time. The input capa citor must then support

the instantaneous current requirements of both controllers

simultaneously, resulting in increased ripple voltage and

current. The higher RMS ripple current lowers the efficiency

due to the power loss associated with the ESR of the input

capacitor. This typically requires more low-ESR capacitors in

parallel to minimize the input voltage ripple and ESR-related

losses, or to meet the required ripple current rating.

With dual synchronized out-of-phase operation, the high-side

MOSFETs of the ISL6443A turn on 180o out-of-phase. The

instantaneous input current peaks of both regulators no longer

overlap, resulting in reduced RMS ripple current and input

voltage ripple. This reduces the required input capacitor ripple

current rating, allowing fewer or less expensive capacitors, and

reducing the shielding requirements for EMI. The “Typical

Performance Curves Oscilloscope Plots are Taken Using the

ISL6443A EVAL Evaluation Board, VIN = 12V Unless

Otherwise Noted.” on page 8 show the synchronized 180° out-

of-phase operation.

Input Voltage Range

The ISL6443A is designed to operate from input supplies

ranging from 4.5V to 24V. However, the inpu t voltage range

can be effectively limited by the available maximum duty

cycle (DMAX = 93%).

where,

Vd1 = Sum of the parasitic voltage drops in the inductor

discharge path, including the lower FET, inductor and PC

board.

Vd2 = Sum of the voltage drops in the charging path,

including the upper F ET, ind uctor and PC board resistances.

The maximum input voltage and minimum output voltage is

limited by the minimum on-time (tON(min)).

where, tON(min) = 30ns

Gate Control Logic

The gate control logic translates generated PWM signals into

gate drive signals, which provides amplification, level shifting

and shoot-through protection. The gate drivers have some

circuitry that helps optimize the ICs performance over a wide

range of operational conditions. As MOSFET switching times

can vary dramatically from type to type and with input voltage,

the gate control logic provides adaptive dead time by

monitoring real gate waveforms of both the upper and the lower

MOSFETs. Shoot-through control logic provides a 20ns

deadtime to ensure that both the upper and lower MOSFETs

will not turn on simultaneously and cause a shoot-through

condition.

Gate Drivers

The low-side gate driver is supplied from VCC_5V and

provides a peak sink/source current of 400 mA. The high-side

gate driver is also capable of 400mA curren t. Gate-drive

voltages for the upper N -Channe l MOSFET are generated by

the flying capaci tor bo ot circuit. A boot cap a cito r conne cted

from the BOOT pin to the PHASE node provides power to the

high side MOSFET driver. To limit the peak current in the IC,

an external resistor may be placed between the UGATE pin

and the gate of the external MOSFET. This small series

resistor also damps any oscillation s caused by the resonant

tank of the parasitic induct ances in the traces of the board and

the FET’s input ca p acit ance.

At start-up, the low-side MOSFET turns on and forces PHASE

to ground in order to charge the BOOT capacitor to 5V . After the

low-side MOSFET turns off, the high-side MOSFET is turned

on by closing an internal switch between BOOT and UGATE.

This provides the necessary gate-to-source voltage to turn on

the upper MOSFET, an action that boosts the 5V gate drive

signal above VIN. The current required to drive the upper

MOSFET is drawn from the internal 5V regulator .

Protection Circuits

The converter output is monitored and protected against

ove r loa d , sh ort c irc u i t an d undervoltage conditions. A

sustained overload on the output sets the PGOOD low and

initiates hiccup mode.

Overcurrent Protection

Both PWM controllers use the lower MOSFET’s ON-resistance,

rDS(ON), to monitor the current in the converter . The sensed

voltage drop is compared with a threshold set by a resistor

connected from the OCSETx pin to ground.

VIN min()

VOUT Vd1

0.93

--------------------------------

⎝⎠

⎛⎞

Vd2 Vd1

–+= (EQ. 3)

VIN max()

VOUT

tON min()

300kHz×

----------------------------------------------------

≤(EQ. 4)

BOOT

UGATE

PHASE

VCC_5V VIN

ISL6443A

FIGURE 15. GATE DRIVER

ISL6443A

13 FN6600.2

June 2, 2008

where, IOC is the desired overcurrent protection thresho ld,

and RCS is a value of the current sense resistor connected to

the ISENx pin. If an overcurren t is detected for 2 conse cutive

clock cycles, then the IC enters a hiccup mode by turning of f

the gate drivers and enteri ng into sof t-st art. The IC wil l cycle

2x through soft-st art before trying to rest art. The IC will

continue to cycle through soft-st art until the overcurrent

condition is removed. Hiccup mode is active during soft-st art,

so care must be taken to ensu re that the peak inductor current

does not exceed the overcurrent threshold during sof t-st art.

Because of the nature of this current sensing technique, and

to accommodate a wide range of rDS(ON) variations, the

value of the overcurrent threshold should represent an

overload current about 150% to 180% of th e maximum

operating current. If more accurate current protection is

desired, place a current sense resistor in series with the

lower MOSFET source.

Over-Temperature Protection

The IC incorporates an over-temperature protection circuit

that shuts the IC down when a die temperature of +150°C

is reached. Normal operation resumes when the die

temperatures drops below +130°C through the initiation of

a full soft-start cycle.

Implementing Synchronization

The SYNC pin may be used to synchronize two or more

controllers. When the SYNC pins of two controllers are

connected together, one controller becomes th e master and

the other controller synchronizes to the master. A pull-down

resistor is required and must be sized to provide a low

enough time constant to pass the SYNC pulse. Connect this

pin to VCC_5V if not used. Fig ure 16 shows the SYNC pin

waveform operating at 16x the switching frequency.

Feedback Loop Compensation

To reduce the number of external component s and to simplify

the process of determining compensation compone nt s, both

PWM controllers have internally compensated error

amplifiers. To make internal compensation po ssible, several

design measures were t aken.

First, the ramp signal applied to the PWM comparator is

proportional to the input voltage provided via the VIN pin.

This keeps the modulator gain constant with variation in the

input voltage. Second, the load current proportional signal is

derived from the voltage drop across the lower MOSFET

during the PWM time interval and is subtracted from the

amplified error signal on the comparator input. This creates

an internal current control loop. The resistor connected to

the ISEN pin sets the gain in the curre nt feedback loop.

Equation 6 estimates the required value of the current sense

resistor depending on the maximum operating load current

and the value of the MOSFET’s rDS(ON).

Choosing RCS to provide 32µA of current to the current

sample and hold circuitry is recommended but values down

to 2µA and up to 100µA can be used.

Due to the current loop feedback, the modulator has a single

pole response with -20dB slope at a frequency determined

by the load.

where RO is load resistance and CO is load capacit ance. For

this type of modulator, a Type 2 compensation circuit is

usually sufficient.

Figure 17 shows a Type 2 amplifier and its response along

with the responses of the current mode modulator and the

converter. The T ype 2 amplifier, in addition to the pole at

origin, has a zero-pole pair that causes a flat gain region at

frequencies in between the zero and the pole.

FIGURE 16. SYNC WAVEFORM

ROCSET 7()RCS

()

IOC

()rDS on()

()

-----------------------------------------

=(EQ. 5)

RCS IMAX

()rDS ON()

()

32μA

-----------------------------------------------

≥(EQ. 6)

FPO 1

2πROCO

⋅⋅

--------------------------------- =(EQ. 7)

FZ1

2πR2C1

⋅⋅

-------------------------------6kHz== (EQ. 8)

FP1

2πR1C2

⋅⋅

-------------------------------600kHz== (EQ. 9)

ISL6443A

14 FN6600.2

June 2, 2008

The zero frequency, the amplifier high-frequency gain, and

the modulator gain are chosen to satisfy most typical

applications. The crossover frequency will appear at the

point where the modulator attenuation equals the amplifier

high frequency gain. The only task that the system designer

has to complete is to specify the output filter capacitors to

position the load main pole somewhere within one decade

lower than the amplifier zero frequency. With this type of

compensation plenty of phase margin is easily achieved due

to zero-pole pair phase ‘boost’.

Conditional stability may occur only when the main load pole

is positioned too much to the left side on the frequency axis

due to excessive output filter capacitance. In this case, the

ESR zero placed within the 1.2kHz to 30kHz range gives

some additional phase ‘boost’. Some phase boost can also

be achieved by connecting capacitor CZ in parallel with the

upper resistor R1 of the divider that sets the output voltage

value. Please refer to “Output Inductor Selection” and

“Output Capacitor Selection” on page 16 for further details.

Linear Regulator

The linear regulator controller is a transconductance

amplifier with a nominal gain of 2A/V. The N-Channel

MOSFET output device can sink a minimum of 50mA. The

reference voltage is 0.8V. With 0V differential at it’s input, the

controller sinks 21mA of current. An external PNP transistor

or PFET pass element can be used. The dominant pole for

the loop can be placed at the base of the PNP (or gate of the

PFET), as a capacitor from emitter to base (source to gate of

a PFET). Better load transient response is achieved,

however, if the dominant pole is placed at the output, with a

capacitor to ground at the output of the regulator.

Under no-load conditions, leakage currents from the pass

transistors supply the output capacitors, even when the

transistor is o ff. Generally this is no t a problem since the

feedback resistor drains the excess charge. However,

charge may build up on the output capacitor making VLDO

rise above its set point. Care must be taken to ensure that

the feedback resistor’s current exceeds the pass transistors

leakage current over the entire temperature range.

The linear regulator output can be supplied by the output of

one of the PWMs. When using a PFET, the output of the

linear regulator will track the PWM supply after the PWM

output rises to a voltage greater than the threshold of the

PFET pass device. The voltage differential between the

PWM and the linear output will be the load current times the

rDS(ON). Figure 18 shows the linear regulator (2.5V) start-up

waveform and the PWM (3.3V) start-up waveform.

Base-Drive Noise Reduction

The high-impedance base driver is susceptible to system

noise, especially when the linear regulator is lightly loaded.

Capacitively coupled switching noise or inductively coupled

EMI onto the base drive causes fluctuations in the base

current, which appear as noise on the linear regula to r’s

output. Keep the base drive traces away from the step-down

converter, and as short as possible, to minimize noise

coupling. A resistor in series with the gate drivers reduce s

the switching noise generated by PWM. Additionally, a

FIGURE 17. FEEDBACK LOOP COMPENSATION

R2 C1

FPO

FZFP

MODULATOR

CONVERTER

TYPE 2 EA

GEA = 18dB

GM = 17.5dB

FIGURE 18. LINEAR REGULATOR START-UP WAVEFORM

VOUT2 1V/DIV

VOUT3 1V/DIV

0.79 0.80 0.82 0.83 0.85

FEEDBACK VOLTAGE (V)

ERROR AMPLIFIER SINK

CURRENT (mA)

0.81 0.84

FIGURE 19. LINEAR CONTROLLER GAIN

ISL6443A

15 FN6600.2

June 2, 2008

bypass capacitor may be placed across the base-to-emitter

resistor. This bypass capacitor, in addition to the transistor’s

input capacitor, could bring in a second pole that will

destabilize the linear regulator. Therefore, the stability

requirements determine the maximum base-to-emitter

capacitance.

Layout Guidelines

Careful attention to layout requirements is necessary for

successful implementation of a ISL6443A based DC/DC

converter. The ISL6443A switches at a very high frequency

and theref or e the switching times are very shor t. At thes e

switching fre q ue n cie s, even the shortest trace has

significant impedance. Also the peak gate drive current rises

significantly in extremely short time. Transition speed of the

current from one device to another causes voltage spikes

across the interconnecting impedances and parasitic circuit

elements. These voltage spikes can degrade efficiency,

generate EMI, increase device overvoltage stress and

ringing. Careful component selection and proper PC board

layout minimizes the magnitude of these voltage spikes.

There are two sets of critical componen ts in a DC/DC

converter using the ISL6443A. The switching power

components and the small signal components. The

switching power components are the most critical from a

layout point of view because they switch a large amount of

energy so they tend to generate a large amount of noise.

The critical small signal components are those connected to

sensitive nodes or those supplying critical bias currents. A

multi-layer printed circuit board is recommended.

Layout Considerations

1. The Input capacitors, Upper FET, Lower FET, Inductor

and Output capacitor should be placed first. Isolate these

power components on the topside of the board with their

ground terminals adjacent to one another . Place the input

high frequency decoupling ceramic capacitor very close

to the MOSFETs.

2. Use separate ground planes for power ground and small

signal ground. Connect the SGND an d PGND together

close to the IC. Do not connect them together anywhere

else.

3. The loop formed by Input capacitor, the top FET and the

bottom FET must be kept as small as possible.

4. Ensure the current paths from the input capacitor to the

MOSFET, to the output inductor and output capacitor are

as short as possible with maximum allowable trace

widths.

5. Place The PWM controller IC close to lower FET. The

LGA TE connection should be short and wide. The IC can

be best placed over a quiet ground area. Avoid switching

ground loop current in this area.

6. Place VCC_5V bypass capacitor very close to VCC_5V

pin of the IC and connect its ground to the PGND plane.

7. Place the gate drive components BOOT diode and BOOT

capacitors together near controller IC

8. The output capacitors should be placed as close to the

load as possible. Use short wide copper regions to

connect output capacitors to load to avoid inductance and

resistances.

9. Use copper filled polygons or wide but short trace to

connect the junction of upper FET, lower FET and output

inductor . Also keep the PHASE node connection to the IC

short. It is unnecessary to oversize the copper islands for

PHASE node. Since the phase nodes are subjected to

very high dv/dt voltages, the stray capacitor formed

between these islands and the surrounding circuitry will

tend to couple switching noise.

10. Route all high speed switching nodes away from the

control circuitry.

1 1. Create a separate small analog ground plane near the IC.

Connect the SGND pin to this plane. All small signal

grounding paths, including feedback resistors, current

limit setting resistors, and SYNC/SDx pull-down resistors

should be connected to this SGND plane.

12. Ensure the feedback connection to the output capacitor is

short and direct.

Component Selection Guidelines

MOSFET Considerations

The logic level MOSFETs are chosen for optimum efficiency

given the potentially wide input voltage range and output

power requirements. Two N-Channel MOSFETs are used in

each of the synchronous-rectified buck conve rters for the

PWM1 and PWM2 outputs. These MOSFETs should be

selected based upon rDS(ON), gate supply requirements,

and thermal management considerations.

The power dissipation includes two loss co mpo nent s;

conduction loss and switching loss. These losses are

distributed between the upper and low er MOSFETs according

to duty cycle (see Equations 10 and 11). The conduction

losses are the main component of power dissip ation for the

lower MOSFETs. Only the upper MOSFET has significant

switching losses, since the lower device turns on and of f into

near zero voltage. Equatio ns 10 and 11 assume linear

voltage-current transitions an d do not model powe r loss due

to the reverse-recovery of the lower MOSFET’ s body diode.

A large gate-charge increases the switching time, tSW,

which increases the upper MOSFET switching lo sses.

Ensure that both MOSFETs are within their maximum

junction temperature at high ambi ent temperature by

PUPPER IO2

()rDS ON()

()VOUT

()

VIN

--------------------------------------------------------------- IO

()VIN

()tSW

()FSW

()

------------------------------------------------------------

+= (EQ. 10)

PLOWER IO2

()rDS ON()

()VIN VOUT

–()

VIN

-------------------------------------------------------------------------------

=(EQ. 11)

ISL6443A

16 FN6600.2

June 2, 2008

calculating the temperature rise according to package

thermal-resistance specifications.

Output Capacitor Select ion

The output capacitors for each output have unique

requirements. In general, the output capacitors should be

selected to meet the dynamic regulation requirements

including ripple voltage and load transients. Selection of

output capacitors is also dependent on the output inductor,

so some inductor analysis is required to select the output

capacitors.

One of the parameters limiting the converter’s response to a

load transient is the time required for the inductor current to

slew to it’s new level. The ISL6443A will provide either 0% or

93% duty cycle in response to a load transient.

The response time is the time interval required to slew the

inductor current from an initial current value to the load

current level. During this interval the difference between the

inductor current and the transient current level must be

supplied by the output capacitor(s). Minimizing the response

time can minimize the output capacitance required. Also, if

the load transient rise time is slower than the inductor

response time, as in a hard drive or CD drive, it reduces the

requirement on the output capacitor.

The maximum capacitor value required to provide the full,

rising step, transient load current during the response time of

the inductor is:

where, COUT is the output capacitor(s) required, LO is the

output inductor, ITRAN is the transient load current step, VIN

is the input voltage, VO is output voltage, and DVOUT is the

drop in output voltage allowed during the load transient.

High frequency capacitors initially supply the transient

current and slow the load rate-of-change seen by the bulk

capacitors. The bulk filter capacitor values are generally

determined by the ESR (Equivalent Series Resistance) and

voltage rating requirements as well as actual capacitance

requirements.

The output voltage ripple is due to the inductor ripple current

and the ESR of the output capacitors as defined by

Equation 13:

where, IL is calculated in “Output Inductor Selection” on

page 16.

High frequency decoupling capacitors sho uld be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manu f act urer of the load

circuitry for specific decoupling requirements.

Use only specialized low-ESR cap aci tors intend ed for

switching-regulator applications at 300kHz for the bul k

capacitors. In most cases, multiple small-case electrolytic

capacitors perform better than a single large-case cap acitor.

The stability requirement on the selection of the output

capacitor is that the ‘ESR zero’ (fZ) be between 1.2kHz and

30kHz. This range is set by an internal, single compensation

zero at 6kHz. The ESR zero can be a factor of five on either

side of the internal zero and still contribute to increased

phase margin of the co ntrol loop. Therefore,

In conclusion, the output cap acitors must meet three criteria:

1. They must have sufficient bulk capacitance to sustain the

output voltage during a load transient while the output

inductor current is slewing to the value of th e load

transient.

2. The ESR must be sufficiently low to meet the desired

output voltage ripple due to the output inductor current.

3. The ESR zero should be placed, in a rather large range,

to provide additional phase margin.

The recommended output capacitor value for the ISL6443A

is between 150µF to 680µF, to meet stability criteria with

external compensation. Use of aluminum electrolytic,

POSCAP, or tantalum type capacitors is recommended. Use

of low ESR ceramic capacitors is possible but would take

more rigorous loop analysis to ensure stability.

Output Inductor Selection

The PWM converters require output inductors. The output

inductor is selected to meet the output voltage ripple

requirements. The inductor value determines the converter’s

ripple current and the ripple voltage is a function of the ripple

current and output capacitor(s) ESR. The ripple voltage

expression is given in “Output Capacitor Selection” on

page 16 and the ripple current is approximated by

Equation 15:

For the ISL6443A, inductor values between 6.4µH to 10µH

are recommended when using the “Typical Application

Schematic” on page 4. Other values can be used but a

thorough stability study should be done.

COUT LO

()ITRAN

()

IN VO

–()DVOUT

()

-----------------------------------------------------------

=(EQ. 12)

VRIPPLE ΔILESR()=(EQ. 13)

COUT 1

2ΠESR()fZ

()

-------------------------------------

=(EQ. 14)

ΔILVIN VOUT

–()VOUT

()

()L()VIN

()

----------------------------------------------------------

=(EQ. 15)

ISL6443A

17 FN6600.2

June 2, 2008

Input Capacitor Selection

The important parameters for the bulk in put capacitor(s) are

the voltage rating and the RMS current rating. For reliable

operation, select bulk input capacitors with voltage and

current ratings above the maximum input voltage and largest

RMS current required by the circuit. The capacitor voltage

rating should be at least 1.25x greater than the maximum

input voltage and 1.5x is a conservative guideline. The AC

RMS Input current varies with the load. The total RMS

current supplied by the input capacitance is:

where,

DC is duty cycle of the respective PWM.

Depending on the specifics of the input power and its

impedance, most (or all) of this current is supplied by the

input capacitor(s). Figure 20 shows the advantage of having

the PWM converters operating out-of-phase. If the

converters were operating in-phase, the combine d RMS

current would be the algebraic sum, which is a much larger

value as shown. Th e co mb in e d ou t -of-phase current is the

square root of the sum of the square of the individua l

reflected currents and is significantly less than the combined

in-phase current.

Use a mix of input bypass capacitors to control the voltage

ripple across the MOSFETs. Use ceramic capacitors for the

high frequency decoupling and bulk capacitors to supply the

RMS current. Small ceramic capacitors can be placed very

close to the upper MOSFET to suppress the voltage induced

in the parasitic circuit impedances.

For board designs that allow through-hole components, the

Sanyo OS-CON® series offer low ESR and good

temperature performance. For surface mount designs, solid

tantalum capacitors can be used, but caution must be

exercised with regard to the capacitor surge current rating.

These capacitors must be capable of handling the

surge-current at power-up. The TPS series available from

AVX is surge-current tested.

IRMS IRMS1

2IRMS2

+= (EQ. 16)

IRMSx DC DC2

–IO

⋅=(EQ. 17) FIGURE 20. INPUT RMS CURRENT vs LOAD

12345

3.3V AND 5V LOAD CURRENT

INPUT RMS CURRENT

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

IN-PHASE

OUT-OF-PHASE

3.3V

ISL6443A

18 FN6600.2

June 2, 2008

ISL6443A

Package Outline Drawing

L28.5x5

28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 2, 10/07

located within the zone indicated . Th e pin #1 identifier may be

Unless otherwise specified, tol erance : Decim al ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optio nal, but must be

between 0.15mm an d 0.3 0m m from the te rminal tip.

Dimension b applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994 .

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

BOTTOM VIEW

SIDE VIEW

5.00 A

5.00

INDEX AREA

PIN 1

(4X) 0.15

28X 0.55 ± 0.10 4

28X 0.25

M0.10 C B

14 8

0.50

24X

3.0

PIN #1 INDEX AREA

3 .10 ± 0 . 15

0 . 90 ± 0.1 BASE PLANE

SEE DETAIL "X"

SEATING PLANE

0.10 C

0.08 C

0 . 2 REF

0 . 05 MAX.

0 . 00 MIN.

( 3. 10)

( 4. 65 TYP )

( 24X 0 . 50)

(28X 0 . 25 )

( 28X 0 . 75)

+ 0.05

- 0.07

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6600.2

June 2, 2008

ISL6443A

Thin Shrink Small Outline Plastic Packages (TSSOP)

INDEX

AREA E1

123

-B-

0.10(0.004) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004) c

E0.25(0.010) BM M

0.25

0.010

GAUGE

PLANE

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AE, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for r e ference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-

sion at maximum material condition. Minimum space between protru-

sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact. (Angles in degrees)

0.05(0.002)

M28.173

28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.378 0.386 9.60 9.80 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N28 287

α0o8o0o8o-

Rev. 0 6/98