© Semiconductor Components Industries, LLC, 2019
July, 2020 − Rev. 2
1Publication Order Number:
FAN3223/D
Gate Drivers, High-Speed,
Low-Side, Dual 4-A
FAN3223/FAN3224/FAN3225
Description
The FAN3223−25 family of dual 4 A gate drivers is designed to
drive N−channel enhancement−mode MOSFETs in low-side
switching applications by providing high peak current pulses during
the short switching intervals. The driver is available with either TTL
or CMOS input thresholds. Internal circuitry provides an
under−voltage lockout function by holding the output LOW until the
supply voltage is within the operating range. In addition, the drivers
feature matched internal propagation delays between A and B
channels for applications requiring dual gate drives with critical
timing, such as synchronous rectifiers. This also enables connecting
two drivers in parallel to effectively double the current capability
driving a single MOSFET.
The FAN322X drivers incorporate MillerDrive™ architecture for
the final output stage. This bipolar−MOSFET combination provides
high current during the Miller plateau stage of the MOSFET turn−on /
turn−off process to minimize switching loss, while providing
rail−to−rail voltage swing and reverse current capability.
The FAN3223 offers two inverting drivers and the FAN3224 offers
two non−inverting drivers. Each device has dual independent enable
pins that default to ON if not connected. In the FAN3225, each channel
has dual inputs of opposite polarity, which allows configuration as
non−inverting or inverting with an optional enable function using the
second input. If one or both inputs are left unconnected, internal
resistors bias the inputs such that the output is pulled LOW to hold the
power MOSFET OFF.
Features
•Industry−Standard Pinouts
•4.5 V to 18 V Operating Range
•5 A Peak Sink/Source at VDD = 12 V
•4.3 A Sink / 2.8 A Source at VOUT = 6 V
•Choice of TTL or CMOS Input Thresholds
•Three Versions of Dual Independent Drivers:
♦Dual Inverting + Enable (FAN3223)
♦Dual Non−Inverting + Enable (FAN3224)
♦Dual−Inputs (FAN3225)
•Internal Resistors Turn Driver Off If No Inputs
•MillerDrive Technology
•12 ns / 9 ns Typical Rise/Fall Times (2.2 nF Load)
•Under 20 ns Typical Propagation Delay Matched within 1 ns to the
Other Channel
•Double Current Capability by Paralleling Channels
•8−Lead 3x3 mm MLP, 8−Lead SOIC Package
•Rated from –40°C to +125°C Ambient
•These are Pb−Free Devices
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MARKING DIAGRAMS
See detailed ordering and shipping information on page 20 of
this data sheet.
ORDERING INFORMATION
1
WDFN8 3x3, 0.65P
CASE 511CD
SOIC8
CASE 751EB
1
8
A = Assembly Lot Code
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
SOIC8WDFN8
Applications
•Switch−Mode Power Supplies
•High-Efficiency MOSFET Switching
•Synchronous Rectifier Circuits
•DC-to-DC Converters
•Motor Control
Related Resources
•AN−6069 — Application Review and
Comparative Evaluation of Low−Side Gate
Drivers
(Note: Microdot may be in either location)
1
8
XXXXX
AYWWG
G
XXXXX
XXXXX
ALYWG
G
*This information is generic. Please refer to device
data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
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PACKAGE OUTLINES
Figure 1. 3x3 mm MLP−8 (Top View)
18
7
2
6
3
45
2
3
8
6
1
4
7
5
Figure 2. SOIC−8 (Top View)
THERMAL CHARACTERISTICS (Note 1)
Package
QL
(Note 2)
QJT
(Note 3)
QJA
(Note 4)
YJB
(Note 5)
YJT
(Note 6) Unit
8−Lead 3x3 mm Molded Leadless Package (MLP) 1.2 64 42 2.8 0.7 °C/W
8−Pin Small Outline Integrated Circuit (SOIC) 38 29 87 41 2.3 °C/W
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (QJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad)
that are typically soldered to a PCB.
3. Theta_JT (QJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform
temperature by a top−side heatsink.
4. Theta_JA (QJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given
is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51−2, JESD51−5, and JESD51−7,
as appropriate.
5. Psi_JB (YJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application
circuit board reference point for the thermal environment defined in Note 4. For the MLP−8 package, the board reference is defined as the
PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC−8 package, the board reference
is defined as the PCB copper adjacent to pin 6.
6. Psi_JT (YJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of
the top of the package for the thermal environment defined in Note 4.
FAN3223/FAN3224/FAN3225
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Figure 3. Pin Assignment
1
ENA
INA
GND
ENB
VDD
INB
OUTA
OUTB
2
3
4
8
6
5
A7
B
1ENB
VDD
OUTA
OUTB
2
3
4
8
6
5
7
A
B
ENA
INA
GND
INB
1INA+
VDD
OUTA
OUTB
2
3
4
8
6
5
7
INB+
GND
INB−
INA−
+
−A
+
−B
PIN DEFINITIONS
Name Pin Description
ENA Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and
CMOS INx threshold
ENB Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and
CMOS INx threshold
GND Ground. Common ground reference for input and output circuits
INA Input to Channel A
INA+ Non−Inverting Input to Channel A. Connect to VDD to enable output
INA−Inverting Input to Channel A. Connect to GND to enable output
INB Input to Channel B
INB+ Non−Inverting Input to Channel B. Connect to VDD to enable output
INB−Inverting Input to Channel B. Connect to GND to enable output
OUTA Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold
OUTB Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold
OUTA Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold
OUTB Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold
P1 Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected
to GND; NOT suitable for carrying current
VDD Supply Voltage. Provides power to the IC
OUTPUT LOGIC
FAN3223 (x = A or B) FAN3224 (x = A or B) FAN3225 (x = A or B)
ENx INx OUTx ENx INx OUTx INx+ INx−OUTx
0 0 0 0 0 (Note 7) 00 (Note 7) 0 0
01 (Note 7) 0 0 1 0 0 (Note 7) 1 (Note 7) 0
1 (Note 7) 0 1 1 (Note 7) 0 (Note 7) 0 1 0 1
1 (Note 7) 1 (Note 7) 01 (Note 7) 1 1 1 1 (Note 7) 0
7. Default input signal if no external connection is made.
FAN3223/FAN3224/FAN3225
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BLOCK DIAGRAMS
Figure 4. FAN3223 Block Diagram
6VDD
7
5
INA 2
ENA 1
GND 3
UVLO
100 kW
8ENB
INB 4
100 kW
100 kW
100 kW
100 kW
100 kW
VDD VDD
VDD VDD_OK
OUTA
OUTB
VDD
Figure 5. FAN3224 Block Diagram
6VDD
7OUTA
5
INA 2
ENA 1
GND 3UVLO
8ENB
INB 4OUTB
100 kW
VDD
100 kW
VDD
100 kW
100 kW
100 kW
100 kW
VDD_OK
FAN3223/FAN3224/FAN3225
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Figure 6. FAN3225 Block Diagram
6VDD
7OUTA
5OUTB
INA−1
INA+ 8
GND
2
UVLO
3
INB−
INB+
4
100 kW
VDD
100 kW
VDD_OK
VDD
100 kW
100 kW
100 kW
100 kW
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min. Max. Unit
VDD VDD to PGND −0.3 20.0 V
VEN ENA and ENB to GND GND − 0.3 VDD + 0.3 V
VIN INA, INA+, INA–, INB, INB+ and INB– to GND GND − 0.3 VDD + 0.3 V
VOUT OUTA and OUTB to GND DC GND − 0.3 VDD + 0.3 V
TLLead Soldering Temperature (10 Seconds) +260 °C
TJJunction Temperature −55 +150 °C
TSTG Storage Temperature −65 +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min. Max. Unit
VDD Supply Voltage Range 4.5 18.0 V
VEN Enable Voltage ENA and ENB 0 VDD V
VIN Input Voltage INA, INA+, INA–, INB, INB+ and INB– 0 VDD V
VOUT OUTA and OUTB to GND Repetitive Pulse < 200 ns −2.0 VDD + 0.3 V
TAOperating Ambient Temperature −40 +125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, VDD = 12 V, TJ = −40°C to +125°C. Currents are defined as positive into the device and negative out of the device.)
Symbol Parameter Characteristic Min Typ Max Unit
SUPPLY
VDD Operating Range 4.5 18.0 V
IDD Supply Current, Inputs /
EN Not Connected
All except FAN3225C 0.70 0.95 mA
FAN3225C (Note 8) 0.21 0.35 mA
VON Turn−On Voltage INA = ENA = VDD, INB = ENB = 0 V 3.5 3.9 4.3 V
VOFF Turn−Off Voltage INA = ENA = VDD, INB = ENB = 0 V 3.3 3.7 4.1 V
INPUTS (FAN322XT) (Note 9)
VINL_T INx Logic LOW Threshold 0.8 1.2 V
VINH_T INx Logic HIGH Threshold 1.6 2.0 V
VHYS_T TTL Logic Hysteresis Voltage 0.2 0.4 0.8 V
IIN+ Non−Inverting Input Current IN from 0 to VDD −1 175 mA
IIN−Inverting Input Current IN from 0 to VDD −175 1mA
INPUTS (FAN322XC) (Note 9)
VINL_C INx Logic Low Threshold 30 38 %VDD
VINH_C INx Logic High Threshold 55 70 %VDD
VHYS_C CMOS Logic Hysteresis Voltage 17 %VDD
IIN+ Non−Inverting Input Current IN from 0 to VDD −1 175 mA
IIN−Inverting Input Current IN from 0 to VDD −175 1mA
ENABLE (FAN3223C, FAN3223T, FAN3224C, FAN3224T)
VENL Enable Logic Low Threshold EN from 5 V to 0 V 0.8 1.2 V
VENH Enable Logic High Threshold EN from 0 V to 5 V 1.6 2.0 V
VHYS_T TTL Logic Hysteresis Voltage
(Note 10)
0.4 V
RPU Enable Pull−Up Resistance
(Note 10)
100 kW
tD3 EN to Output Propagation
Delay (Note 11)
0 V to 5 V EN, 1 V/ns Slew Rate 9 17 26 ns
tD4 5 V to 0 V EN, 1 V/ns Slew Rate 11 18 28 ns
OUTPUTS
ISINK OUT Current, Mid−Voltage,
Sinking (Note 10)
OUT at VDD/2, CLOAD = 0.22 mF,
f = 1 kHz
4.3 A
ISOURCE OUT Current, Mid−Voltage,
Sourcing (Note 10)
OUT at VDD/2, CLOAD=0.22 mF,
f = 1 kHz
−2.8 A
IPK_SINK OUT Current, Peak, Sinking
(Note 10)
CLOAD = 0.22 mF, f = 1 kHz 5 A
IPK_SOURCE OUT Current, Peak, Sourcing
(Note 10)
CLOAD = 0.22 mF, f = 1 kHz −5 A
tRISE Output Rise Time (Note 12) CLOAD = 2200 pF 12 20 ns
tFALL Output Fall Time (Note 12) CLOAD = 2200 pF 9 17 ns
tDEL.MATCH Propagation Matching Between
Channels
INA = INB, OUTA and OUTB at 50%
Point
2 4 ns
IRVS Output Reverse Current
Withstand (Note 10)
500 mA
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ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, VDD = 12 V, TJ = −40°C to +125°C. Currents are defined as positive into the device and negative out of the device.)
Symbol UnitMaxTypMinCharacteristicParameter
OUTPUTS
tD1, tD2 Output Propagation Delay,
CMOS Inputs (Note 12)
0 – 12 VIN, 1 V/ns Slew Rate 10 18 29 ns
tD1, tD2 Output Propagation Delay,
TTL Inputs (Note 12)
0 – 5 VIN, 1 V/ns Slew Rate 9 17 29 ns
8. Lower supply current due to inactive TTL circuitry.
9. EN inputs have TTL thresholds; refer to the ENABLE section.
10.Not tested in production.
11. See Timing Diagrams of Figure 9 and Figure 10.
12.See Timing Diagrams of Figure 7 and Figure 8.
TIMING DIAGRAMS
Figure 7. Non−Inverting (EN HIGH or Floating)
Input
90%
10%
Output
90%
10%
Output
Input
90%
10%
Output
Enable
Input
HIGH
LOW
90%
10%
Output
Enable
Input
HIGH
LOW
Figure 8. Inverting (EN HIGH or Floating)
Figure 9. Non−Inverting (IN HIGH) Figure 10. Inverting (IN LOW)
VINH
VINL
tD1 tD2
tRISE tFALL
VINH
VINL
tD1 tD2
tFALL tRISE
VENH
VENL
tD3 tD4
tRISE tFALL
VENH
VENL
tD3 tD4
tRISE tFALL
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TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted.
Figure 11. IDD (Static) vs. Supply Voltage (Note 13) Figure 12. IDD (Static) vs. Supply Voltage (Note 13)
Figure 13. IDD (Static) vs. Supply Voltage (Note 13) Figure 14. IDD (No−Load) vs. Frequency
Figure 15. IDD (No−Load) vs. Frequency Figure 16. IDD (2.2 nF Load) vs. Frequency
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TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted. (continued)
Figure 17. IDD (2.2 nF Load) vs. Frequency Figure 18. IDD (Static) vs. Temperature (Note 13)
Figure 19. IDD (Static) vs. Temperature (Note 13) Figure 20. IDD (Static) vs. Temperature (Note 13)
Figure 21. Input Thresholds vs. Supply Voltage Figure 22. Input Thresholds vs. Supply Voltage
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TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted. (continued)
Figure 23. Input Threshold % vs. Supply Voltage Figure 24. Input Thresholds vs. Temperature
Figure 25. Input Thresholds vs. Temperature Figure 26. UVLO Thresholds vs. Temperature
Figure 27. UVLO Threshold vs. Temperature
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TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted. (continued)
Figure 28. Propagation Delay vs. Supply Voltage Figure 29. Propagation Delay vs. Supply Voltage
Figure 30. Propagation Delay vs. Supply Voltage Figure 31. Propagation Delay vs. Supply Voltage
Figure 32. Propagation Delays vs. Temperature Figure 33. Propagation Delays vs. Temperature
IN fall to OUT rise
IN rise to OUT fall
IN fall to OUT rise
IN rise to OUT fall
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TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted. (continued)
Figure 34. Propagation Delays vs. Temperature Figure 35. Propagation Delays vs. Temperature
Figure 36. Fall Time vs. Supply Voltage Figure 37. Rise Time vs. Supply Voltage
Figure 38. Rise and Fall Times vs. Temperature
IN Rise to OUT Rise
IN Fall to OUT Fall
IN or EN Rise to OUT Rise
IN or EN Fall to OUT Fall
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TYPICAL PERFORMANCE CHARACTERISTICS
Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted. (continued)
Figure 39. Rise/Fall Waveforms with 2.2 nF Load Figure 40. Rise/Fall Waveforms with 10 nF Load
Figure 41. Quasi−Static Source Current
with VDD = 12 V (Note 14)
Figure 42. Quasi−Static Sink Current with
VDD = 12 V (Note 14)
Figure 43. Quasi−Static Source Current
with VDD = 8 V (Note 14)
Figure 44. Quasi−Static Sink Current with
VDD = 8 V (Note 14)
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13. For any inverting inputs pulled low, non−inverting inputs pulled high, or outputs driven high, static IDD increases by the current flowing through
the corresponding pull−up/down resistor shown in the block diagram.
14.The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the current−measurement loop.
TEST CIRCUIT
Figure 45. Quasi−Static IOUT / VOUT Test Circuit
470 mF
Al. El.
1 mF
ceramic
4.7 mF
ceramic
0.22 mF
IN
1 kHz
Current Probe
LECROY AP015
VDD
VOUT
IOUT CLOAD
APPLICATIONS INFORMATION
Input Thresholds
Each member of the FAN322x driver family consists of
two identical channels that may be used independently at
rated current or connected in parallel to double the
individual current capacity. In the FAN3223 and FAN3224,
channels A and B can be enabled or disabled independently
using ENA or ENB, respectively. The EN pin has TTL
thresholds for parts with either CMOS or TTL input
thresholds. If ENA and ENB are not connected, an internal
pull−up resistor enables the driver channels by default. ENA
and ENB have TTL thresholds in parts with either TTL or
CMOS INx threshold.
If the channel A and channel B inputs and outputs are
connected in parallel to increase the driver current capacity,
ENA and ENB should be connected and driven together. In
addition, it is recommended to include an individual gate
resistance for each channel output to limit the shoot through
current possibly happening between the two channels due to
variations in propagation delay or in input threshold
between the two channels.
The FAN322x family offers versions in either TTL or
CMOS input thresholds. In the FAN322xT, the input
thresholds meet industry-standard TTL-logic thresholds
independent of the VDD voltage, and there is a hysteresis
voltage of approximately 0.4 V. These levels permit the
inputs to be driven from a range of input logic signal levels
for which a voltage over 2 V is considered logic HIGH. The
driving signal for the TTL inputs should have fast rising and
falling edges with a slew rate of 6 V/µs or faster, so a rise
time from 0 to 3.3 V should be 550 ns or less. With reduced
slew rate, circuit noise could cause the driver input voltage
to exceed the hysteresis voltage and retrigger the driver
input, causing erratic operation.
In the FAN322xC, the logic input thresholds are
dependent on the VDD level and, with VDD of 12 V, the logic
rising edge threshold is approximately 55% of VDD and the
input falling edge threshold is approximately 38% of VDD.
The CMOS input configuration offers a hysteresis voltage of
approximately 17% of VDD. The CMOS inputs can be used
with relatively slow edges (approaching DC) if good
decoupling and bypass techniques are incorporated in the
system design to prevent noise from violating the input
voltage hysteresis window. This allows setting precise
timing intervals by fitting an R−C circuit between the
controlling signal and the IN pin of the driver. The slow
rising edge at the IN pin of the driver introduces a delay
between the controlling signal and the OUT pin of the driver.
Static Supply Current
In the IDD (static) typical performance characteristics
(Figure 11 − Figure 13 and Figure 18 − Figure 20), the curve
is produced with all inputs/enables floating (OUT is low)
and indicates the lowest static IDD current for the tested
configuration. For other states, additional current flows
through the 100 kW resistors on the inputs and outputs
shown in the block diagram of each part (see Figure 4 −
Figure 6). In these cases, the actual static IDD current is the
value obtained from the curves plus this additional current.
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MillerDrive Gate Drive Technology
FAN322x gate drivers incorporate the MillerDrive
architecture shown in Figure 46. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the bulk of
the current as OUT swings between 1/3 to 2/3 VDD and the
MOS devices pull the output to the HIGH or LOW rail.
The purpose of the MillerDrive architecture is to speed up
switching by providing high current during the Miller
plateau region when the gate−drain capacitance of the
MOSFET is being charged or discharged as part of the
turn−on / turn−off process.
For applications that have zero voltage switching during
the MOSFET turn−on or turn−off interval, the driver
supplies high peak current for fast switching even though the
Miller plateau is not present. This situation often occurs in
synchronous rectifier applications because the body diode is
generally conducting before the MOSFET is switched ON.
The output pin slew rate is determined by VDD voltage and
the load on the output. It is not user adjustable, but a series
resistor can be added if a slower rise or fall time at the
MOSFET gate is needed.
Input
stage
Figure 46. MillerDrive Output Architecture
VDD
VOUT
Under−Voltage Lockout
The FAN322x startup logic is optimized to drive
ground-referenced N−channel MOSFETs with an
under−voltage lockout (UVLO) function to ensure that the
IC starts up in an orderly fashion. When VDD is rising, yet
below the UVLO level, this circuit holds the output LOW,
regardless of the status of the input pins. After the part is
active, the supply voltage must drop 0.2 V before the part
shuts down. This hysteresis helps prevent chatter when low
VDD supply voltages have noise from the power switching.
This configuration is not suitable for driving high−side
P−channel MOSFETs because the low output voltage of the
driver would turn the P−channel MOSFET ON with VDD
below the UVLO level.
VDD Bypass Capacitor Guidelines
To enable this IC to turn a device ON quickly, a local
high-frequency bypass capacitor, CBYP
, with low ESR and
ESL should be connected between the VDD and GND pins
with minimal trace length. This capacitor is in addition to the
bulk electrolytic capacitance of 10 mF to 47 mF commonly
found on the driver and controller bias circuits.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply to ≤5%. This is
often achieved with a value ≥20 times the equivalent load
capacitance CEQV
, defined here as QGATE/VDD. Ceramic
capacitors of 0.1 mF to 1 mF or larger are common choices,
as are dielectrics, such as X5R and X7R with good
temperature characteristics and high pulse current
capability.
If circuit noise affects normal operation, the value of CBYP
may be increased to 50−100 times the CEQV
, or CBYP may
be split into two capacitors. One should be a larger value,
based on equivalent load capacitance, and the other a smaller
value, such as 1−10 nF mounted closest to the VDD and
GND pins to carry the higher frequency components of the
current pulses. The bypass capacitor must provide the pulsed
current from both of the driver channels and, if the drivers
are switching simultaneously, the combined peak current
sourced from the CBYP would be twice as large as when a
single channel is switching.
Layout and Connection Guidelines
The FAN3223−25 family of gate drivers incorporates
fast-reacting input circuits, short propagation delays, and
powerful output stages capable of delivering current peaks
over 4 A to facilitate voltage transition times from under
10 ns to over 150 ns. The following layout and connection
guidelines are strongly recommended:
•Keep high−current output and power ground paths
separate logic and enable input signals and signal
ground paths. This is especially critical when dealing
with TTL−level logic thresholds at driver inputs and
enable pins
•Keep the driver as close to the load as possible to
minimize the length of high-current traces. This reduces
the series inductance to improve high-speed switching,
while reducing the loop area that can radiate EMI to the
driver inputs and surrounding circuitry
•If the inputs to a channel are not externally connected,
the internal 100 kΩ resistors indicated on block
diagrams command a low output. In noisy
environments, it may be necessary to tie inputs of an
unused channel to VDD or GND using short traces to
prevent noise from causing spurious output switching
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•Many high-speed power circuits can be susceptible to
noise injected from their own output or other external
sources, possibly causing output re−triggering. These
effects can be obvious if the circuit is tested in
breadboard or non−optimal circuit layouts with long
input, enable, or output leads.
For best results, make connections to all pins as short
and direct as possible
•The FAN322x is compatible with many other
industry-standard drivers. In single input parts with
enable pins, there is an internal 100 kW resistor tied to
VDD to enable the driver by default; this should be
considered in the PCB layout
•The turn−on and turn−off current paths should be
minimized, as discussed in the following section
Figure 47 shows the pulsed gate drive current path when
the gate driver is supplying gate charge to turn the MOSFET
ON. The current is supplied from the local bypass capacitor,
CBYP
, and flows through the driver to the MOSFET gate and
to ground. To reach the high peak currents possible, the
resistance and inductance in the path should be minimized.
The localized CBYP acts to contain the high peak current
pulses within this driver−MOSFET circuit, preventing them
from disturbing the sensitive analog circuitry in the PWM
controller.
PWM
FAN322x
Figure 47. Current Path for MOSFET Turn−On
VDD VDS
CBYP
Figure 48 shows the current path when the gate driver
turns the MOSFET OFF. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn−off times, the resistance and
inductance in this path should be minimized.
PWM
FAN322x
Figure 48. Current Path for MOSFET Turn−Off
VDD VDS
CBYP
Truth Table of Logic Operation
The FAN3225 truth table indicates the operational states
using the dual−input configuration. In a non−inverting
driver configuration, the IN− pin should be a logic LOW
signal. If the IN− pin is connected to logic HIGH, a disable
function is realized, and the driver output remains LOW
regardless of the state of the IN+ pin.
IN+ IN−OUT
0 0 0
0 1 0
1 0 1
1 1 0
In the non−inverting driver configuration in Figure 49, the
IN− pin is tied to ground and the input signal (PWM) is
applied to IN+ pin. The IN− pin can be connected to logic
HIGH to disable the driver and the output remains LOW,
regardless of the state of the IN+ pin.
Figure 49. Dual−Input Driver Enabled,
Non−Inverting Configuration
VDD
GND
IN−
IN+
OUT
PWM
FAN3225
FAN3223/FAN3224/FAN3225
www.onsemi.com
17
In the inverting driver application in Figure 50, the IN+
pin is tied HIGH. Pulling the IN+ pin to GND forces the
output LOW, regardless of the state of the IN− pin.
Figure 50. Dual−Input Driver Enabled,
Inverting Configuration
VDD
GND
IN−
IN+
OUT
PWM
FAN3225
Operational Waveforms
At power-up, the driver output remains LOW until the
VDD voltage reaches the turn−on threshold. The magnitude
of the OUT pulses rises with VDD until steady−state VDD is
reached. The non−inverting operation illustrated in
Figure 51 shows that the output remains LOW until the
UVLO threshold is reached, then the output is in−phase with
the input.
Figure 51. Non−Inverting Startup Waveforms
VDD
IN+
IN−
OUT
Turn−on threshold
For the inverting configuration of Figure 50, startup
waveforms are shown in Figure 52. With IN+ tied to VDD
and the input signal applied to IN–, the OUT pulses are
inverted with respect to the input. At power-up, the inverted
output remains LOW until the VDD voltage reaches the
turn−on threshold, then it follows the input with inverted
phase.
Figure 52. Inverting Startup Waveforms
VDD
IN+
(VDD)
IN−
OUT
Turn−on threshold
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at high
frequencies can dissipate significant amounts of power. It is
important to determine the driver power dissipation and the
resulting junction temperature in the application to ensure
that the part is operating within acceptable temperature
limits.
The total power dissipation in a gate driver is the sum of
two components, PGATE and PDYNAMIC:
PTOTAL +PGATE )PDYNAMIC (eq. 1)
PGATE (Gate Driving Loss): The most significant power
loss results from supplying gate current (charge per unit
time) to switch the load MOSFET on and off at the switching
frequency. The power dissipation that results from driving
a MOSFET at a specified gate−source voltage, VGS, with
gate charge, QG, at switching frequency, fSW, is determined
by:
PGATE +QG VGS fSW n(eq. 2)
where n is the number of driver channels in use (1 or 2).
PDYNAMIC (Dynamic Pre−Drive / Shoot−through
Current): A power loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull−up / pull−down resistors. The internal
current consumption (IDYNAMIC) can be estimated using the
graphs in Figure 14 and Figure 15 of the Typical
Performance Characteristics to determine the current
IDYNAMIC drawn from VDD under actual operating
conditions:
PDYNAMIC +IDYNAMIC VDD n(eq. 3)
where n is the number of driver ICs in use. Note that n is
usually be one IC even if the IC has two channels, unless two
or more.driver ICs are in parallel to drive a large load.
FAN3223/FAN3224/FAN3225
www.onsemi.com
18
Once the power dissipated in the driver is determined, the
driver junction rise with respect to circuit board can be
evaluated using the following thermal equation, assuming
YJB was determined for a similar thermal design (heat
sinking and air flow):
TJ+PTOTAL yJB )TB(eq. 4)
where:
TJ = driver junction temperature;
YJB = (psi) thermal characterization parameter relating
temperature rise to total power dissipation; and
TB = board temperature in location as defined in the Thermal
Characteristics table.
To give a numerical example, assume for a 12 V VDD
(VBIAS) system, the synchronous rectifier switches of
Figure 56 have a total gate charge of 60 nC at
VGS = 7 V. Therefore, two devices in parallel would have
120 nC gate charge. At a switching frequency of 300 kHz,
the total power dissipation is:
PGATE +120nC 7V 300 kHz 2+0.504 W (eq. 5)
PDYNAMIC +3.0 mA 12 V 1+0.036 W (eq. 6)
PTOTAL +0.540 W (eq. 7)
The SOIC−8 has a junction−to−board thermal
characterization parameter of YJB = 42°C/W. In a system
application, the localized temperature around the device is
a function of the layout and construction of the PCB along
with airflow across the surfaces. To ensure reliable
operation, the maximum junction temperature of the device
must be prevented from exceeding the maximum rating of
150°C; with 80% derating, TJ would be limited to 120°C.
Rearranging Equation 4 determines the board temperature
required to maintain the junction temperature below 120°C:
TB, MAX +TJ*PTOTAL yJB (eq. 8)
TB, MAX +120°C*0.54 W 42°CńW+97°C(eq. 9)
FAN3223/FAN3224/FAN3225
www.onsemi.com
19
TYPICAL APPLICATION DIAGRAMS
Figure 53. High Current Forward Converter
with Synchronous Rectification
PWM
1
2
36
7
8
45
Timing/
Isolation
FAN3224
Vbias
FAN3224
1
2
36
7
8
45
VDDGND
ENB
ENA
B
A
Figure 54. Center−Tapped Bridge Output with
Synchronous Rectifiers
VOUT
VIN
Figure 55. Secondary Controlled Full Bridge with Current Doubler Output,
Synchronous Rectifiers (Simplified)
PWM − A
PWM − B
PWM − C
PWM − D
Secondary
Phase Shift
Controller
QA
QB
QC
QD
SR− 2
SR− 1
FAN3224
FAN3225
FAN3225
VIN
FAN3223/FAN3224/FAN3225
www.onsemi.com
20
ORDERING INFORMATION
Part Number Logic
Input
Threshold Package
Packing
Method
Quantity per
Reel
FAN3223CMPX Dual Inverting
Channels + Dual Enable
CMOS 3x3 mm MLP−8Tape & Reel 3,000
FAN3223CMX SOIC−8Tape & Reel 2,500
FAN3223TMPX TTL 3x3 mm MLP−8Tape & Reel 3,000
FAN3223TMX SOIC−8Tape & Reel 2,500
FAN3224CMPX Dual Non−Inverting
Channels + Dual Enable
CMOS 3x3 mm MLP−8Tape & Reel 3,000
FAN3224CMX SOIC−8Tape & Reel 2,500
FAN3224TMPX (Note 15) TTL 3x3 mm MLP−8Tape & Reel 3,000
FAN3224TMNTXG (Note 15)
FAN3224TMX Dual Non−Inverting
Channels + Dual Enable
TTL SOIC−8Tape & Reel 2,500
FAN3225CMPX Dual Channels of
Two−Input / One−Output
Drivers
CMOS 3x3 mm MLP−8Tape & Reel 3,000
FAN3225CMX SOIC−8Tape & Reel 2,500
FAN3225TMPX TTL 3x3 mm MLP−8Tape & Reel 3,000
FAN3225TMX SOIC−8Tape & Reel 2,500
15.FAN3224TMPX = Pin 1 location upper left in tape & reel for MLP−8.
FAN3224TMNTXG = Pin 1 location upper right in tape & reel for MLP−8.
FAN3223/FAN3224/FAN3225
www.onsemi.com
21
RELATED PRODUCTS
Type Part Number
Gate Drive
(Note 17)
(Sink/Src)
Input
Threshold Logic Package
Single 1 A FAN3111C +1.1 A / −0.9 A CMOS Single Channel of Dual−Input/Single−Output SOT23−5, MLP6
Single 1 A FAN3111E +1.1 A / −0.9 A External
(Note 17)
Single Non−Inverting Channel with External
Reference
SOT23−5, MLP6
Single 2 A FAN3100C +2.5 A / −1.8 A CMOS Single Channel of Two−Input/One−Output SOT23−5, MLP6
Single 2 A FAN3100T +2.5 A / −1.8 A TTL Single Channel of Two−Input/One−Output SOT23−5, MLP6
Single 2 A FAN3180 +2.4 A / −1.6 A TTL Single Non−Inverting Channel + 3.3 V LDO SOT23−5
Dual 2 A FAN3216T +2.4 A / −1.6 A TTL Dual Inverting Channels SOIC8
Dual 2 A FAN3217T +2.4 A / −1.6 A TTL Dual Non−Inverting Channels SOIC8
Dual 2 A FAN3226C +2.4 A / −1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8
Dual 2 A FAN3226T +2.4 A / −1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8
Dual 2 A FAN3227C +2.4 A / −1.6 A CMOS Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8
Dual 2 A FAN3227T +2.4 A / −1.6 A TTL Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8
Dual 2 A FAN3228C +2.4 A / −1.6 A CMOS Dual Channels of Two−Input/One−Output,
Pin Config.1
SOIC8, MLP8
Dual 2 A FAN3228T +2.4 A / −1.6 A TTL Dual Channels of Two−Input/One−Output,
Pin Config.1
SOIC8, MLP8
Dual 2 A FAN3229C +2.4 A / −1.6 A CMOS Dual Channels of Two−Input/One−Output,
Pin Config.2
SOIC8, MLP8
Dual 2 A FAN3229T +2.4 A / −1.6 A TTL Dual Channels of Two−Input/One−Output,
Pin Config.2
SOIC8, MLP8
Dual 2 A FAN3268T +2.4 A / −1.6 A TTL 20 V Non−Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
SOIC8
Dual 2 A FAN3278T +2.4 A / −1.6 A TTL 30 V Non−Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
SOIC8
Dual 4 A FAN3213T +4.3 A / −2.8 A TTL Dual Inverting Channels SOIC8
Dual 4 A FAN3214T +4.3 A / −2.8 A TTL Dual Non−Inverting Channels SOIC8
Dual 4 A FAN3223C +4.3 A / −2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8
Dual 4 A FAN3223T +4.3 A / −2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8
Dual 4 A FAN3224C +4.3 A / −2.8 A CMOS Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8
Dual 4 A FAN3224T +4.3 A / −2.8 A TTL Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8,
SOIC8−EP
Dual 4 A FAN3225C +4.3 A / −2.8 A CMOS Dual Channels of Two−Input/One−Output SOIC8, MLP8
Dual 4 A FAN3225T +4.3 A / −2.8 A TTL Dual Channels of Two−Input/One−Output SOIC8, MLP8
Single 9 A FAN3121C +9.7 A / −7.1 A CMOS Single Inverting Channel + Enable SOIC8, MLP8
Single 9 A FAN3121T +9.7 A / −7.1 A TTL Single Inverting Channel + Enable SOIC8, MLP8
Single 9 A FAN3122T +9.7 A / −7.1 A TTL Single Non−Inverting Channel + Enable SOIC8, MLP8
Single 9 A FAN3122C +9.7 A / −7.1 A CMOS Single Non−Inverting Channel + Enable SOIC8, MLP8
Dual 12 A FAN3240 +12.0 A TTL Dual−Coil Relay Driver, Timing Config. 0 SOIC8
Dual 12 A FAN3241 +12.0 A TTL Dual−Coil Relay Driver, Timing Config. 1 SOIC8
16.Typical currents with OUTx at 6 V and VDD = 12 V.
17.Thresholds proportional to an externally supplied reference voltage.
MillerDrive is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
WDFN8 3x3, 0.65P
CASE 511CD
ISSUE O
DATE 29 APR 2014
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
A
D
E
B
C0.10
PIN ONE
2X
REFERENCE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
L
D2
E2
C
C0.10
C0.05
C0.05
A1 SEATING
PLANE
8X
NOTE 3
b
8X
0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.70 0.80
A1 0.00 0.05
b0.25 0.35
D3.00 BSC
D2 2.05 2.25
E3.00 BSC
E2 1.10 1.30
e0.65 BSC
L0.30 0.50
14
8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.65
PITCH
1.36 3.30
1
DIMENSIONS: MILLIMETERS
0.63
8X
1
NOTE 4
0.40
8X
DETAIL A
A3 0.20 REF
A3
A
DETAIL B
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
ÉÉÉ
ÇÇÇ
ÇÇÇ
A1
A3
L
ÇÇÇ
ÉÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
L1 0.00 0.15
OUTLINE
PACKAGE
e
RECOMMENDED
K
5
2.31
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
(Note: Microdot may be in either location)
e/2
K
0.20 −−−
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON84944F
DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
WDFN8, 3X3, 0.65P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON13735G
DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SOIC8
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
www.onsemi.com
1
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