1. General description
The 74LVC1G58 provides configurable multiple functions. The output state is de termined
by eight patterns of 3-bit inpu t. The user can choose the logic functions AND, OR, NAND,
NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 Vand 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the outpu t, preventing the damaging ba ckflow current through the device
when it is powered down.
All inputs (A, B and C) are Schmitt trigger inputs. They are capable of tran sforming slowly
changing input signals into sharply defined, jitter-free output signals.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2. 7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
24 mA output drive (VCC =3.0V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.
74LVC1G58
Low-power configurable multiple function gate
Rev. 7 — 6 December 2011 Product data sheet
74LVC1G58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 6 December 2011 2 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC1G58GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363
74LVC1G58GV 40 C to +125 C TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457
74LVC1G58GM 40 C to +125 C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1.45 0.5 mm SOT886
74LVC1G58GF 40 Cto+125C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1 10.5 mm SOT891
74LVC1G58GN 40 C to +125 C XSON6 extremely thin small outline package; no l eads;
6 terminals; body 0.9 1.0 0.35 mm SOT1115
74LVC1G58GS 40 C to +125 C XSON6 extremely thin small outline package; no l eads;
6 terminals; body 1.0 1.0 0.35 mm SOT1202
Table 2. Marking
Type number Marking code[1]
74LVC1G58GW YK
74LVC1G58GV V58
74LVC1G58GM YK
74LVC1G58GF YK
74LVC1G58GN YK
74LVC1G58GS YK
Fig 1. Logic symbol
Y
C
B
A
6
1
3
4
001aab687
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Product data sheet Rev. 7 — 6 December 2011 3 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level
Fig 2. Pin configuration SOT363
and SOT457 Fig 3. Pin configuration SOT886 Fig 4. Pin configuration SOT891,
SOT1115 and SOT1202
74LVC1G58
BC
GND
AY
001aab686
1
2
3
6
VCC
5
4
GND
001aab731
B
A
V
CC
C
Y
Transparent top view
2
3
1
5
4
6
74LVC1G58
74LVC1G58
GND
001aaf956
B
A
VCC
C
Y
Transparent top view
2
3
1
5
4
6
Table 3. Pin description
Symbol Pin Description
B 1 data input
GND 2 ground (0 V)
A 3 data input
Y 4 data output
VCC 5 supply voltage
C 6 data input
Table 4. Function table[1]
Inputs Output
C B A Y
LLLL
LLHH
LHLL
LHHH
HLLH
HLHH
HHLL
HHHL
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Product data sheet Rev. 7 — 6 December 2011 4 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
7.1 Logic configurations
Table 5. Function selection table
Logic function Figure
2-input NAND see Figure 5
2-input NAND with both inputs inverted see Figure 8
2-input AND with inverted input see Figure 6 and 7
2-input NOR with inverted input see Figure 6 and 7
2-input OR see Figure 8
2-input OR with both inputs inverted see Figure 5
2-input XOR see Figure 9
Buffer see Figure 10
Inverter see Figure 11
Fig 5. 2-input NAND gate or 2-input OR with both
inputs inverted Fig 6. 2-input AND gate with inverted B input or
2-input NOR ga te with inverted C input
001aab688
BB6
YC1
52
43Y
Y
C
B
C
V
CC
001aab689
BB6
YC1
52
43Y
Y
C
B
C
VCC
Fig 7. 2-input AND gate with inv erte d C in pu t or
2-input NOR gate with inverted A input Fig 8. 2-input OR gate or 2-input NAND gate with
both inputs inverted
001aab690
A
A
6
YC1
52
43Y
Y
C
A
C
V
CC
001aab691
A
6C1
52
43Y
VCC
AY
C
Y
A
C
Fig 9. 2-input XOR gate Fig 10. Buffer
001aab692
B6C1
52
43Y
VCC
Y
B
C
001aab693
A
A
6
Y
1
52
43Y
VCC
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Product data sheet Rev. 7 — 6 December 2011 5 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For SC-88 and SC-74 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Fig 11. Inverter
001aab694
BB6
Y
1
52
43Y
VCC
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI<0V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO>V
CC or VO<0V - 50 mA
VOoutput voltage Active mode [1][2] 0.5 +6.5 V
Power-down mode [1][2] 0.5 +6.5 V
IOoutput curren t VO=0VtoV
CC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 Cto+125C[3] -250 mW
Table 7. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage Active mode 0 - VCC V
Power-down mode; VCC =0V 0 - 5.5 V
Tamb ambient temperature 40 - +125 C
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Product data sheet Rev. 7 — 6 December 2011 6 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
10. Static characteristics
Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Tamb =40 Cto+85C
VOL LOW-level output voltage VI=V
T+ or VT
IO= 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V
IO=4mA; V
CC = 1.65 V - - 0.45 V
IO=8mA; V
CC = 2.3 V - - 0.3 V
IO=12mA; V
CC = 2.7 V - - 0.4 V
IO=24mA; V
CC = 3.0 V - - 0.55 V
IO=32mA; V
CC = 4.5 V - - 0.55 V
VOH HIGH-level output voltage VI=V
T+ or VT
IO=100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V
IO=4mA; V
CC = 1.65 V 1.2 - - V
IO=8mA; V
CC = 2.3 V 1.9 - - V
IO=12 mA; VCC = 2.7 V 2.2 - - V
IO=24 mA; VCC = 3.0 V 2.3 - - V
IO=32 mA; VCC = 4.5 V 3.8 - - V
IIinput leakage current VI=5.5VorGND; V
CC =0Vto5.5V - 0.1 5A
IOFF power-off leakage current VIor VO=5.5V; V
CC = 0 V - 0.1 10 A
ICC supply current VI=5.5VorGND;
VCC =1.65Vto5.5V; I
O=0A -0.110A
ICC additional supply current VI=V
CC 0.6 V; IO=0A;
VCC = 2.3 V to 5.5 V -5500A
CIinput capacitance - 2.5 - pF
Tamb =40 C to +125 C
VOL LOW-level output voltage VI=V
T+ or VT
IO= 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V
IO=4mA; V
CC = 1.65 V - - 0.7 V
IO=8mA; V
CC = 2.3 V - - 0.45 V
IO=12mA; V
CC = 2.7 V - - 0.6 V
IO=24mA; V
CC = 3.0 V - - 0.8 V
IO=32mA; V
CC = 4.5 V - - 0.8 V
VOH HIGH-level output voltage VI=V
T+ or VT
IO=100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V
IO=4mA; V
CC = 1.65 V 0.95 - - V
IO=8mA; V
CC = 2.3 V 1.7 - - V
IO=12 mA; VCC = 2.7 V 1.9 - - V
IO=24 mA; VCC = 3.0 V 2.0 - - V
IO=32 mA; VCC = 4.5 V 3.4 - - V
IIinput leakage current VI=5.5VorGND; V
CC =0Vto5.5V - - 100 A
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Product data sheet Rev. 7 — 6 December 2011 7 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
[1] Typical values are measured at maximum VCC and Tamb = 25 C.
11. Dynamic characteristics
[1] Typical values are measured at nominal VCC and at Tamb = 25 C.
[2] tpd is the same as tPLH and tPHL
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
IOFF power-off leakage current VIor VO=5.5V; V
CC = 0 V - - 200 A
ICC supply current VI=5.5VorGND;
VCC =1.65Vto5.5V; I
O=0A --200A
ICC additional supply current VI=V
CC 0.6 V; IO=0A;
VCC = 2.3 V to 5.5 V - - 5000 A
Table 8. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay A, B, C to Y; see Figure 12 [2]
VCC = 1.65 V to 1.95 V 1.0 6.0 14.4 1.0 18.0 ns
VCC = 2.3 V to 2.7 V 0.5 3.5 8.3 0.5 10.4 ns
VCC = 2.7 V 0.5 4.2 8.5 0.5 10.6 ns
VCC = 3.0 V to 3.6 V 0.5 3.8 6.3 0.5 7.9 ns
VCC = 4.5 V to 5.5 V 0.5 3.0 5.1 0.5 6.4 ns
CPD power dissipation
capacitance VCC =3.3V; V
I=GNDtoV
CC [3] -20- - -pF
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Product data sheet Rev. 7 — 6 December 2011 8 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
12. Waveforms
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Input A, B, C to output Y propagation delay times
Y output
A, B, C input
Y output
GND
VI
VOH
VOH
VOL
VOL
VMVM
VMVM
VMVM
tPLH
tPLH
tPHL
tPHL
001aab593
Table 10. Mea surement points
Supply voltage Input Output
VCC VMVM
1.65 V to 1.95 V 0.5 VCC 0.5 VCC
2.3 V to 2.7 V 0.5 VCC 0.5 VCC
2.7V 1.5V 1.5V
3.0V to3.6V 1.5V 1.5V
4.5 V to 5.5 V 0.5 VCC 0.5 VCC
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Product data sheet Rev. 7 — 6 December 2011 9 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
13. Transfer characteristics
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Test circuit for measuring switching times
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
Table 11. Test data
Supply voltage Input Load VEXT
VCC VItr=t
fCLRLtPLH, tPHL
1.65 V to 1.95 V VCC 2.0ns 30pF 1kopen
2.3 V to 2.7 V VCC 2.0 ns 30 pF 500 open
2.7V 2.7V 2.5 ns 50 pF 500 open
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open
4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open
Table 12. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VT+ positive-going
threshold voltage see Figure 14, Figure 15,
Figure 16 and Figure 17
VCC = 1.8 V 0.70 1.02 1.20 0.67 1.20 V
VCC = 2.3 V 1.11 1.42 1.60 1 .08 1.60 V
VCC = 3.0 V 1.50 1.79 2.00 1.47 2.00 V
VCC = 4.5 V 2.16 2.52 2.74 2.13 2.74 V
VCC = 5.5 V 2.61 2.99 3.33 2.58 3.33 V
VTnegative-going
threshold voltage see Figure 14, Figure 15,
Figure 16 and Figure 17
VCC = 1.8 V 0.30 0.53 0.72 0.30 0.75 V
VCC = 2.3 V 0.58 0.77 1.00 0.58 1.03 V
VCC = 3.0 V 0.80 1.04 1.30 0.80 1.33 V
VCC = 4.5 V 1.21 1.55 1.90 1.21 1.93 V
VCC = 5.5 V 1.45 1.86 2.29 1.45 2.32 V
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Product data sheet Rev. 7 — 6 December 2011 10 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
[1] Typical values are measured at Tamb =25C.
14. Waveforms transfer characteristics
VHhysteresis voltage (VT+ VT);
see Figure 14, Figure 15,
Figure 16 and Figure 17
VCC = 1.8 V 0.30 0.48 0.62 0.23 0.62 V
VCC = 2.3 V 0.40 0.64 0.80 0.34 0.80 V
VCC = 3.0 V 0.50 0.75 1.00 0.44 1.00 V
VCC = 4.5 V 0.71 0.97 1.20 0.65 1.20 V
VCC = 5.5 V 0.71 1.13 1.40 0.65 1.40 V
Table 12. Transfer characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VT+ and VT limits are at 70 % and 20 %.
Fig 14. Tr an sfer characteristics Fig 15. Definition of VT+, VT and VH
mna207
VO
VI
VHVT+
VT−
mna208
V
O
V
I
V
H
V
T+
V
T−
VT+ and VT limits are at 70 % and 20 %.
Fig 16. Tr an sfer characteristics Fig 17. Definition of VT+, VT and VH
001aab684
V
O
V
I
V
H
V
T+
V
T−
mnb155
V
O
V
I
V
H
V
T+
V
T−
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Product data sheet Rev. 7 — 6 December 2011 11 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
Fig 18. Typical 74LVC1G58 transfer characteristics; VCC = 3.0 V
001aab594
VI (V)
0321
8
4
12
16
ICC
(mA)
0
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Product data sheet Rev. 7 — 6 December 2011 12 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
15. Package outline
Fig 19. Package outline SOT363 (SC-88)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT363 SC-88
wBM
bp
D
e1
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
456
Plastic surface-mounted package; 6 leads SOT363
UNIT A1
max bpcDEe1HELpQywv
mm 0.1 0.30
0.20 2.2
1.8
0.25
0.10 1.35
1.15 0.65
e
1.3 2.2
2.0 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.25
0.15
A
1.1
0.8
04-11-08
06-03-16
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Product data sheet Rev. 7 — 6 December 2011 13 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
Fig 20. Package outline SOT457 (TSOP6)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT457 SC-74
wBM
bp
D
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
scale
c
X
132
4
56
0 1 2 mm
Plastic surface-mounted package (TSOP6); 6 leads SOT457
UNIT A1bpcDEHELpQywv
mm 0.1
0.013 0.40
0.25 3.1
2.7
0.26
0.10 1.7
1.3
e
0.95 3.0
2.5 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2 0.33
0.23
A
1.1
0.9
05-11-07
06-03-16
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Product data sheet Rev. 7 — 6 December 2011 14 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
Fig 21. Package outline SOT886 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT886 MO-252
SOT886
04-07-15
04-07-22
DIMENSIONS (mm are the original dimensions)
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17 1.5
1.4 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
6
2
5
3
4
6×
(2)
4×
(2)
A
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Product data sheet Rev. 7 — 6 December 2011 15 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
Fig 22. Package outline SOT891 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT891
SOT891
05-04-06
07-05-15
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm 0.20
0.12 1.05
0.95 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.350.55
A
max
0.5 0.04
1
6
2
5
3
4
A
6×
(1)
4×
(1)
Note
1. Can be visible in some manufacturing processes.
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Product data sheet Rev. 7 — 6 December 2011 16 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
Fig 23. Package outline SOT1 115 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1115
sot1115_po
10-04-02
10-04-07
Unit
mm max
nom
min
0.35 0.04 0.95
0.90
0.85
1.05
1.00
0.95 0.55 0.3 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
L1
b
321
6 5 4
(6×)(2) A1A
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Product data sheet Rev. 7 — 6 December 2011 17 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
Fig 24. Package outline SOT1202 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1202
sot1202_po
10-04-02
10-04-06
Unit
mm max
nom
min
0.35 0.04 1.05
1.00
0.95
1.05
1.00
0.95 0.55 0.35 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
b
123
L1
6 5 4
(6×)(2)
A
A1
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Product data sheet Rev. 7 — 6 December 2011 18 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
16. Abbreviations
17. Revision history
Table 13. Abbreviation s
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC1G58 v.7 2011120 6 Product data sheet - 74LVC1G58 v.6
Modifications: •Legal pages updated.
74LVC1G58 v.6 20110923 Product data sheet - 74LVC1 G58 v.5
74LVC1G58 v.5 20101015 Product data sheet - 74LV C1G58 v.4
74LVC1G58 v.4 20090427 Product data sheet - 74LV C1G58 v.3
74LVC1G58 v.3 20070827 Product data sheet - 74LV C1G58 v.2
74LVC1G58 v.2 20070222 Product data sheet - 74LV C1G58 v.1
74LVC1G58 v.1 20040915 Product data sheet - -
74LVC1G58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 6 December 2011 19 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
18. Legal information
18.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
18.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains dat a from the objective specificati on for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC1G58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 6 December 2011 20 of 21
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
18.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC1G58
Low-power configurable multiple function gate
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 December 2011
Document identifier: 74LVC1G58
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
20. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
7.1 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 5
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Transfer characteristics . . . . . . . . . . . . . . . . . . 9
14 Waveforms transfer characteristics. . . . . . . . 10
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
19 Contact information. . . . . . . . . . . . . . . . . . . . . 20
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
