1
®
FN8197.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9428
Low Noise/Low Power/2-Wire Bus
Single Digitally Controlled Potentiometer
(XDCP™)
FEATURES
• Solid state potentiometer
• 2-wire serial interface
• Register oriented format
—Direct Read/Write/Transfer wiper position
—Store as many as four positions per
potentiometer
• Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low power CMOS
—Standby current < 1µA
—Ideal for battery operated applications
• High reliability
—Endurance–100,000 Data changes per bit per
register
—Register data retention–100 years
• 4-bytes of nonvolatile memory
•10kΩ resistor array
• Resolution: 64 taps each potentiometer
• 16 Ld SOIC, 14 Ld TSSOP packages
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9428 integrates a digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Interface
and
Control
Circuitry
SCL
SDA
A0
A2
A3
VH/RH
VL/RL
Data
8
VW/RW
WP
VCC
VSS
V+
V–
Data Sheet April 26, 2006
NOT RECOMMENDED FOR NEW DESIGNS
INTERSIL SUGGESTS THE
ISL22316 OR ISL22319
2FN8197.1
April 26, 2006
Ordering Information
PART NUMBER PART
MARKING VCC LIMITS (V) POTENTIOMETER
ORGANIZATION (kΩ)TEMP. RANGE
(°C) PACKAGE PKG. DWG. #
X9428WS16* X9428WS 5 to ±10% 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9428WS16Z* (Note) X9428WS Z 0 to +70 16 Ld SOIC (300 mil)
(Pb-free) M16.3
X9428WS16I* X9428WS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9428WS16IZ* (Note) X9428WS ZI -40 to +85 16 Ld SOIC (300 mil)
(Pb-free) M16.3
X9428WV14* X9428 W 0 to +70 14 Ld TSSOP
(4.4mm) M14.173
X9428WV14Z* (Note) X9428 Z 0 to +70 14 Ld TSSOP
(4.4mm) (Pb-free) M14.173
X9428WV14I* X9428 WI -40 to +85 14 Ld TSSOP
(4.4mm) M14.173
X9428WV14IZ* (Note) X9428 ZI -40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free) M14.173
X9428YS16* X9428YS 2 0 to +70 16 Ld SOIC (300 mil) M16.3
X9428YS16Z* (Note) X9428YS Z 0 to +70 16 Ld SOIC (300 mil)
(Pb-free) M16.3
X9428YS16I* X9428YS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9428YS16IZ* (Note) X9428YS ZI -40 to +85 16 Ld SOIC (300 mil)
(Pb-free) M16.3
X9428YV14* X9428 Y 0 to +70 14 Ld TSSOP
(4.4mm) M14.173
X9428YV14Z* (Note) X9428 YZ 0 to +70 14 Ld TSSOP
(4.4mm) (Pb-free) M14.173
X9428YV14I* X9428 YI -40 to +85 14 Ld TSSOP
(4.4mm) M14.173
X9428YV14IZ* (Note) X9428 YZI -40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free) M14.173
X9428WS16-2.7* X9428WS F 2.7 to 5.5 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9428WS16Z-2.7*
(Note) X9428WS ZF 0 to +70 16 Ld SOIC (300 mil)
(Pb-free) M16.3
X9428WS16I-2.7* X9428WS G -40 to +85 16 Ld SOIC (300 mil) M16.3
X9428WS16IZ-2.7*
(Note) X9428WS ZG -40 to +85 16 Ld SOIC (300 mil)
(Pb-free) M16.3
X9428WV14-2.7* X9428 WF 0 to +70 14 Ld TSSOP
(4.4mm) M14.173
X9428WV14Z-2.7*
(Note) X9428 ZF 0 to +70 14 Ld TSSOP
(4.4mm) (Pb-free) M14.173
X9428WV14I-2.7* X9428 WG -40 to +85 14 Ld TSSOP
(4.4mm) M14.173
X9428WV14IZ-2.7*
(Note) X9428 ZG -40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free) M14.173
X9428YS16-2.7* X9428YS F 2 0 to +70 16 Ld SOIC (300 mil) M16.3
X9428YS16Z-2.7*
(Note) X9428YS ZF 0 to +70 16 Ld SOIC (300 mil)
(Pb-free) M16.3
X9428
3FN8197.1
April 26, 2006
X9428YS16I-2.7* X9428YS G 2.7 to 5.5 2 -40 to +85 16 Ld SOIC (300 mil) M16.3
X9428YS16IZ-2.7*
(Note) X9428YS ZG -40 to +85 16 Ld SOIC (300 mil)
(Pb-free) M16.3
X9428YV14-2.7* X9428 YF 0 to +70 14 Ld TSSOP
(4.4mm) M14.173
X9428YV14Z-2.7*
(Note) X9428 YZF 0 to +70 14 Ld TSSOP
(4.4mm) (Pb-free) M14.173
X9428YV14I-2.7* X9428 YG -40 to +85 14 Ld TSSOP
(4.4mm) M14.173
X9428YV14IZ-2.7*
(Note) X9428 YZG -40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free) M14.173
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Ordering Information (Continued)
PART NUMBER PART
MARKING VCC LIMITS (V) POTENTIOMETER
ORGANIZATION (kΩ)TEMP. RANGE
(°C) PACKAGE PKG. DWG. #
X9428
4FN8197.1
April 26, 2006
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9428.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Device Address (A0, A2, A3)
The Address inputs are used to set the least
significant 3 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9428. A maximum of 8
devices may occupy the 2-wire serial bus.
Potentiometer Pins
RH/VH, RL/VL
The RH/VH and RL/VL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
RW/VW
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input WP
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Analog Supply V+, V-
The Analog Supply V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
PIN NAMES
Symbol Description
SCL Serial clock
SDA Serial data
A0, A2, A3 Device address
RH/VH, VL/RHPotentiometer Pins
(terminal equivalent)
RW/VWPotentiometer Pin (wiper equivalent)
WP Hardware write protection
V+,V- Analog and voltage follower
VCC System supply voltage
VSS System ground
NC No connection
VCC
A2
RL/VL
SDA
WP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V+
NC
A0
NC
A3
SCL
NC
V-
DIP/SOIC
X9428
VSS
RH/VH
RW/VW
1
2
3
4
5
6
7
14
13
12
11
10
9
8
TSSOP
X9428
A2
RL
SDA
WP
VSS
RH
RW
VCC
V+
A0
NC
A3
SCL
V-
X9428
5FN8197.1
April 26, 2006
PRINCIPLES OF OPERATION
The X9428 is a highly integrated microcircuit
incorporating a resistor array and its associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9428 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9428 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9428 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (tHIGH). The X9428 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9428 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9428 will respond with a final acknowledge.
Array Description
The X9428 is comprised of a resistor array. The array
contains 63 discrete resistive segments that are
connected in series. The physical ends of the array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers and
the WCR can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9428
this is fixed as 0101[B].
Figure 1. Slave Address
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0, A2, A3 inputs. The X9428
compares the serial data stream with the address
input state; a successful compare of all four address
bits is required for the X9428 to respond with an
acknowledge. The A0, A2, A3 inputs can be actively
driven by CMOS input signals or tied to VCC or VSS.
100
A3 A2 0 A0
Device Type
Identifier
Device Address
1
X9428
6FN8197.1
April 26, 2006
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9428
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9428 is still busy with the write operation no ACK will
be returned. If the X9428 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.
Flow 1. ACK Polling Sequence
Instruction Structure
The next byte sent to the X9428 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of four associated registers. The format is
shown below in Figure 2.
Figure 2. Instruction Byte Format
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers that
is to be acted upon when a register oriented instruction
is issued. Bits 0 and 1 are defined to be 0.
Four of the seven instructions end with the transmission
of the instruction byte. The basic sequence is illustrated
in Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the
Data Registers. A transfer from a Data Register to a
Wiper Counter Register is essentially a write to a static
RAM. The response of the wiper to this action will be
delayed tWRL. A transfer from the Wiper Counter
Register (current wiper position), to a Data Register is a
write to nonvolatile memory and takes a minimum of
tWR to complete.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9428; either between the host and one of
the Data Registers or directly between the host and the
Wiper Counter Register. These instructions are: Read
Wiper Counter Register (read the current wiper position
of the selected pot), write Wiper Counter Register
(change current wiper position of the selected pot), read
Data Register (read the contents of the selected
nonvolatile register) and write Data Register (write a
new value to the selected Data Register). The
sequence of operations is shown in Figure 4.
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Further
Operation?
Issue
Instruction Issue STOP
NO
YES
YES
Proceed
Issue STOP
NO
Proceed
I1I2I3 I0 R1 R0 0 0
Register
Select
Instructions
X9428
7FN8197.1
April 26, 2006
Figure 3. Two-Byte Instruction Sequence
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9428 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(tHIGH) while SDA is HIGH, the selected wiper will
move one resistor segment towards the VH/RH
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the VL/RL terminal. A detailed
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
Table 1. Instruction Set
Note: (7) 1/0 = data is one or zero
S
T
A
R
T
0101A3A20A0A
C
K
I3 I2 I1 I0 R1 R0 0 0 A
C
K
SCL
SDA
S
T
O
P
Instruction
Instruction Set
OperationI3I2I1I0R1R0X1X0
Read Wiper Counter
Register
1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register
Write Wiper Counter
Register
1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register
Read Data Register 1 0 1 1 1/0 1/0 0 0 Read the contents of the Data Register pointed to by
R1 - R0
Write Data Register 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to by
R1 - R0
XFR Data Register to
Wiper Counter Register
1 1 0 1 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to
by R1 - R0 to its Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register
to the Data Register pointed to by R1 - R0
Increment/Decrement
Wiper Counter Register
0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Wiper Counter
Register
X9428
8FN8197.1
April 26, 2006
Figure 4. Three-Byte Instruction Sequence
Figure 5. Increment/Decrement Instruction Sequence
Figure 6. Increment/Decrement Timing Limits
S
T
A
R
T
0 1 0 1 A3 A2 0 A0 A
C
K
I3 I2 I1 I0 R1 R0 0 0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
0 0 D5 D4 D3 D2 D1 D0
S
T
A
R
T
0101A3A20A0A
C
K
I3 I2 I1 I0 R0 0 0 A
C
K
SCL
SDA
S
T
O
P
XX
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
R1
SCL
SDA
VW/RW
INC/DEC
CMD
Issued
Voltage Out
tWRID
X9428
9FN8197.1
April 26, 2006
Figure 7. Acknowledge Response from Receiver
Figure 8. Detailed Potentiometer Block Diagram
SCL from
Data Output
from Transmitter
189
START Acknowledge
Master
Data Output
from Receiver
Serial Data Path
From Interface
Circuitry
Register 0 Register 1
Register 2 Register 3
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
INC/DEC
Logic
UP/DN
CLK
Modified SCL
UP/DN
VH/RH
VL/RL
VW/RW
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
8 6
C
o
u
n
t
e
r
D
e
c
o
d
e
(WCR)
X9428
10 FN8197.1
April 26, 2006
DETAILED OPERATION
The potentiometer has a Wiper Counter Register and
four Data Registers. A detailed discussion of the
register organization and array operation follows.
Wiper Counter Register
The X9428 contains a Wiper Counter Register. The
Wiper Counter Register can be envisioned as a 6-bit
parallel and serial load counter with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written directly by the host via
the write Wiper Counter Register instruction (serial
load); it may be written indirectly by transferring the
contents of one of four associated Data Registers via
the XFR Data Register instruction (parallel load); it can
be modified one step at a time by the
Increment/Decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
The WCR is a volatile register; that is, its contents are
lost when the X9428 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-down.
Data Registers
The potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Register Descriptions
Data Registers, (6-Bit), Nonvolatile
Four 6-bit Data Registers for each XDCP. (eight 6-bit
registers in total).
– {D5~D0}: These bits are for general purpose not
volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the Wiper Counter
Register on power-up.
Wiper Counter Register, (6-Bit), Volatile
One 6-bit wiper counter register for each XDCP. (Four
6-bit registers in total.)
– {D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.
D5 D4 D3 D2 D1 D0
NV NV NV NV NV NV
(MSB) (LSB)
WP5 WP4 WP3 WP2 WP1 WP0
VVVVVV
(MSB) (LSB)
X9428
11 FN8197.1
April 26, 2006
Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode S
A
C
K
wiper position
(sent by slave on SDA) M
A
C
K
S
T
O
P
0101A
3
A
20A
010010000 00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode S
A
C
K
wiper position
(sent by master on SDA) S
A
C
K
S
T
O
P
0101A
3
A
20A
010100000 00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
register
addresses S
A
C
K
wiper position/data
(sent by slave on SDA) M
A
C
K
S
T
O
P
0101A
3
A
20A
01011R
1
R
000 00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
register
addresses S
A
C
K
wiper position/data
(sent by master on SDA) S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A
3
A
20A
01100R
1
R
000 00
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
register
addresses S
A
C
K
S
T
O
P
0101A
3
A
20A
01101R
1
R
000
X9428
12 FN8197.1
April 26, 2006
XFR Wiper Counter Register (WCR) to Data Register (DR)
Increment/Decrement Wiper Counter Register (WCR)
SYMBOL TABLE Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
register
addresses S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A
3
A
20A
01110R
1
R
000
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode S
A
C
K
increment/decrement
(sent by master on SDA) S
T
O
P
0101A
3
A
20A
000100000 I/
D
I/
D....
I/
D
I/
D
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
120
100
80
40
60
20
20 40 60 80 100 120
00
Resistance (K)
Bus Capacitance (pF)
Min.
Resistance
Max.
Resistance
RMAX
= CBUS
tR
RMIN
= IOL MIN
VCC MAX=1.8kΩ
X9428
13 FN8197.1
April 26, 2006
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address
input with respect to VSS......................... -1V to +7V
Voltage on V+ (referenced to VSS)........................ 10V
Voltage on V- (referenced to VSS)........................-10V
(V+) - (V-) .............................................................. 12V
Any VH/RH..............................................................V+
Any VL/RL.................................................................V-
Lead temperature (soldering, 10 seconds)........ 300°C
IW (10 seconds)................................................±12mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
End to end resistance tolerance ±20 %
Power rating 50 mW 25°C, each pot
IW Wiper current ±6 mA
RWWiper resistance 150 250 ΩWiper current = ± 1mA, VCC = 3V
40 100 ΩWiper current = ± 1mA, VCC = 5V
V+ Voltage on V+ pin X9428 +4.5 +5.5 V
X9428-2.7 +2.7 +5.5
V- Voltage on V- pin X9428 -5.5 -4.5 V
X9428-2.7 -5.5 -2.7
VTERM Voltage on any VH/RH or VL/RL pin V- V+ V
Noise -140 dBV Ref: 1kHz
Resolution (4) 1.6 %
Absolute linearity (1) ±1 MI(3) Vw(n)(actual) - Vw(n)(expected)
Relative linearity (2) ±0.2 MI(3) Vw(n + 1 )- [Vw(n) + MI]
Temperature Coefficient of RTOTAL ±300 ppm/°C
Ratiometric Temperature Coefficient ±20 ppm/°C
CH/CL/C
W
Potentiometer Capacitances 10/10/25 pF See Circuit #3,
Spice Macromodel
RECOMMENDED OPERATING CONDITIONS
Temp Min. Max.
Commercial 0°C+70°C
Industrial -40°C+85°C
Device Supply Voltage (VCC) Limits
X9428 5V ± 10%
X9428-2.7 2.7V to 5.5V
X9428
14 FN8197.1
April 26, 2006
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-
eter. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH - RL)/63, single pot
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER-UP AND POWER-DOWN
There are no restrictions on the power-up or power-down sequencing of the bias supplies VCC, V+, and V- provided
that all three supplies reach their final values within 1msec of each other. However, at all times, the voltages on the
potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory
is not in effect until all supplies reach their final value.
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
ICC1 VCC supply current
(nonvolatile write)
1mAf
SCL = 400kHz, SDA = Open,
Other Inputs = VSS
ICC2 VCC supply current
(move wiper, write, read)
100 µA fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ISB VCC current (standby) 1 µA SCL = SDA = VCC, Addr. = VSS
ILI Input leakage current 10 µA VIN = VSS to VCC
ILO Output leakage current 10 µA VOUT = VSS to VCC
VIH Input HIGH voltage VCC x 0.7 VCC x 0.5 V
VIL Input LOW voltage -0.5 VCC x 0.1 V
VOL Output LOW voltage 0.4 V IOL = 3mA
Parameter Min. Unit
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 Years
Symbol Test Max. Unit Test Conditions
CI/O(5) Input/output capacitance (SDA) 8 pF VI/O = 0V
CIN(5) Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V
Symbol Parameter Min. Typ. Max. Unit
tPUR(6) Power-up to initiation of read operation 1 ms
tPUW(6) Power-up to initiation of write operation 5 ms
tRVCC(7) VCC Power-up ramp rate 0.2 50 V/msec
X9428
15 FN8197.1
April 26, 2006
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Circuit #3 SPICE Macro Model
AC TIMING (over recommended operating conditions)
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
5V
1533Ω
100pF
SDA Output
2.7V
100pF
10pF
RH
RTOTAL
CH
25pF
CW
CL
10pF
RW
RL
Symbol Parameter Min. Max. Unit
fSCL Clock frequency 100 400 kHz
tCYC Clock cycle time 2500 ns
tHIGH Clock high time 600 ns
tLOW Clock low time 1300 ns
tSU:STA Start setup time 600 ns
tHD:STA Start hold time 600 ns
tSU:STO Stop setup time 600 ns
tSU:DAT SDA data input setup time 100 ns
tHD:DAT SDA data input hold time 30 ns
tRSCL and SDA rise time 300 ns
tF SCL and SDA fall time 300 ns
tAA SCL low to SDA data output valid time 900 ns
tDH SDA data output hold time 50 ns
TINoise suppression time constant at SCL and SDA inputs 50 ns
tBUF Bus free time (prior to any transmission) 1300 ns
tSU:WPA WP, A0, A1, A2 and A3 setup time 0 ns
tHD:WPA WP, A0, A1, A2 and A3 hold time 0 ns
X9428
16 FN8197.1
April 26, 2006
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS
START and STOP Timing
Input Timing
Output Timing
Symbol Parameter Typ. Max. Unit
tWR High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Unit
tWRPO Wiper response time after the third (last) power supply is stable 10 µs
tWRL Wiper response time after instruction issued (all load instructions) 10 µs
tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 10 µs
tSU:STA tHD:STA tSU:STO
SCL
SDA
tR
(START) (STOP)
tF
tRtF
SCL
SDA
tHIGH
tLOW
tCYC
tHD:DAT
tSU:DAT tBUF
SCL
SDA
tDH
tAA
X9428
17 FN8197.1
April 26, 2006
XDCP Timing (for All Load Instructions)
XDCP Timing (for Increment/Decrement Instruction)
Write Protect and Device Address Pins Timing
SCL
SDA
VW/RW
(STOP)
LSB
tWRL
SCL
SDA
VW/RW
tWRID
Wiper Register Address Inc/Dec Inc/Dec
SDA
SCL ...
...
...
WP
A0, A2, A3
tSU:WPA tHD:WPA
(START) (STOP)
(Any Instruction)
X9428
18 FN8197.1
April 26, 2006
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
VW/RW
+VR
I
Three terminal Potentiometer;
Variable voltage divider Two terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysteresis
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9428
19 FN8197.1
April 26, 2006
Application Circuits (continued)
Inverting Amplifier Equivalent L-R Circuit
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
Function Generator
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
Attenuator Filter
+
–
VS
VO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2
GO = 1 + R2/R1
fc = 1/(2πRC)
R2
R4All RS = 10kΩ
+
–
VS
R2
R1
R
C
VO
X9428
20 FN8197.1
April 26, 2006
X9428
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.041 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.195 0.199 4.95 5.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N14 147
α0o8o0o8o-
Rev. 2 4/06
21
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or it s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8197.1
April 26, 2006
X9428
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0° 8° 0° 8° -
Rev. 1 6/05
