SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Operation From Very Slow Edges
D
Improved Line-Receiving Characteristics
D
High Noise Immunity
description
Each circuit functions as an inverter , but because
of the Schmitt action, it has different input
threshold levels for positive-going (VT+) and
negative-going (VT–) signals.
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean, jitter-free output signals.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP N
Tube SN7414N SN7414N
PDIP
–
N
Tube SN74LS14N SN74LS14N
Tube SN7414D
7414
0°Cto70°C
SOIC D
Tape and reel SN7414DR
7414
0°C
to
70°C
SOIC
–
D
Tube SN74LS14D
LS14
Tape and reel SN74LS14DR
LS14
SOP – NS Tape and reel SN7414NSR SN7414
SSOP – DB Tape and reel SN74LS14DBR LS14
Tube SN5414J SN5414J
CDIP J
Tube SNJ5414J SNJ5414J
CDIP
–
J
Tube SN54LS14J SN54LS14J
–55°C to 125°CTube SNJ54LS14J SNJ54LS14J
CFP W
Tube SNJ5414W SNJ5414W
CFP
–
W
Tube SNJ54LS14W SNJ54LS14W
LCCC – FK Tube SNJ54LS14FK SNJ54LS14FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN5414, SN54LS14 ...J OR W PACKAGE
SN7414 . . . D, N, OR NS PACKAGE
SN74LS14 . . . D, DB, OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
3212019
910111213
4
5
6
7
8
18
17
16
15
14
6Y
NC
5A
NC
5Y
2A
NC
2Y
NC
3A
1Y
1A
NC
4Y
4A 6A
3Y
GND
NC
NC – No internal connection
VCC
SN54LS14 . . . FK PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
1
3
5
9
11
13
2
4
6
8
10
12
Y = A
Pin numbers shown are for the D, DB, J, N, NS, and W packages.
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic
’14
GND
Output Y
100 Ω
VCC
6 kΩ
Input A
GND
Output Y
VCC
20 kΩ
Input A
’LS14
Resistor values shown are nominal.
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage: ’14 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
’LS14 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2):D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperaturerange, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7
recommended operating conditions
SN5414 SN7414
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current –0.8 –0.8 mA
IOL Low-level output current 16 16 mA
TAOperating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
‡
SN5414
SN7414 UNIT
TEST
CONDITIONS
MIN TYP§MAX
VT+ VCC = 5 V 1.5 1.7 2 V
VT–VCC = 5 V 0.6 0.9 1.1 V
Hysteresis
(VT+ – VT–)VCC = 5 V 0.4 0.8 V
VIK VCC = MIN, II = –12 mA –1.5 V
VOH VCC = MIN, VI = 0.6 V, IOH = –0.8 mA 2.4 3.4 V
VOL VCC = MIN, VI = 2 V, IOL = 16 mA 0.2 0.4 V
IT+ VCC = 5 V, VI = VT+ –0.43 mA
IT–VCC = 5 V, VI = VT––0.56 mA
IIVCC = MAX, VI = 5.5 V 1 mA
IIH VCC = MAX, VIH = 2.4 V 40 µA
IIL VCC = MAX, VIL = 0.4 V –0.8 –1.2 mA
IOSVCC = MAX –18 –55 mA
ICCH VCC = MAX 22 36 mA
ICCL VCC = MAX 39 60 mA
‡For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§All typical values are at VCC = 5 V, TA = 25°C.
Not more than one output should be shorted at a time.
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN5414
SN7414 UNIT
PARAMETER
(INPUT)
(OUTPUT)
TEST
CONDITIONS
UNIT
tPLH
A
Y
RL= 400 Ω
CL=15
p
F
15 22
ns
tPHL
A
Y
RL
=
400
Ω
,
CL
=
15
F
15 22
ns
recommended operating conditions
SN54LS14 SN74LS14
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current –0.4 –0.4 mA
IOL Low-level output current 4 8 mA
TAOperating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54LS14 SN74LS14
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VT+ VCC = 5 V 1.4 1.6 1.9 1.4 1.6 1.9 V
VT–VCC = 5 V 0.5 0.8 1 0.5 0.8 1 V
Hysteresis
(VT+ – VT–)VCC = 5 V 0.4 0.8 0.4 0.8 V
VIK VCC = MIN, II = –18 mA –1.5 –1.5 V
VOH VCC = MIN, VI = 0.5 V, IOH = –0.4 mA 2.5 3.4 2.7 3.4 V
VOL
VCC = MIN
VI=19V
IOL= 4 mA 0.25 0.4 0.25 0.4
V
V
OL
V
CC =
MIN
,
V
I = –
1
.
9
V
IOL = 8 mA 0.35 0.5
V
IT+ VCC = 5 V, VI = VT+ –0.14 –0.14 mA
IT–VCC = 5 V, VI = VT––0.18 –0.18 mA
IIVCC = MAX, VI = 7 V 0.1 0.1 mA
IIH VCC = MAX, VIH = 2.7 V 20 20 µA
IIL VCC = MAX, VIL = 0.4 V –0.4 –0.4 mA
IOS§VCC = MAX –20 –100 –20 –100 mA
ICCH VCC = MAX 8.6 16 8.6 16 mA
ICCL VCC = MAX 12 21 12 21 mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2)
PARAMETER
FROM TO
TEST CONDITIONS
UNIT
PARAMETER
(INPUT) (OUTPUT)
TEST
CONDITIONS
UNIT
tPLH
A
Y
RL=2kΩ
CL=15
p
F
15 22
ns
tPHL
A
Y
RL
=
2
kΩ
,
CL
=
15
F
15 22
ns
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC RL
From Output
Under Test
CL
(see Note A)
Test
Point
1 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series
54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
W aveform 1
(see Notes C
and D)
W aveform 2
(see Notes C
and D) ≈1.5 V
VOH – 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
tw
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
VOH
VOL
Figure 1. Load Circuits and Voltage Waveforms
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
W aveform 1
(see Notes C
and D)
W aveform 2
(see Notes C
and D) ≈1.5 V
VOH – 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
tw
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
VOL
VOH
Figure 2. Load Circuits and Voltage Waveforms
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS OF ’14 CIRCUITS†
T+
Figure 3
–25–50–75
1.64
1.62
1.61
1.60 02550
– Positive-Going Threshold Voltage – V
1.66
1.67
POSITIVE-GOING THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
1.70
75 100 125
1.65
1.63
TA – Free-Air Temperature – °C
V
VCC = 5 V
1.68
1.69
Figure 4
T–
–25–50–75
0.84
0.82
0.81
0.80 02550
– Negative-Going Threshold Voltage – V
0.86
0.87
NEGATIVE-GOING THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
0.90
75 100 125
0.85
0.83
TA – Free-Air Temperature – °C
V
VCC = 5 V
0.88
0.89
T+ –
–25–50–75
790
770
760
750 02550
– Hysteresis – mV
810
820
HYSTERESIS
vs
FREE-AIR TEMPERATURE
850
75 100 125
800
780
TA – Free-Air Temperature – °C
V
VCC = 5 V
830
840
Figure 5
T–
V
†Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS OF ’14 CIRCUITS†
Figure 6
780760 800 820 840
DISTRIBUTION OF UNITS
FOR HYSTERESIS
860 880 900
VT+ – VT– – Hysteresis – mV
VCC = 5 V
TA = 25°C
Relative Frequency of Occurence
740
Figure 7
4.754.5
0.8
0.4
0.2
05
Threshold Voltage -– V
1.2
1.4
THRESHOLD VOLTAGES
vs
SUPPLY VOLTAGE
2.0
5.25 5.5
1.0
0.6
TA = 25°C
1.6
1.8
VT+ – VT– – Hysteresis – mV
Positive-Going Threshold Voltage, VT+
Negative-Going Threshold Voltage, VT–
4.5
0.8
0.4
0.2
0
1.2
1.4
2.0
1.0
0.6
1.6
1.8
Figure 8
4.75 5
HYSTERESIS
vs
SUPPLY VOLTAGE
5.25 5.5
TA = 25°C
VCC – Supply Voltage – V
T+ –– Hysteresis – VVT–
V
V
Figure 9
0.40
1
00.8
2
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
4
1.2 2
3
VCC – Supply Voltage – V
O– Output Voltage – V
VCC = 5 V
TA = 25°C
1.6
VT–VT+
†Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS OF ’LS14 CIRCUITS†
Figure 10
1.64
1.62
1.61
1.60
Positive-Going Threshold Voltage – V
1.66
1.67
POSITIVE-GOING THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
1.70
1.65
1.63
VCC = 5 V
1.68
1.69
TA – Free-Air Temperature – °C
–25–50–75 0 25 50 75 100 125
T+ –
V
Figure 11
0.84
0.82
0.81
0.80
0.86
0.87
NEGATIVE-GOING THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
0.90
0.85
0.83
VCC = 5 V
0.88
0.89
–25–50–75 0 25 50 75 100 125
TA – Free-Air Temperature – °C
–
N
ega
ti
ve-
G
o
i
ng
Th
res
h
o
ld
V
o
lt
age –
V
T–
V
Figure 12
790
770
760
750
810
820
HYSTERESIS
vs
FREE-AIR TEMPERATURE
850
800
780
VCC = 5 V
830
840
–25–50–75 0 25 50 75 100 125
TA – Free-Air Temperature – °C
T+ –– Hysteresis – VVT–
V
Figure 13
760740 780 800 820
DISTRIBUTION OF UNITS
FOR HYSTERESIS
840 860 880
VT+ – VT– – Hysteresis – mV
VCC = 5 V
TA = 25°C
Relative Frequency of Occurence
720
99% ARE
ABOVE
735 mV
†Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS OF ’LS14 CIRCUITS†
Figure 14
0.8
0.4
0.2
0
1.2
1.4
THRESHOLD VOLTAGES AND HYSTERESIS
vs
SUPPLY VOLTAGE
2.0
1.0
0.6
TA = 25°C
1.6
1.8
VCC – Supply Voltage – V
4.754.5 5 5.25 5.5
Threshold Voltage – V
Positive-Going Threshold Voltage, VT+
Negative-Going Threshold Voltage, VT–
Hysteresis, VT+ – VT–
Figure 15
0.40
1
00.8
2
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
4
1.2 2
3
VI – Input Voltage – V
O– Output Voltage – VV
VCC = 5 V
TA = 25°C
1.6
VT–VT+
†Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B – DECEMBER 1983 – REVISED FEBRUARY 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL APPLICATION DATA
TTL System
CMOS
Sine-Wave
Oscillator
TTL System Interface
for Slow Input W aveforms
330 Ω
Input
Multivibrator
0.1 Hz to 10 MHz
Open-Collector
Output
Input Output
Pulse Stretcher
Pulse Shaper
Input
Output
VT–
VT+
VT–
VT+
Input
Output
Threshold Detector
VT+
Input
Output
Point A
A
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9665801Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9665801Q2A
SNJ54LS
14FK
5962-9665801QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9665801QC
A
SNJ54LS14J
5962-9665801QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9665801QD
A
SNJ54LS14W
5962-9665801VCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 5962-9665801VC
A
SNV54LS14J
5962-9665801VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9665801VD
A
SNV54LS14W
JM38510/31302BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
31302BCA
M38510/31302BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
31302BCA
SN5414J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN5414J
SN54LS14J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS14J
SN7414D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7414
SN7414DE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7414
SN7414DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7414
SN7414DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7414
SN7414DRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7414
SN7414DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7414
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN7414N ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN7414N
SN7414N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70
SN7414NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN7414N
SN7414NSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN7414
SN7414NSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN7414
SN7414NSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN7414
SN74LS14D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS14
SN74LS14DBR ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS14
SN74LS14DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS14
SN74LS14DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS14
SN74LS14DE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS14
SN74LS14DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS14
SN74LS14DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS14
SN74LS14DRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS14
SN74LS14DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS14
SN74LS14N ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS14N
SN74LS14N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70
SN74LS14NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS14N
SN74LS14NSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS14
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LS14NSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS14
SN74LS14NSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS14
SNJ5414J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5414J
SNJ5414W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5414W
SNJ54LS14FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9665801Q2A
SNJ54LS
14FK
SNJ54LS14J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9665801QC
A
SNJ54LS14J
SNJ54LS14W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9665801QD
A
SNJ54LS14W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 4
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN5414, SN54LS14, SN54LS14-SP, SN7414, SN74LS14 :
•Catalog: SN7414, SN74LS14, SN54LS14
•Military: SN5414, SN54LS14
•Space: SN54LS14-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN7414DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN7414NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LS14DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LS14DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LS14NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN7414DR SOIC D 14 2500 367.0 367.0 38.0
SN7414NSR SO NS 14 2000 367.0 367.0 38.0
SN74LS14DBR SSOP DB 14 2000 367.0 367.0 38.0
SN74LS14DR SOIC D 14 2500 367.0 367.0 38.0
SN74LS14NSR SO NS 14 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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