LTC3118
1
3118fa
For more information www.linear.com/LTC3118
Typical applicaTion
FeaTures DescripTion
18V, 2A Buck-Boost DC/DC
Converter with Low Loss
Dual Input PowerPath
The LT C
®
3118 is a dual-input, wide voltage range syn-
chronous buck-boost DC/DC converter with an intelligent,
integrated, low loss PowerPath control. The unique power
switch architecture provides efficient operation from either
input source to a programmable output voltage above,
below or equal to the input. Voltage capability of up to 18V
provides flexibility and voltage margin for a wide variety
of applications and power sources.
The LTC3118 uses a low noise, current mode architecture
with a fixed 1.2MHz PWM mode frequency that minimizes
the solution footprint. For high efficiency at light loads,
automatic Burst Mode operation can be selected consum-
ing only 50µA of quiescent current in sleep.
System level features include ideal diode or VIN priority
modes, VIN and VOUT power good indicators, accurate RUN
comparators to program independent UVLO thresholds,
and output disconnect in shutdown. Other features include
2µA shutdown current, short-circuit protection, soft-start,
current limit and thermal overload protection.
The LTC3118 is offered in thermally enhanced 24-lead
4mm × 5mm QFN and 28-lead TSSOP packages.
applicaTions
n Integrated High Efficiency Dual Input PowerPath™
Plus Buck-Boost DC/DC Converter
n Ideal Diode or Priority VIN Select Modes
n VIN1 and VIN2 Range: 2.2V to 18V
n VOUT Range: 2V to 18V
n Either VIN Can Be Above, Below or Equal to VOUT
n Generates 5V at 2A for VIN > 6V
n 1.2MHz Low Noise Fixed Frequency Operation
n Current Mode Control
n All Internal N-Channel MOSFETs
n Pin-Selectable PWM or Burst Mode
®
Operation
n Accurate, Independent RUN Pin Thresholds
n Up to 94% Efficiency
n VIN and VOUT Power Good Indicators
n IQ of 50µA in Sleep, 2µA in Shutdown
n 4mm × 5mm 24-Lead QFN or 28-Lead TSSOP Packages
n Systems with Multiple Input Sources
n Back Up Power Systems
n Wall Adapter or Li-Ion(s) Input to 5VOUT
n Battery or Super Capacitor Input for Reserve Power
n Replace Diode-OR Designs with Higher Efficiency,
Flexibility and Performance
L, LT , LT C , LT M , Linear Technology, the Linear logo and Burst Mode are registered trademarks
and PowerPath and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents, including 7709976.
CONTROL
SIGNALS
3.3µH
0.1µF 0.1µF
400k
40.2k
47nF
22µF
22µF
100µF
INDICATORS
4.7µF
10nF
22pF
BST1 BST2
VIN1
VIN2
VIN1
VIN2
SW1 SW2
3118 TA01a
CM1
47nF
CM2
CP1
VOUT VOUT
5V
VC
V1GD
FB
V2GD
PGD
MODE
SEL
RUN1
RUN2
CN1
10nF
CN2
CP2
PGND VCC GND
LTC3118
1.8nF
100k
100µs/DIV 3118 TA01b
5VOUT
AC-COUPLED
500mV/DIV
SW1
10V/DIV
SEL
5V/DIV SELECT VIN2 SELECT VIN1
VIN1 = 5V, VIN2 = 12V, VOUT = 5V AT 1A
Input Switchover Response
LTC3118
2
3118fa
For more information www.linear.com/LTC3118
absoluTe MaxiMuM raTings
pin conFiguraTion
VIN1, VIN2 Voltage ....................................... –0.3V to 20V
VOUT Voltage .............................................. –0.3V to 20V
SW1 DC Voltage (Note 4) ...............–0.3V to (VIN1 + 0.3V)
or (VIN2 + 0.3V)
SW2 DC Voltage (Note 4).............–0.3V to (VOUT + 0.3V)
BST1 Voltage .....................(SW1 – 0.3V) to (SW1 + 6V)
BST2 Voltage ....................(SW2 – 0.3V) to (SW2 + 6V)
RUN1, RUN2 Voltage .................................. –0.3V to 20V
PGD, V1GD, V2GD Voltage ......................... –0.3V to 20V
CM1, CM2 Voltage ....................................... –0.3 to 20V
(Note 1)
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3118EUFD#PBF LTC3118EUFD#TRPBF 3118 24-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LTC3118IUFD#PBF LTC3118IUFD#TRPBF 3118 24-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LTC3118HUFD#PBF LTC3118HUFD#TRPBF 3118 24-Lead (4mm × 5mm) Plastic QFN –40°C to 150°C
LTC3118MPUFD#PBF LTC3118MPUFD#TRPBF 3118 24-Lead (4mm × 5mm) Plastic QFN –55°C to 150°C
LTC3118EFE#PBF LTC3118EFE#TRPBF 3118FE 28-Lead Plastic TSSOP –40°C to 125°C
LTC3118IFE#PBF LTC3118IFE#TRPBF 3118FE 28-Lead Plastic TSSOP –40°C to 125°C
LTC3118HFE#PBF LTC3118HFE#TRPBF 3118FE 28-Lead Plastic TSSOP –40°C to 150°C
LTC3118MPFE#PBF LTC3118MPFE#TRPBF 3118FE 28-Lead Plastic TSSOP –55°C to 150°C
Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
8 9
TOP VIEW
25
PGND
UFD PACKAGE
24-LEAD (4mm × 5mm) PLASTIC QFN
10 11 12
24 23 22 21 20
6
5
4
3
2
1
SEL
VIN1
RUN1
RUN2
VCC
MODE
GND
CP2
VIN2
SW1
BST1
BST2
SW2
VOUT
CP1
CN1
CM1
CM2
CN2
VC
FB
V1GD
V2GD
PGD
7
14
15
16
17
18
19
13
TJMAX = 150°C, θJC = 3.4°C/W, θJA = 43°C/W
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
FE PACKAGE
28-LEAD PLASTIC TSSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CM1
CN1
CP1
SEL
VIN1
RUN1
RUN2
VCC
MODE
GND
GND
VC
FB
V1GD
CM2
CN2
PGND
CP2
VIN2
SW1
BST1
BST2
SW2
VOUT
PGND
PGND
PGD
V2GD
29
PGND
TJMAX = 150°C, θJC = 5°C/W, θJA = 30°C/W
EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB
CP1 Voltage ........................ (VIN1 – 0.3V) to (VIN1 + 6V)
CP2 Voltage ........................ (VIN2 – 0.3V) to (VIN2 + 6V)
VCC, CN1, CN2 Voltage ................................... –0.3 to 6V
MODE, SEL, FB, VC Voltage ........................... –0.3 to 6V
Operating Junction Temperature Range (Notes 2, 3)
LTC3118E/LTC3118I ........................... –40°C to 125°C
LTC3118H .......................................... –40°C to 150°C
LTC3118MP ........................................ –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) TSSOP ...... 300°C
LTC3118
3
3118fa
For more information www.linear.com/LTC3118
elecTrical characTerisTics
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Operating Voltage Range VIN1 or VIN2, VCC ≥ 2.5V l2.2 18 V
Output Operating Voltage l2 18 V
Undervoltage Lockout Threshold on VCC VCC Rising, VIN = 2.5V l2.2 2.35 2.5 V
Minimum VIN Start-Up Voltage VCC Powered from VIN1 or VIN2 (IVCC = 10mA) l2.2 2.5 2.65 V
Input Quiescent Current in Shutdown RUN1 and RUN2 < 0.2V 2 µA
Input Quiescent Current in Burst Mode Operation Active VIN1 or VIN2, FB = 1.2V 50 µA
Inactive VIN1 or VIN2, FB = 1.2V 5 µA
Input Quiescent Current in PWM Mode Operation Active VIN1 or VIN2, FB = 0.8V 12 mA
Output Quiescent Current in Burst Mode Operation 1 µA
Oscillator Frequency l1000 1200 1400 kHz
Oscillator Frequency Variation Active VIN = 3V to 18V 0.1 %/V
Feedback Voltage l0.98 1.0 1.02 V
Feedback Voltage Line Regulation Active VIN = 3V to 18V 0.2 %
Error Amplifier Transconductance VC Current = ±4µA 80 µS
Feedback Pin Input Current FB = 1V 0 50 nA
VC Source Current VC = 0.5V, FB = 0.8V –14 µA
VC Sink Current VC = 0.5V, FB = 1.2V 14 µA
RUN Pin Threshold: Accurate RUN1 or RUN2 Rising l1.17 1.22 1.27 V
RUN Pin Hysteresis: Accurate Accurate RUN (Rising – Falling) 170 mV
RUN Pin Logic Threshold for VCC Enable/Shutdown l0.2 0.65 1.15 V
RUN Pin Leakage Current RUN1 or RUN2 = 4V 0.2 µA
VCC Output Voltage IVCC = 1mA l3.5 3.8 4.1 V
VCC Load Regulation IVCC = 1mA to 10mA –1 %
VCC Line Regulation IVCC = 1mA, VIN = 5V to 18V 0.5 %
VCC Current Limit VIN > 6V 60 mA
Average Inductor Current Limit (Note 5) l3.0 3.6 5.2 A
Overload Current Limit (Note 5) Current from VIN1 or VIN2 6 A
Reverse Inductor Current Limit (Note 5) PWM Mode –200 mA
Maximum Duty Cycle Percentage of Period SW2 Is Low in Boost Mode l90 95 %
Percentage of Period SW1 Is High in Boost Mode l83 88 %
Minimum Duty Cycle Percentage of Period SW1 Is High in Buck Mode l0 %
SW1 and SW2 Forced Low Time BST1 or BST2 Capacitor Charge Time 100 ns
N-Channel Switch Resistance Switch A1 (From VIN1 to SW1) 80 mΩ
Switch A2 (From VIN2 to SW1) 120 mΩ
Switch B (From SW1 to PGND) 80 mΩ
Switch C (From SW2 to PGND) 80 mΩ
Switch D (From PVOUT to SW2) 80 mΩ
N-Channel Switch Leakage VIN2, VIN2 or VOUT = 18V 0.1 10 µA
Soft-Start Time 1 ms
MODE and SEL Threshold Voltage l0.3 0.75 1.2 V
MODE and SEL Leakage Pin = 5V 0 0.5 µA
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TJ ≈ TA = 25°C (Note 2). Unless otherwise noted, VIN1 or VIN2 = 5V, VOUT = 5V.
LTC3118
4
3118fa
For more information www.linear.com/LTC3118
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN1 Becomes Active Input in Ideal Diode Mode VIN2 = SEL = 5V
Rising
Falling
5
4.2
5.4
4.6
5.8
5
V
V
PGD Threshold Percent of FB Voltage Rising 90 94 98 %
PGD Hysteresis Percent of FB Voltage Falling –2 %
V1GD, V2GD, PGD Low Voltage ISINK = 5mA 300 mV
V1GD, V2GD, PGD Leakage Pin = 18V 1 µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3118 is tested under pulsed load conditions such that TJ ≈
TA. The LTC3112E is guaranteed to meet specifications from 0°C to 85°C
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3118I is guaranteed
to meet specifications over the –40°C to 125°C operating junction
temperature, the LTC3118H is guaranteed to meet specifications over the
–40°C to 150°C operating junction temperature range and the LTC3118MP
is guaranteed and tested to meet specifications over the full –55°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes; operating lifetime is derated for temperatures
greater than 125°C.
The maximum ambient temperature is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TJ ≈ TA = 25°C (Note 2). Unless otherwise noted, VIN1 or VIN2 = 5V, VOUT = 5V.
resistance and other environmental factors. The junction temperature
(TJ in °C) is calculated from the ambient temperature (TA in °C) and power
dissipation (PD in Watts) according to the following formula:
TJ = TA + (PD • θJA) where θJA is the thermal impedance of the package.
Note 3: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 4: Voltage transients on the switch pins beyond the DC limit specified
in the Absolute Maximum Ratings, are non disruptive to normal operation
when using good layout practices, as shown on the demo board or
described in the data sheet and application notes.
Note 5: Current measurements are performed when the LTC3118 is
not switching. The current limit values measured in operation will be
somewhat higher, while the reverse current thresholds may be lower due
to the propagation delay of the comparators and inductor value.
LTC3118
5
3118fa
For more information www.linear.com/LTC3118
VOUT = 12V, Efficiency and Power
Loss vs Load Current from VIN1
VOUT = 12V, Efficiency and Power
Loss vs Load Current from VIN2
12VOUT Efficiency vs VIN1 or VIN2
Voltage with 500mA and 1A Load
Current
Typical perForMance characTerisTics
VOUT = 3.3V Efficiency and Power
Loss vs Load Current from VIN1
VOUT = 3.3V Efficiency and Power
Loss vs Load Current from VIN2
3.3VOUT Efficiency vs VIN1 or VIN2
Voltage with 500mA and 1A Load
Current
VOUT = 5V, Efficiency and Power
Loss vs Load Current from VIN1
VOUT = 5V, Efficiency and Power
Loss vs Load Current from VIN2
5VOUT Efficiency vs VIN1 or VIN2
Voltage with 500mA and 1A Load
Current
TA = 25°C, unless otherwise noted.
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
40
60
10
3118 G01
20
00.001 0.01 0.1 1
100
30
50
10
70
80
90
5VIN
12VIN
18VIN
PWM
BURST
LOSS
PWM POWER LOSS (W)
2
3
1
0
5
4
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
PWM POWER LOSS (W)
40
60
10
3118 G02
20
00.001 0.01 0.1 1
100
30
50
10
70
80
2
3
1
0
5
4
90
5VIN
12VIN
18VIN
PWM
LOSS
BURST
INPUT VOLTAGE (V)
2
EFFICIENCY (%)
90
18
3118 G03
80
70 412 14 166 810
100
85
95
75
VIN1, LOAD = 500mA
VIN2, LOAD = 500mA
VIN1, LOAD = 1A
VIN2, LOAD = 1A
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
40
60
10
3118 G04
20
00.001 0.01 0.1 1
100
30
50
10
70
80
90
PWM
BURST
LOSS
PWM POWER LOSS (W)
2
3
1
0
5
4
3.6VIN
5VIN
12VIN
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
40
60
10
3118 G05
20
00.001 0.01 0.1 1
100
30
50
10
70
80
90
3.6VIN
5VIN
12VIN
PWM
BURST
LOSS
PWM POWER LOSS (W)
2
3
1
0
5
4
INPUT VOLTAGE (V)
2
EFFICIENCY (%)
90
18
3118 G06
80
70 412 14 166 810
100
85
95
75
VIN1, LOAD = 500mA
VIN2, LOAD = 500mA
VIN1, LOAD = 1A
VIN2, LOAD = 1A
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
40
60
10
3118 G07
20
00.001 0.01 0.1 1
100
30
50
10
70
80
90
PWM POWER LOSS (W)
2
3
1
0
5
4
PWM
2.7VIN
5VIN
12VIN
LOSS
BURST
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
40
60
10
3118 G08
20
00.001 0.01 0.1 1
100
30
50
10
70
80
90
PWM POWER LOSS (W)
2
3
1
0
5
4
PWM
2.7VIN
5VIN
12VIN
LOSS
BURST
INPUT VOLTAGE (V)
2
EFFICIENCY (%)
90
18
3118 G09
80
70 4 12 14 166 8 10
100
85
95
75
VIN1, LOAD = 500mA
VIN2, LOAD = 500mA
VIN1, LOAD = 1A
VIN2, LOAD = 1A
LTC3118
6
3118fa
For more information www.linear.com/LTC3118
Typical perForMance characTerisTics
N-Channel MOSFET Leakage
vs Die Temperature and Stand-Off
Voltage
Normalized N-MOSFET
Resistance vs VCC
Normalized N-Channel MOSFET
Resistance vs Die Temperature
PWM to Burst Mode Thresholds
vs VIN
Maximum Load Current vs VIN in
PWM Mode
Inductor Overload, Average and
Reverse Current Limits
vs Temperature
VIN1 OR VIN2 VOLTAGE (V)
2
PWM TO BURST THRESHOLD (mA)
280
18
3118 G13
140
06 14 164 8 1210
420
210
350
70
5VOUT
L = 3.3µH
12VOUT
L = 6.8µH
VIN1 OR VIN2 VOLTAGE (V)
2
MAXIMUM LOAD CURRENT (A)
2.5
18
3118 G14
1.5
06 14 164 8 1210
3.5
2.0
3.0
1.0
0.5
12VOUT
L = 6.8µH
5VOUT
L = 3.3µH
DIODE FROM VOUT = 5V
TO VCC
TEMPERATURE (°C)
–50
INDUCTOR CURRENT (A)
1
150
3118 G15
0
–1 –10 70 90 110 130–30 10 5030
6
2
3
4
5OVERLOAD
AVERAGE
REVERSE
STAND-OFF VOLTAGE (V)
0
LEAKAGE CURRENT (µA)
10
18
3118 G16
06 153 9 12
1000
1
100
25°C
50°C
75°C
100°C
125°C
150°C
175°C
VCC VOLTAGE (V)
2.5
NORMALIZED RESISTANCE
1.0
5.5
3118 G17
0.8
0.6 3.53 4 54.5
1.3
0.9
1.1
1.2
0.7
TEMPERATURE (°C)
–50
NORMALIZED RESISTANCE
1.0
150
3118 G18
0.8
0.6 0 10050
1.4
1.3
0.9
1.1
1.2
0.7
Die Temperature Rise vs Load
Current, VOUT = 12V, 4-Layer
LTC3118 Demo Board
Die Temperature Rise vs Load
Current, VOUT = 5V, 4-Layer
LTC3118 Demo Board
Die Temperature Rise vs Load
Current, VOUT = 3.3V, 4-Layer
LTC3118 Demo Board
LOAD CURRENT (A)
0
DIE TEMPERATURE RISE FROM AMBIENT (°C)
40
2.5
3118 G12
20
01 1.5 20.5
100
30
50
70
60
80
90
10
VIN = 2.7V
VIN = 5V
VIN = 12V
LOAD CURRENT (A)
0
DIE TEMPERATURE RISE FROM AMBIENT (°C)
40
2.5
3118 G11
20
01 1.5 20.5
100
60
30
50
70
90
80
10
VIN = 3.6V
VIN = 5V
VIN = 12V
LOAD CURRENT (A)
0
DIE TEMPERATURE RISE FROM AMBIENT (°C)
40
2.5
3118 G10
20
01 1.5 20.5
100
30
50
80
60
70
90
10
VIN = 5V
VIN = 12V
VIN = 18V
LTC3118
7
3118fa
For more information www.linear.com/LTC3118
FB Program Voltage
vs Temperature VCC vs Active VIN
Typical perForMance characTerisTics
MODE and SEL Logic Thresholds
Active VIN in Ideal Diode Mode
with Hysteresis
RUN1 and RUN2 Thresholds for
VIN UVLO and VCC Enable
RUN1 and RUN2 Current
vs Voltage
VCC vs Supply Current (VIN > 5V)
Showing Current Limit
No-Load Active VIN Current in
Burst Mode
No-Load Active VIN Current in
PWM
TEMPERATURE (°C)
–50
FB VOLTAGE (V)
1.000
150
3118 G19
0.985
0.975 0 10050
1.025
1.015
0.990
0.995
1.005
1.010
1.020
0.980
ACTIVE VIN VOLTAGE (V)
2
VCC VOLTAGE (V)
3.3
18
3118 G20
2.7
2.3 4 6 8 16141210
3.9
2.9
3.1
3.5
3.7
2.5
VCC SUPPLY CURRENT (mA)
0
VCC VOLTAGE (V)
80
3118 G21
3.6
3.4 604020
3.9
3.7
3.8
3.5
ACTIVE VIN VOLTAGE (V)
2
QUIESCENT CURRENT (µA)
125
18
3118 G22
50
04 6 8 16141210
250
150
75
100
200
225
175
25
VOUT = 5V
DIODE FROM VOUT = 5V TO VCC
VOUT = 12V
ACTIVE VIN VOLTAGE (V)
2
QUIESCENT CURRENT (mA)
20
18
3118 G23
12
04 6 8 16141210
24
16
4
8
VOUT = 12V
VOUT = 5V
DIODE FROM VOUT = 5V TO VCC
TEMPERATURE (°C)
–50
THRESHOLD VOLTAGE (V)
1.0
150
3118 G24
0.4
00 10050
1.4
0.6
0.8
1.2
0.2
RISING
FALLING
VIN2 VOLTAGE (V)
2
VIN1 VOLTAGE (V)
18
3118 G25
12
24 6 8 16141210
18
14
16
10
4
6
8
VIN1 ACTIVE
VIN2 ACTIVE
SEL = VCC
TEMPERATURE (°C)
–50
THRESHOLD VOLTAGE (V)
150
3118 G26
1.0
00 50 100
1.4
1.2
0.8
0.2
0.4
0.6
VCC ON
VCC OFF
VIN UVLO RISING
VIN UVLO FALLING
RUN VOLTAGE (V)
0 2
RUN CURRENT (µA)
4.5
18
3118 G27
3.0
04 6 8 16141210
5.0
3.5
4.0
2.5
1.0
1.5
2.0
0.5
LTC3118
8
3118fa
For more information www.linear.com/LTC3118
Typical perForMance characTerisTics
5VIN Burst Mode Waveforms
12VOUT, 50mA
12VIN Burst Mode Waveforms
12VOUT, 100mA
18VIN Burst Mode Waveforms
12VOUT, 100mA
Switch and VOUT Waveforms
(12VIN, 12VOUT)
12VIN2 to 5VIN1 Switchover
Waveforms, VOUT = 12V 500mA
Load
100mA to 1A Load Step PWM
Mode (12VIN, 12VOUT)
200ns/DIV
3118 G29
12VOUT
RIPPLE
100mV/DIV
IL
1A/DIV
SW1
5V/DIV
SW2
5V/DIV
500µs/DIV 3118 G30
12VOUT
AC-COUPLED
500mV/DIV
IL
1A/DIV
SEL
5V/DIV
SW1
10V/DIV
L = 6.8µH
COUT = 100µF
500µs/DIV 3118 G31
12VOUT
AC-COUPLED
500mV/DIV
IL
1A/DIV
INDUCTOR
1A/DIV
VC
200mV/DIV
L = 6.8µH
COUT = 100µF
5µs/DIV 3118 G32
12VOUT
RIPPLE
100mV/DIV
IL
0.5A/DIV
SW2
10V/DIV
SW1
10V/DIV
L = 6.8µH
COUT = 100µF
5µs/DIV 3118 G33
12VOUT
RIPPLE
100mV/DIV
IL
0.5A/DIV
SW2
10V/DIV
SW1
10V/DIV
L = 6.8µH
COUT = 100µF
5µs/DIV 3118 G34
12VOUT
RIPPLE
100mV/DIV
IL
0.5A/DIV
SW2
10V/DIV
SW1
10V/DIV
L = 6.8µH
COUT = 100µF
SW1, SW2 Minimum Low Time
vs VCC
VCC VOLTAGE (V)
2.5 3
MINIMUM LOW TIME (ns)
5.5
3118 G28
80 3.5 4 4.5 5
160
120
140
100
LTC3118
9
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For more information www.linear.com/LTC3118
Typical perForMance characTerisTics
Soft-Start Waveforms with 500mA
Load (12VIN, 12VOUT)
VOUT Short-Circuit Waveforms
Response and Recovery
(12VIN, 12VOUT)
VCC Short-Circuit Waveforms
Response and Recovery
(12VIN, 12VOUT, 500mA Load)
200µs/DIV 3118 G35
VOUT
5V/DIV
IL
1A/DIV
VC
500mV/DIV
RUN1 OR
RUN2
5V/DIV
RL = 24Ω
1ms/DIV 3118 G36
VOUT
5V/DIV
IL
2A/DIV
VC
500mV/DIV
VOUT SHORTED SHORT
RELEASED
2ms/DIV 3118 G37
VOUT
10V/DIV
IL
1A/DIV
VCC
5V/DIV VCC
SHORTED SHORT
RELEASED
LTC3118
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For more information www.linear.com/LTC3118
pin FuncTions
SEL (Pin 1/Pin 4): Input Select Pin.
SEL = Logic Low (ground): VIN1 priority mode, the con-
verter will operate from VIN1 if RUN1 and VIN1 voltages
are above their respective thresholds. If these conditions
are not met, the converter will operate from VIN2 as long
as RUN2 and VIN2 voltages are above their thresholds.
SEL = Logic High (connect to VCC): Ideal diode mode,
the converter will operate from the higher voltage of VIN1
or VIN2.
VIN1 (Pin 2/Pin 5): The first input voltage source for the
converter. Connect a minimum of 22µF ceramic decou-
pling capacitor from this pin to ground, as close to the IC
as possible. In ideal diode mode (SEL = 1), this input will
be selected if VIN1 > VIN2, VIN1 is above its internal UVLO
threshold, and RUN1 > 1.22V. In priority mode (SEL =
0), this input will be selected if VIN1 is above its internal
UVLO threshold and RUN1 > 1.22V.
Since this input has lower RDS(ON) MOSFETs between VIN1
and SW1, it should be considered for use with the source
where high efficiency is more critical.
RUN1 (Pin 3/Pin 6): Input to enable and disable the IC and
program the UVLO threshold for VIN1. Pull RUN1 above
1.22V to enable the converter. Connecting this pin to a
resistor divider from VIN1 to ground allows programming
of VIN1’s UVLO threshold above 2.2V. Pulling both RUN1
and RUN2 to logic low states will put the IC in a low cur-
rent shutdown state.
RUN2 (Pin 4/Pin 7): Input to enable and disable the IC and
program the UVLO threshold for VIN2. Pull RUN2 above
1.22V to enable the converter. Connecting this pin to a
resistor divider from VIN2 to ground allows programming
of VIN2’s UVLO threshold above 2.2V. Pulling both RUN1
and RUN2 to logic low states will put the IC in a low cur-
rent shutdown state.
VCC (Pin 5/Pin 8): Output voltage of the internal VCC regula-
tor. This is the supply pin for the internal driver circuitry.
Bypass this output with a 4.7µF ceramic capacitor. This
pin may be back driven by an external supply, up to 5.5V.
VCC will be generated from either VIN1 or VIN2 depending
upon which input the converter is operating from.
MODE (Pin 6/Pin 9): PWM or Auto Burst Mode Select Pin.
MODE = Logic Low (ground): Enables automatic Burst
Mode operation.
MODE = Logic High (connect to VCC): Forces PWM mode
operation.
GND (Pin 7/Pins 10, 11): Signal Ground for the IC. Provide
a short direct PCB path from this pin to the ground plane.
VC (Pin 8/Pin 12): Output of the voltage error amplifier
used to program average inductor current. An RC from
this pin to ground sets the voltage loop compensation.
The average current loop is internally compensated.
FB (Pin 9/Pin 13): Feedback input to the voltage error am-
plifier. Connect to a resistor divider from VOUT to ground.
The output voltage can be adjusted from 2V to 18V by:
VOUT = 1 + (R1/R2).
V1GD (Pin 10/Pin 14): Open-drain indicator that pulls to
ground when both VIN1 and RUN1 are above their respec-
tive thresholds. Connect a pull-up resistor from this pin
to a positive supply.
V2GD (Pin 11/Pin 15): Open-drain indicator that pulls to
ground when both VIN2 and RUN2 are above their respec-
tive thresholds. Connect a pull-up resistor from this pin
to a positive supply.
PGD (Pin 12/Pin 16): Open-drain output that pulls to
ground when VOUT is greater than 92% of the programmed
output voltage. Connect a pull-up resistor from this pin
to a positive supply.
VOUT (Pin 13/Pin 19): Regulated Output Voltage. Con-
nect a minimum of 47µF ceramic or low ESR decoupling
capacitor from this pin to ground. The capacitor should
be placed as close to the IC as possible with short, wide
traces to VOUT and GND.
SW2 (Pin 14/Pin 20): Switch Pin. Connect to the other
side of the inductor. Keep PCB trace lengths as short and
wide as possible to reduce EMI.
BST2 (Pin 15/Pin 21): Bootstrapped floating supply for
high side N-channel MOSFET gate drive. Connect to SW2
through a 0.1µF capacitor, as close to the part as possible.
(QFN/TSSOP)
LTC3118
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pin FuncTions
(QFN/TSSOP)
BST1 (Pin 16/Pin 22): Bootstrapped floating supply for
high side N-channel MOSFET gate drive for VIN1 or VIN2.
Connect to SW1 through a 0.1µF capacitor, as close to
the part as possible. This capacitor provides gate drive
for the N-channel MOSFETs connected between SW1 and
either VIN1 or VIN2.
SW1 (Pin 17/Pin 23): Switch Pin. Connect to one side of
the inductor. Keep PCB trace lengths as short and wide
as possible to reduce EMI.
VIN2 (Pin 18/Pin 24): The second input voltage source for
the converter. Connect a minimum of 22µF ceramic decou-
pling capacitor from this pin to ground, as close to the IC
as possible. In ideal diode mode (SEL = 1), this input will
be selected if VIN2 > VIN1, VIN2 is above its internal UVLO
threshold, and RUN2 > 1.22V. In priority mode (SEL = 0),
this input will only be selected if VIN1 is below its internal
UVLO threshold or RUN1 < 1.05V.
Since this input has the higher RDS(ON) MOSFETs between
VIN2 and SW1, it should be considered for use with the
source where slightly lower conversion efficiency is ac-
ceptable.
CP2 (Pin 19/Pin 25): Positive pin for the VIN2 top N-channel
MOSFET charge-pump capacitor. This pin toggles between
VIN2 and VIN2 + VCC when VIN2 is active.
CN2 (Pin 20/Pin 27): Negative pin for the VIN2 top
N-channel MOSFET charge-pump capacitor. This pin is
driven between VCC and GND when VIN2 is active. Connect
a 10nF ceramic capacitor between CN2 and CP2. This pin
can be monitored to indicate operation from VIN2.
CM2 (Pin 21/Pin 28): Filter pin for the common connec-
tion of VIN2 to SW1 N-channel MOSFETs. Connect a 47nF
capacitor from this pin to the ground plane.
CM1 (Pin 22/Pin 1): Filter pin for the common connec-
tion of VIN1 to SW1 N-channel MOSFETs. Connect a 47nF
capacitor from this pin to the ground plane.
CN1 (Pin 23/Pin 2): Negative pin for the VIN1 top N-channel
MOSFET charge-pump capacitor. This pin is driven be-
tween VCC and GND when VIN1 is active. Connect a 10nF
ceramic capacitor between CN1 and CP1. This pin can be
monitored to indicate operation from VIN1.
CP1 (Pin 24/Pin 3): Positive pin for the VIN1 top N-channel
MOSFET charge-pump capacitor. This pin toggles between
VIN1 and VIN1 + VCC when VIN1 is active.
PGND (Exposed Pad Pin 25/Pins 17, 18, 26, Exposed Pad
Pin 29): Power Ground for the IC. The exposed pad must
be soldered to the PCB ground plane. It serves as the
power ground connection, and as a means of conducting
heat away from the die.
LTC3118
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block DiagraM
+
–
+
–
+
–
+
–
+
–
+
–
VCC
VCC
VCC
VIN2
FB
0.92V
VIN1
VIN2
2V
VCC
2.35V
6A
VIN2
PGD
VIN1
VCC
VCC
1V
ISENSE
RCS
1.2MHz RAMPS/
OSCILLATOR
SOFT-START
RAMP
3118 BD
ISWA
ISWB
CM1
CM2
PGND
B
D
C
L
VIN2
VIN1
VIN2
2.2V TO 18V VOUT 2V TO 18V
2.2V TO 18V
BST1 BST2VIN1 SW1 SW2 VOUT
3.8V REGULATOR
1.22V REFERENCE
CP2
CN2
CP1
CN1
+
–
VCC
VC
FB
R1
R2
SEL
RUN1
RUN2
MODE
GND
V1GD
V2GD
VIN1GOOD
PWM
COMPARATOR
AVERAGE
CURRENT
AMPLIFIER
1.22V
VIN2GOOD
RUN/SD
VSELECT
RUNBURST
SWITCH
COMMANDS
UVLO
DRIVERS
ADRV BDRV CDRV DDRV
IDEAL DIODE
MODE
UP TO 18V
V1PRIORITY
MODE
VIN1GOOD
VIN1GOO2
ISENSE
ISENSE
ISWA
ISWB
CLK
SEL2
PMP2
VIN1
VCC
CLK
SEL1
PMP1
+
–
gm
+
–
BDRV
CP1 CP2
+
–
–
+
IPEAK
DDRV
CDRV
IREV
A FETs
AND DRIVERS
–200mA
COUT
LTC3118
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For more information www.linear.com/LTC3118
operaTion
Introduction
The LTC3118 is a dual-input, current mode, monolithic
buck-boost DC/DC converter that can operate over a wide
input voltage range of 2.2V to 18V. The output voltage
can be programmed between 2V to 18V and deliver more
than 2A of load current. The LTC3118 operates from either
VIN1 or VIN2 depending on the state of the SEL pin. If SEL
is commanded to be a logic high, VOUT will be powered
from the highest valid input voltage. If SEL is a logic low,
VOUT will be powered from VIN1 (priority mode) assuming
sufficient input voltage is present. Internal, low RDS(ON)
N-channel power switches reduce the solution complexity
and maximize efficiency.
A proprietary switch algorithm allows the buck-boost
converter to maintain output voltage regulation with in-
put voltages that are above, below or equal to the output
voltage. Transitions between the step-up or step-down
operating modes are seamless and free of transients and
subharmonic switching, making this product ideal for noise
sensitive applications. The LTC3118 operates at a fixed
nominal switching frequency of 1.2MHz, which provides
an ideal trade-off between small solution size and high
efficiency. Current mode control provides inherent input
line voltage rejection, simplified compensation and rapid
response to load transients. Burst Mode operation capabil-
ity is also included in the LTC3118 and is user-selected
via the MODE input pin. In Burst Mode operation, the
LTC3118 provides exceptional efficiency at light output
loads by operating the converter only when necessary to
maintain voltage regulation. At higher loads, the LTC3118
automatically transitions to fixed frequency PWM mode
when Burst Mode operation is selected.
For 5V VOUT applications, the input quiescent currents in
Burst Mode operation can be reduced with the internal
LDO regulator bootstrapped to the output voltage. If the
application requires extremely low noise, continuous PWM
operation can also be selected via the MODE pin. The
LTC3118 also features accurate, resistor programmable
RUN comparator thresholds with hysteresis for each VIN.
This allows the buck-boost DC/DC converter to turn on
and off at user-selected voltage thresholds depending on
the power source for each VIN. With a wide voltage range
and high efficiency, the LTC3118 is well suited for many
demanding power systems.
Power Stage Topology
Figure 1 shows the topology of the dual-input LTC3118
power stage switches and their associated gate drivers.
The LTC3118 integrates independent switch paths from
VIN1 to SW1 and VIN2 to SW1 to provide isolation between
the selected input and the inactive input. This configuration
allows conversion from either input source, regardless of
their respective voltage levels, enabling ideal diode or VIN1
priority modes (see SEL pin description).
Figure 1. LTC3118 Dual-Input Power Stage
3118 F01
VIN1 VOUT
VCC
VCC
PUMP1
A1ON
BST1
A1
CM1
VIN2
A2ON
SW1 SW2
BST1
A2
CM2
BST2
L
PGND
B C
D
BON CON
DON
PUMP2
LTC3118
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operaTion
If operation from VIN1 is selected, PUMP1 connects the
low RDSON static switch between VIN1 and CM1 as shown.
Switch A1 is then driven on for a portion of each switching
cycle, as commanded by the PWM circuitry and powered
by the flying capacitor between BST1 and SW1. When
operating from VIN1, PUMP2 and A2 are disabled.
Operation from VIN2 is accomplished in a similar man-
ner, except that PUMP2 connects VIN2 to CM2 and A2 is
commanded on by the PWM. With operation from VIN2,
PUMP1 and A1 are disabled providing isolation from VIN1.
PWM Mode Operation
If the MODE pin is high, or if the load current on the
converter is high enough to force PWM mode operation,
the LTC3118 operates at a fixed 1.2MHz frequency us-
ing a current mode control loop. PWM mode minimizes
output voltage ripple and yields a low noise switching
frequency spectrum. A proprietary switching algorithm
provides seamless transitions between operating modes
and eliminates discontinuities in the average inductor
current, inductor ripple current and loop transfer function
throughout all modes of operation. These advantages
result in increased efficiency, improved loop stability and
lower output voltage ripple. In PWM mode operation, both
SW1 and SW2 transition on every cycle independent of
the input and output voltages. In response to the internal
control loop command, an internal pulse width modulator
generates the appropriate switch duty cycle to maintain
regulation of the output voltage.
When stepping down from a high input voltage to a lower
output voltage, the converter operates in buck mode and
switch D remains on for the entire switching cycle except
for a minimum SW2 low duration (typically 100ns). Dur-
ing the switch low duration, switch C is turned on which
forces SW2 low and charges the flying capacitor between
BST2 and SW2. This ensures that the switch D gate driver
power supply rail on BST2 is maintained. The duty cycle of
switch A1 (or A2) and switch B are adjusted by the PWM
circuit to maintain output voltage regulation in buck mode.
If the input voltage is lower than the output voltage, the
converter operates in boost mode. Switch A1 (or A2)
remains on for the entire switching cycle except for the
minimum switch low duration (typically 100ns). During the
switch low duration, switch B is turned on which forces
SW1 low and charges the flying capacitor between BST1
and SW1. This ensures that switch A1 (or A2) gate driver
power supply rail on BST1 is maintained. The duty cycle
of switch C and switch D are adjusted by the PWM circuit
to maintain output voltage regulation in boost mode.
Oscillator
The LTC3118 operates from an internal oscillator with
a nominal fixed frequency of 1.2MHz. This allows the
DC/DC converter efficiency to be maximized while still
using small external components.
Input Select Logic and VIN Power Good Indicators
A simplified schematic diagram of the LTC3118’s input
select circuitry is shown in Figure 2. UVLO comparators
on VIN1, VIN2 and VCC set minimum operating voltages to
ensure proper operation. VCC must be greater than 2.35V
before operation is allowed from either input. Once VCC
is valid, one of the inputs must be greater than 2V typical
before the LTC3118 enables switching. Finally, the RUN
pin voltage for the particular input must be greater than
1.22V to enable operation. This condition will be met if the
appropriate RUN pin is connected to its own VIN, RUN1 to
VIN1 for example, but may not be met if a resistor divider
is used to program the accurate RUN pin higher than the
VIN UVLO minimum. Detailed discussions of VCC, VIN and
RUN pin UVLOs are presented in later sections.
Once the UVLO conditions are satisfied, internal VIN1GOOD
and/or VIN2GOOD will assert and the LTC3118 is allowed
to operate. The state of each VINGOOD signal and the SEL
pin are decoded in logic to determine which input source
is selected, as shown on the table in Figure 2.
Open-drain indicator pins V1GD and V2GD are driven
by their respective internal VINGOOD signals and can be
used to alert the system of undervoltage conditions on
the inputs. External pull-up resistors can be connected
between these pins and any supply voltage up to 18V.
Since these pins pull low with valid input voltages, even
in Burst Mode operation, high value resistors are recom-
mended for applications where minimal no-load quiescent
current is critical.
LTC3118
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operaTion
If SEL is a logic low, the LTC3118 operates in VIN1 priority
mode where VIN1 is selected for operation if conditions
are met for VIN1GOOD to be high. If VIN1GOOD is low in
priority mode, the LTC3118 will revert to VIN2 operation
if VIN2(GOOD) is asserted, keeping VOUT powered.
If SEL is a logic high, the LTC3118 operates in ideal diode
mode, where VOUT is powered from the highest input
voltage source with a high VINGOOD signal. An internal
comparator with 400mV hysteresis monitors the input
voltages to determine which is higher. If the state of this
comparator changes during PWM operation, switching
will be suspended for six clock cycles before resuming
from the other input source. An approximate 250µs filter/
time constant prevents rapid transitions between inputs.
As with priority mode, if one of the VINGOOD signals is low
the LTC3118 will operate from the other input in order to
keep the output powered. If both VINGOOD signals are low
in either mode, the LTC3118 will not deliver power to VOUT.
VOUT Power Good Indicator
The VOUT power good indicator is an open-drain output
pin similar to the V1GD and V2GD pins shown in Figure 2.
PGD is driven by an internal comparator that monitors the
FB pin. If FB is below 0.92V (VOUT is 8% low) PGD will open
circuit, allowing an external resistor to pull high indicating
the output voltage is not in regulation. The power good
comparator has internal filtering for glitch suppression.
Figure 2. Simplified Input Select Logic and VIN Power Good Indicators
3118 F02
+
–
2V
VIN2
V2GD
+
–
1.22V
RUN2
+
–
1.22V
RUN1
V1GD
+
–
2V
VIN1
+
–
2.35V
VCC
VCCGOOD
VIN2GOOD
VIN1GOOD
UVLO COMPARATORS
INPUT VOLTAGE SELECT LOGIC
SEL PIN VIN1GOOD VIN2GOOD SELECTED VIN
1
IDEAL
DIODE
MODE
1 1 Highest VIN
1 0 VIN1
0 1 VIN2
0 0 No Switching
0
PRIORITY
MODE
1 1 VIN1
1 0 VIN1
0 1 VIN2
0 0 No Switching
LTC3118
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operaTion
Current Mode Control
The LTC3118 utilizes average current mode control for the
pulse width modulator, as shown in Figure 3. Current mode
control, both average and the better known peak method,
enjoy some benefits compared to other control methods,
including: simplified loop compensation, rapid response
to load transients and inherent line voltage rejection.
Referring to Figure 3, an internal high gain transcon-
ductance error amplifier, labeled VAMP, monitors VOUT
through a voltage divider connected to the FB pin and
provides an output, VC, used by the current mode control
loop to command the appropriate inductor current level.
To ensure stability, external frequency compensation
components (RZ, CP1 and CP2) must be installed be-
tween VC and GND. The procedure for determining these
components is provided in the Applications Information
section of this data sheet. VC is internally connected to the
noninverting input of a high gain, integrating, operational
amplifier, referred to in Figure 3 as IAMP. The inverting
input of the average current amplifier is connected to the
inductor current sense resistor RCS through a gain-setting
resistor RA1 and to its output (ICOMP) through an internal
frequency compensation network comprised of RA2 and
CA. The average current amplifier’s output provides the
cycle-by-cycle duty cycle command into the buck-boost
PWM circuitry.
The non-inverting reference level input to the average
current amplifier is VC and the feedback or inverting input
is driven from the inductor current sensing circuitry. The
inductor current sensing circuitry alternately measures the
current through switches A1 (or A2) and B. The output of
the sensing circuitry produces a voltage across resistor RCS
that resembles the inductor current waveform transformed
to a voltage. If there is an increase in the power converter
load on VOUT, the instantaneous level of VOUT will drop
slightly, which will increase the voltage level on VC by
the inverting action of the voltage error amplifier. When
the increase on VC first occurs, the output of the current
averaging amplifier, ICOMP, will increase momentarily to
command a larger duty cycle. This duty cycle increase
will result in a higher inductor current level, ultimately
raising the average voltage across RCS. Once the average
Figure 3. Average Current Mode Control Loop
3118 F03
VOUT
1V
1.2MHz RAMPS/
OSCILLATOR
TO
SWITCHES
IL
ICOMP
SW1 SW2
RA1 RA2
CA
INDUCTOR
CURRENT
SENSE
VC
CP1
CP2
+
–
FB
IAMP
VAMP
RCS
R1
R2
RZ
IAVG
PWM
DRIVE LOGIC
–
+
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operaTion
value of the voltage on RCS is equivalent to the VC level,
the voltage on ICOMP will revert very closely to its previ-
ous level into the PWM, and force the correct duty cycle
to maintain voltage regulation at this new higher inductor
current level. The average current amplifier is configured as
an integrator, so in steady state, the average value of the
voltage applied to its inverting input (voltage across RCS)
will be equivalent to the voltage on its noninverting input
VC. As a result, the average value of the inductor current
is controlled in order to maintain voltage regulation. The
entire current amplifier and PWM can be simplified as a
voltage controlled current source, with the driving volt-
age coming from VC. VC is commonly referred to as the
current command for this reason, and the voltage on VC
is directly proportional to average inductor current, which
can prove useful for many applications.
The voltage error amplifier monitors VOUT through a voltage
divider and makes adjustments to the current command
as necessary to maintain regulation. The voltage error
amplifier therefore controls the outer voltage regulation
loop. The average current amplifier makes adjustments
to the inductor current as directed by the voltage error
amplifier output via VC and is commonly referred to as
the inner current loop amplifier. The average current mode
control technique is similar to peak current mode control
except that the average current amplifier, by virtue of its
configuration as an integrator, controls average current
instead of the peak current. This difference eliminates the
peak-to-average current error inherent to peak current
mode control, while maintaining most of the advantages
inherent to peak current mode control.
Average current mode control requires appropriate
compensation for the inner current loop, unlike peak
current mode control. The compensation network must
have high DC gain to minimize VOUT regulation errors
and high bandwidth to quickly change the commanded
current level following transient load steps. The inner
loop compensation components are fixed internally on
the LTC3118. External compensation of the voltage loop
is detailed in the Applications Information section and is
similar to techniques used for peak current mode control.
Inductor Current Sense and Maximum Output Current
As part of the current control loop, the LTC3118 has cur-
rent sense circuitry that measures the inductor current
of the buck-boost converter, as shown in Figure 3. This
circuitry measures the current through switches A1 (or
A2) and B separately and produces proportional output
currents that are summed at the current sense resistor RCS.
Sensed A and B switch currents form a voltage replica of
the inductor current at RCS, which is used by the average
current amplifier, as described in the previous section.
The voltage amplifier output, VC, is internally clamped to
a nominal value of 1V. Since the average inductor current
is proportional to VC, the 1V clamp sets the maximum
average inductor current that can be programmed by the
inner current loop. Taking into account the current sense
amplifier’s gain, and the value of RCS, the maximum average
inductor current is 3.6A typical. In buck mode, the output
current is approximately equal to the inductor current IL.
IOUT(BUCK) ≈ IL • 0.85
The 100ns SW1/SW2 forced low time on each switching
cycle briefly disconnects the inductor from VOUT and VIN,
resulting in slightly less output current in either buck or
boost mode for a given inductor current. In boost mode,
the output current is related to average inductor current
and duty cycle by:
IOUT(BOOST) ≈ IL • (1 – D)
where D is the converter duty cycle.
Since the output current in boost mode is reduced by the
duty cycle (D), the output current rating in buck mode is
always greater than in boost mode. Also, because boost
mode operation requires a higher inductor current for a
given output current compared to buck mode, the efficiency
in boost mode will be lower due to higher conduction
(IL² • RDS(ON)) losses in the power switches. This will fur-
ther reduce the output current capability in boost mode. In
either operating mode, however, the inductor peak-to-peak
ripple current does not play a major role in determining
the output current capability.
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operaTion
The maximum load current capability in PWM mode curves
in the Typical Performance Characteristics section show
the relationship of input voltage and the ability to deliver
load current at VOUT = 5V and 12V. When the input voltage
is a volt or more above VOUT in buck mode, the LTC3118
is capable of providing more than 2A of load current. In
boost mode, the output current capability is further reduced
by the boost ratio or duty cycle (D) as described in the
preceding equation.
Overload Current Limit and Reverse Current
Comparators
The internal current sense waveforms are used by the
peak overload current (IPEAK) and reverse current (IREV)
comparators. The IPEAK current comparator monitors
ISENSE and interrupts normal PWM operation if the induc-
tor current level exceeds its maximum internal threshold.
This threshold is approximately 60% above the maximum
average current level of the current control loop. If the
internal current sense waveform rises above this level, the
LTC3118 will disconnect the inductor from VIN by shut-
ting off switch A1 (or A2) to prevent higher current in the
inductor. The IPEAK circuitry is reset by the oscillator clock
at the end of each switching cycle. In the event that the
overload comparator is tripped as the result of an output
short-circuit condition, where VOUT is discharged below
approximately 1V, the LTC3118 will initiate a soft-start
event keeping the on-chip power dissipation to low levels.
Once the short circuit is removed, the LTC3118 will restart
in the normal fashion. If the average current loop is able
to prevent inductor current from reaching IPEAK during a
short-circuit event, soft-start will not be initiated, but the
maximum current capability of the current loop will be
reduced by 40% to reduce power dissipation.
The LTC3118 contains a reverse current comparator set to
a nominal value of –200mA. If the internal current sense
waveform transitions below the internally set reverse cur-
rent threshold, the LTC3118 will disconnect the inductor
from VOUT by shutting off switch D, to prevent rapid dis-
charge of the output capacitor. The IREV circuitry is reset
by the oscillator clock at the end of the switching cycle.
Burst Mode Operation
When the MODE pin is held low, the LTC3118 is configured
for automatic Burst Mode operation. As a result, the buck-
boost DC/DC converter will operate
with normal continuous
PWM switching above a predetermined average inductor
current and will automatically transition to power saving
Burst Mode operation below this level. Refer to the Typical
Performance Characteristics section of this data sheet to
determine the Burst Mode transition threshold for various
combinations of VIN and VOUT.
With MODE held low at light output loads, the LTC3118
will go into a standby or sleep state when the output volt-
age achieves its nominal regulation level. The sleep state
halts PWM switching and powers down all nonessential
functions of the IC, significantly reducing the quiescent
current of the LTC3118. This greatly improves overall
power conversion efficiency when the output load is
light. Since the converter does not operate in sleep, the
output voltage will slowly decay at a rate determined by
the output load resistance and the output capacitor value.
When the output voltage has decayed by a small amount,
the LTC3118 will wake up and resume normal PWM
switching operation until the voltage on VOUT is restored
to the previous level. If the load is very light, the LTC3118
may only need to switch for a few cycles to restore VOUT,
and may sleep for extended periods of time, significantly
improving conversion efficiency.
LTC3118
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Soft-Start
The LTC3118 soft-start circuit minimizes inrush current
and output voltage overshoot on initial power up. The
required timing components for soft-start are internal to
the LTC3118 and produce typical soft-start durations of
approximately 1ms. The internal soft-start circuit slowly
ramps the error amplifier output at VC. In doing so, the
current command of the IC is slowly increased, starting
from zero. After initial power-up, soft-start can be reset by
UVLO on VCC, both VIN1GOOD and VIN2GOOD de-asserting,
thermal shutdown, or a VOUT short circuit.
VCC Regulator
An internal low dropout regulator (LDO) generates a
nominal 3.8V rail from the active input VIN1 or VIN2. The
VCC rail powers the internal control circuitry and power
device gate drivers of the LTC3118, including the BST pin
capacitors. The VCC regulator is disabled in shutdown to
reduce quiescent current and is enabled by forcing one
RUN pin above its logic threshold. The VCC regulator
includes current-limit protection to safeguard against
accidental short-circuiting of the LDO rail. In 5V VOUT ap-
plications, VCC can be powered by VOUT through an external
Schottky diode. This technique is commonly referred to
as bootstrapping. Bootstrapping can provide a significant
efficiency improvement, particularly when the active VIN
is high, and also allows operation to the minimum rated
input voltage of 2V. For more information see Bootstrap-
ping the VCC Regulator with 5V VOUT or External Supply,
in the Applications Information section.
Undervoltage Lockouts
The LTC3118 undervoltage lockout (UVLO) circuits disable
operation of the internal power switches if both VIN1 and
VIN2 or the VCC voltages are below their respective UVLO
thresholds (see Figure 2). There are three UVLO circuits,
one for each VIN and another that monitors VCC. The VIN
UVLO comparators have a falling voltage threshold of 1.8V
(typical at room temperature). If both input voltages fall
below this level, switching is disabled until one VIN rises
above 2V, as long as VCC is above its UVLO threshold. The
VCC UVLO has a falling voltage threshold of 2.2V (typical).
If VCC falls below this threshold, IC operation is disabled
until VCC rises above 2.35V as long as one VIN is above
its UVLO threshold level.
Depending on the particular application, any of these
UVLO thresholds could be the limiting factor affecting
the minimum input voltage required for operation. The
LTC3118 VCC regulator uses VIN1 or VIN2 for its power
input, whichever is active (see the Input Select Logic and
VIN Power Good Indicators section). If VCC is not boot-
strapped, there exists a voltage drop between the active
VIN and VCC. The dropout voltage is proportional to the
loading on VCC due to the gate charge to the internal power
switches. The Typical Performance Characteristics section
of this data sheet provides information on the dropout
voltage between VIN1 (or VIN2) and VCC.
In applications where VCC is bootstrapped (powered by
VOUT through a Schottky diode or auxiliary power rail),
the minimum input voltage for operation (after start-up)
will be limited only by the VIN UVLO thresholds (1.8V
typical). Please note: If the bootstrap voltage is derived
from the LTC3118 VOUT and not an independent power
rail, then the minimum input voltages required for
initial
start-up
are still limited by the minimum VCC voltage
(2.35V typical).
operaTion
LTC3118
20
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RUN1 and RUN2 Pin Comparators
Forcing both RUN1 and RUN2 to a logic low places the
LTC3118 in a low current shutdown state. When the volt-
age on either pin is brought above a 0.65V logic threshold,
certain IC functions are enabled as shown in Figure 4a.
The RUN1 and RUN2 pins also include accurate internal
comparators that allow them to be used to set custom
rising and falling ON/OFF thresholds for VIN1 and VIN2,
respectively, with the addition of external resistor dividers.
If either RUN pin voltage is increased to exceed its accurate
comparator threshold (1.22V nominal), all functions of the
buck-boost converter will be enabled and switching will
commence, assuming the respective VIN and VCC UVLO
circuits are cleared (see Figure 2).
If both RUN1 and RUN2 are brought below the accurate
comparator threshold, the buck-boost converter will inhibit
switching, but the VCC regulator and control circuitry will
remain powered unless both RUN pins are brought below
the logic threshold. Therefore, in order to completely
shut down the IC and reduce the VIN currents to < 2µA
(typical), it is necessary to ensure that both RUN pins are
brought below the worst-case low logic threshold of 0.2V.
RUN1 and RUN2 are high voltage capable inputs but must
be connected to their respective VIN1 and VIN2 supplies
through a high value resistor greater than 200k to prevent
a potential latch condition at the pin. The RUN pins can
be driven above VIN or VOUT within their specified voltage
ratings. If either RUN pin is forced above 5V, it will sink a
small current, as given by the following equation:
IRUN ≈
V
RUN
−5V
3MΩ
With the addition of optional resistor divider(s), as shown
in Figure 4a, the RUN pin(s) can be used to establish a
user-programmable turn-on and turn-off threshold.
The buck-boost converter is enabled when the voltage
on either RUN pin reaches 1.22V. Therefore, the turn-on
voltage threshold on VIN is given by:
VTURNON =1.22V 1+RT
RB
Figure 4. (a) Accurate RUN1 or RUN2 Pin Comparators, (b) Manual VIN Select with Overlap Timing, (c) Active VIN Indicators
operaTion
1.22V
VIN
LTC3118
3118 F04a
RUN1 OR
RUN2
RT
RB
ENABLE
SWITCHING
LOGIC
THRESHOLD
ACCURATE
THRESHOLD
ENABLE LDO AND
CONTROL CIRCUITS
+
–
0.65V
+
–
(a) (b) (c)
3118 F04b
1M
LOGIC
SIGNAL
LOGIC
SIGNAL
100pF
RUN1
1M 100pF
RUN2
VIN1
VIN2
VIN1
VIN2
3118 F04c
1M 100pF
VIN1 ACTIVE
VIN2 ACTIVE
CN1
1M 100pF
CN2
LTC3118
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The RUN comparators include a built-in hysteresis of
approximately 170mV, so that the turn-off threshold will
be approximately 15% lower than the turn-on threshold.
Put another way, the internal threshold levels for the RUN
comparators to disable switching from a particular input
is 1.05V.
VTURNOFF =1.05V 1+RT
RB
The RUN comparator is relatively noise insensitive, but
there may be cases due to PCB layout, very large value
resistors for RT and RB (Figure 4a), or proximity to noisy
components where noise pickup is unavoidable and may
cause the turn-on or turn-off levels to be intermittent. In
these cases, a small value filter capacitor can be added
across RB to ensure proper operation.
Selecting Priority or Ideal Diode Mode Operation
Priority Mode (SEL=0)
Priority mode operation is suggested for most applications,
since powering from one of the sources is typically
preferred. In priority mode, the primary input is connected
to VIN1 and the auxiliary input is connected to VIN2. The
LTC3118 will maintain operation from VIN1 until either
the RUN1 or minimum VIN1 UVLO circuits transition the
LTC3118 to VIN2 operation if valid. It is important that the
RUN1 turn-off threshold programs the minimum VIN1
above 2.5V in Priority Mode unless VCC is back-fed and
held above 2.5V. This prevents an unintended soft-start
cycle from occurring if VCC hits its UVLO threshold when
the VIN1 source is removed, before transitioning to VIN2
operation.
Depending on the maximum load current of the application,
the RUN1 and RUN2 minimum VIN turn-off thresholds
may need to set well above 2.5V to prevent VOUT from
losing regulation, especially in step-up mode. Please
refer to Maximum Load Current vs VIN curves found in
the Typical Performance Characteristics. Maximum load
current capability when VIN1 or VIN2 is less than 3.8V can
be improved if VCC is boot-strapped to 5V as shown in
Figure 7.
Ideal Diode Mode (SEL=1)
Ideal Diode mode operation is available on the LTC3118 for
systems with low ESR sources or where the programmed
operating range of the two inputs can be separated as will
be discussed. In Ideal Diode mode, an internal comparator
monitors the voltage on both VIN1 and VIN2 to determine
which input is higher. The comparator has approximately
800mV of hysteresis to help prevent the part from switching
between the two inputs if the source voltages are equal. The
comparator has an approximate 250µs filter delay to prevent
rapid switching between inputs and erratic operation. When
the LTC3118 switches between inputs, current supplied
from one source is suspended before transitioning to the
other source. Depending on the impedance of each source
and the amount of input current required to support the
load on VOUT, it is possible for the voltage ripple on one
or both inputs to exceed this comparator’s hysteresis.
As an example, if both input sources have 300mΩ of
impedance and 2A of current is being drawn from the
active source, a 600mV step will occur on the inputs
during switchover, approaching the comparator’s 800mV
of typical hysteresis. When the input voltages are equal,
the LTC3118 could toggle between VIN1 and VIN2 operation
at high load currents. For such systems, operation in
Priority mode is recommended, unless the RUN pins can
be programmed such that the minimum operating voltage
of one input is set above the maximum source voltage of
the other input. As with priority mode, the minimum VIN
operating voltages should be set by their RUN pins above
VCC UVLO and higher if needed to support maximum load
current. Low ESR 100µF to 220µF aluminum electrolytic
capacitors close to both input pins help to reduce resonant
ringing during VIN switchover, due to cable inductances
found in some applications and bench evaluation set-ups.
operaTion
LTC3118
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operaTion
Manual VIN Select Circuits
The SEL pin can be used to manually switch between VIN1
and VIN2, if VIN2 is connected to a voltage greater than
VIN1. In this case, both RUN pins must remain asserted
above their 1.22V thresholds. The LTC3118 will run off
VIN1 when SEL is low and the higher VIN2 source when
SEL is high.
For systems requiring manual VIN selection where the
relative voltages are unknown, the RUN pins can be used
with a few precautions. Each RUN pin contains internal
filtering to reduce the chance of unintended turn-on or
turn-off due to noise events. The turn-on delay is typically
50µs in order to manage inductive ringing during supply
plug in. Accordingly, a >100µs overlap time of asserted
RUN1 and RUN2 signals is recommended to prevent a
momentary shutdown of the IC and a subsequent soft-
start cycle.
If this overlap timing cannot be provided by the system
micro-controller, an external circuit similar to Figure 4b
can be added to each RUN pin. With the added circuit, VIN1
and VIN2 can be driven alternately off and on as shown.
The diode provides a faster turn-on path, where the RC
delay to GND is set to ~100µs in order to prevent VOUT
from drooping during switch-over.
Active VIN Indicator
The V1GD and V2GD indicators can be monitored to
determine if VIN1 or VIN2 have sufficient voltage based on
internal UVLO circuits and the RUN pin divider networks
as previously discussed. Some applications may require
an additional indication of which VIN is active and which
is inactive. This indication can be implemented with the
CN1 and CN2 charge-pump pins and an external circuit
similar to Figure 4c. The diode and RC network provide
peak detection and filtering of the active CN pin which is
switching in PWM mode and held high in sleep. The CN
pin for the inactive VIN is held low.
Thermal Considerations
The power switches of the LTC3118 are designed to oper-
ate continuously with currents up to the internal current
limit thresholds. However, when operating at high current
levels, there may be significant heat generated within the
IC. In addition, the VCC regulator can generate a significant
amount of heat when the active VIN is high. This adds to the
total power dissipation of the IC. As described elsewhere
in this data sheet, bootstrapping of VCC for 5V output ap-
plications can essentially eliminate this power dissipation
term and significantly improve efficiency.
Careful consideration must be given to the thermal envi-
ronment of the IC in order to provide a means to remove
heat from the IC and ensure that the LTC3118 is able
to provide its full rated output current. Specifically, the
exposed die attach pad of both the QFN and FE packages
must be soldered to a copper layer on the PCB to maximize
the conduction of heat out of the IC package. This can be
accomplished by utilizing multiple vias from the die attach
pad connection underneath the IC package to other PCB
layer(s) containing large copper planes. A recommended
board layout incorporating these concepts is shown in
Figure 5. Typical temperature rise versus load current
curves using the PCB in Figure 5 are given in the Typical
Performance Characteristics section.
If the IC die temperature exceeds approximately 165°C,
thermal shutdown will be invoked and all switching will
be inhibited. The part will remain disabled until the die
temperature cools by approximately 10°C, at which time
a soft-start is initiated to provide a smooth recovery.
applicaTions inForMaTion
LTC3118
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applicaTions inForMaTion
Figure 6. Inactive VIN Current vs Voltage and Inductor Current (IL)
Active VIN = VOUT = 12V in PWM Mode
INACTIVE INPUT VOLTAGE (V)
0
CURRENT INTO INACTIVE INPUT (µA)
60
18
3118 F06
20
–20 3156 912
100
40
80
0
IL = 0A
IL = 0.5A
IL = 1A
IL = 2A
Inactive VIN Leakage Currents
The inactive input (VIN1 or VIN2) consumes a small amount
of bias current and will exhibit some amount of leakage
current, through the disabled switches, depending on the
temperature of the die and the average DC voltage between
the inactive VIN and SW1 (stand-off voltage). Please refer to
the Die Temperature Rise and N-Channel MOSFET leakage
curves in the Typical Performance Characteristics of the
data sheet. The stand-off voltage can be positive or negative
depending on the VIN1 and VIN2 voltages and varies with
SW1 duty cycle. Figure 6 shows typical currents into the
inactive input as a function of its voltage at various levels
of inductor current as the LTC3118 operates in PWM mode
from an active 12V input and 12V output. Higher inductor
currents generally translate to higher leakage currents due
to power dissipation, resulting in a die temperature rise.
Referring to the curves in Figure 6, leakage currents are
generally supplied from the inactive source into its re-
spective VIN pin above a few volts. At lower voltages, it is
possible to get reverse current back-fed into the source,
causing a depleted battery or unplugged input to slowly
charge. In some cases, a dummy load resistor across the
inactive input may be needed to prevent that input from
rising above its UVLO causing a momentary turn-on. A
good thermal design will help to reduce unwanted leakage
currents into or out of the inactive input, especially at high
switch currents where die temperatures increase. A tight
board layout near the VIN1/CM1 and VIN2/CM2 pins to
ground is advised to reduce leakage that may occur due
to SW1 edge rates and parasitic inductances in the traces.
LTC3118
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applicaTions inForMaTion
Figure 7. Bootstrapping VCC
A standard application circuit for the LTC3118 is shown on
the front page of this data sheet. The appropriate selection
of external components is dependent upon the required
performance of the IC in each particular application, given
considerations and trade-offs such as PCB area, input
and output voltage range, output voltage ripple, required
efficiency, thermal considerations and cost. This section
of the data sheet provides some basic guidelines and con-
siderations to aid in the selection of external components
and the design of the applications circuit.
VCC Capacitor Selection
VCC is generated by a low dropout linear regulator from
either VIN1 or VIN2, whichever is selected. Both VCC regula-
tors have been designed for stable operation with a wide
range of output capacitors. For most applications, a low
ESR capacitor of 4.7µF should be used. The capacitor
should be located as close to VCC as possible and con-
nected to ground through the shortest trace possible. If
the connecting trace cannot be made short, an additional
0.1µF bypass capacitor should be connected between
VCC and ground, as close to the package pins as possible.
Bootstrapping the VCC Regulator with 5V VOUT or
External Supply
The high and low side gate drivers are powered by VCC,
which is generated from the selected VIN through an
internal linear regulator. In some applications, especially
at high input voltages, the power dissipation in the linear
regulator can become a significant contributor to thermal
heating of the IC. The Typical Performance Characteristics
section of this data sheet provides data on VCC current in
VOUT
4.7µF
3118 F07
VOUT
LTC3118
VCC
PWM operation, which is supplied by VIN. A significant
performance advantage can be attained in applications
where VOUT is programmed to 5V, if VCC is powered by
VOUT rather than the selected VIN. This can be done by
connecting a Schottky diode from VOUT to VCC, as shown
in Figure 7. With the bootstrap diode installed, the gate
driver currents are supplied by the buck-boost converter
at high efficiency rather than through the less efficient
internal linear regulator. The internal linear regulator
contains reverse blocking circuitry that allows VCC to be
driven slightly above their nominal regulation level with
only a slight amount of reverse current. Please note that the
bootstrapping supply (either VOUT or a separate regulator)
must limit VCC to less than 6V.
BST, Charge Pump and CM Capacitor Selection
Small ceramic capacitors are needed to provide a suf-
ficient amount of charge to the high side switches. As
shown in the applications circuits and the front page of
this data sheet, small capacitors are required from BST1
to SW1, BST2 to SW2, CN1 to CP1, CN2 to CP2, CM1 to
GND and CM2 to GND. Recommended initial values for
the BST to SW capacitors are 0.1µF with > 5V rating, CN
to CP capacitors are 10nF with > 20V rating, and CM to
GND capacitors are 47nF with > 20V rating.
Inductor Selection
The choice of inductor used in LTC3118 applications
influences the maximum deliverable output current, the
converter bandwidth, the magnitude of the inductor current
ripple and the overall converter efficiency. The inductor
must have a low DC series resistance and high output
LTC3118
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current capability or efficiency will be compromised. Larger
inductor values reduce inductor current ripple, but will
not increase output current capability as is the case with
peak current mode control, as described in the Inductor
Current Sense and Maximum Output Current section of
this data sheet. Larger value inductors also tend to have
a higher DC series resistance for a given case size, which
will have a negative impact on efficiency. Larger values
of inductance also lower the right half plane (RHP) zero
frequency when operating in boost mode, requiring the
converter bandwidth to be set lower in frequency, thereby
slowing the converter’s load transient response. Most
LTC3118 application circuits deliver the best performance
with an inductor value between 3.3µH and 10µH. In gen-
eral, a 3.3µH inductor is recommended for VOUT up to 5V,
6.8µH for VOUT = 12V and 10µH for VOUT = 18V. Inductor
values for other output voltages can be scaled accordingly.
Regardless of inductor value, the saturation current rat-
ing should be such that it is greater than the worst-case
average inductor current plus half of the ripple cur-
rent. The peak-to-peak inductor current ripple for each
operational mode can be calculated from the following
formula, where f is the switching frequency (1.2MHz),
L is the inductance in µH, and tLOW is the switch pin
minimum low time in µs. The switch pin minimum low
time is typically 0.1µs.
∆I
L(P-P)BUCK
=
VOUT
L
VIN −VOUT
VIN
1
f−tLOW
Amps
∆IL(P-P)BOOST =
VIN
L
VOUT −VIN
VOUT
1
f−tLOW
Amps
It should be noted that the worst-case inductor peak-to-
peak inductor ripple current occurs when the duty cycle
in buck mode is maximum (highest VIN), and in boost
mode when the duty cycle is 50% (VOUT = 2 • VIN). As an
example, if VIN (minimum) = 2.7V and VIN (maximum) =
18V, VOUT = 5V and L = 3.3µH, the peak-to-peak inductor
ripples at the voltage extremes (18V VIN for buck and 2.7V
VIN for boost) are:
Buck = 600mA peak-to-peak
Boost = 200mA peak-to-peak
One-half of this inductor ripple current must be added to
the highest expected average inductor current in order to
select the proper saturation current rating for the inductor
(about 4A).
In addition to its influence on power conversion efficiency,
the inductor DC resistance can also impact the maximum
output current capability of the buck-boost converter par-
ticularly at low input voltages. In buck mode, the output
current of the buck-boost converter is primarily limited
by the inductor current reaching the average current limit
threshold defined by VC. However, in boost mode, espe-
cially at large step-up ratios, the output current capability
can also be limited by the total resistive losses in the power
stage. These losses include switch resistances, inductor
DC resistance and PCB trace resistance. Avoid inductors
with a high DC resistance (DCR), as they can degrade the
maximum output current capability from what is shown
in the Typical Performance Characteristics section. As a
guideline, the inductor DCR should be significantly less
than the typical power switch resistance of 100mΩ. The
only exceptions are applications that have a maximum
output current much less than what the LTC3118 is ca-
pable of delivering.
Different inductor core materials and styles have an impact
on the size and price of an inductor at any given current
rating. Shielded construction is generally preferred as it
minimizes the chances of interference with other circuitry.
The choice of inductor style depends upon the price, sizing
and EMI requirements of a particular application. Table 1
provides a small sampling of inductors that are well suited
to many LTC3118 applications.
Output Capacitor Selection
A low effective series resistance (ESR) output capacitor
should be connected at the output of the buck-boost con-
verter in order to minimize output voltage ripple. Multilayer
ceramic capacitors are an excellent option as they have low
ESR and are available in small footprints. The capacitor
applicaTions inForMaTion
LTC3118
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Table 1. Representative Buck-Boost Surface Mount Inductors
PART NUMBER
VALUE
(µH)
DCR
(mΩ)
MAX DC
CURRENT (A)
SIZE
(W × L × H) mm MANUFACTURER
MSS7341T
XAL7030
3.3
6.8
18
42
3.7
4.4
7 × 7 × 4
8 × 8 × 3
Coilcraft
www.coilcraft.com
SD8328 3.3
4.7
14
19
4.0
3.6
8 × 8 × 3
8 × 8 × 3
Coiltronics
www.coiltronics.com
LQH88PN
LQH88PN
LQH88PN
3.3
4.7
6.8
16
22
28
5
4.2
3.8
8 × 8 × 4
8 × 8 × 4
8 × 8 × 4
Murata
www.murata.com
CDRH8D28NP 3.3
4.7
18
25
4
3.4
8 × 8 × 3
8 × 8 × 3
Sumida
www.sumida.com
VLP840 3.3
6.8
15
24
5.2
3.6
8 × 8 × 4
8 × 8 × 4
TDK Electronics
www.tdk.co.jp
FDSD0603 3.3
6.8
23
51
5.6
3.7
7 × 7 × 3
7 × 7 × 3
Toko
www.toko.co.jp
7447789003
7447789004
7447779006
3.3
4.7
6.8
30
35
35
4.2
3.9
3.3
7 × 7 × 3
7 × 7 × 3
7 × 7 × 4.5
Würth Elektronik
www.we-online.com
applicaTions inForMaTion
value should be chosen large enough to reduce the output
voltage ripple to acceptable levels. Neglecting the capaci-
tor’s ESR and ESL, the peak-to-peak output voltage ripple
can be calculated by the following formula, where f is the
frequency in MHz (1.2MHz), COUT is the capacitance in
µF, tLOW is the switch pin minimum low time in µs (0.1µs)
and ILOAD is the output current in Amps.
∆VP-P(BUCK) =
I
LOAD
t
LOW
COUT
Volts
∆VP-P(BOOST) =
ILOAD
fC
OUT
VOUT −VIN +tLOW fVIN
V
OUT
Volts
Examining the previous equations reveals that the output
voltage ripple increases with load current and is gener-
ally higher in boost mode than in buck mode. Note that
these equations only take into account the voltage ripple
that occurs from the inductor current to the output being
discontinuous. They provide a good approximation to the
ripple at any significant load current but underestimate the
output voltage ripple at very light loads where the output
voltage ripple is dominated by the inductor current ripple.
In addition to the output voltage ripple generated across
the output capacitance, there is also output voltage ripple
produced across the internal resistance of the output
capacitor. The ESR-generated output voltage ripple is pro-
portional to the series resistance of the output capacitor,
and is given by the following expressions where RESR is
the series resistance of the output capacitor and all other
terms as previously defined.
∆VP-P(BUCK) =
I
LOAD
R
ESR
1−tLOW f≅ILOAD RESRVolts
∆VP-P(BOOST) =
ILOAD RESR VOUT
VIN 1−tLOW f
( )
≅ILOAD RESR
VOUT
VIN
Volts
In most LTC3118 applications, an output capacitor between
47µF and 100µF will work well.
Input Capacitor Selection
The VIN1 or VIN2 pin carries the full inductor current and
provides power to internal control circuits in the IC. To
minimize input voltage ripple and ensure proper operation
of the IC, a low ESR bypass capacitor with a value of at
least 10µF should be located as close to the pin as possible.
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The traces connecting this capacitor to VIN1 or VIN2 and
the ground plane should be made as short as possible.
When powered through long leads or from a high ESR
power source, a larger value bulk input capacitor may be
required. In such applications, a 47µF to 100µF electrolytic
capacitor in parallel with a 1µF ceramic capacitor gener-
ally yields a high performance, low cost solution. In ideal
diode mode, the voltage ripple on each input must be kept
below the VIN comparator’s 800mV hysteresis to prevent
repetitive switching between VIN1 and VIN2 operation when
the input voltages are similar.
Recommended Input and Output Capacitors
The capacitors used to filter the input and output of the
LTC3118 must have low ESR and must be rated to handle
the large AC currents generated by the switching convert-
ers. This is important to maintain proper functioning of
the IC and to reduce output voltage ripple. There are many
capacitor types that are well suited to these applications
including multilayer ceramic, low ESR tantalum, OS-CON
and POSCAP technologies. In addition, there are certain
types of electrolytic capacitors, such as solid aluminum
organic polymer capacitors, that are designed for low
ESR and high AC currents and these are also well suited
to some LTC3118 applications. Table 2 provides a partial
listing of appropriate capacitors to use. The choice of
capacitor technology is primarily dictated by a trade-off
between size, leakage current and cost. In backup power
applications, the input or output capacitor might be a super
or ultra capacitor with a capacitance value measuring in
the Farad range. The selection criteria in these applications
are generally similar except that voltage ripple is generally
not a concern. Some capacitors exhibit a high DC leak-
age current which may preclude their consideration for
applications that require a very low quiescent current in
Burst Mode operation.
Table 2. Representative Bypass and Output Capacitors
PART NUMBER
VALUE
(µF)
VOLTAGE
(V)
CAPACITOR TYPE
ESR (mΩ)
SIZE
(W × L × H) mm MANUFACTURER
12103D226MAT2A 22 25 X5R Ceramic 3.2 × 2.5 × 2.8 AVX
www. avx.com
C2220X226K3RACTU
A700D226M016ATE030
22
22
25
16
X7R Ceramic,
Aluminum
Polymer 30mΩ
5.7 × 5 × 2.4
7.3 × 4.3 × 2.8
Kemet
www.kemet.com
GRM32ER71E226KE15L 22 25 X7R Ceramic 3.2 × 2.5 × 2.5 Murata
www.murata.com
PLV 1E121MDL1 82 25 Aluminum
Polymer, 25mΩ
8 × 8 × 3 Nichicon
www.nichicon.com
ECJ-4YB1E226M 22 25 X5R Ceramic 3.2 × 2.5 × 2.5 Panasonic
www.panasonic.com
25TQC22MV
16TQC100M
25SVPF47M
22
100
47
25
16
25
POSCAP, 50mΩ
POSCAP, 45mΩ
OS-CON, 30mΩ
7.3 × 4.3 × 1.9
7.3 × 4.3 × 3.1
6.6 × 6.6 × 5.9
Sanyo
www.sanyo.com
TMK325BJ226MM-T 22 25 X5R Ceramic 3.2 × 2.5 × 2.5 Taiyo Yuden
www.t-yuden.com
CKG57NX5R1E476M 47 25 X5R Ceramic 6.5 × 5.5 × 5.5 TDK
www.tdk.com
applicaTions inForMaTion
LTC3118
29
3118fa
For more information www.linear.com/LTC3118
Ceramic capacitors are often utilized in switching con-
verter applications due to their small size, low ESR and
low leakage currents. However, many ceramic capacitors
intended for power applications experience a significant
loss in capacitance from their rated value as the DC bias
voltage on the capacitor increases. It is not uncommon
for a small surface mount capacitor to lose more than
50% of its rated capacitance when operated near its
maximum rated voltage. This effect is generally reduced
as the case size is increased for the same nominal value
capacitor. As a result, it is often necessary to use a larger
value capacitance or a higher voltage rated capacitor than
would ordinarily be required to actually realize the intended
capacitance at the operating voltage of the application. X5R
and X7R dielectric types are recommended as they exhibit
the best performance over the wide operating range and
temperature of the LTC3118. To verify that the intended
capacitance is achieved in the application circuit, be sure
to consult the capacitor vendor’s curve of capacitance
versus DC bias voltage.
Compensation of the Buck-Boost Converter
The LTC3118 utilizes an average current architecture to
regulate the output voltage. Average current mode control
has two loops that require frequency compensation, the
inner average current loop and the outer voltage loop. The
compensation for the inner average current loop is fixed
within the LTC3118 to simplify the loop design and provide
the highest possible bandwidth over a wide operating range.
The outer voltage loop does require external compensation
components, allowing the overall loop characteristics to
be customized for the application.
The average current mode control used in the LTC3118 can
be conceptualized as a voltage-controlled current source
(VCCS), driving the output load formed primarily by RLOAD
and COUT, as shown in Figure 8.
The voltage error amplifier output (VC), provides a com-
mand input to the VCCS. The full-scale range of VC is 0.6V
(200mV to 800mV). With a full-scale command on VC,
Figure 8. Simplified Representation of Average Current Mode Control Loop
applicaTions inForMaTion
3118 F08
1V
800mV
gm = 3.6A/0.6V
+
–
FB
VOLTAGE
ERROR
AMP
VOLTAGE
CONTROLLED
CURRENT
SOURCE
VC
GND
RZ
R1
400k
R2
100k
RCOESR
0.01Ω
RLOAD
5Ω
CP1
COUT
47µF
VOUT = 5V
CP2
–
+
gm
LTC3118
30
3118fa
For more information www.linear.com/LTC3118
the LTC3118 buck-boost converter will generate an aver-
age 3.6A of inductor current (typical) from the converter
making the transconductance gain 6A/V. As with peak
current mode control, the inner average current control
loop effectively turns the inductor into a current source over
the frequency range of interest, resulting in a frequency
response from the power stage that exhibits a single pole
(–20dB / decade) roll-off. The output capacitor (COUT) and
load resistance (RLOAD) form a dominant low frequency
pole, where the effective series resistance of the output
capacitor and its capacitance form a zero, usually at a high
enough frequency to be ignored.
A potentially troublesome right half plane zero (RHPZ)
is also encountered if the converter is operated in boost
mode. The RHPZ causes an increase in gain, like a zero, but
a decrease in phase, like a pole. This can ultimately limit
the maximum converter bandwidth that can be achieved
with the LTC3118. The RHPZ is not present when operat-
ing in buck mode.
The overall open loop gain at DC is the product of the
following terms:
Voltage Error Amp Gain:
gm•REA =80µS •5MΩ =
400V
V
(fixed)
Voltage Divider Gain:
V
FB
V
OUT
=
1V
V
OUT
Current Loop Transconductance:
gc=
6A
V
(fixed
)
Load Resistance:
RLOAD =
V
OUT
I
LOAD
The frequency dependent terms that affect the loop gain
include:
Output Load Pole (P1):
1
2π•R
LOAD
•C
OUT
(application dependent)
Right Half Plane Zero (RHPZ):
VIN 2•RL
V
OUT
2•2π•L(application dependent)
Voltage Error Amplifier Compensation: 2 poles and 1 zero
(application dependent)
The voltage amplifier’s frequency response is designed
to optimize the response for the overall loop. Measure-
ment of the power stage gain over line, load, component
variation and frequency is strongly recommended prior
to loop design. The design parameters for compensation
design will focus on the series resistor and capacitors
connected from VC to ground (RZ, CP1 and CP2). Being a
buck-boost converter, the target loop crossover frequency
for the compensation design will be dictated by the high-
est boost ratio and load current that is expected, as this
will result in the lowest RHPZ frequency. The general goal
is to set the crossover frequency and provide sufficient
phase boost using the external compensation network.
applicaTions inForMaTion
LTC3118
31
3118fa
For more information www.linear.com/LTC3118
Compensation Example
This section will demonstrate how to derive and select
the compensation components for a typical LTC3118 ap-
plication. Designing compensation for other applications
is a matter of substituting different values in the equations
provided based on the power stage bode plots. Since the
compensation design procedure uses a simplified model
of the LTC3118, the results from the following compensa-
tion design should always be verified with time domain
step load response tests to validate the effectiveness of
the compensation design. It is assumed that the value
and type of output capacitor will be selected based on the
guidelines provided elsewhere in this data sheet. Particular
attention needs to be paid to the voltage bias effect on
ceramic capacitors typically used for output bypassing.
Similarly, it is assumed that the inductor value and current
rating has been selected as well, based on the application
requirements.
Example Application Details:
VIN = 3V to 15V
VOUT = 5V
Maximum IOUT (boost mode) = 1A, RLOAD = 5Ω
Maximum IOUT (buck mode) = 1A, RLOAD = 5Ω
(could supply 2A if VIN > 5V)
COUT = 100µF but use 66µF in calculations to account
for DC voltage bias effects.
L = 3.3µH
Since this application includes boost mode operation, the
first step is to calculate the worst-case RHPZ frequency
as this will dictate the maximum loop bandwidth for the
converter.
RHPZ(f) =VIN
2
•RLOAD
VOUT2•2π•L=
3V2•5Ω
5V2•2π•3.3µH =87kHz
In order to account for internal IC component variations,
it is a good practice to set the converter bandwidth, or
crossover frequency, at least 4 to 5 times lower than the
RHPZ frequency, to avoid excessive phase loss from the
RHPZ when operating in boost mode. In some instances
such as higher output voltage applications, an even greater
separation between the loop crossover frequency and
the RHPZ frequency may be necessary. In this example
design, we’ll plan to achieve a loop bandwidth (fCC) of
20kHz, well below the RHPZ frequency. The 5V, 1A de-
sign example bode plots are shown in Figure 9. The top
curve set shows the power stage gain (and phase) in buck
(> 5VIN) and 3VIN boost mode operation. The DC gain in
buck mode is simply the current loop transconductance
(6A/V) multiplied by the load resistance (5Ω). The VOUT
resistor divider will be accounted for in voltage amplifier
network.
Buck DC Gain:
20log 6A/V•5Ω
( )
=29dB
In boost mode the gain is reduced by VIN /VOUT.
Boost DC Gain at 3VIN:
20log
6A/V •3V •5Ω
5V
=25dB
The output load pole will move depending on the output
load resistance. The power stage poles at full load are
shown in the top set of curves in Figure 9.
Output Load Pole:
1
2π•RLOAD •COUT
=
1
2π•5Ω•66µF =480Hz
applicaTions inForMaTion
LTC3118
32
3118fa
For more information www.linear.com/LTC3118
These values were verified in the top set of curves in
Figure 9. The resulting power stage crossover frequency
is around 40kHz in buck mode (VIN > 5V), 20kHz in boost
mode at 3.5VIN.
The uncompensated power stage crossover frequency
is higher than the goal of 20kHz. More importantly, the
uncompensated power stage DC gain is low, especially in
boost mode. A pole-zero-pole network will now be added
to the voltage amplifier to increase the DC gain, reduce
the crossover frequency and reduce the overall gain at
high frequencies:
VA Pole 1 =
1
2πREA CP1
Figure 9. Bode Plot Showing Power Stage Gain (Top), VA Loop (Center), and Total Loop Gain vs Frequency
applicaTions inForMaTion
3118 F08
FREQUENCY
VOLTAGE LOOP GAIN (dB)
10Hz 10kHz 100kHz 1MHz100Hz 1kHz
FREQUENCY
–40
TOTAL LOOP GAIN (dB)
–20
10
0
10Hz 10kHz 100kHz 1MHz
–70
–60
100Hz 1kHz
30
20
–30
–10
60
50
70
40
–50
FREQUENCY
–30
POWER STAGE GAIN (dB)
PHASE (DEG)
–18
–6
10Hz 10kHz 100kHz 1MHz100Hz 1kHz
6
0
–24
–12
24
18
30
12
–36
–180
–60
0
–120
60
120
PHASE (DEG)
–120
–100
–60
–40
–80
–20
0
PHASE MARGIN (DEG)
–180
–60
–120
180
120
210
0
60
–30
–18
–6
6
0
–24
–12
24
18
36
30
12
–36
–VC/ VOUTA
VOUT / VOUTA
VOUT / VC
BOOST MODE BUCK MODE
BUCK MODE
GAIN
PHASE
GAIN
PHASE
GAIN
PHASE MARGIN
BOOST MODE
LTC3118
33
3118fa
For more information www.linear.com/LTC3118
this pole is close to DC, REA = Voltage Error Amp output
resistance, which is approximately 5MΩ. This pole is
mentioned for completeness, but has no effect on the
overall loop design:
VA Zero 1 =
1
2πR
Z
C
P1
this zero is placed below the crossover frequency to flatten
the VA gain at the crossover to improve phase margin:
VA Pole 2 =
1
2πR
Z
C
P2
This pole is placed above the crossover frequency to reduce
the gain to suppress noise and mitigate any RHPZ effects.
Referring to the power stage gain curves in Figure 9, the
loop gain needs to be reduced by 4dB to achieve a total
loop crossover frequency of 20kHz. Assuming Zero 1 is
placed well below the crossover frequency and Pole 2 is
placed well above the crossover frequency, the voltage
amplifiers gain at crossover is given by:
VA gain at crossover:
20log VFB •gm•RZ
VOUT
=
20log 1V •80µA/V •40k
5V
= − 4dB
Where gm is the VA transconductance, VFB/ VOUT is the
feedback divider gain, and RZ is the external zero resistor.
As shown, a 40kΩ value for RZ will provide –4db of gain
at crossover. With RZ selected, CP1’s value is determined
by setting the Zero 1 frequency at one-tenth the crossover
frequency, or 2kHz.
CP1 =
1
2π•RZ•fZERO1
=
1
2π•40kΩ•2kHz
≅1.8nF
Finally, the high frequency Pole 2 is set at 10 times the
crossover frequency to provide a high frequency pole at
200kHz.
CP2 =
1
2π•RZ•fPOLE2
=
1
2π•40kΩ•200kHz
≅22pF
The second set of curves in Figure 9 show the resulting VA
response to the selected values. Notice that the separation
between Zero 1 and Pole 2 provides 60 degrees phase
bump near the crossover frequency.
Combining the power stage and VA frequency responses,
the measured overall loop gains are shown in the bottom set
of curves of Figure 9. As shown, the crossover frequency
was reduced to 20kHz in buck mode, 10kHz in boost. The
phase margin at crossover is around 70 degrees. The
VA design provided the additional benefits of high gain
(>50dB) at DC and gain attenuation above the crossover
frequency to prevent RHPZ issues.
applicaTions inForMaTion
LTC3118
34
3118fa
For more information www.linear.com/LTC3118
Typical applicaTions
System Power (Priority) or 3-Cell Li-Ion to 5V VOUT Regulator with Automatic Burst Mode Operation
Efficiency vs Load Current: VIN1 = 5V,
VIN2 = 10.8V, VOUT = 5V
100mA to 1A Load Step, VIN1 = 5V,
VOUT = 5V, Auto Burst Mode
3.3µH
0.1µF0.1µF
232k
+
100k
402k
5V UP TO 1.5A,
VIN > 4.5V
100k
40.2k
47nF
47nF
4V TO 5.5V
10nF
22µF
100µF
PGND
POWER GOOD
INDICATORS
22µF
523k
10nF
22pF
SYSTEM
POWER
7.5V TO 12.6V
Li-Ion
+
+
+
4.7µF BAT-54
SCHOTTKY DIODE
BST1 BST2
VIN1 SW1 SW2
3118 TA02a
CM1
PGND
CM2
RUN1
CP1
CP2
VOUT
VC
GND
V1GD
FB
V2GD
PGD
CN2
CN1 VCC
SEL
MODE
VIN2
PGND
RUN2
LTC3118
100k
1.8nF
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
40
60
10
3118 TA02b
20
00.001 0.01 0.1 1
100
30
50
10
70
80
90
VIN1
VIN2
PWM
BURST
100µs/DIV 3118 TA02c
5VOUT
TRANSIENT
200mV/DIV
INDUCTOR
CURRENT
1A/DIV
LOAD
CURRENT
1A/DIV
VC
200mV/DIV
LTC3118
35
3118fa
For more information www.linear.com/LTC3118
Typical applicaTions
12V Wall Adapter (When Present) or 2-Cell Li-Ion to 12V VOUT Regulator with Automatic Burst Mode Operation
Efficiency vs Load Current: VIN1 = 7V,
VIN2 = 12V, VOUT = 12V
12VIN2 to 6VIN1 SEL Pin Switchover
with VOUT = 12V and 800mA Load
402k
100k
1100k
12V AT 800mA
100k
60.4k
47nF
47nF
6V TO 8.2V
10nF
22µF
100µF
PGND
POWER GOOD
INDICATORS
100µF
750k
10nF
22pF
10V TO 14V
Li-Ion
+
+
4.7µF
BST1 BST2
VIN1 SW1 SW2
3118 TA03a
CM1
PGND
CM2
RUN1
CP1
CP2
VOUT
VC
GND
V1GD
FB
V2GD
PGD
CN2
CN1 VCC
SEL
MODE
VIN2
PGND
RUN2
LTC3118
100k
1.2nF
+
12V WALL
ADAPTER
6.8µH
0.1µF0.1µF
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
40
60
10
3118 TA03b
20
00.001 0.01 0.1 1
100
30
50
10
70
80
90
VIN1
VIN2
PWM
BURST
500µs/DIV 3118 TA03c
12VOUT
TRANSIENT
500mV/DIV
INDUCTOR
CURRENT
1A/DIV
SW1
10V/DIV
SEL
1A 2A
12VIN2 Inductive Cable Insertion
with VOUT = 12V and 800mA Load
100µs/DIV 3118 TA03d
12VOUT
TRANSIENT
500mV/DIV
INDUCTOR
CURRENT
2A/DIV
VIN2
5V/DIV
VIN1
5V/DIV
CABLE
INSERTION
VOUT = 12V
SWITCHOVER TO VIN2
VIN2 = 12V
VIN1 = 6V
LTC3118
36
3118fa
For more information www.linear.com/LTC3118
Efficiency vs Load Current: VIN1 = 5V,
VIN2 = 12V, VOUT = 3.3V
100mA to 1A Load Step, VIN = 12V,
VOUT = 3.3V, Auto Burst Mode
Typical applicaTions
Dual Battery System to 3.3V VOUT, Runs from Lead Acid (Priority) When Present
Automatic Burst Mode Operation
232k
3.3V UP TO 2.5A, VIN > 4.5V
100k
18.2k
47nF
47nF
3V TO 16.5V
10nF
22µF
100µF
PGND
POWER GOOD
INDICATORS
22µF
301k
10nF
47pF
10.5V TO 14.5V
STACK OF 3-10 NiMH
OR ALKALINE BATTERIES
4.7µF
BST1 BST2
VIN1 SW1 SW2
3118 TA04a
CM1
PGND
CM2
RUN1
CP1
CP2
VOUT
VC
GND
V1GD
FB
V2GD
PGD
CN2
CN1 VCC
SEL
MODE
VIN2
PGND
RUN2
LTC3118
768k
100k
200k
3.9nF
+
LEAD ACID
BATTERY
–
3.3µH
0.1µF0.1µF
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
40
60
10
3118 TA04b
20
00.001 0.01 0.1 1
100
30
50
10
70
80
90
PWM
BURST
VIN1
VIN2
100µs/DIV 3118 TA04c
3.3VOUT
TRANSIENT
200mV/DIV
INDUCTOR
CURRENT
1A/DIV
LOAD CURRENT
1A/DIV
VC
200mV/DIV
LTC3118
37
3118fa
For more information www.linear.com/LTC3118
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
23 24
1
2
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05 R = 0.115
TYP
R = 0.05 TYP PIN 1 NOTCH
R = 0.20 OR C = 0.35
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD24) QFN 0506 REV A
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.65 ±0.05
2.00 REF
3.00 REF
4.10 ±0.05
5.50 ±0.05
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
2.65 ±0.10
2.00 REF
3.00 REF
3.65 ±0.10
3.65 ±0.05
UFD Package
24-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1696 Rev A)
LTC3118
38
3118fa
For more information www.linear.com/LTC3118
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE28 (EB) TSSOP REV K 0913
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10 11 12 13 14
192022 21 151618 17
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
2.74
(.108)
28 27 26 2524 23
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
4.75
(.187)
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation EB
LTC3118
39
3118fa
For more information www.linear.com/LTC3118
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 09/15 Text clarification
Pin name corrections for SW1, SW2, BST1 and BST2
1
34, 35
LTC3118
40
3118fa
For more information www.linear.com/LTC3118
LINEAR TECHNOLOGY CORPORATION 2015
LT 0915 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3118
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC3111 1.5A (IOUT), 15V Synchronous Buck-Boost DC/DC Converter VIN = 2.5V to 15V, VOUT = 2.5V to 15V, IQ = 49µA, ISD < 1µA,
DFN and MSOP Packages
LTC3112 2.5A (IOUT), 15V Synchronous Buck-Boost DC/DC Converter VIN = 2.7V to 15V, VOUT = 2.5V to 14V, IQ = 40μA, ISD < 1μA,
DFN and TSSOP Packages
LTC3113 3A (IOUT), 5V Synchronous Buck-Boost DC/DC Converter VIN = 1.8V to 5.5V, VOUT = 1.8V to 5.25V, IQ = 30μA, ISD < 1μA,
DFN and TSSOP Packages
LTC3114-1 1A (IOUT), 40V Synchronous Buck-Boost DC/DC Converter VIN = 2.2V to 40V, VOUT = 2.7V to 15V, IQ = 30µA, ISD < 3µA,
DFN and TSSOP Packages
LTC3115-1 2A (IOUT), 40V Synchronous Buck-Boost DC/DC Converter VIN = 2.7V to 40V, VOUT = 2.7V to 40V, IQ = 30μA, ISD < 3μA,
DFN and TSSOP Packages
LTC3122 2.5A ISW, 3MHz, Synchronous Step-Up DC/DC Converter with
Output Disconnect, Burst Mode Operation, Up to 95% Efficiency
Operating Range VIN = 1.8V to 5.5V (500mV After Start-Up), VOUT = Up
to 15V, IQ = 25μA, ISD <1µA, 3mm × 4mm DFN and MSOP Packages
LTC3124 5A ISW, 3MHz, 2-Phase Synchronous Step-Up DC/DC
Converter, Output Disconnect, Burst Mode Operation,
Up to 95% Efficiency
Operating Range VIN = 1.8V to 5.5V (500mV After Start-Up), VOUT Up
to 15V, IQ = 25µA, ISD < 1µA, 3mm × 5mm DFN and TSSOP Packages
LTC3129 200mA (IOUT), 15V Synchronous Buck-Boost DC/DC Converter VIN = 2.42V to 15V, VOUT = 2.5V to 14V, IQ = 1.3μA, ISD = 10nA,
QFN and MSOP Packages
LTC4412 28V Low Loss PowerPath Controller in ThinSOT™ Operating Range 3V to 36V, IQ = 11µA, 6-Lead ThinSOT Package
LTC4417 Prioritized PowerPath Controller VIN = 2.5V to 36V, –42V Reverse Protection, IQ = 28µA, ISD < 1µA,
QFN and SSOP Packages
12V VIN to 5V VOUT Converter with Capacitor Backup
Runs from VIN1 (Priority) in Normal Mode, VIN2 During Backup Event
10mF, 18V Back-Up Capacitor Supports
200mA Load for >1 Second
200ms/DIV 3118 TA05b
VIN2
10V/DIV
VIN1
10V/DIV
VOUT
5V/DIV
INDUCTOR
CURRENT
1A/DIV
768k
+
100k
402k
100k
40.2k
40.2k
47nF
47nF
10.5V TO 14.5V
10nF
22µF
47µF
5V
PGND
BAT-54
SCHOTTKY DIODE
POWER GOOD
INDICATORS
VCC BACK FED
FROM VOUT
FOR LOW VIN
OPERATION
22µF
2M
10nF
10mF
CAPACITOR
BACKUP
22pF
LEAD ACID
BATTERY OR 12V
SYSTEM POWER
18V MAX, RUNS
DOWN TO 2.2V
+
4.7µF
BST1 BST2
VIN1
SW1 SW2
3118 TA05a
CM1
PGND
CM2
RUN1
CP1
CP2
VOUT
VC
GND
V1GD
FB
V2GD
PGD
CN2
CN1 VCC
SEL
MODE
VIN2
PGND
RUN2
LTC3118
1.8nF
3.3µH
0.1µF0.1µF
40.2k
CAN’T RUN FROM VIN2 UNTIL VOUT STARTS UP
