FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async 3.3 Volt Asynchronous x9 First-In/First-Out Queue Memory Configuration Device 8,192 x 9 FQV05 4,096 x 9 FQV04 2,048 x 9 FQV03 1,024 x 9 FQV02 512 x 9 FQV01 Key Features: * * * * * * * * * * * Industry leading First-In/First-Out Queues (up to 50MHz) Independent Write and Read cycle time Asynchronous and simultaneous read and write 3.3V power supply Fully expandable in both word depth and width Retransmit capability Full, Empty, and Half Full flag indicators Available packages: 32-pin Plastic Lead Chip Carrier (PLCC) (0C to 70C) Commercial operating temperature available for access time of 15ns and above (-40C to 85C) Industrial operating temperature available for access time of 15ns and above Pin-to-pin compatible with IDT (72V01, 72V02, 72V03, 72V04, 72V05) Product Description: HBA's FlexQTM Async FIFO offers industry leading 0.25um process technology and memory densities from 512 x 9 to 8,192 x 9. System designer has full flexibility of implementing deeper and wider queues using the depth and width expansion features. Full and Empty indicators allow easy handshaking between transmitters and receivers. Independent Write and Read controls provide rate-matching capability. System designer can re-read data from the starting ________ __________ position by using Retransmit (RET). Retransmit allows reset of the read pointer to its initial position. Half Full flag (HALF) is available in the single device mode and width expansion mode, but not in depth expansion mode. These FlexQTM Async devices have low power consumption, hence minimizing system power requirements. In addition, industry standard 32 - pin PLCC are offered to save system board space. These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test equipment, medical systems, network switching, etc. 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 1 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async READ ( R ) WRITE (W) DATA IN (D8 - 0) FULL ( FULL ) DATA OUT (Q 8 - 0) FQV01 FQV02 FQV03 FQV04 FQV05 EMPTY ( EMPTY ) RETRANSMIT ( RET ) RESET ( RST ) EXPANSION OUT / HALF ( XO/ HALF ) FIRST LOAD ( FIRST ) EXPANSION IN ( XI ) Figure 1. Device Configuration Signal Flow Diagram Block Diagram of Single Aynchronous Queue 8,192 x 9 / 4,096 x 9 / 2,048 x 9 / 1,024 x 9 / 512 x 9 W Write Control Logic RST RET Reset Logic Write Pointer D 8-0 SRAM Input Register Output Register Output Buffer Q 8-0 Read Pointer FIRST XI EMPTY Expansion Logic XO Read Control Logic Flag Logic FULL HALF R Figure 2. Device Architecture 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 2 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 D8 W NC Vcc D4 D5 Index D3 FlexQTM Async 4 3 2 1 32 31 30 29 D6 D1 6 28 D7 D0 7 27 NC XI 8 26 FIRST / RET FULL 9 25 RST Q0 10 24 EMPTY Q1 11 23 XO / HALF 12 22 Q7 21 Q6 17 18 19 20 Q5 16 Q4 15 R 13 14 Q3 Q2 NC NC GND 5 Q8 D2 PLCC - 32 (Drw No: J-01A; Order code: J) Top View Figure 3. Device Pin-Out 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 3 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async Pin # Symbol Name Input/ Output Description 25 RST Reset Input Reset is required to initialize Write and Read pointers to the first position of the queue by setting RST low. FULL will go high; EMPTY will go low. ____ 2 3, 4, 5, 6, 7, 28, 29, 30, 31 W Write Input Writes data into queue during low to high transitions of W if queue is not full yet. D8 - 0 Data Inputs Input 9 - bit wide input data bus. R Read Input Reads data from queue during high to low transitions of R if queue is not empty. Q8 - 0 Data Output Output ____ ___ 18 10, 11, 13, 14, 15, 19, 20, 21, 22 ___ 9 - bit wide output data bus. ___________ ___________ 26 FIRST / ________ RET First Load/ Retransmit ________ Input FIRST / RET is used differently depending on mode. In Depth Expansion Mode, the pin is grounded to indicate first load. In Single Device Mode, the pin acts as retransmit. Input XI is used to indicate operations in different modes. When the pin is grounded, it indicates an operation in the Single Device Mode. When it is tied to Vcc, it indicates an operation in Depth Expansion Mode. Output Queue is full when FULL goes low. This prohibits further writes into the queue.____The assertion of FULL is synchronous to the falling edge___of W and the deassertion is synchronous to the rising edge of R . Output Queue is empty when EMPTY goes low. This prohibits further reads from the queue. The ___ assertion of EMPTY is synchronous to the falling edge of____ R and the deassertion is synchronous to the rising edge of W. ____ 8 9 24 ____ XI FULL EMPTY Expansion In Full Flag Empty Flag ______ ______ __________ XO / HALF is used differently depending on mode. In Depth ____ ______ Expansion Mode, XI is connected to the previous device's XO pin. When the previous device has reached the last location of memory, this pin will send pulses to the next____ device in the Daisy Chain. In Single Device Mode, when XI is grounded, this pin indicates queue is half-full. 23 __________ XO / HALF Expansion Out / Half Full Flag Output 32 Vcc Power N/A 3.3V power supply. 16 GND Ground N/A 0V Ground. 1, 12, 17, 27 NC No Connection N/A No connection. Table 1. Pin Descriptions 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 4 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async Symbol Rating Com'l & Ind'l Unit VTERM Terminal Voltage with respect to GND -0.5 to + 7 V TSTG Storage Temperature -55 to +125 IOUT DC Output Current -50 to +50 C NOTES: Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended period of operation is outside this range. Standard operation should fall within the Recommended Operating Conditions. mA Table 2. Absolute Maximum Ratings FQV05, FQV04, FQV03, FQV02, FQV01 Symbol Parameter Recommended Operating Conditions VCC Supply Voltage Com'l/Ind'l GND Supply Voltage VIH Input High Voltage Com'l/Ind'l Input Low Voltage Com'l/Ind'l Operating Temperature Commercial Operating Temperature Industrial VIL TA TA Commercial tA = 15ns, 25ns, 35ns, 50ns Min. Typ. Max. Industrial tA = 15ns, 25ns, 35ns, 50ns Min. Typ. Max. Unit 3.0 3.3 3.6 3.0 3.3 3.6 V 0 0 0 0 0 0 V 2.0 - - 2.0 - - V - - 0.8 - - 0.8 V 0 - 70 0 - 70 -40 - 85 -40 - 85 C C DC Electrical Characteristics ILI(1) Input Leakage Current (any input) -10 - 10 -10 - 10 A ILO Output Leakage Current -10 - 10 -10 - 10 A VOH Output Logic "1" Voltage, IOH=-2mA Output Logic "0" Voltage, IOL = 8mA 2.4 - - 2.4 - - V - - 0.4 - - 0.4 V VOL Power Consumption ICC1(2,3,4) Active Power Supply Current - - 50 - - 50 mA ICC2(2,5) Standby Current - - 5 - - 5 mA Capacitance at 1.0MHz Ambient Temperature (25C) Symbol Parameter (6) CIN Input Capacitance COUT(6) Output Capacitance Conditions Max. Unit VIN= 0V 8 pF VOUT= 0V 8 pF NOTES: 1. 2. 3. 4. 5. 6. Measurement with 0.4<=VIN<=Vcc Tested with outputs open (IOUT=0) Tested at f=20MHz Typical Icc1=15+2*fs+0.02*CL*fc (in mA) with Vcc=3.3V, tA=25C, fs=WCLK frequency=RCLK frequency (in MHz, using TTL levels), data switching at fs/2, CL=Capacitive load (in PF) ___ ____ _______ ___________ ________ All inputs = Vcc-0.2V or GND+0.2V and (R =W =RST=FIRST/RET=VIH) Design simulated, not tested. Table 3. DC Specifications 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 5 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async Commercial & Industrial FQV04-15 FQV03-15 FQV02-15 FQV01-15 FQV05-15 tXOH FQV05-35 FQV04-35 FQV03-35 FQV02-35 FQV01-35 FQV05-50 FQV04-50 FQV03-50 FQV02-50 FQV01-50 Min. Max Min. Max Min. Max Min. Max Unit Shift Frequency - 40 - 28.5 - 22.2 - 15 MHz Read Cycle Time 25 - 35 - 45 - 65 - ns Symbol fS tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tWR tDS tDH tRSTC tRST tRSTS tRSTR tRETC tRET tRETS tRETR tEFL tHFH, tFFH tRETF tREMPTY tRFULL tRPE tWEMPTY tWFULL tWHALF tRHALF tWPF tXOL FQV05-25 FQV04-25 FQV03-25 FQV02-25 FQV01-25 Parameter Access Time - 15 - 25 - 35 - 50 ns Read Recovery Time 10 - 10 - 10 - 15 - ns Read Pulse Width 15 - 25 - 35 - 50 - ns Read Pulse Low to Data Bus at Low Z (1) 3 - 3 - 3 - 3 - ns Write Pulse High to Data Bus at Low Z (1,2) 5 - 5 - 5 - 5 - ns Data Valid from Read Pulse High 5 - 5 - 5 - 5 - ns Read Pulse High to Data Bus at High Z (1) - 15 - 18 - 20 - 30 ns 25 - 35 - 45 - 65 - ns Write Cycle Time Write Pulse Width 15 - 25 - 35 - 50 - ns Write Recovery Time 10 - 10 - 10 - 15 - ns Data Set-up Time 11 - 15 - 18 - 30 - ns Data Hold Time 0 - 0 - 0 - 5 - ns Reset Cycle Time 25 - 35 - 45 - 65 - ns Reset Pulse Width 15 - 25 - 35 - 50 - ns Reset Set-up Time (1) 15 - 25 - 35 - 50 - ns Reset Recovery Time 10 - 10 - 10 - 15 - ns Retransmit Cycle Time 25 - 35 - 45 - 65 - ns Retransmit Pulse Width 15 - 25 - 35 - 50 - ns Retransmit Set-up Time (1) 15 - 25 - 35 - 50 - ns Retransmit Recovery Time 10 - 10 - 10 - 15 - ns Reset to Empty Flag Low - 25 - 35 - 45 - 65 ns Reset to Half-Full and Full Flag High - 25 - 35 - 45 - 65 ns Retransmit Low to Flags Valid - 25 - 35 - 45 - 65 ns Read Low to Empty Flag Low - 15 - 25 - 30 - 45 ns Read High to Full Flag High - 15 - 25 - 30 - 45 ns Read Pulse Width after Empty Flag High 15 - 25 - 35 - 50 - ns Write High to Empty Flag High - 15 - 25 - 30 - 45 ns Write Low to Full Flag Low - 15 - 25 - 30 - 45 ns Write Low to Half-Full Flag Low - 25 - 35 - 45 - 65 ns Read High to Half-Full Flag High Write Pulse Width after Full Flag High _____ Read/Write to XO Low _____ - 25 - 35 - 45 - 65 ns 15 - 25 - 35 - 50 - ns - 15 - 25 - 35 - 50 ns - 15 - 25 - 35 - 50 ns tXI _____ 15 - 25 - 35 - 50 - ns tXIR _____ 10 - 10 - 10 - 10 - ns tXIS _____ 10 - 10 - 10 - 15 - ns Read/Write to XO High X I Pulse Width X I Recovery Time X I Set-up Time NOTES: 1. 2. Design simulated, not tested. Only applies to read data flow-through mode. Table 4. AC Electrical Characteristics NOTES: 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 6 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Refer to Figure 4 Table 5. AC Test Condition 3.3V 1.1k D.U.T. 30pF* 680 Figure 4. Output Load *Includes jig and scope capacitances. 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 7 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async Timing Diagrams tRSTC tRST RST tRSTS tRSTR W tRSTS R tEFL EMPTY tHFH, tFFH HALF, FULL NOTES: ______________ __________ ___________ EMPTY , FULL, and HALF may change status during Reset, but are valid at tRSTC. 1. ____ ___ _______ 2. W and R = VIH near rising edge of RST. Diagram 1. Reset Timing tRPW tRC tRR tA tA R tRLZ tDV Q8 - Q0 tRHZ Data Out Valid Data Out Valid tWC W tWR tWPW tDS D8 - D0 tDH Data In Valid Data In Valid Diagram 2. Asynchronous Write and Read Operation 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 8 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async Last Write Ignored Write Additional Reads First Read First Write R W tWFULL tRFULL FULL Diagram 3. Full Flag From Last Write to First Read Last Read Ignored Read First Write Additional Writes First Read W R tREMPTY tWEMPTY EMPTY tA Q8-0 Valid Valid Diagram 4. Empty Flag From Last Read to First Write tRETC tRET RET tRETS tRETR W, R tRETF HALF, EMPTY, FULL Flag Valid Diagram 5. Retransmit W tWEMPTY EMPTY tRPE R Diagram 6. Minimum Timing for an Empty Flag Coincident Read Pulse 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 9 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async R tRFULL FULL tWPF W Diagram 7. Minimum Timing for a Full Flag Coincident Write Pulse W tRHF R tWHF HALF Half-Full or Less More Than Half-Full Half-Full or Less Diagram 8. Half-Full Flag Timing W Write to Last Physical Location Read from Last Physical Location R tXOL tXOH tXOL tXOH XO Diagram 9. Expansion Out tXI tXIR XI tXIS W Write to First Physical Location tXIS Read from First Physical Location R Diagram 10. Expansion In 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 10 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async Operating Modes Single Device Mode: When application requirements are for 256/512/1,024/2,048/4,096/8,192 words or less, a single device ____ may be used. These devices are in Single Device Mode when Expansion In (XI) is grounded. READ ( R ) WRITE (W) DATA OUT (Q 8 - 0) FQV01 FQV02 FQV03 FQV04 FQV05 DATA IN (D8 - 0) FULL ( FULL ) EMPTY ( EMPTY ) RETRANSMIT ( RET ) RESET ( RST ) EXPANSION OUT / HALF ( XO/ HALF ) EXPANSION IN ( XI ) Figure 5. Single Device Mode Depth Expansion Mode: When application requirements are greater than 256/512/1,024/2,048/4,096/8,192 words, multiple devices may be used for Depth Expansion. These devices are in Depth Expansion Mode when the following conditions are met: ___________ ) pin must be grounded. 1. The first device's First Load (FIRST ___________ 2. All other devices' First Load ______ (FIRST) pin must be tied to HIGH ____ be tied to the next devices' Expansion In (XI) pin. 3. All devices' _______ Expansion Out (XO) pin must __________ in Depth Expansion Mode. 4. Retransmit (RET) and Half-Full Flag (HALF) are non-functional__________ _____________ 5. An external logic is required to generate a composite Full Flag (FULL) and Empty Flag (EMPTY). This requires the ORing of all Empty and Full Flags. XO W DATA IN (D8 - 0) 9 9 FULL FQV01 FQV02 EMPTY FQV03 FQV04 FQV05 FIRST XI R 9 Vcc DATA OUT (Q 8 - 0) XO FULL 9 FULL FQV01 FQV02 FQV03 FQV04 FQV05 EMPTY EMPTY FIRST XI XO 9 RST FULL FQV01 FQV02 FQV03 FQV04 FQV05 XI EMPTY FIRST Figure 6. Depth Expansion Mode 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 11 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async Usage Modes Width Expansion Mode: When applications require increased word width, multiple devices may be used for Width Expansion Mode. These devices are in Width Expansion Mode when the same signals from multiple devices are connected. Any word width may be achieved by connecting additional devices. Status flags are functional for any one device. HALF DATA IN (D17 - 0) 18 HALF 9 9 W FQV01 FQV02 FQV03 FQV04 FQV05 FULL RST FQV01 FQV02 FQV03 FQV04 FQV05 R EMPTY RET 9 9 XI XI 18 DATA OUT (Q17 - 0) Figure 7. Width Expansion Mode Bidirectional Mode: When applications require data buffering between two systems that are capable of Read and Write operations, a pair of devices may be used for Bidirectional Mode. Both Depth Expansion and Width Expansion may be used in this mode. WX FULL X System X RX EMPTY X RY FQV01 FQV02 FQV03 FQV04 FQV05 EMPTYY HALF Y DX 8 - 0 QY8 - 0 QX 8 - 0 DY 8 - 0 FQV01 FQV02 FQV03 FQV04 FQV05 HALF X System Y WY FULL Y Figure 8. Bidirectional Mode Data Flow-Through Mode: There are two types of flow-through modes, read flow-through and write flow-through. In the read flow-through mode, the device allows a single word to be read after one word of data has been written into an empty FIFO. The ____ ___ data is enabled on the bus_____________ after the rising edge of W, and remains on the bus until R goes from Low to High. Then the bus goes write flowinto a three-state mode. EMPTY will have a pulse showing temporary deassertion and then would be asserted. In the ___ causes through mode, the device allows a single word to be written after one word of data has been read from a full FIFO. R __________ ____ FULL to be deasserted but a Low W causes it to be asserted again for the new data word. The new word goes into the FIFO on ____ ____ __________ the rising edge of W. W must be toggled when FULL is not asserted to write new data into the FIFO and to increment the write pointer. 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 12 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async Data In W tRPE R EMPTY tREMPTY tWEMPTY tA tWLZ Data Out Valid Data Out Diagram 11. Read Data Flow-Through Mode R tWPF W tRFULL FULL tWFULL tDH Data In Valid Data In tA tDS Data Out Valid Data Out Diagram 12. Write Data Flow-Through Mode Compound Expansion Mode: Compound Expansion Mode is a combination of Depth and Width Expansion Modes to achieve large FIFO arrays. DATA OUT (Q n - 0) R W RST FQV01 FQV02 FQV03 FQV04 FQV05 Depth Expansion Block FQV01 FQV02 FQV03 FQV04 FQV05 Depth Expansion Block FQV01 FQV02 FQV03 FQV04 FQV05 Depth Expansion Block DATA IN (Dn - 0) Figure 9. Compound Expansion Mode 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 13 of 14 FQV01 * FQV02 * FQV03 * FQV04 * FQV05 FlexQTM Async Order Information: HBA Device Family Device Type Power Speed (ns)* Package** Temperature Range XX FQV XX 05 (8,192 x 9) X Low XX 15 - 40 MHz X J X Blank - Commercial (0C to 70C) 04 (4,096 x 9) 25 - 29 MHz 03 (2,048 x 9) 35 - 22 MHz 02 (1,024 x 9) 50 - 15 MHz I - Industrial (-40 to 85C) 01 (512 x 9) *Speed - Slower speeds available upon request. **Package - 32 - pin Plastic Lead Chip Carrier (PLCC) Example: FQV05L15J FQV01L25PFI (8k x 9, 15ns, PLCC, Commercial temp) (512 x 9, 25ns, PLCC, Industrial temp) USA 2107 North First Street, Suite 415 San Jose, CA 95131, USA www.hba.com Tel: 408.453.8885 Fax: 408.453.8886 Taiwan No. 81, Suite 8F-9, Shui-Lee Rd. Hsinchu, Taiwan, R.O.C. www.hba.com Tel: 886.3.516.9118 Fax: 886.3.516.9181 3FA09B MAY 2003 (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 14 of 14