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FEATURES
DESCRIPTION
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GND
VCC
VCC
GND
ATX/RX
A1A
A2A
A3A
A4A
BTX/RX
B1A
B2A
B3A
B4A
GND
VCC
VCC
GND
C1A
C2A
C3A
C4A
CTX/RX
D1A
D2A
D3A
D4A
DTX/RX
GND
VCC
VCC
GND
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
D4Y
D4Z
SN65LVDM1676DGG ( Marked as LVDM1676)
SN65LVDM1677DGG (Marked as LVDM1677)
(TOP VIEW)
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVERS
•Sixteen Low-Voltage Differential Transceivers.Designed for Signaling Rates up to 200 Mbpsper Receiver or 650 Mbps per Transmitter.•Simplex (Point-to-Point) or Half-Duplex(Multipoint) Interface•Typical Differential Output Voltage of 340 mVInto a 50- ΩLoad•Integrated 110- ΩLine Termination on'LVDM1677 Product•Propagation Delay Time:– Driver: 2.5 ns Typ– Receiver: 3 ns Typ•Driver is High Impedance When Disabled orWith V
CC
< 1.5 V for Power Up/DownGlitch-Free Performance and Hot-PluggingEvents
•Bus-Terminal ESD Protection Exceeds 12 kV•Low-Voltage TTL (LVTTL) Logic Input LevelsAre 5-V Tolerant•Packaged in Thin Shrink Small-OutlinePackage With 20 mil Terminal Pitch
The SN65LVDM1676 and SN65LVDM1677(integrated termination) are sixteen differential linetransmitters or receivers (tranceivers) that uselow-voltage differential signaling (LVDS) to achievesignaling rates up to 200 Mbps per transceiverconfigured as a receiver and up to 650 Mbps pertransceiver configured as a transmitter. Theseproducts are similar to TIA/EIA-644 standardcompliant devices (SN65LVDS) counterparts exceptthat the output current of the drivers are doubled.This modification provides a minimum differentialoutput voltage magnitude of 247 mV into a 50- Ωloadand allows double-terminated lines and half-duplexoperation. The receivers detect a voltage differenceof 100 mV with up to 1 V of ground potentialdifference between a transmitter and receiver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION (CONTINUED)
Z
Y
A
TX/RX
LVD Transceiver
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
The intended application of this device and signaling technique is for point-to-point baseband data transmissionover controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit boardtraces, backplanes, or cables. The large number of transceivers integrated into the same substrate along withthe low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data forsynchronous parallel data transfers. (Note: The ultimate rate and distance of data transfer is dependent upon theattenuation characteristics of the media, the noise coupling to the environment, and other systemcharacteristics.)
The SN65LVDM1676 and SN65LVDM1677 are characterized for operation from –40 °C to 85 °C.
FUNCTION TABLE
(1)
INPUTS OUTPUTS
(Y – Z) TX/ RX A Y Z AV
ID
≥100 mV L NA Z Z H–100 mV < V
ID
< 100 mV L NA Z Z ?V
ID
≤-100 mV L NA Z Z LOpen circuit L NA Z Z HNA H L L H ZNA H H H L Z
(1) H = high level, L= low level, Z= high impedance, ? = indeterminate
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A1Z
A1Y
A1A
A2Z
A2Y
A2A
A3Z
A3Y
A3A
A4Z
A4Y
A4A
ATX/RX
B1Z
B1Y
B1A
B2Z
B2Y
B2A
B3Z
B3Y
B3A
B4Z
B4Y
B4A
BTX/RX
C1Z
C1Y
C1A
C2Z
C2Y
C2A
C3Z
C3Y
C3A
C4Z
C4Y
C4A
CTX/RX
D1Z
D1Y
D1A
D2Z
D2Y
D2A
D3Z
D3Y
D3A
D4Z
D4Y
D4A
DTX/RX
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
LOGIC DIAGRAM (POSITIVE LOGIC)
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
7 V
300 kΩ
50 Ω
VCC
A, TX/RX Input
VCC
5 Ω
7 V
Y or Z
Output
10 kΩ
300 kΩ300 kΩ
VCC
7 V 7 V
Y Input Z Input
VCC
5 Ω
7 V
A Output
110 Ω
’LVDM1677 Product Only
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
2.4 –ŤVIDŤ
2
ŤVIDŤ
2
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
over operating free-air temperature range (unless otherwise noted)
(1) (2)
RATING
V
CC
Supply voltage range –0.5 V to 4 VA, TX/ RX –0.5 V to 6 VV
I
Input voltage range
Y or Z –0.5 V to 4 V|V
ID
| Differential input voltage magnitude, (SN65LVDM1677 only) 1 VI
O
Receiver output current ±20 mAP
D
Continuous power dissipation See the Dissipation Rating TableY, Z, and GND Class 3, A: 8 kV, B: 600 VESD Electrostatic discharge
(3)
All Pins Class 3, A: 7 kV, B: 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with MIL-STD-883C Method 3015.7.
T
A
≤25 °C DERATING FACTOR
(1)
T
A
= 85 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING
DGG 2094 mW 16.7 mW/ °C 1089 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no airflow.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6V
IH
High-level input voltage 2V
IL
Low-level input voltage 0.8
V|V
ID
| Magnitude of differential input voltage 0.1 0.6
V
IC
Common-mode input voltage
V
CC
–0.8 VI
OL
Receiver low-level output current 8
mAI
OH
Receiver high-level output current –8
(1)
T
A
Operating free-air temperature –40 85 °C
(1) The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
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ELECTRICAL CHARACTERISTICS
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
over recommended operating free-air temperature range (unless otherwise noted)
TYP
(PARAMETER TEST CONDITIONS MIN MAX UNIT1)
DRIVER
Driver enabled, receiver disabled
140 175R
L
= 50 Ω('LVDM1676) or R
L
= 100 Ω('LVDM1677)I
CC
Supply current mADriver disabled, receiver enabled, no load 45 60|V
OD
| Differential output voltage magnitude 247 340 454R
L
= 50 Ω('LVDM1676) orR
L
= 100 Ω('LVDM1677), mVChange in differential output voltage∆|V
OD
| –50 50See Figure 2 and Figure 1magnitude between logic states
1.37V
OC(SS)
Steady-state common-mode output voltage 1.125 V5∆V
OC(S
Change in steady-state common-mode R
L
= 50 Ω('LVDM1676) or
–50 50 mVS)
output voltage between logic states R
L
= 100 Ω('LVDM1677), See Figure 3Peak-to-peak common-mode outputV
OC(PP)
50 150 mVvoltageI
IH
High-level input current V
IH
= 2 V 3 20 µAI
IL
Low-level input current V
IL
= 0.8 V 2 10 µAV
OY
or V
OZ
= 0 V 10 mAI
OS
Short-circuit output current
V
OD
= 0 V 10 mAI
O(OFF)
Power-off output current V
CC
= 1.5 V, V
O
= 2.4 V –10 10 µAC
IN
Input capacitance V
I
= 0.4 sin (4E6 πt) + 0.5 V 5 pF
RECEIVER
Positive-going differential input voltageV
IT+
100threshold
See Figure 6 and Table 1 mVNegative-going differential input voltageV
IT–
–100thresholdV
OH
High-level output voltage I
OH
= -8 mA 2.4 VV
OL
Low-level output voltage I
OL
= 8 mA 0.4 VV
IY
= V
IZ
= 0 V –40 –24I
I
Input current (Y or Z inputs) µAV
IY
= V
IZ
= 2.4 V –8 –1.2V
IY
= 0 V and V
IZ
= 100 mV,'LVDM1676 5 10 µAV
IY
= 2.4 V and V
IZ
= 2.3 VI
ID
Differential input current |I
IY
– I
IZ
| (inputs)
V
IY
= 0.2 V and V
IZ
= 0 V,'LVDM1677 1.5 2.2 mAV
IY
= 2.4 V and V
IZ
= 2.2 VI
I(OFF)
Power-off input current (Y or Z inputs) V
CC
= 0 V, V
I
= 2.4 V –25 25 µA
(1) All typical values are at 25 °C and with a 3.3-V supply.
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SWITCHING CHARACTERISTICS
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
DRIVER
t
PLH
Propagation delay time, low-to-high-level output 1.3 2.5 3.6t
PHL
Propagation delay time, high-to-low-level output 1.3 2.5 3.6t
r
Differential output signal rise time 0.5 1.2R
L
= 50 Ω('LVDM1676) ort
f
Differential output signal fall time R
L
= 100 Ω('LVDM1677), 0.5 1.2C
L
= 10 pF, See Figure 4t
sk(p)
Pulse skew (|t
PHL
- t
PLH
|) 0.1 0.6t
sk(o)
Channel-to-channel output skew
(2)
0.1 0.4 nst
sk(pp)
Part-to-part skew
(3)
1t
PZH
Propagation delay time, high-impedance-to-high-level output 11 20t
PZL
Propagation delay time, high-impedance-to-low-level output 10 20See Figure 5t
PHZ
Propagation delay time, high-level-to-high-impedance output 3 10t
PLZ
Propagation delay time, low-level-to-high-impedance output 3 10
RECEIVER
t
PLH
Propagation delay time, low-to-high-level output 1.5 3 4.5t
PHL
Propagation delay time, high-to-low-level output 1.5 3 4.5t
r
Output signal rise time 0.6 1.6C
L
= 10 pF,t
f
Output signal fall time 0.6 1.6See Figure 7t
sk(p)
Pulse skew (|t
PHL
– t
PLH
|) 0.2 0.8t
sk(o)
Channel-to-channel output skew
(4)
0.7 1.2 nst
sk(pp)
Part-to-part skew
(5)
1t
PZH
Propagation delay time, high-impedance-to-high-level output 9 15t
PZL
Propagation delay time, high-impedance-to-low-level output 8 15See Figure 8t
PHZ
Propagation delay time, high-level-to-high-impedance output 12 20t
PLZ
Propagation delay time, low-level-to-high-impedance output 11 20
(1) All typical values are at 25 °C and with a 3.3-V supply.(2) t
sk(o)
is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in thesame direction while driving identical specified loads.(3) t
sk(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.(4) t
sk(o)
is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in thesame direction while driving identical specified loads.(5) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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PARAMETER MEASUREMENT INFORMATION
±
3.75 kΩ
0 V ≤ VTEST ≤ 2.4 V
Y
ZVOD
Input RL3.75 kΩ
Y
Z
Input
C =10pF
L
(2Places)
R /2(2Places)
L
VOC
VOC
VOC(PP)
VOC(SS)
0V
3V
A
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
Figure 1. Driver Voltage and Current Definitions
Figure 2. Driver V
OD
Test Circuit
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. C
L
includes instrumentation and fixture capacitance within 0,06 m ofthe D.U.T. The measurement of V
OC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
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Y
Z
Input
Input
Output
C =10pF
L
(2Places)
RL
VOD
tpHL
VOD(H)
VOD(L)
0V
V /2
CC
0%
tpLH
tr
tf
0V
3V
100%
80%
20%
C =10pF
L
(2Places)
Y
Z
TX/RX
R /2(2Places)
L
1.2V
tpZL tpHZ
3V
V /2
CC
0V
@1.4V
1.25V
1.2V
@1V
1.2V
1.15V
TX/RX
V orV
OZ OY
VOY VOZ
0.8Vor2V
+
–
V orV
OY OZ
tpZH tpHZ
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
PARAMETER MEASUREMENT INFORMATION (continued)
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 10 ±0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 m ofthe D.U.T.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. C
L
includes instrumentation and fixture capacitance within 0,06 m ofthe D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
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VID
Y
Z
A
VO
VIZ
IIZ
IO
VIY
IIY
VIC
(VIY IZ
+V )/2
VID
VO
VIZ
VIY CL = 10 pF
tpHL tpLH
tftr
80%
20%
VIY
VIZ
VID
VO
1.4 V
1 V
0.4 V
0 V
–0.4 V
~VCC
VCC/2
~ 0 V
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
RESULTING DIFFERENTIAL RESULTING COMMON-APPLIED VOLTAGES
INPUT VOLTAGE MODE INPUT VOLTAGE
V
IY
V
IZ
V
ID
V
IC
1.25 V 1.15 V 100 mV 1.2 V1.15 V 1.25 V –100 mV 1.2 V2.4 V 2.3 V 100 mV 2.35 V2.3 V 2.4 V –100 mV 2.35 V0.1 V 0 V 100 mV 0.05 V0 V 0.1 V –100 mV 0.05 V1.5 V 0.9 V 600 mV 1.2 V0.9 V 1.5 V –600 mV 1.2 V2.4 V 1.8 V 600 mV 2.1 V1.8 V 2.4 V –600 mV 2.1 V0.6 V 0 V 600 mV 0.3 V0 V 0.6 V –600 mV 0.3 V
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 10 ±0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 m ofthe D.U.T.
Figure 7. Timing Test Circuit and Waveforms
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Z
Y
VO±
500 Ω
VTEST
10 pF
1.2 V
tpZL
tpLZ
2.5 V
1 V
3 V
VCC/2
0 V
2.5 V
VCC/2
VOL
VTEST
Y
TX/RX
A
TX/RX
A
VOL + 0.5 V
tpZH
tpHZ
0 V
1.4 V
3 V
VCC/2
0 V
VOH
VCC/2
0 V
VTEST
Y
TX/RX
AVOH – 0.5 V
NOTE: All input pulses are supplied by a generator having the following
characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture
capacitance within 0,06 m of the D.U.T.
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
Figure 8. Enable/Disable Time Test Circuit and Waveforms
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TYPICAL CHARACTERISTICS
|VID|− Differential Input Voltage − V
1
00.1 0.3
2
1.5
0.5
0.2 0.4 0.6
2.5
0 0.5
VCC = 3 V
− Common-Mode Input Voltage − V
VIC
VCC > 3.15 V
MIN
IOL − Low-Level Output Current − mA
1
080
2
VCC = 3.3 V
TA = 25°C
3
124
VOL− Low-Level Output Voltage − V
4
6 102
IOH − High-Level Output Current − mA
1
.5
0−4 −6
3
0
1.5
VCC = 3.3 V
TA = 25°C
2
2.5
−8−2
VOH− High-Level Output Voltage − V
3.5
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
COMMON-MODE INPUT VOLTAGE
vsDIFFERENTIAL INPUT VOLTAGE
Figure 9.
DRIVER DRIVERLOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGEvs vsLOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 10. Figure 11.
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0IOH − High-Level Output Current − mA
4
0−80
2
−20
VOH
−40 −60
3
1
− High-Level Output Voltage − V
VCC = 3.3 V
TA = 25°C
0IOL − Low-Level Output Current − mA
5
0
2
20
VOL
40 60
3
1
− Low-Level Output Votlage − V
80
4
VCC = 3.3 V
TA = 25°C
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
RECEIVER RECEIVERHIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGEvs vsHIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 12. Figure 13.
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DRIVER EYE PATTERN
TEST CONDITIONS
EQUIPMENT
HewlettPackardHP6624A
DCPowerSupply
BenchTestBoard
AgilentParBERT
(E4832A)
TektronixTDS6604
DigitalStorageScope
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
•V
CC
= 3.6 V•T
A
= 25 °C (ambient temperature)•All 16 channels switching simultaneously with NRZ data. Scope is triggered at the same frequency with pulse. Inputsignal level = 0 V to 3 V single ended.•Resistive loading with no added capacitance
•Hewlett Packard HP6624A DC power supply•Tektronix TDS6604 Digital Storage Scope•Agilent ParBERT E4832A
Figure 14. Equipment Setup
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(a)representative TransceiverconfiguredasRx@200Mbps
(Ch1=xyA)
(b)representative Transceiverconfiguredas Tx@650Mbps
(M1=xyY-xyZ)
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
NOTE: x represents transceiver group A, B, C, or D, and y represents transceiver 1, 2, 3, or 4.
Figure 15. Typical Driver Eye Pattern for the SN65LVDM1676 With 12 Transceivers Configured as Rx and4 Transceivers Configured as Tx all Switching Frequency Asynchronous Data(T
A
= 25 °C; V
CC
= 3.6 V; PRBS = 2
23-1
)
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APPLICATION INFORMATION
FAIL SAFE
Rt = 100 Ω (Typ)
300 kΩ300 kΩ
VCC
VIT ≈ 2.3 V
A
BY
SN65LVDM1676
SN65LVDM1677
SLLS430D – NOVEMBER 2000 – REVISED JUNE 2007
One of the most common problems with differential signaling applications is how the system responds when nodifferential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in thatits output logic state can be indeterminate when the differential input voltage is between –50 mV and 50 mV andwithin its recommended input common-mode voltage range. TI's LVDS receiver is different, however, in how ithandles the open-input circuit situation.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could bewhen the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiverwill pull each line of the signal pair to near V
CC
through 300-k Ωresistors as shown in Figure 16 . The fail-safefeature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force theoutput to a high-level, regardless of the differential input voltage.
Figure 16. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 50-mV differentialinput voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function aslong as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground thatcould defeat the pullup currents from the receiver and the fail-safe feature.
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LVDM1676DGG ACTIVE TSSOP DGG 64 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDM1676DGGG4 ACTIVE TSSOP DGG 64 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDM1676DGGR ACTIVE TSSOP DGG 64 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDM1676DGGRG4 ACTIVE TSSOP DGG 64 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDM1677DGG ACTIVE TSSOP DGG 64 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDM1677DGGG4 ACTIVE TSSOP DGG 64 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDM1677DGGR ACTIVE TSSOP DGG 64 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65LVDM1677DGGRG4 ACTIVE TSSOP DGG 64 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-May-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDM1676DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 Q1
SN65LVDM1677DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDM1676DGGR TSSOP DGG 64 2000 346.0 346.0 41.0
SN65LVDM1677DGGR TSSOP DGG 64 2000 346.0 346.0 41.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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